Created
September 5, 2023 14:13
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RG405V Device Trees
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| /dts-v1/; | |
| / { | |
| model = "Spreadtrum UMS512-1H10 Board"; | |
| compatible = "sprd,ums512-1h10\0sprd,ums512"; | |
| sprd,sc-id = "ums512 1h10 1000"; | |
| fragment { | |
| target-path = "/"; | |
| __overlay__ { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| lcds { | |
| lcd_d53e6ea8966_mipi_2lane_960X544 { | |
| sprd,dsi-work-mode = <0x01>; | |
| sprd,dsi-lane-number = <0x02>; | |
| sprd,dsi-color-format = "rgb888"; | |
| sprd,phy-bit-clock = <0x59d80>; | |
| sprd,phy-escape-clock = <0x4e20>; | |
| sprd,width-mm = <0x6d>; | |
| sprd,height-mm = <0x3e>; | |
| sprd,esd-check-enable = <0x00>; | |
| sprd,esd-check-mode = <0x03>; | |
| sprd,esd-check-period = <0x3e8>; | |
| sprd,esd-check-register = <0x0a>; | |
| sprd,esd-check-value = <0x9c>; | |
| sprd,reset-on-sequence = <0x01 0x32 0x00 0x32 0x01 0x78>; | |
| sprd,reset-off-sequence = <0x00 0x14>; | |
| sprd,use-dcs-write; | |
| sprd,initial-command = <0x39000006 0xff770100 0x132300 0x2ef08 0x39000006 0xff770100 0x102300 0x3c04f 0x3230000 0x3c10c02 0x23000003 0xc2100623 0x2c7 0x4230000 0x2cc3839 0x11b0 0x40161d0e 0x12060c0a 0x9250003 0x3f3f1c 0x39000011 0xb140161e 0xe11060c 0x8092600 0x15003f3f 0x1c390000 0x6ff7701 0x1123 0x2b0 0x4d230000 0x2b13523 0x2b2 0x7230000 0x2b38023 0x2b5 0x47230000 0x2b78523 0x2b8 0x20230000 0x2b91023 0x2bc 0x3230000 0x2c08923 0x2c1 0x78230000 0x2c27823 0x2d0 0x88390000 0x4e00000 0x2390000 0xce10400 0x500 0x20 0x20390000 0xee20000 0x00 0x00 0x39 0x5e3 0x3300 0x23000003 0xe4220039 0x11e5 0x45ca0a0 0x65ca0a0 0x00 0x00 0x39000005 0xe6000033 0x230000 0x3e72200 0x39000011 0xe8055ca0 0xa0075ca0 0xa0000000 0x00 0x390000 0x8eb0200 0x40400000 0x230000 0x3ec0000 0x39000011 0xedfa450b 0xffffffff 0xffffffff 0xffffb054 0xaf390000 0x7ef0808 0x8453f54 0x39000006 0xff770100 0x2300 0x23617 0x23000002 0x3a7713c8 0x11113 0xa000129>; | |
| sprd,sleep-in-command = [13 0a 00 01 28 13 78 00 01 10]; | |
| sprd,sleep-out-command = [13 78 00 01 11 13 64 00 01 29]; | |
| phandle = <0x14>; | |
| display-timings { | |
| native-mode = <0x01>; | |
| timing0 { | |
| clock-frequency = <0x186a000>; | |
| hactive = <0x1e0>; | |
| vactive = <0x280>; | |
| hback-porch = <0x3c>; | |
| hfront-porch = <0x3c>; | |
| vback-porch = <0x0a>; | |
| vfront-porch = <0x0a>; | |
| hsync-len = <0x2a>; | |
| vsync-len = <0x04>; | |
| phandle = <0x01>; | |
| }; | |
| timing1 { | |
| clock-frequency = <0x186a000>; | |
| hactive = <0x1e0>; | |
| vactive = <0x280>; | |
| hback-porch = <0x3c>; | |
| hfront-porch = <0x3c>; | |
| vback-porch = <0x0a>; | |
| vfront-porch = <0x0a>; | |
| hsync-len = <0x2a>; | |
| vsync-len = <0x04>; | |
| phandle = <0x15>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dtbo { | |
| compatible = "sprd,dtbo-test"; | |
| reg = <0x00 0x00 0x00 0x11>; | |
| phandle = <0x16>; | |
| }; | |
| sprd_backlight { | |
| compatible = "sprd,sharkl5pro-backlight"; | |
| pwms = <0xffffffff 0x02 0x9c40>; | |
| pwm-names = "backlight"; | |
| sprd,max-brightness-level = <0x370>; | |
| default-brightness-level = <0xfa>; | |
| sprd,brightness-scale = <0x3ff>; | |
| brightness-levels = <0x00 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1f 0x21 0x23 0x25 0x27 0x29 0x2b 0x2d 0x2e 0x30 0x32 0x34 0x36 0x38 0x3a 0x3c 0x3e 0x40 0x42 0x44 0x46 0x48 0x4a 0x4c 0x4e 0x50 0x52 0x54 0x56 0x58 0x5a 0x5c 0x5e 0x60 0x62 0x64 0x66 0x68 0x6a 0x6c 0x6e 0x70 0x72 0x74 0x76 0x78 0x7a 0x7c 0x7e 0x80 0x82 0x84 0x86 0x88 0x8a 0x8c 0x8e 0x90 0x92 0x94 0x96 0x98 0x9a 0x9c 0x9e 0xa0 0xa2 0xa4 0xa6 0xa9 0xac 0xaf 0xb2 0xb5 0xb8 0xbb 0xbe 0xc1 0xc4 0xc7 0xca 0xcd 0xd0 0xd3 0xd6 0xd9 0xdc 0xdf 0xe2 0xe5 0xe8 0xeb 0xee 0xf1 0xf4 0xf7 0xfa 0xfd 0x100 0x103 0x106 0x109 0x10c 0x10f 0x112 0x115 0x118 0x11b 0x11e 0x122 0x126 0x12a 0x12e 0x132 0x136 0x13a 0x13e 0x142 0x146 0x14a 0x14e 0x152 0x156 0x15a 0x15e 0x162 0x166 0x16a 0x16e 0x172 0x176 0x17a 0x17e 0x182 0x186 0x18a 0x18e 0x192 0x196 0x19a 0x19e 0x1a2 0x1a6 0x1aa 0x1ae 0x1b2 0x1b6 0x1ba 0x1be 0x1c3 0x1c8 0x1cd 0x1d2 0x1d7 0x1dc 0x1e1 0x1e6 0x1eb 0x1f0 0x1f5 0x1fa 0x1ff 0x204 0x209 0x20e 0x213 0x218 0x21d 0x222 0x227 0x22c 0x231 0x236 0x23b 0x240 0x245 0x24a 0x24f 0x254 0x259 0x25e 0x263 0x268 0x26d 0x272 0x277 0x27c 0x281 0x286 0x28c 0x292 0x298 0x29e 0x2a4 0x2aa 0x2b0 0x2b6 0x2bc 0x2c2 0x2c8 0x2ce 0x2d4 0x2da 0x2e0 0x2e6 0x2ec 0x2f2 0x2f8 0x2fe 0x304 0x30a 0x310 0x316 0x31c 0x322 0x328 0x32e 0x334 0x33a 0x340 0x346 0x34c 0x352 0x358 0x35e 0x364 0x36a 0x370>; | |
| phandle = <0x07>; | |
| }; | |
| battery { | |
| compatible = "simple-battery"; | |
| charge-full-design-microamp-hours = <0x4c4b40>; | |
| charge-term-current-microamp = <0x1d4c0>; | |
| constant-charge-voltage-max-microvolt = <0x419ce0>; | |
| factory-internal-resistance-micro-ohms = <0x1fbd0>; | |
| voltage-min-design-microvolt = <0x340850>; | |
| fullbatt-voltage = <0xa730>; | |
| fullbatt-current = <0x1d4c0>; | |
| fullbatt-track-end-vol = <0x40d990>; | |
| fullbatt-track-end-cur = <0x1fbd0>; | |
| first-calib-voltage = <0x349cc0>; | |
| first-calib-capacity = <0x32>; | |
| ocv-capacity-celsius = <0x19>; | |
| ocv-capacity-table-0 = <0x418d40 0x64 0x3facc8 0x5f 0x3e6890 0x5a 0x3d7a48 0x55 0x3c97b8 0x50 0x3bbcf8 0x4b 0x3af1d8 0x46 0x3a3270 0x41 0x3982a8 0x3c 0x38d6c8 0x37 0x383a88 0x32 0x37c558 0x2d 0x377b20 0x28 0x373ca0 0x23 0x370208 0x1e 0x36c770 0x19 0x367d38 0x14 0x361f78 0x0f 0x35aa48 0x0a 0x350a20 0x05 0x33e140 0x00>; | |
| voltage-temp-table = <0x10b558 0x320 0xf0b90 0x352 0xd65b0 0x384 0xbd358 0x3b6 0xa5870 0x3e8 0x900b0 0x41a 0x7c830 0x44c 0x6b6c0 0x47e 0x5c490 0x4b0 0x4f1a0 0x4e2 0x43df0 0x514 0x3a1b0 0x546 0x31ce0 0x578 0x2ab98 0x5aa 0x249f0 0x5dc 0x1f7e8 0x60e 0x1b198 0x640 0x17700 0x672>; | |
| capacity-temp-table = <0x2d 0x64 0x19 0x64 0x0a 0x62 0x00 0x5d 0xfffffff6 0x55 0xffffffec 0x40>; | |
| resistance-temp-table = <0x2d 0x62 0x19 0x61 0x0a 0x61 0x00 0x61 0xfffffff6 0x62 0xffffffec 0x62>; | |
| charge-sdp-current-microamp = <0x7a120 0x7a120>; | |
| charge-dcp-current-microamp = <0x1e8480 0x2dc6c0>; | |
| charge-cdp-current-microamp = <0x1e8480 0x1e8480>; | |
| charge-unknown-current-microamp = <0x118c30 0x118c30>; | |
| dcp-jeita-temp-table = <0x3e8 0x406 0x00 0x432380 0x47e 0x49c 0xaae60 0x432380 0x5aa 0x58c 0x1e8480 0x432380 0x640 0x622 0xaae60 0x3e8fa0>; | |
| sdp-jeita-temp-table = <0x3e8 0x406 0x00 0x432380 0x47e 0x49c 0x7a120 0x432380 0x5aa 0x58c 0x1e8480 0x432380 0x640 0x622 0x7a120 0x3e8fa0>; | |
| cdp-jeita-temp-table = <0x3e8 0x406 0x00 0x432380 0x47e 0x49c 0xaae60 0x432380 0x5aa 0x58c 0x1e8480 0x432380 0x640 0x622 0xaae60 0x3e8fa0>; | |
| unknown-jeita-temp-table = <0x3e8 0x406 0x00 0x432380 0x47e 0x49c 0x7a120 0x432380 0x5aa 0x58c 0x7a120 0x432380 0x640 0x622 0x7a120 0x3e8fa0>; | |
| force-jeita-status = <0x02>; | |
| phandle = <0x02>; | |
| }; | |
| charger-manager { | |
| compatible = "charger-manager"; | |
| cm-name = "battery"; | |
| cm-poll-mode = <0x02>; | |
| cm-poll-interval = <0x3a98>; | |
| cm-battery-stat = <0x02>; | |
| cm-fullbatt-vchkdrop-ms = <0x7530>; | |
| cm-fullbatt-vchkdrop-volt = <0xea60>; | |
| cm-fullbatt-capacity = <0x64>; | |
| cm-fullbatt-soc = <0x64>; | |
| cm-fullbatt-voltage = <0x419ce0>; | |
| cm-fullbatt-current = <0x1d4c0>; | |
| cm-num-chargers = <0x01>; | |
| cm-chargers = "aw32257"; | |
| cm-fuel-gauge = "sc27xx-fgu"; | |
| cm-battery-cold = <0xc8>; | |
| cm-battery-cold-in-minus; | |
| cm-battery-hot = <0x320>; | |
| cm-battery-temp-diff = <0x64>; | |
| cm-charging-max = <0x1499700>; | |
| cm-discharging-max = <0x2932e0>; | |
| cm-wdt-interval = <0x3c>; | |
| cm-shutdown-voltage = <0x2f4d60>; | |
| cm-tickle-time-out = <0x5dc>; | |
| cm-one-cap-time = <0x1e>; | |
| cm-thermal-zone = "board-thmzone"; | |
| cm-charge-voltage-max = <0x632ea0>; | |
| cm-charge-voltage-drop = <0xaae60>; | |
| monitored-battery = <0x02>; | |
| cm-cap-remap-table = <0x01 0x02 0x03 0x02 0x03 0x02 0x62 0x63 0x02 0x63 0x64 0x03>; | |
| regulator@0 { | |
| cm-regulator-name = "vddgen0"; | |
| cable@0 { | |
| cm-cable-name = "USB"; | |
| extcon = <0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| thermal-sensor { | |
| compatible = "generic-adc-thermal"; | |
| #thermal-sensor-cells = <0x00>; | |
| io-channels = <0xffffffff 0x01>; | |
| io-channel-names = "sensor-channel"; | |
| temperature-lookup-table = <0xffff64c2 0x46b 0xffff8baf 0x456 0xffffb3e8 0x432 0xffffedb9 0x3d7 0x277e 0x346 0x60e5 0x28e 0xaf7a 0x19d 0xd677 0x13c 0xfd7f 0xee 0x12484 0xb2 0x14b93 0x85 0x172a3 0x64 0x199b0 0x4b 0x1c0c9 0x39 0x1e7c8 0x2b>; | |
| phandle = <0x04>; | |
| }; | |
| gpio-keys { | |
| compatible = "gpio-keys"; | |
| autorepeat; | |
| pinctrl-names = "gpio_124"; | |
| pinctrl-0 = <0x03>; | |
| key-power { | |
| label = "Power Key"; | |
| linux,code = <0x74>; | |
| gpios = <0xffffffff 0x01 0x01>; | |
| debounce-interval = <0x02>; | |
| wakeup-source; | |
| }; | |
| key-volumedown { | |
| label = "Volume Down Key"; | |
| linux,code = <0x72>; | |
| gpios = <0xffffffff 0x04 0x00>; | |
| debounce-interval = <0x02>; | |
| wakeup-source; | |
| }; | |
| key-volumeup { | |
| label = "Volume Up Key"; | |
| linux,code = <0x73>; | |
| gpios = <0xffffffff 0x1e 0x01>; | |
| debounce-interval = <0x02>; | |
| wakeup-source; | |
| }; | |
| }; | |
| singleadc-joypad { | |
| compatible = "singleadc-joypad"; | |
| joypad-name = "retrogame_joypad"; | |
| joypad-product = <0x1101>; | |
| joypad-revision = <0x100>; | |
| vdd-supply = <0xffffffff>; | |
| vdd-voltage = <0x325aa0>; | |
| status = "okay"; | |
| io-channels = <0xffffffff 0x02>; | |
| io-channel-names = "joypad_adc"; | |
| amux-count = <0x04>; | |
| amux-a-gpios = <0xffffffff 0x24 0x01>; | |
| amux-b-gpios = <0xffffffff 0x25 0x01>; | |
| amux-en-gpios = <0xffffffff 0x0f 0x01>; | |
| adc-power-ctl1 = <0xffffffff 0x13 0x01>; | |
| adc-power-ctl2 = <0xffffffff 0x15 0x01>; | |
| adc-power-ctl3 = <0xffffffff 0x16 0x01>; | |
| adc-power-ctl4 = <0xffffffff 0x18 0x01>; | |
| adc-power-en-gpios = <0xffffffff 0x10 0x01>; | |
| fan-power-en-gpios = <0xffffffff 0x8b 0x01>; | |
| button-adc-scale = <0x02>; | |
| button-adc-deadzone = <0xd8>; | |
| button-adc-fuzz = <0x40>; | |
| button-adc-flat = <0x20>; | |
| abs_x-p-tuning = <0x190>; | |
| abs_x-n-tuning = <0x190>; | |
| abs_y-p-tuning = <0x190>; | |
| abs_y-n-tuning = <0x190>; | |
| abs_rx-p-tuning = <0x190>; | |
| abs_rx-n-tuning = <0x190>; | |
| abs_ry-p-tuning = <0x190>; | |
| abs_ry-n-tuning = <0x190>; | |
| poll-interval = <0x04>; | |
| key-resetn { | |
| label = "Home"; | |
| linux,code = <0x44>; | |
| gpios = <0xffffffff 0x7e 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw1 { | |
| label = "GPIO DPAD-UP"; | |
| linux,input-type = <0x03>; | |
| linux,code = <0x11>; | |
| gpios = <0xffffffff 0x1a 0x01>; | |
| linux,abs-value = <0x02>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw2 { | |
| label = "GPIO DPAD-DOWN"; | |
| linux,input-type = <0x03>; | |
| linux,code = <0x11>; | |
| gpios = <0xffffffff 0x19 0x01>; | |
| debounce-interval = <0x02>; | |
| linux,abs-value = <0x01>; | |
| }; | |
| sw3 { | |
| label = "GPIO DPAD-LEFT"; | |
| linux,input-type = <0x03>; | |
| linux,code = <0x10>; | |
| gpios = <0xffffffff 0x61 0x01>; | |
| linux,abs-value = <0x02>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw4 { | |
| label = "GPIO DPAD-RIGHT"; | |
| linux,input-type = <0x03>; | |
| linux,code = <0x10>; | |
| gpios = <0xffffffff 0x56 0x01>; | |
| debounce-interval = <0x02>; | |
| linux,abs-value = <0x01>; | |
| }; | |
| sw5 { | |
| label = "GPIO BTN-A"; | |
| linux,code = <0x134>; | |
| gpios = <0xffffffff 0x74 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw6 { | |
| label = "GPIO BTN-B"; | |
| linux,code = <0x131>; | |
| gpios = <0xffffffff 0x70 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw7 { | |
| label = "GPIO BTN-X"; | |
| linux,code = <0x133>; | |
| gpios = <0xffffffff 0x58 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw8 { | |
| label = "GPIO BTN-Y"; | |
| linux,code = <0x130>; | |
| gpios = <0xffffffff 0x71 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw9 { | |
| label = "GPIO BTN_SELECT"; | |
| linux,code = <0x13a>; | |
| gpios = <0xffffffff 0x37 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw10 { | |
| label = "GPIO BTN_START"; | |
| linux,code = <0x13b>; | |
| gpios = <0xffffffff 0x57 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw11 { | |
| label = "GPIO BACK KEY"; | |
| linux,code = <0x9e>; | |
| gpios = <0xffffffff 0x7c 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw12 { | |
| label = "GPIO BTN_TL"; | |
| linux,code = <0x136>; | |
| gpios = <0xffffffff 0x0e 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw13 { | |
| label = "GPIO BTN_TR"; | |
| linux,code = <0x137>; | |
| gpios = <0xffffffff 0x01 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw14 { | |
| label = "GPIO BTN_TL2"; | |
| linux,code = <0x138>; | |
| gpios = <0xffffffff 0x03 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw15 { | |
| label = "GPIO BTN_TR2"; | |
| linux,code = <0x139>; | |
| gpios = <0xffffffff 0x02 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw16 { | |
| label = "GPIO BTN_THUMBL"; | |
| linux,code = <0x13d>; | |
| gpios = <0xffffffff 0x14 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| sw17 { | |
| label = "GPIO BTN_THUMBR"; | |
| linux,code = <0x13e>; | |
| gpios = <0xffffffff 0x17 0x01>; | |
| debounce-interval = <0x02>; | |
| }; | |
| }; | |
| sprd_uid { | |
| compatible = "sprd-uid"; | |
| nvmem-cells = <0xffffffff 0xffffffff>; | |
| nvmem-cell-names = "uid_start\0uid_end"; | |
| }; | |
| sprd-marlin3 { | |
| compatible = "unisoc,marlin3lite_sdio"; | |
| m2-wakeup-ap-gpios = <0xffffffff 0x21 0x01>; | |
| reset-gpios = <0xffffffff 0x5f 0x01>; | |
| enable-gpios = <0xffffffff 0x8f 0x01>; | |
| m2-to-ap-irq-gpios = <0xffffffff 0x5e 0x01>; | |
| avdd12-supply = <0xffffffff>; | |
| avdd33-supply = <0xffffffff>; | |
| dcxo18-supply = <0xffffffff>; | |
| clock-names = "clk_32k\0source\0enable"; | |
| clocks = <0xffffffff 0x02 0xffffffff 0xffffffff 0x03>; | |
| extcon = <0xffffffff>; | |
| sdhci-name = <0xffffffff>; | |
| sprd,btwf-file-name = "/dev/block/platform/soc/soc:ap-apb/71400000.sdio/by-name/wcnmodem"; | |
| sprd,gnss-file-name = "/vendor/firmware/gnssmodem.bin"; | |
| adma-tx; | |
| adma-rx; | |
| avdd12-parent-bound-chip = <0x1a4c 0x01 0x00 0x01>; | |
| avdd12-bound-wbreq = <0x1ac8 0x1000 0x00 0x1000>; | |
| avdd33-bound-wbreq = <0x1acc 0x04 0x00 0x04>; | |
| phandle = <0x17>; | |
| wlan { | |
| compatible = "sprd,sc2355-sdio-wifi"; | |
| }; | |
| gnss { | |
| compatible = "sprd,gnss"; | |
| }; | |
| sprd-mtty { | |
| compatible = "sprd,mtty"; | |
| sprd,name = "ttyBT"; | |
| }; | |
| sprd-fm { | |
| compatible = "sprd,marlin3-fm"; | |
| sprd,name = "sprd-fm"; | |
| }; | |
| }; | |
| pwm-fan { | |
| compatible = "pwm-fan"; | |
| pwms = <0xffffffff 0x00 0x9c40>; | |
| pwm-names = "fan"; | |
| }; | |
| }; | |
| }; | |
| fragment@0 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| board-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x04>; | |
| phandle = <0x18>; | |
| }; | |
| }; | |
| }; | |
| fragment@1 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| heap@1 { | |
| reg = <0x01>; | |
| label = "carveout_mm"; | |
| type = <0x02>; | |
| memory-region = <0x05>; | |
| }; | |
| heap@2 { | |
| reg = <0x02>; | |
| label = "carveout_fd"; | |
| type = <0x02>; | |
| memory-region = <0x06>; | |
| }; | |
| }; | |
| }; | |
| fragment@2 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "okay"; | |
| clock-frequency = <0x61a80>; | |
| }; | |
| }; | |
| fragment@3 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "okay"; | |
| clock-frequency = <0x61a80>; | |
| }; | |
| }; | |
| fragment@4 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "okay"; | |
| touchscreen@14 { | |
| compatible = "goodix,gt9xx"; | |
| reg = <0x14>; | |
| vdd-supply = <0xffffffff>; | |
| vdd-voltage = <0x325aa0>; | |
| irq-gpios = <0xffffffff 0x90 0x00>; | |
| reset-gpios = <0xffffffff 0x91 0x00>; | |
| touchscreen-max-id = <0x0b>; | |
| touchscreen-size-x = <0x1e0>; | |
| touchscreen-size-y = <0x280>; | |
| touchscreen-max-w = <0x200>; | |
| touchscreen-max-p = <0x200>; | |
| irq-flags = <0x02>; | |
| goodix,slide-wakeup = <0x00>; | |
| goodix,type-a-report = <0x00>; | |
| goodix,driver-send-cfg = <0x01>; | |
| goodix,resume-in-workqueue = <0x00>; | |
| goodix,int-sync = <0x01>; | |
| goodix,swap-x2y = <0x00>; | |
| goodix,esd-protect = <0x01>; | |
| goodix,auto-update-cfg = <0x00>; | |
| goodix,power-off-sleep = <0x00>; | |
| goodix,pen-suppress-finger = <0x00>; | |
| goodix,cfg-group0 = [48 80 02 e0 01 0a 3d 00 01 0f 28 0f 50 32 03 01 00 00 00 00 00 00 00 18 1a 1e 14 86 26 55 52 54 ee 06 00 00 09 b9 02 1d 00 00 00 00 00 00 00 00 00 00 00 46 5a 94 f5 02 07 0a 40 04 00 47 00 00 4b 00 00 4f 00 00 53 00 00 57 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 0c 0d 0e 0f 10 11 14 15 16 ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00 23 22 21 20 1f 1e 08 07 06 04 02 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 00 00 f3 01]; | |
| }; | |
| }; | |
| }; | |
| fragment@5 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| charger@6a { | |
| compatible = "aw32257"; | |
| reg = <0x6a>; | |
| phys = <0xffffffff>; | |
| monitored-battery = <0x02>; | |
| extcon = <0xffffffff>; | |
| ti,current-limit = <0x1e8480>; | |
| ti,weak-battery-voltage = <0xd48>; | |
| ti,battery-regulation-voltage = <0x1068>; | |
| ti,charge-current = <0x1e8480>; | |
| ti,termination-current = <0x1e8480>; | |
| ti,resistor-sense = <0x21>; | |
| phandle = <0x19>; | |
| otg-vbus { | |
| regulator-name = "vddvbus"; | |
| phandle = <0x09>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| fragment@6 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| status = "okay"; | |
| clock-frequency = <0xf4240>; | |
| }; | |
| }; | |
| fragment@7 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| sprd-scene = "boost\0lcdon\0lcdoff\0camlow\0camhigh\0camveryhigh\0faceid\0top"; | |
| sprd-freq = <0x74a 0x74a 0x100 0x180 0x200 0xbacd 0x535 0xbacd>; | |
| }; | |
| }; | |
| fragment@8 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| sprd,backlight = <0x07>; | |
| sprd,surface-width = <0x1e0>; | |
| sprd,surface-height = <0x280>; | |
| reset-gpio = <0xffffffff 0x32 0x00>; | |
| }; | |
| }; | |
| fragment@9 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| sprd,backlight = <0x07>; | |
| sprd,logo-memory = <0x08>; | |
| }; | |
| }; | |
| fragment@10 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| bootargs_ext = "androidboot.hardware=ums512_1h10"; | |
| }; | |
| }; | |
| fragment@11 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| logobuffer@9e000000 { | |
| reg = <0x00 0x9e000000 0x00 0x9e4000>; | |
| phandle = <0x08>; | |
| }; | |
| widevine@e3800000 { | |
| reg = <0x00 0xe3800000 0x00 0xc800000>; | |
| phandle = <0x05>; | |
| }; | |
| faceid-mem@fd270000 { | |
| reg = <0x00 0xfd270000 0x00 0x500000>; | |
| phandle = <0x06>; | |
| }; | |
| vdsp-mem@fd770000 { | |
| reg = <0x00 0xfd770000 0x00 0x2800000>; | |
| phandle = <0x1a>; | |
| }; | |
| }; | |
| }; | |
| fragment@12 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| sprd,hw-channels = <0x02 0x18cc 0x03 0x18cc 0x0d 0x1854 0x0f 0x1874 0x11 0x1844 0x13 0x1844 0x15 0x1864 0x1e 0x1820 0x20 0x197c 0x21 0x1988 0x23 0x19b8 0x27 0x19ac>; | |
| }; | |
| }; | |
| fragment@13 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| regulator-always-on; | |
| }; | |
| }; | |
| fragment@14 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| vdd-supply = <0xffffffff>; | |
| extcon = <0xffffffff>; | |
| status = "okay"; | |
| usb-switch-gpio = <0xffffffff 0x72 0x00>; | |
| otg-ctrl-gpio = <0xffffffff 0x60 0x00>; | |
| }; | |
| }; | |
| fragment@15 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| extcon = <0xffffffff 0xffffffff>; | |
| status = "okay"; | |
| vbus-supply = <0x09>; | |
| }; | |
| }; | |
| fragment@16 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| monitored-battery = <0x02>; | |
| sprd,calib-resistance-micro-ohms = <0x2710>; | |
| sprd,comp-resistance-mohm = <0x14>; | |
| fgu-capacity-track; | |
| phys = <0xffffffff>; | |
| }; | |
| }; | |
| fragment@17 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| cd-gpios = <0xffffffff 0x13 0x01>; | |
| sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>; | |
| sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>; | |
| sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>; | |
| sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>; | |
| vmmc-supply = <0xffffffff>; | |
| vqmmc-supply = <0xffffffff>; | |
| sd-uhs-sdr104; | |
| sd-uhs-sdr50; | |
| sprd,name = "sdio_sd"; | |
| status = "okay"; | |
| }; | |
| }; | |
| fragment@18 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x76 0x69 0x69>; | |
| sprd,phy-delay-sd-uhs-sdr50 = <0x7f 0xf7 0xf5 0xf5>; | |
| sd-uhs-sdr104; | |
| sd-uhs-sdr50; | |
| }; | |
| }; | |
| fragment@19 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| sprd,phy-delay-mmc-hs400es = <0x40 0x7f 0x2d 0x2d>; | |
| sprd,phy-delay-mmc-hs400 = <0x3f 0xdf 0x2f 0x2f>; | |
| sprd,phy-delay-mmc-hs200 = <0x7f 0xde 0xd4 0xd4>; | |
| sprd,phy-delay-mmc-ddr52 = <0x3e 0x37 0x24 0x24>; | |
| sprd,phy-delay-mmc-highspeed = <0x60 0xb7 0x34 0x34>; | |
| vmmc-supply = <0xffffffff>; | |
| voltage-ranges = <0xbb8 0xbb8>; | |
| bus-width = <0x08>; | |
| non-removable; | |
| cap-mmc-hw-reset; | |
| mmc-hs400-enhanced-strobe; | |
| mmc-hs400-1_8v; | |
| mmc-hs200-1_8v; | |
| mmc-ddr-1_8v; | |
| no-sdio; | |
| no-sd; | |
| status = "okay"; | |
| }; | |
| }; | |
| fragment@20 { | |
| target = <0xffffffff>; | |
| __overlay__ { | |
| pinctrl-names = "gpio_121\0gpio_122\0gpio_123\0gpio_124\0gpio_125\0gpio_126\0gpio_144\0gpio_145\0gpio_146\0gpio_147\0gpio_16"; | |
| pinctrl-0 = <0x0a>; | |
| pinctrl-1 = <0x0b>; | |
| pinctrl-2 = <0x0c>; | |
| pinctrl-3 = <0x03>; | |
| pinctrl-4 = <0x0d>; | |
| pinctrl-5 = <0x0e>; | |
| pinctrl-6 = <0x0f>; | |
| pinctrl-7 = <0x10>; | |
| pinctrl-8 = <0x11>; | |
| pinctrl-9 = <0x12>; | |
| pinctrl-10 = <0x13>; | |
| keyout0 { | |
| pins = "SHARKL5PRO_KEYOUT0"; | |
| function = "func4"; | |
| phandle = <0x0a>; | |
| }; | |
| keyout1 { | |
| pins = "SHARKL5PRO_KEYOUT1"; | |
| function = "func4"; | |
| phandle = <0x0b>; | |
| }; | |
| keyout2 { | |
| pins = "SHARKL5PRO_KEYOUT2"; | |
| function = "func4"; | |
| phandle = <0x0c>; | |
| }; | |
| keyin0 { | |
| pins = "SHARKL5PRO_KEYIN0"; | |
| function = "func4"; | |
| phandle = <0x03>; | |
| }; | |
| keyin1 { | |
| pins = "SHARKL5PRO_KEYIN1"; | |
| function = "func4"; | |
| phandle = <0x0d>; | |
| }; | |
| keyin2 { | |
| pins = "SHARKL5PRO_KEYIN2"; | |
| function = "func4"; | |
| phandle = <0x0e>; | |
| }; | |
| extint0 { | |
| pins = "SHARKL5PRO_EXTINT0"; | |
| function = "func4"; | |
| phandle = <0x0f>; | |
| }; | |
| extint1 { | |
| pins = "SHARKL5PRO_EXTINT1"; | |
| function = "func4"; | |
| phandle = <0x10>; | |
| }; | |
| scl3 { | |
| pins = "SHARKL5PRO_SCL3"; | |
| function = "func4"; | |
| phandle = <0x12>; | |
| }; | |
| sda3 { | |
| pins = "SHARKL5PRO_SDA3"; | |
| function = "func4"; | |
| phandle = <0x11>; | |
| }; | |
| rffe1_sda { | |
| pins = "SHARKL5PRO_RFFE1_SDA"; | |
| function = "func4"; | |
| phandle = <0x13>; | |
| }; | |
| }; | |
| }; | |
| __symbols__ { | |
| lcd_d53e6ea8966_mipi_2lane_960X544 = "/fragment/__overlay__/lcds/lcd_d53e6ea8966_mipi_2lane_960X544"; | |
| d53e6ea8966_truly_timing0 = "/fragment/__overlay__/lcds/lcd_d53e6ea8966_mipi_2lane_960X544/display-timings/timing0"; | |
| d53e6ea8966_truly_timing1 = "/fragment/__overlay__/lcds/lcd_d53e6ea8966_mipi_2lane_960X544/display-timings/timing1"; | |
| dtbo = "/fragment/__overlay__/dtbo"; | |
| pwm_backlight = "/fragment/__overlay__/sprd_backlight"; | |
| bat = "/fragment/__overlay__/battery"; | |
| tboard_thermistor = "/fragment/__overlay__/thermal-sensor"; | |
| sprd_marlin3 = "/fragment/__overlay__/sprd-marlin3"; | |
| bd_thmzone = "/fragment@0/__overlay__/board-thmzone"; | |
| aw32257 = "/fragment@5/__overlay__/charger@6a"; | |
| vddvbus = "/fragment@5/__overlay__/charger@6a/otg-vbus"; | |
| logo_reserved = "/fragment@11/__overlay__/logobuffer@9e000000"; | |
| widevine_reserved = "/fragment@11/__overlay__/widevine@e3800000"; | |
| fd_reserved = "/fragment@11/__overlay__/faceid-mem@fd270000"; | |
| vdsp_reserved = "/fragment@11/__overlay__/vdsp-mem@fd770000"; | |
| gpio_121 = "/fragment@20/__overlay__/keyout0"; | |
| gpio_122 = "/fragment@20/__overlay__/keyout1"; | |
| gpio_123 = "/fragment@20/__overlay__/keyout2"; | |
| gpio_124 = "/fragment@20/__overlay__/keyin0"; | |
| gpio_125 = "/fragment@20/__overlay__/keyin1"; | |
| gpio_126 = "/fragment@20/__overlay__/keyin2"; | |
| gpio_144 = "/fragment@20/__overlay__/extint0"; | |
| gpio_145 = "/fragment@20/__overlay__/extint1"; | |
| gpio_147 = "/fragment@20/__overlay__/scl3"; | |
| gpio_146 = "/fragment@20/__overlay__/sda3"; | |
| gpio_16 = "/fragment@20/__overlay__/rffe1_sda"; | |
| }; | |
| __fixups__ { | |
| pwms = "/fragment/__overlay__/sprd_backlight:pwms:0\0/fragment/__overlay__/pwm-fan:pwms:0"; | |
| pmic_typec = "/fragment/__overlay__/charger-manager/regulator@0/cable@0:extcon:0\0/fragment@15/__overlay__:extcon:4"; | |
| pmic_adc = "/fragment/__overlay__/thermal-sensor:io-channels:0\0/fragment/__overlay__/singleadc-joypad:io-channels:0"; | |
| pmic_eic = "/fragment/__overlay__/gpio-keys/key-power:gpios:0\0/fragment/__overlay__/gpio-keys/key-volumedown:gpios:0"; | |
| ap_gpio = "/fragment/__overlay__/gpio-keys/key-volumeup:gpios:0\0/fragment/__overlay__/singleadc-joypad:amux-a-gpios:0\0/fragment/__overlay__/singleadc-joypad:amux-b-gpios:0\0/fragment/__overlay__/singleadc-joypad:amux-en-gpios:0\0/fragment/__overlay__/singleadc-joypad:adc-power-ctl1:0\0/fragment/__overlay__/singleadc-joypad:adc-power-ctl2:0\0/fragment/__overlay__/singleadc-joypad:adc-power-ctl3:0\0/fragment/__overlay__/singleadc-joypad:adc-power-ctl4:0\0/fragment/__overlay__/singleadc-joypad:adc-power-en-gpios:0\0/fragment/__overlay__/singleadc-joypad:fan-power-en-gpios:0\0/fragment/__overlay__/singleadc-joypad/key-resetn:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw1:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw2:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw3:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw4:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw5:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw6:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw7:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw8:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw9:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw10:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw11:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw12:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw13:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw14:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw15:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw16:gpios:0\0/fragment/__overlay__/singleadc-joypad/sw17:gpios:0\0/fragment/__overlay__/sprd-marlin3:m2-wakeup-ap-gpios:0\0/fragment/__overlay__/sprd-marlin3:reset-gpios:0\0/fragment/__overlay__/sprd-marlin3:enable-gpios:0\0/fragment/__overlay__/sprd-marlin3:m2-to-ap-irq-gpios:0\0/fragment@4/__overlay__/touchscreen@14:irq-gpios:0\0/fragment@4/__overlay__/touchscreen@14:reset-gpios:0\0/fragment@8/__overlay__:reset-gpio:0\0/fragment@14/__overlay__:usb-switch-gpio:0\0/fragment@14/__overlay__:otg-ctrl-gpio:0"; | |
| vddldo1 = "/fragment/__overlay__/singleadc-joypad:vdd-supply:0\0/fragment@4/__overlay__/touchscreen@14:vdd-supply:0"; | |
| uid_start = "/fragment/__overlay__/sprd_uid:nvmem-cells:0"; | |
| uid_end = "/fragment/__overlay__/sprd_uid:nvmem-cells:4"; | |
| vddwcn = "/fragment/__overlay__/sprd-marlin3:avdd12-supply:0"; | |
| vddwifipa = "/fragment/__overlay__/sprd-marlin3:avdd33-supply:0"; | |
| vddsim2 = "/fragment/__overlay__/sprd-marlin3:dcxo18-supply:0"; | |
| aon_clk = "/fragment/__overlay__/sprd-marlin3:clocks:0"; | |
| ext_32k = "/fragment/__overlay__/sprd-marlin3:clocks:8"; | |
| aonapb_gate = "/fragment/__overlay__/sprd-marlin3:clocks:12"; | |
| sdio1 = "/fragment/__overlay__/sprd-marlin3:extcon:0\0/fragment/__overlay__/sprd-marlin3:sdhci-name:0\0/fragment@18:target:0"; | |
| thm_zone = "/fragment@0:target:0"; | |
| ion = "/fragment@1:target:0"; | |
| i2c0 = "/fragment@2:target:0"; | |
| i2c1 = "/fragment@3:target:0"; | |
| i2c3 = "/fragment@4:target:0"; | |
| i2c4 = "/fragment@5:target:0"; | |
| hsphy = "/fragment@5/__overlay__/charger@6a:phys:0\0/fragment@14:target:0\0/fragment@16/__overlay__:phys:0"; | |
| extcon_gpio = "/fragment@5/__overlay__/charger@6a:extcon:0\0/fragment@14/__overlay__:extcon:0\0/fragment@15/__overlay__:extcon:0"; | |
| aon_i2c0 = "/fragment@6:target:0"; | |
| ddr_dfs = "/fragment@7:target:0"; | |
| panel = "/fragment@8:target:0"; | |
| dpu = "/fragment@9:target:0"; | |
| chosen = "/fragment@10:target:0"; | |
| reserved_memory = "/fragment@11:target:0"; | |
| adi_bus = "/fragment@12:target:0"; | |
| vddldo0 = "/fragment@13:target:0"; | |
| vddusb33 = "/fragment@14/__overlay__:vdd-supply:0"; | |
| usb = "/fragment@15:target:0"; | |
| pmic_fgu = "/fragment@16:target:0"; | |
| sdio0 = "/fragment@17:target:0"; | |
| eic_sync = "/fragment@17/__overlay__:cd-gpios:0"; | |
| vddsdcore = "/fragment@17/__overlay__:vmmc-supply:0"; | |
| vddsdio = "/fragment@17/__overlay__:vqmmc-supply:0"; | |
| sdio3 = "/fragment@19:target:0"; | |
| vddemmccore = "/fragment@19/__overlay__:vmmc-supply:0"; | |
| pin_controller = "/fragment@20:target:0"; | |
| }; | |
| __local_fixups__ { | |
| fragment { | |
| __overlay__ { | |
| lcds { | |
| lcd_d53e6ea8966_mipi_2lane_960X544 { | |
| display-timings { | |
| native-mode = <0x00>; | |
| }; | |
| }; | |
| }; | |
| charger-manager { | |
| monitored-battery = <0x00>; | |
| }; | |
| gpio-keys { | |
| pinctrl-0 = <0x00>; | |
| }; | |
| }; | |
| }; | |
| fragment@0 { | |
| __overlay__ { | |
| board-thmzone { | |
| thermal-sensors = <0x00>; | |
| }; | |
| }; | |
| }; | |
| fragment@1 { | |
| __overlay__ { | |
| heap@1 { | |
| memory-region = <0x00>; | |
| }; | |
| heap@2 { | |
| memory-region = <0x00>; | |
| }; | |
| }; | |
| }; | |
| fragment@5 { | |
| __overlay__ { | |
| charger@6a { | |
| monitored-battery = <0x00>; | |
| }; | |
| }; | |
| }; | |
| fragment@8 { | |
| __overlay__ { | |
| sprd,backlight = <0x00>; | |
| }; | |
| }; | |
| fragment@9 { | |
| __overlay__ { | |
| sprd,backlight = <0x00>; | |
| sprd,logo-memory = <0x00>; | |
| }; | |
| }; | |
| fragment@15 { | |
| __overlay__ { | |
| vbus-supply = <0x00>; | |
| }; | |
| }; | |
| fragment@16 { | |
| __overlay__ { | |
| monitored-battery = <0x00>; | |
| }; | |
| }; | |
| fragment@20 { | |
| __overlay__ { | |
| pinctrl-0 = <0x00>; | |
| pinctrl-1 = <0x00>; | |
| pinctrl-2 = <0x00>; | |
| pinctrl-3 = <0x00>; | |
| pinctrl-4 = <0x00>; | |
| pinctrl-5 = <0x00>; | |
| pinctrl-6 = <0x00>; | |
| pinctrl-7 = <0x00>; | |
| pinctrl-8 = <0x00>; | |
| pinctrl-9 = <0x00>; | |
| pinctrl-10 = <0x00>; | |
| }; | |
| }; | |
| }; | |
| }; |
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| /dts-v1/; | |
| / { | |
| interrupt-parent = <0x01>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| cpuinfo_hardware = "Unisoc ums512"; | |
| soc-module = "UMS512"; | |
| soc-manufacturer = "Spreadtrum"; | |
| model = "Spreadtrum UMS512-1H10 SoC"; | |
| compatible = "sprd,ums512"; | |
| sprd,sc-id = "ums512 1000 1000"; | |
| qos { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qos@0 { | |
| reg = <0x00>; | |
| awqos-high = [0a]; | |
| awqos-low = [0a]; | |
| arqos-high = [0d]; | |
| arqos-low = [0c]; | |
| arqos-threshold = [0c]; | |
| awqos-threshold = [0f]; | |
| phandle = <0x20>; | |
| }; | |
| mm { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| qos@0 { | |
| reg = <0x00>; | |
| arqos = [0a]; | |
| awqos-high = [0d]; | |
| awqos-low = [0c]; | |
| phandle = <0x1a>; | |
| }; | |
| qos@1 { | |
| reg = <0x01>; | |
| awqos-high = [07]; | |
| awqos-low = [06]; | |
| arqos-high = [07]; | |
| arqos-low = [06]; | |
| phandle = <0x17>; | |
| }; | |
| qos@2 { | |
| reg = <0x02>; | |
| awrqos = [01]; | |
| phandle = <0x1d>; | |
| }; | |
| qos@3 { | |
| reg = <0x03>; | |
| arqos = [01]; | |
| awqos = [01]; | |
| phandle = <0xd5>; | |
| }; | |
| qos@4 { | |
| reg = <0x04>; | |
| arqos-high = [07]; | |
| arqos-low = [01]; | |
| awqos = [01]; | |
| phandle = <0xd6>; | |
| }; | |
| qos@5 { | |
| reg = <0x05>; | |
| arqos-threshold = [06]; | |
| awqos-threshold = [06]; | |
| phandle = <0x14>; | |
| }; | |
| }; | |
| }; | |
| aliases { | |
| i2c0 = "/soc/apb@70000000/i2c@300000"; | |
| i2c1 = "/soc/apb@70000000/i2c@400000"; | |
| i2c2 = "/soc/apb@70000000/i2c@500000"; | |
| i2c3 = "/soc/apb@70000000/i2c@600000"; | |
| i2c4 = "/soc/apb@70000000/i2c@700000"; | |
| i2c5 = "/soc/aon/i2c@32060000"; | |
| spi0 = "/soc/apb@70000000/spi@800000"; | |
| spi1 = "/soc/apb@70000000/spi@900000"; | |
| spi2 = "/soc/apb@70000000/spi@a00000"; | |
| spi3 = "/soc/apb@70000000/spi@b00000"; | |
| spi4 = "/soc/aon/spi@32100000"; | |
| v2-modem0 = "/modem@0"; | |
| v2-modem1 = "/modem@1"; | |
| seth0 = "/sipc-virt/core@5/channel@7"; | |
| seth1 = "/sipc-virt/core@5/channel@8"; | |
| seth2 = "/sipc-virt/core@5/channel@9"; | |
| seth3 = "/sipc-virt/core@5/channel@18"; | |
| seth4 = "/sipc-virt/core@5/channel@19"; | |
| seth5 = "/sipc-virt/core@5/channel@20"; | |
| seth6 = "/sipc-virt/core@5/channel@24"; | |
| seth7 = "/sipc-virt/core@5/channel@25"; | |
| seth8 = "/sipc-virt/core@5/channel@26"; | |
| seth9 = "/sipc-virt/core@5/channel@27"; | |
| seth10 = "/sipc-virt/core@5/channel@28"; | |
| seth11 = "/sipc-virt/core@5/channel@29"; | |
| seth12 = "/sipc-virt/core@5/channel@30"; | |
| seth13 = "/sipc-virt/core@5/channel@31"; | |
| cooling-device0 = "/cooling-devices/cluster0-cooling"; | |
| cooling-device1 = "/cooling-devices/cluster1-cooling"; | |
| gpu-cooling0 = "/gpu-cooling-devices/gpu-cooling0"; | |
| thm-sensor0 = "/virtual-sensor@0"; | |
| serial0 = "/soc/apb@70000000/serial@0"; | |
| serial1 = "/soc/apb@70000000/serial@100000"; | |
| }; | |
| soc { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| phandle = <0xd7>; | |
| syscon@20100000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x20100000 0x00 0x4000>; | |
| phandle = <0x09>; | |
| }; | |
| syscon@31050000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x31050000 0x00 0x9000>; | |
| phandle = <0x76>; | |
| }; | |
| syscon@322a0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x322a0000 0x00 0x8000>; | |
| phandle = <0x4e>; | |
| }; | |
| syscon@32310000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32310000 0x00 0x1000>; | |
| phandle = <0xab>; | |
| }; | |
| syscon@32320000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32320000 0x00 0x1000>; | |
| phandle = <0xac>; | |
| }; | |
| syscon@32330000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32330000 0x00 0x1000>; | |
| phandle = <0xad>; | |
| }; | |
| syscon@32340000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32340000 0x00 0x1000>; | |
| phandle = <0xae>; | |
| }; | |
| syscon@32350000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32350000 0x00 0x1000>; | |
| phandle = <0xaf>; | |
| }; | |
| syscon@32360000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32360000 0x00 0x1000>; | |
| phandle = <0xb0>; | |
| }; | |
| syscon@32390000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x32390000 0x00 0x3000>; | |
| phandle = <0x79>; | |
| }; | |
| syscon@323b0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x323b0000 0x00 0x3000>; | |
| phandle = <0x65>; | |
| }; | |
| syscon@323c0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x323c0000 0x00 0x3000>; | |
| phandle = <0x64>; | |
| }; | |
| syscon@323e0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x323e0000 0x00 0x3000>; | |
| phandle = <0x7a>; | |
| }; | |
| syscon@323f0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x323f0000 0x00 0x3000>; | |
| phandle = <0x15>; | |
| }; | |
| syscon@327d0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x327d0000 0x00 0x3000>; | |
| phandle = <0x0b>; | |
| }; | |
| syscon@327e0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x327e0000 0x00 0x3000>; | |
| phandle = <0x02>; | |
| }; | |
| vsp-power-domain { | |
| compatible = "sprd,vsp-pd"; | |
| pmu-vsp-force-shutdown-syscon = <0x02 0x18 0x2000000>; | |
| pmu-vsp-auto-shutdown-syscon = <0x02 0x18 0x1000000>; | |
| pmu-pwr-status-syscon = <0x02 0xbc 0xff00>; | |
| #power-domain-cells = <0x00>; | |
| status = "okay"; | |
| phandle = <0x28>; | |
| }; | |
| syscon@3350d000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x3350d000 0x00 0x1000>; | |
| phandle = <0x7b>; | |
| }; | |
| syscon@335e0000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x335e0000 0x00 0x1000>; | |
| phandle = <0x69>; | |
| }; | |
| syscon@60100000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x60100000 0x00 0x3000>; | |
| phandle = <0x0c>; | |
| }; | |
| syscon@60110000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x60110000 0x00 0x3000>; | |
| phandle = <0x0d>; | |
| }; | |
| syscon@62200000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x62200000 0x00 0x3000>; | |
| phandle = <0x11>; | |
| }; | |
| apb@70000000 { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x00 0x70000000 0x10000000>; | |
| serial@0 { | |
| compatible = "sprd,ums512-uart\0sprd,sc9836-uart"; | |
| reg = <0x00 0x100>; | |
| interrupts = <0x00 0x02 0x04>; | |
| source-base = <0x20200028>; | |
| clock-frequency = <0x00>; | |
| uart-eb-syscon = <0x03 0x00 0x4000>; | |
| clocks = <0x04>; | |
| status = "okay"; | |
| phandle = <0xd8>; | |
| }; | |
| serial@100000 { | |
| compatible = "sprd,ums512-uart\0sprd,sc9836-uart"; | |
| reg = <0x100000 0x100>; | |
| interrupts = <0x00 0x03 0x04>; | |
| source-base = <0x2020002c>; | |
| clock-frequency = <0x00>; | |
| uart-eb-syscon = <0x03 0x00 0x8000>; | |
| clocks = <0x04>; | |
| status = "okay"; | |
| phandle = <0xd9>; | |
| }; | |
| i2c@300000 { | |
| compatible = "sprd,ums512-i2c\0sprd,sc9860-i2c"; | |
| reg = <0x300000 0x100>; | |
| interrupts = <0x00 0x0b 0x04>; | |
| clock-frequency = <0x61a80>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0i2c\0source"; | |
| clocks = <0x05 0x09 0x06 0x05 0x04>; | |
| phandle = <0xda>; | |
| }; | |
| i2c@400000 { | |
| compatible = "sprd,ums512-i2c\0sprd,sc9860-i2c"; | |
| reg = <0x400000 0x100>; | |
| interrupts = <0x00 0x0c 0x04>; | |
| clock-frequency = <0x61a80>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0i2c\0source"; | |
| clocks = <0x05 0x0a 0x06 0x06 0x04>; | |
| phandle = <0xdb>; | |
| }; | |
| i2c@500000 { | |
| compatible = "sprd,ums512-i2c\0sprd,sc9860-i2c"; | |
| reg = <0x500000 0x100>; | |
| interrupts = <0x00 0x0d 0x04>; | |
| clock-frequency = <0x61a80>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0i2c\0source"; | |
| clocks = <0x05 0x0b 0x06 0x07 0x04>; | |
| phandle = <0xdc>; | |
| }; | |
| i2c@600000 { | |
| compatible = "sprd,ums512-i2c\0sprd,sc9860-i2c"; | |
| reg = <0x600000 0x100>; | |
| interrupts = <0x00 0x0e 0x04>; | |
| clock-frequency = <0x61a80>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0i2c\0source"; | |
| clocks = <0x05 0x0c 0x06 0x08 0x04>; | |
| phandle = <0xdd>; | |
| }; | |
| i2c@700000 { | |
| compatible = "sprd,ums512-i2c\0sprd,sc9860-i2c"; | |
| reg = <0x700000 0x100>; | |
| interrupts = <0x00 0x0f 0x04>; | |
| clock-frequency = <0x61a80>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "okay"; | |
| clock-names = "enable\0i2c\0source"; | |
| clocks = <0x05 0x0d 0x06 0x09 0x04>; | |
| phandle = <0xde>; | |
| }; | |
| spi@800000 { | |
| compatible = "sprd,ums512-spi\0sprd,sc9860-spi"; | |
| reg = <0x800000 0x1000>; | |
| interrupts = <0x00 0x05 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "okay"; | |
| clock-names = "enable\0spi\0source"; | |
| clocks = <0x05 0x05 0x06 0x0a 0x07 0x03>; | |
| phandle = <0xdf>; | |
| }; | |
| spi@900000 { | |
| compatible = "sprd,ums512-spi\0sprd,sc9860-spi"; | |
| reg = <0x900000 0x1000>; | |
| interrupts = <0x00 0x06 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0spi\0source"; | |
| clocks = <0x05 0x06 0x06 0x0b 0x07 0x03>; | |
| phandle = <0xe0>; | |
| }; | |
| spi@a00000 { | |
| compatible = "sprd,ums512-spi\0sprd,sc9860-spi"; | |
| reg = <0xa00000 0x1000>; | |
| interrupts = <0x00 0x07 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0spi\0source"; | |
| clocks = <0x05 0x07 0x06 0x0c 0x07 0x03>; | |
| phandle = <0xe1>; | |
| }; | |
| spi@b00000 { | |
| compatible = "sprd,ums512-spi\0sprd,sc9860-spi"; | |
| reg = <0xb00000 0x1000>; | |
| interrupts = <0x00 0x08 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| clock-names = "enable\0spi\0source"; | |
| clocks = <0x05 0x08 0x06 0x0d 0x07 0x03>; | |
| phandle = <0xe2>; | |
| }; | |
| apsys-dvfs@1700000 { | |
| compatible = "sprd,hwdvfs-apsys-sharkl5pro"; | |
| reg = <0x1700000 0x15c>; | |
| sprd,ap-dvfs-up-window = <0x40>; | |
| sprd,ap-dvfs-down-window = <0x80>; | |
| phandle = <0xe3>; | |
| }; | |
| }; | |
| syscon@71000000 { | |
| compatible = "sprd,ums512-glbregs\0syscon"; | |
| reg = <0x00 0x71000000 0x00 0x3000>; | |
| phandle = <0x03>; | |
| }; | |
| ap-ahb { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| dma-controller@20000000 { | |
| compatible = "sprd,sharkl5pro-dma\0sprd,sc9860-dma"; | |
| reg = <0x00 0x20000000 0x00 0x4000>; | |
| interrupts = <0x00 0x18 0x04>; | |
| #dma-cells = <0x01>; | |
| #dma-channels = <0x1c>; | |
| clock-names = "enable"; | |
| clocks = <0x08 0x04>; | |
| phandle = <0xe4>; | |
| }; | |
| vdsp@20900000 { | |
| compatible = "sprd,sharkl5pro-vdsp"; | |
| reg = <0x00 0x20900000 0x00 0x10000>; | |
| sprd,syscon-ap-ahb = <0x09>; | |
| sprd,syscon-pmu = <0x02>; | |
| clock-names = "vdsp_clk_set\0vdsp_clk_512"; | |
| clocks = <0x06 0x1c 0x07 0x08>; | |
| iommu_names = "unisoc,iommuvau-epp-l5p\0unisoc,iommuvau-edp-l5p\0unisoc,iommuvau-idma-l5p\0unisoc,iommuvau-vdma-l5p"; | |
| queue-priority = <0x07 0x08 0x09>; | |
| device-irq = <0x00 0x04 0x01>; | |
| device-irq-host-offset = <0x00>; | |
| device-irq-mode = <0x01>; | |
| host-irq = <0x08 0x00>; | |
| host-irq-mode = <0x01>; | |
| interrupts = <0x00 0xa9 0x04>; | |
| firmware-name = "vdsp_firmware.bin"; | |
| status = "okay"; | |
| phandle = <0xe5>; | |
| }; | |
| }; | |
| mm { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| gpu@60000000 { | |
| compatible = "sprd,mali-gondul"; | |
| reg = <0x00 0x60000000 0x00 0x100000>; | |
| gpu-supply = <0x0a>; | |
| system-coherency = <0x1f>; | |
| top_force_shutdown = <0x02 0x30 0x2000000>; | |
| mem_repaired_flag = <0x0b 0x83c 0xffffffff>; | |
| gpu_qos_sel = <0x0c 0x10 0x10000>; | |
| gpu_qos = <0x0c 0x10 0xffff>; | |
| dvfs_index_cfg = <0x0d 0x8c 0x07>; | |
| sw_dvfs_ctrl = <0x0d 0x20 0x171>; | |
| freq_upd_cfg = <0x0d 0xa4 0x03>; | |
| core_index0_map = <0x0d 0x48 0x1c000>; | |
| core_index1_map = <0x0d 0x4c 0x1c000>; | |
| core_index2_map = <0x0d 0x50 0x1c000>; | |
| core_index3_map = <0x0d 0x54 0x1c000>; | |
| core_index4_map = <0x0d 0x58 0x1c000>; | |
| core_index5_map = <0x0d 0x5c 0x1c000>; | |
| core_index6_map = <0x0d 0x60 0x1c000>; | |
| core_index7_map = <0x0d 0x64 0x1c000>; | |
| interrupts = <0x00 0x3c 0x04 0x00 0x3c 0x04 0x00 0x3c 0x04>; | |
| interrupt-names = "JOB\0MMU\0GPU"; | |
| nvmem-cells = <0x0e>; | |
| nvmem-cell-names = "cpu_flag"; | |
| operating-points = <0x5dc00 0xaae60 0x7d000 0xb71b0 0x96000 0xb71b0 0xbb800 0xc3500 0xcf850 0xc3500>; | |
| sprd,dvfs-lists = <0x5dc00 0xaae60 0x04 0x01 0x7d000 0xb71b0 0x05 0x01 0x96000 0xb71b0 0x06 0x01 0xbb800 0xc3500 0x07 0x01 0xcf850 0xc3500 0x08 0x01>; | |
| sprd,dvfs-default = <0x00>; | |
| sprd,dvfs-scene-extreme = <0x03>; | |
| sprd,dvfs-scene-high = <0x02>; | |
| sprd,dvfs-scene-medium = <0x01>; | |
| sprd,dvfs-scene-low = <0x00>; | |
| sprd,dvfs-range-max = <0x04>; | |
| sprd,dvfs-range-min = <0x00>; | |
| clocks = <0x0f 0x08 0x10 0x00 0x10 0x02 0x10 0x04 0x07 0x02 0x07 0x08 0x07 0x16 0x07 0x01 0x07 0x1d>; | |
| phandle = <0xe6>; | |
| }; | |
| power-domain@327e0024 { | |
| compatible = "sprd,sharkl5pro-camsys-domain"; | |
| force-shutdown = <0x02 0x24 0x2000000>; | |
| shutdown-en = <0x02 0x24 0x1000000>; | |
| power-state = <0x02 0x10c 0xff0000>; | |
| qos-ar = <0x11 0x0c 0xf0>; | |
| qos-aw = <0x11 0x0c 0x0f>; | |
| aon-apb-mm-eb = <0x0b 0x00 0x200>; | |
| clock-names = "clk_mm_eb\0clk_mm_ahb_eb\0clk_mm_ahb\0clk_mm_ahb_parent\0clk_mm_mtx\0clk_mm_mtx_parent\0clk_isppll"; | |
| clocks = <0x0f 0x07 0x12 0x07 0x13 0x00 0x07 0x0f 0x13 0x01 0x07 0x08 0x07 0x1b>; | |
| mm_qos_threshold = <0x14>; | |
| #power-domain-cells = <0x00>; | |
| status = "okay"; | |
| phandle = <0x1b>; | |
| }; | |
| mipi-csi-phy0 { | |
| compatible = "sprd,mipi-csi-phy"; | |
| sprd,phyid = <0x00>; | |
| sprd,phyname = "4lane"; | |
| status = "disabled"; | |
| phandle = <0xe7>; | |
| }; | |
| mipi-csi-phy1 { | |
| compatible = "sprd,mipi-csi-phy"; | |
| sprd,phyid = <0x01>; | |
| sprd,phyname = "2p2"; | |
| status = "disabled"; | |
| phandle = <0xe8>; | |
| }; | |
| mipi-csi-phy1-m { | |
| compatible = "sprd,mipi-csi-phy"; | |
| sprd,phyid = <0x03>; | |
| sprd,phyname = "2p2_m"; | |
| status = "disabled"; | |
| phandle = <0xe9>; | |
| }; | |
| mipi-csi-phy1-s { | |
| compatible = "sprd,mipi-csi-phy"; | |
| sprd,phyid = <0x04>; | |
| sprd,phyname = "2p2_s"; | |
| status = "disabled"; | |
| phandle = <0xea>; | |
| }; | |
| mipi-csi-phy2 { | |
| compatible = "sprd,mipi-csi-phy"; | |
| sprd,phyid = <0x02>; | |
| sprd,phyname = "2lane"; | |
| status = "disabled"; | |
| phandle = <0xeb>; | |
| }; | |
| csi00@62300000 { | |
| compatible = "sprd,csi-controller"; | |
| reg = <0x00 0x62300000 0x00 0x1000>; | |
| interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04 0x00 0x30 0x04>; | |
| clock-names = "clk_mipi_csi_gate_eb\0clk_csi_eb\0mipi_csi_src_eb"; | |
| clocks = <0x12 0x10 0x12 0x06 0x13 0x0b>; | |
| sprd,aon-apb-syscon = <0x0b>; | |
| sprd,cam-ahb-syscon = <0x11>; | |
| sprd,anlg_phy_g10_controller = <0x15>; | |
| sprd,csi-id = <0x00>; | |
| sprd,dcam-id = <0x00>; | |
| sprd,ip-version = <0x200>; | |
| status = "okay"; | |
| phandle = <0xec>; | |
| }; | |
| csi01@62400000 { | |
| compatible = "sprd,csi-controller"; | |
| reg = <0x00 0x62400000 0x00 0x1000>; | |
| interrupts = <0x00 0x31 0x04 0x00 0x32 0x04 0x00 0x33 0x04 0x00 0x34 0x04>; | |
| clock-names = "clk_mipi_csi_gate_eb\0clk_csi_eb\0mipi_csi_src_eb"; | |
| clocks = <0x12 0x0f 0x12 0x05 0x13 0x0c>; | |
| sprd,aon-apb-syscon = <0x0b>; | |
| sprd,cam-ahb-syscon = <0x11>; | |
| sprd,anlg_phy_g10_controller = <0x15>; | |
| sprd,csi-id = <0x01>; | |
| sprd,dcam-id = <0x01>; | |
| sprd,ip-version = <0x200>; | |
| status = "okay"; | |
| phandle = <0xed>; | |
| }; | |
| csi02@62500000 { | |
| compatible = "sprd,csi-controller"; | |
| reg = <0x00 0x62500000 0x00 0x1000>; | |
| interrupts = <0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x37 0x04 0x00 0x38 0x04>; | |
| clock-names = "clk_mipi_csi_gate_eb\0clk_csi_eb\0mipi_csi_src_eb"; | |
| clocks = <0x12 0x0e 0x12 0x04 0x13 0x0d>; | |
| sprd,aon-apb-syscon = <0x0b>; | |
| sprd,cam-ahb-syscon = <0x11>; | |
| sprd,anlg_phy_g10_controller = <0x15>; | |
| sprd,csi-id = <0x02>; | |
| sprd,dcam-id = <0x02>; | |
| sprd,ip-version = <0x200>; | |
| status = "okay"; | |
| phandle = <0xee>; | |
| }; | |
| isp@62000000 { | |
| compatible = "sprd,isp"; | |
| reg = <0x00 0x62000000 0x00 0x100000>; | |
| interrupts = <0x00 0x2b 0x04 0x00 0x2c 0x04>; | |
| interrupts_name = "ispch0\0ispch1"; | |
| clock-names = "isp_eb\0isp_axi_eb\0isp_clk\0isp_clk_256m\0isp_clk_307m2\0isp_clk_384m\0isp_clk_468m\0isp_clk_512m\0isp_clk_parent"; | |
| clocks = <0x12 0x03 0x12 0x08 0x13 0x0a 0x07 0x09 0x07 0x0c 0x07 0x02 0x07 0x1b 0x07 0x08 0x07 0x08>; | |
| reset = <0x11 0x04 0x400>; | |
| isp_ahb_reset = <0x11 0x04 0x1000>; | |
| isp_vau_reset = <0x11 0x04 0x800>; | |
| isp_enable = <0x11 0x00 0x08>; | |
| sprd,cam-ahb-syscon = <0x11>; | |
| sprd,isp-count = <0x01>; | |
| iommus = <0x16>; | |
| isp_qos = <0x17>; | |
| status = "okay"; | |
| phandle = <0x18>; | |
| }; | |
| iommu@62000000 { | |
| compatible = "unisoc,iommuvaul5p-isp"; | |
| reg = <0x00 0x62000000 0x00 0xff000 0x00 0x620ff000 0x00 0x80>; | |
| iova-base = <0x40000000>; | |
| iova-size = <0x20000000>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0x16>; | |
| }; | |
| dcam@62900000 { | |
| compatible = "sprd,sharkl5pro-cam"; | |
| reg = <0x00 0x62900000 0x00 0x1000 0x00 0x62901000 0x00 0x1000 0x00 0x62902000 0x00 0x1000 0x00 0x62903000 0x00 0x1000>; | |
| reg-names = "dcam0_reg\0dcam1_reg\0dcam2_reg\0axi_ctrl_reg"; | |
| interrupts = <0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3b 0x04>; | |
| interrupt-names = "dcam0\0dcam1\0dcam2"; | |
| clock-names = "dcam_eb\0dcam_clk\0dcam_clk_192m\0dcam_clk_256m\0dcam_clk_307m2\0dcam_clk_384m\0dcam_clk_468m\0dcam_clk_parent\0dcam_axi_eb\0dcam_axi_clk\0dcam_axi_clk_256m\0dcam_axi_clk_307m2\0dcam_axi_clk_384m\0dcam_axi_clk_468m\0dcam_axi_clk_parent"; | |
| clocks = <0x12 0x02 0x13 0x08 0x07 0x03 0x07 0x09 0x07 0x0c 0x07 0x02 0x07 0x1b 0x07 0x1b 0x12 0x11 0x13 0x09 0x07 0x09 0x07 0x0c 0x07 0x02 0x07 0x1b 0x07 0x1b>; | |
| dcam_all_reset = <0x11 0x04 0x800000>; | |
| dcam0_reset = <0x11 0x04 0x20>; | |
| dcam1_reset = <0x11 0x04 0x10>; | |
| dcam2_reset = <0x11 0x04 0x08>; | |
| sprd,cam-ahb-syscon = <0x11>; | |
| sprd,isp = <0x18>; | |
| sprd,dcam-count = <0x03>; | |
| sprd,dcam-superzoom = <0x02>; | |
| sprd,project-id = <0x03>; | |
| iommus = <0x19>; | |
| dcam_qos = <0x1a>; | |
| power-domains = <0x1b>; | |
| status = "okay"; | |
| phandle = <0xef>; | |
| }; | |
| iommu@62900000 { | |
| compatible = "unisoc,iommuvaul5p-dcam"; | |
| reg = <0x00 0x62900000 0x00 0xf000 0x00 0x6290f000 0x00 0x80>; | |
| iova-base = <0x40000000>; | |
| iova-size = <0x40000000>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0x19>; | |
| }; | |
| cpp@62800000 { | |
| compatible = "sprd,cpp"; | |
| reg = <0x00 0x62800000 0x00 0x1000>; | |
| interrupts = <0x00 0x29 0x04>; | |
| clock-names = "cpp_eb\0cpp_axi_eb\0cpp_clk\0cpp_clk_parent"; | |
| clocks = <0x12 0x00 0x12 0x03 0x13 0x05 0x07 0x02>; | |
| sprd,cam-ahb-syscon = <0x11>; | |
| iommus = <0x1c>; | |
| cpp_qos = <0x1d>; | |
| power-domains = <0x1b>; | |
| status = "okay"; | |
| phandle = <0xf0>; | |
| }; | |
| iommu@62800000 { | |
| compatible = "unisoc,iommuvaul5p-cpp"; | |
| reg = <0x00 0x62800000 0x00 0x200 0x00 0x62800200 0x00 0x80>; | |
| iova-base = <0x40000000>; | |
| iova-size = <0x20000000>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0x1c>; | |
| }; | |
| iommu@62a00000 { | |
| compatible = "unisoc,iommuvaul5p-fd"; | |
| reg = <0x00 0x62a00000 0x00 0x200 0x00 0x62a00110 0x00 0x80>; | |
| iova-base = <0x10000000>; | |
| iova-size = <0x10000000>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0xf1>; | |
| }; | |
| jpg-codec@62700000 { | |
| compatible = "sprd,sharkl5pro-jpg"; | |
| reg = <0x00 0x62700000 0x00 0xc000>; | |
| interrupts = <0x00 0x2a 0x04>; | |
| reset-syscon = <0x11 0x04 0x02>; | |
| aon-apb-eb-syscon = <0x0b 0x00 0x200>; | |
| iommus = <0x1e>; | |
| power-domains = <0x1b>; | |
| status = "okay"; | |
| clock-names = "jpg_domain_eb\0jpg_dev_eb\0jpg_ckg_eb\0jpg_clk\0clk_src_76m8\0clk_src_128m\0clk_src_256m\0clk_src_384m"; | |
| clocks = <0x0f 0x07 0x12 0x01 0x12 0x07 0x13 0x06 0x07 0x10 0x07 0x0a 0x07 0x09 0x07 0x02>; | |
| phandle = <0xf2>; | |
| }; | |
| iommu@62700300 { | |
| compatible = "unisoc,iommuvaul5p-jpg"; | |
| reg = <0x00 0x62700300 0x00 0x80 0x00 0x62700300 0x00 0x80>; | |
| iova-base = <0x60000000>; | |
| iova-size = <0x10000000>; | |
| reg_name = "mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0x1e>; | |
| }; | |
| dpu@20300000 { | |
| compatible = "sprd,sharkl5pro-dpu"; | |
| reg = <0x00 0x20300000 0x00 0x1000>; | |
| reset-syscon = <0x09 0x04 0x02>; | |
| interrupts = <0x00 0x1b 0x04>; | |
| status = "okay"; | |
| iommus = <0x1f>; | |
| sprd,qos = <0x20>; | |
| clock-names = "clk_src_96m\0clk_src_128m\0clk_src_153m6\0clk_src_192m\0clk_src_256m\0clk_src_307m2\0clk_src_384m\0clk_dpu_core\0clk_dpu_dpi\0clk_ap_ahb_disp_eb"; | |
| clocks = <0x07 0x04 0x07 0x0a 0x07 0x0f 0x07 0x03 0x07 0x09 0x07 0x0c 0x07 0x02 0x06 0x17 0x06 0x18 0x08 0x01>; | |
| phandle = <0xf3>; | |
| port { | |
| phandle = <0xbe>; | |
| endpoint { | |
| remote-endpoint = <0x21>; | |
| phandle = <0x23>; | |
| }; | |
| }; | |
| }; | |
| gsp@20300000 { | |
| compatible = "sprd,gsp-core"; | |
| reg = <0x00 0x20300000 0x00 0x2000>; | |
| core-id = <0x00>; | |
| kcfg-num = <0x10>; | |
| interrupts = <0x00 0x1a 0x04>; | |
| iommus = <0x1f>; | |
| clock-names = "clk_dpu_core_src\0clk_dpu_core\0clk_ap_ahb_disp_eb"; | |
| clocks = <0x07 0x02 0x06 0x17 0x08 0x01>; | |
| phandle = <0xb5>; | |
| }; | |
| iommu@20300000 { | |
| compatible = "unisoc,iommuvaul5p-dispc"; | |
| reg = <0x00 0x20300000 0x00 0x800 0x00 0x20300800 0x00 0x80>; | |
| iova-base = <0x30000000>; | |
| iova-size = <0x10000000>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0x1f>; | |
| }; | |
| dsi@20400000 { | |
| compatible = "sprd,sharkl5pro-dsi-host"; | |
| reg = <0x00 0x20400000 0x00 0x1000>; | |
| reset-syscon = <0x09 0x04 0x01>; | |
| interrupts = <0x00 0x1e 0x04 0x00 0x1f 0x04>; | |
| status = "okay"; | |
| clock-names = "clk_ap_ahb_dsi_eb"; | |
| clocks = <0x08 0x00>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0xf4>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x22>; | |
| phandle = <0x26>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x23>; | |
| phandle = <0x21>; | |
| }; | |
| }; | |
| }; | |
| panel { | |
| compatible = "sprd,generic-mipi-panel"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| phandle = <0xf5>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x24>; | |
| phandle = <0x25>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| dphy { | |
| compatible = "sprd,sharkl5pro-dsi-phy"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00 0x20400000 0x00 0x1000>; | |
| enable-syscon = <0x09 0x40 0x03>; | |
| power-syscon = <0x03 0x35c 0x08>; | |
| status = "okay"; | |
| phandle = <0xf6>; | |
| ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x25>; | |
| phandle = <0x24>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x26>; | |
| phandle = <0x22>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| video-codec@20500000 { | |
| compatible = "sprd,sharkl5pro-vsp"; | |
| reg = <0x00 0x20500000 0x00 0xc000>; | |
| interrupts = <0x00 0x22 0x04>; | |
| reset-syscon = <0x09 0x04 0x2800>; | |
| vsp-domain-eb-syscon = <0x0b 0x04 0x20>; | |
| iommus = <0x27>; | |
| power-domains = <0x28>; | |
| status = "okay"; | |
| clock-names = "clk_ahb_gate_vsp_eb\0clk_src_256m\0clk_src_307m2\0clk_src_384m\0clk_vsp"; | |
| clocks = <0x08 0x02 0x07 0x09 0x07 0x0c 0x07 0x02 0x06 0x16>; | |
| phandle = <0xf7>; | |
| }; | |
| iommu@20500000 { | |
| compatible = "unisoc,iommuvaul5p-vsp"; | |
| reg = <0x00 0x20500000 0x00 0x80 0x00 0x20500000 0x00 0x80>; | |
| iova-base = <0x20000000>; | |
| iova-size = <0x10000000>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0x27>; | |
| }; | |
| iommu@20600000 { | |
| compatible = "unisoc,iommuvau-epp-l5p"; | |
| reg = <0x00 0x20600000 0x00 0x400 0x00 0x20600000 0x00 0x400>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| iova-base = <0x80000000>; | |
| iova-size = <0x20000000>; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0xf8>; | |
| }; | |
| iommu@20700000 { | |
| compatible = "unisoc,iommuvau-edp-l5p"; | |
| reg = <0x00 0x20700000 0x00 0x400 0x00 0x20700000 0x00 0x400>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| iova-base = <0x80000000>; | |
| iova-size = <0x20000000>; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0xf9>; | |
| }; | |
| iommu@20800000 { | |
| compatible = "unisoc,iommuvau-idma-l5p"; | |
| reg = <0x00 0x20800000 0x00 0x400 0x00 0x20800000 0x00 0x400>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| iova-base = <0x80000000>; | |
| iova-size = <0x20000000>; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0xfa>; | |
| }; | |
| iommu@20a00000 { | |
| compatible = "unisoc,iommuvau-vdma-l5p"; | |
| reg = <0x00 0x20a00000 0x00 0x400 0x00 0x20a00000 0x00 0x400>; | |
| reg_name = "mmu_interrupt_reg\0mmu_reg"; | |
| iova-base = <0x80000000>; | |
| iova-size = <0x20000000>; | |
| status = "okay"; | |
| #iommu-cells = <0x00>; | |
| phandle = <0xfb>; | |
| }; | |
| }; | |
| aon { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| gpio@32000000 { | |
| compatible = "sprd,sharkl5pro-eic-debounce\0sprd,sc9860-eic-debounce"; | |
| reg = <0x00 0x32020000 0x00 0x80 0x00 0x32030000 0x00 0x80 0x00 0x32230000 0x00 0x80 0x00 0x32270000 0x00 0x80>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupts = <0x00 0x48 0x04>; | |
| phandle = <0xfc>; | |
| }; | |
| gpio@32000080 { | |
| compatible = "sprd,sharkl5pro-eic-latch\0sprd,sc9860-eic-latch"; | |
| reg = <0x00 0x32020080 0x00 0x20 0x00 0x32030080 0x00 0x20 0x00 0x32230080 0x00 0x20 0x00 0x32270080 0x00 0x20>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupts = <0x00 0x48 0x04>; | |
| phandle = <0xfd>; | |
| }; | |
| gpio@320000a0 { | |
| compatible = "sprd,sharkl5pro-eic-async\0sprd,sc9860-eic-async"; | |
| reg = <0x00 0x320200a0 0x00 0x20 0x00 0x320300a0 0x00 0x20 0x00 0x322300a0 0x00 0x20 0x00 0x322700a0 0x00 0x20>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupts = <0x00 0x48 0x04>; | |
| phandle = <0xfe>; | |
| }; | |
| gpio@320000c0 { | |
| compatible = "sprd,sharkl5pro-eic-sync\0sprd,sc9860-eic-sync"; | |
| reg = <0x00 0x320200c0 0x00 0x20 0x00 0x320300c0 0x00 0x20 0x00 0x322300c0 0x00 0x20 0x00 0x322700c0 0x00 0x20>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupts = <0x00 0x48 0x04>; | |
| phandle = <0xff>; | |
| }; | |
| timer@32040000 { | |
| compatible = "sprd,sysfrt-timer"; | |
| reg = <0x00 0x32040000 0x00 0x10>; | |
| }; | |
| timer@32050000 { | |
| compatible = "sprd,sharkl5Pro-timer\0sprd,sc9860-timer"; | |
| reg = <0x00 0x32050000 0x00 0x20>; | |
| interrupts = <0x00 0x47 0x04>; | |
| clocks = <0x29>; | |
| }; | |
| timer@32050020 { | |
| compatible = "sprd,sharkl5Pro-suspend-timer\0sprd,sc9860-suspend-timer"; | |
| reg = <0x00 0x32050020 0x00 0x20>; | |
| clocks = <0x29>; | |
| }; | |
| i2c@32060000 { | |
| compatible = "sprd,sharkl5pro-hw-i2c"; | |
| reg = <0x00 0x32060000 0x00 0x1000>; | |
| interrupts = <0x00 0x44 0x04>; | |
| clock-names = "source\0enable\0i2c\0clk_hw_i2c"; | |
| clock-frequency = <0x61a80>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| status = "disabled"; | |
| phandle = <0x100>; | |
| }; | |
| gpio@32070000 { | |
| compatible = "sprd,sharkl5Pro-gpio\0sprd,sc9860-gpio"; | |
| reg = <0x00 0x32070000 0x00 0x10000>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| interrupts = <0x00 0x3d 0x04>; | |
| phandle = <0x67>; | |
| }; | |
| mailbox@320a0000 { | |
| compatible = "unisoc,mailbox"; | |
| reg = <0x00 0x320a0000 0x00 0x8000 0x00 0x320a8000 0x00 0x8000>; | |
| reg-names = "inbox\0outbox"; | |
| sprd,mailbox_clk = <0x0b 0x04 0x04>; | |
| interrupts = <0x00 0x52 0x04 0x00 0x53 0x04 0x00 0x54 0x04>; | |
| interrupt-names = "inbox\0outbox\0oob-outbox"; | |
| #mbox-cells = <0x02>; | |
| phandle = <0xa1>; | |
| }; | |
| spi@32100000 { | |
| compatible = "sprd,sharkl5pro-adi"; | |
| reg = <0x00 0x32100000 0x00 0x100000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x101>; | |
| pmic@0 { | |
| compatible = "sprd,sc2730"; | |
| reg = <0x00>; | |
| spi-max-frequency = <0x18cba80>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| interrupts = <0x00 0xad 0x04>; | |
| phandle = <0x2a>; | |
| watchdog@40 { | |
| compatible = "sprd,sc2730-wdt\0sprd,sc27xx-wdt"; | |
| reg = <0x40>; | |
| phandle = <0x102>; | |
| }; | |
| led-controller@180 { | |
| compatible = "sprd,sc2730-bltc"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x180>; | |
| led@0 { | |
| label = "blue"; | |
| reg = <0x00>; | |
| }; | |
| led@1 { | |
| label = "red"; | |
| reg = <0x01>; | |
| }; | |
| led@2 { | |
| label = "green"; | |
| reg = <0x02>; | |
| }; | |
| }; | |
| rtc@200 { | |
| compatible = "sprd,sc2731-rtc\0sprd,sc2730-rtc"; | |
| reg = <0x200>; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x01>; | |
| }; | |
| gpio@280 { | |
| compatible = "sprd,sc2731-eic\0sprd,sc2730-eic"; | |
| reg = <0x280>; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x04>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| phandle = <0x31>; | |
| }; | |
| efuse@300 { | |
| compatible = "sprd,sc2730-efuse"; | |
| reg = <0x300>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| hwlocks = <0x2b 0x0c>; | |
| calib@0 { | |
| reg = <0x24 0x02>; | |
| phandle = <0x2f>; | |
| }; | |
| calib@1 { | |
| reg = <0x26 0x02>; | |
| phandle = <0x30>; | |
| }; | |
| calib@2 { | |
| reg = <0x02 0x02>; | |
| phandle = <0x36>; | |
| }; | |
| calib@6 { | |
| reg = <0x06 0x02>; | |
| phandle = <0x35>; | |
| }; | |
| calib@1e { | |
| reg = <0x1e 0x02>; | |
| phandle = <0x37>; | |
| }; | |
| calib@3 { | |
| reg = <0x06 0x02>; | |
| phandle = <0x32>; | |
| }; | |
| calib@d1 { | |
| reg = <0x1a 0x02>; | |
| phandle = <0x2c>; | |
| }; | |
| calib@d2 { | |
| reg = <0x1a 0x02>; | |
| phandle = <0x2d>; | |
| }; | |
| calib@20 { | |
| reg = <0x20 0x02>; | |
| phandle = <0x38>; | |
| }; | |
| calib@22 { | |
| reg = <0x22 0x02>; | |
| phandle = <0x39>; | |
| }; | |
| calib@14 { | |
| reg = <0x28 0x02>; | |
| phandle = <0x2e>; | |
| }; | |
| calib@16 { | |
| reg = <0x2c 0x02>; | |
| phandle = <0xb6>; | |
| }; | |
| }; | |
| typec@380 { | |
| compatible = "sprd,sc2730-typec\0sprd,sc27xx-typec"; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x08>; | |
| reg = <0x380>; | |
| sprd,mode = <0x02>; | |
| nvmem-cells = <0x2c 0x2d>; | |
| nvmem-cell-names = "typec_cc1_cal\0typec_cc2_cal"; | |
| phandle = <0x34>; | |
| }; | |
| fchg@400 { | |
| compatible = "sprd,sc2730-fast-charger"; | |
| reg = <0x400>; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x05 0x04>; | |
| nvmem-cell-names = "fchg_cur_calib"; | |
| nvmem-cells = <0x2e>; | |
| status = "disabled"; | |
| phandle = <0x103>; | |
| }; | |
| adc@504 { | |
| compatible = "sprd,sc2730-adc"; | |
| reg = <0x504>; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x00>; | |
| #io-channel-cells = <0x01>; | |
| hwlocks = <0x2b 0x04>; | |
| nvmem-cells = <0x2f 0x30>; | |
| nvmem-cell-names = "big_scale_calib\0small_scale_calib"; | |
| phandle = <0x33>; | |
| }; | |
| fgu@c00 { | |
| compatible = "sprd,sc2730-fgu"; | |
| reg = <0xc00>; | |
| bat-detect-gpio = <0x31 0x03 0x00>; | |
| nvmem-cell-names = "fgu_calib"; | |
| nvmem-cells = <0x32>; | |
| io-channels = <0x33 0x00 0x33 0x0e>; | |
| io-channel-names = "bat-temp\0charge-vol"; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x03>; | |
| phandle = <0x104>; | |
| }; | |
| pd@e00 { | |
| compatible = "sprd,sc27xx-pd\0sprd,sc2730-pd"; | |
| reg = <0xe00 0x380>; | |
| interrupt-parent = <0x2a>; | |
| interrupts = <0x09 0x04>; | |
| extcon = <0x34>; | |
| nvmem-cells = <0x35 0x36 0x37>; | |
| nvmem-cell-names = "pdrc_calib\0pddelta_calib\0pdref_calib"; | |
| status = "disabled"; | |
| phandle = <0x105>; | |
| }; | |
| audio-codec@1000 { | |
| compatible = "unisoc,sc2730-audio-codec\0unisoc,sc2731-audio-codec"; | |
| #sound-dai-cells = <0x01>; | |
| reg = <0x1000>; | |
| sprd,syscon-pmu-apb = <0x02>; | |
| nvmem-cells = <0x38 0x39 0x32>; | |
| nvmem-cell-names = "aud_pabst_vcal_efuse\0neg_cp_efuse\0fgu_4p2_efuse"; | |
| status = "okay"; | |
| hp-use-inter-pa = <0x01>; | |
| fixed-sample-rate = <0xbb80 0xbb80 0xbb80>; | |
| digital-codec = <0x3a>; | |
| phandle = <0xbd>; | |
| }; | |
| syscon@1800 { | |
| compatible = "sprd,sc2731-syscon\0sprd,sc27xx-syscon"; | |
| reg = <0x1800 0x1ba0 0x1b98>; | |
| }; | |
| power-controller@1800 { | |
| compatible = "sprd,sc2731-regulator\0sprd,sc2730-regulator"; | |
| DCDC_CPU { | |
| regulator-name = "vddcpu"; | |
| regulator-min-microvolt = <0x30d40>; | |
| regulator-max-microvolt = <0x185dcb>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x106>; | |
| }; | |
| DCDC_GPU { | |
| regulator-name = "vddgpu"; | |
| regulator-min-microvolt = <0x30d40>; | |
| regulator-max-microvolt = <0x185dcb>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x0a>; | |
| }; | |
| DCDC_CORE { | |
| regulator-name = "vddcore"; | |
| regulator-min-microvolt = <0x30d40>; | |
| regulator-max-microvolt = <0x185dcb>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x107>; | |
| }; | |
| DCDC_MODEM { | |
| regulator-name = "vddmodem"; | |
| regulator-min-microvolt = <0x30d40>; | |
| regulator-max-microvolt = <0x185dcb>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x108>; | |
| }; | |
| DCDC_MEM { | |
| regulator-name = "vddmem"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-max-microvolt = <0x185196>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x109>; | |
| }; | |
| DCDC_MEMQ { | |
| regulator-name = "vddmemq"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-max-microvolt = <0x185dcb>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x10a>; | |
| }; | |
| DCDC_GEN0 { | |
| regulator-name = "vddgen0"; | |
| regulator-min-microvolt = <0x129da0>; | |
| regulator-max-microvolt = <0x24c881>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x10b>; | |
| }; | |
| DCDC_GEN1 { | |
| regulator-name = "vddgen1"; | |
| regulator-min-microvolt = <0xcf850>; | |
| regulator-max-microvolt = <0x1914e6>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x10c>; | |
| }; | |
| DCDC_SRAM { | |
| regulator-name = "vddsram"; | |
| regulator-min-microvolt = <0x30d40>; | |
| regulator-max-microvolt = <0x185dcb>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x10d>; | |
| }; | |
| LDO_AVDD18 { | |
| regulator-name = "avdd18"; | |
| regulator-min-microvolt = <0x11edd8>; | |
| regulator-max-microvolt = <0x1b8ac8>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x10e>; | |
| }; | |
| LDO_VDDRF18 { | |
| regulator-name = "vddrf18"; | |
| regulator-min-microvolt = <0x11edd8>; | |
| regulator-max-microvolt = <0x1b8ac8>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x10f>; | |
| }; | |
| LDO_VDDCAMIO { | |
| regulator-name = "vddcamio"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x1bec70>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x66>; | |
| }; | |
| LDO_VDDWCN { | |
| regulator-name = "vddwcn"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0x1c2708>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x110>; | |
| }; | |
| LDO_VDDCAMD1 { | |
| regulator-name = "vddcamd1"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0x14d408>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x111>; | |
| }; | |
| LDO_VDDCAMD0 { | |
| regulator-name = "vddcamd0"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0x14d408>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x112>; | |
| }; | |
| LDO_VDDRF1V25 { | |
| regulator-name = "vddrf1v25"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0x14d408>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x113>; | |
| }; | |
| LDO_AVDD12 { | |
| regulator-name = "avdd12"; | |
| regulator-min-microvolt = <0xdbba0>; | |
| regulator-max-microvolt = <0x14d408>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x114>; | |
| }; | |
| LDO_VDDCAMA0 { | |
| regulator-name = "vddcama0"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x115>; | |
| }; | |
| LDO_VDDCAMA1 { | |
| regulator-name = "vddcama1"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x116>; | |
| }; | |
| LDO_VDDCAMMOT { | |
| regulator-name = "vddcammot"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x117>; | |
| }; | |
| LDO_VDDSIM2 { | |
| regulator-name = "vddsim2"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x118>; | |
| }; | |
| LDO_VDDEMMCCORE { | |
| regulator-name = "vddemmccore"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x119>; | |
| }; | |
| LDO_VDDSDCORE { | |
| regulator-name = "vddsdcore"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x11a>; | |
| }; | |
| LDO_VDDSDIO { | |
| regulator-name = "vddsdio"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x11b>; | |
| }; | |
| LDO_VDD28 { | |
| regulator-name = "vdd28"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x11c>; | |
| }; | |
| LDO_VDDWIFIPA { | |
| regulator-name = "vddwifipa"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x11d>; | |
| }; | |
| LDO_VDD18_DCXO { | |
| regulator-name = "vdd18_dcxo"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x11e>; | |
| }; | |
| LDO_VDDUSB33 { | |
| regulator-name = "vddusb33"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x11f>; | |
| }; | |
| LDO_VDDLDO0 { | |
| regulator-name = "vddldo0"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| regulator-always-on; | |
| phandle = <0x120>; | |
| }; | |
| LDO_VDDLDO1 { | |
| regulator-name = "vddldo1"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x121>; | |
| }; | |
| LDO_VDDLDO2 { | |
| regulator-name = "vddldo2"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x122>; | |
| }; | |
| LDO_VDDKPLED { | |
| regulator-name = "vddkpled"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x393870>; | |
| regulator-ramp-delay = <0x61a8>; | |
| phandle = <0x123>; | |
| }; | |
| }; | |
| poweroff@1820 { | |
| compatible = "sprd,sc27xx-poweroff\0sprd,sc2730-poweroff"; | |
| reg = <0x1820>; | |
| }; | |
| tsensor@1b34 { | |
| compatible = "sprd,sc27xx-tsensor\0sprd,sc2730-tsensor"; | |
| #thermal-sensor-cells = <0x01>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x1b34>; | |
| phandle = <0xc9>; | |
| osc-tsensor@0 { | |
| reg = <0x00>; | |
| phandle = <0x124>; | |
| }; | |
| tout-tsensor@1 { | |
| reg = <0x01>; | |
| phandle = <0x125>; | |
| }; | |
| }; | |
| vibrator@1b90 { | |
| compatible = "sprd,sc2730-vibrator"; | |
| reg = <0x1b90>; | |
| }; | |
| hw-reset@1bc0 { | |
| compatible = "sprd,sc27xx-7sreset\0sprd,sc2730-7sreset"; | |
| reg = <0x1bf8 0x1bc0>; | |
| }; | |
| }; | |
| }; | |
| thermal@32200000 { | |
| compatible = "sprd,ums512-thermal"; | |
| reg = <0x00 0x32200000 0x00 0x10000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| clock-names = "enable"; | |
| clocks = <0x0f 0x20>; | |
| #thermal-sensor-cells = <0x01>; | |
| nvmem-cells = <0x3b 0x3c>; | |
| nvmem-cell-names = "thm_sign_cal\0thm_ratio_cal"; | |
| phandle = <0xc6>; | |
| sensor@0 { | |
| reg = <0x00>; | |
| nvmem-cells = <0x3d>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@1 { | |
| reg = <0x01>; | |
| nvmem-cells = <0x3e>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@2 { | |
| reg = <0x02>; | |
| nvmem-cells = <0x3f>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@3 { | |
| reg = <0x03>; | |
| nvmem-cells = <0x40>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@4 { | |
| reg = <0x04>; | |
| nvmem-cells = <0x41>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| }; | |
| thermal@32210000 { | |
| compatible = "sprd,ums512-thermal"; | |
| reg = <0x00 0x32210000 0x00 0x10000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| clock-names = "enable"; | |
| clocks = <0x0f 0x21>; | |
| #thermal-sensor-cells = <0x01>; | |
| nvmem-cells = <0x42 0x43>; | |
| nvmem-cell-names = "thm_sign_cal\0thm_ratio_cal"; | |
| phandle = <0xc7>; | |
| sensor@0 { | |
| reg = <0x00>; | |
| nvmem-cells = <0x44>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@1 { | |
| reg = <0x01>; | |
| nvmem-cells = <0x45>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@2 { | |
| reg = <0x02>; | |
| nvmem-cells = <0x46>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@3 { | |
| reg = <0x03>; | |
| nvmem-cells = <0x47>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@4 { | |
| reg = <0x04>; | |
| nvmem-cells = <0x48>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| sensor@5 { | |
| reg = <0x05>; | |
| nvmem-cells = <0x49>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| }; | |
| thermal@32220000 { | |
| compatible = "sprd,ums512-thermal"; | |
| reg = <0x00 0x32220000 0x00 0x10000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| clock-names = "enable"; | |
| clocks = <0x0f 0x22>; | |
| #thermal-sensor-cells = <0x01>; | |
| nvmem-cells = <0x4a 0x4b>; | |
| nvmem-cell-names = "thm_sign_cal\0thm_ratio_cal"; | |
| phandle = <0xc8>; | |
| sensor@0 { | |
| reg = <0x00>; | |
| nvmem-cells = <0x4c>; | |
| nvmem-cell-names = "sen_delta_cal"; | |
| }; | |
| }; | |
| efuse@32240000 { | |
| compatible = "sprd,ums312-efuse\0sprd,ums512-efuse"; | |
| reg = <0x00 0x32240000 0x00 0x10000>; | |
| clock-names = "enable"; | |
| hwlocks = <0x2b 0x08>; | |
| clocks = <0x0f 0x10>; | |
| phandle = <0x126>; | |
| }; | |
| pwm@32260000 { | |
| compatible = "sprd,sharkl5pro-pwm"; | |
| reg = <0x00 0x32260000 0x00 0x10000>; | |
| clock-names = "pwm0\0enable0\0pwm1\0enable1\0pwm2\0enable2"; | |
| clocks = <0x4d 0x06 0x0f 0x32 0x4d 0x07 0x0f 0x33 0x4d 0x08 0x0f 0x34>; | |
| assigned-clocks = <0x4d 0x06 0x4d 0x07 0x4d 0x08>; | |
| assigned-clock-parents = <0x04 0x04 0x04>; | |
| #pwm-cells = <0x02>; | |
| phandle = <0x127>; | |
| }; | |
| hardware-dvfs-platform { | |
| compatible = "sprd,hardware-cpufreq"; | |
| phandle = <0x128>; | |
| }; | |
| topdvfsctrl@322a0000 { | |
| compatible = "sprd,sharkl5pro-topdvfs-dev\0sprd,topdvfs-dev\0syscon"; | |
| sprd,syscon-enable = <0x0b>; | |
| module-enable-cfg = <0x04 0x07>; | |
| reg = <0x00 0x322a0000 0x00 0x8000>; | |
| sprd,topdvfs-sysctrl = <0x4e>; | |
| cpu-dcdc-cells = <0x4f 0x50>; | |
| device-dcdc-cells = <0x51 0x52>; | |
| phandle = <0x5b>; | |
| dcdc-cpu0 { | |
| dcdc-cpu-dvfs-cfg = <0x53>; | |
| dvfs-blk-sd-syscon = <0x02 0x4fc 0x01>; | |
| phandle = <0x4f>; | |
| }; | |
| dcdc-cpu1 { | |
| dcdc-cpu-dvfs-cfg = <0x54>; | |
| dvfs-blk-sd-syscon = <0x02 0x4fc 0x02>; | |
| phandle = <0x50>; | |
| }; | |
| dcdc-mm { | |
| dcdc-dvfs-enable = <0x18 0x14 0x01>; | |
| dcdc-judge-vol-sw = <0x18 0x01 0x07 0x02>; | |
| dcdc-subsys-cells = <0x55 0x56 0x57>; | |
| phandle = <0x51>; | |
| audcp-sys { | |
| dcdc-subsys-tune-enable = <0x150 0x05 0x00>; | |
| phandle = <0x55>; | |
| }; | |
| gpu-sys { | |
| dcdc-subsys-tune-enable = <0x150 0x01 0x01>; | |
| phandle = <0x56>; | |
| }; | |
| mm-sys { | |
| dcdc-subsys-tune-enable = <0x150 0x02 0x00>; | |
| phandle = <0x57>; | |
| }; | |
| }; | |
| dcdc-modem { | |
| dcdc-dvfs-enable = <0x3c 0x14 0x01>; | |
| dcdc-judge-vol-sw = <0x3c 0x01 0x07 0x02>; | |
| dcdc-subsys-cells = <0x58 0x59 0x5a>; | |
| phandle = <0x52>; | |
| pubcp-sys { | |
| dcdc-subsys-tune-enable = <0x150 0x04 0x00>; | |
| phandle = <0x58>; | |
| }; | |
| wtlcp-sys { | |
| dcdc-subsys-tune-enable = <0x150 0x03 0x00>; | |
| phandle = <0x59>; | |
| }; | |
| ap-sys { | |
| dcdc-subsys-tune-enable = <0x150 0x00 0x01>; | |
| phandle = <0x5a>; | |
| }; | |
| }; | |
| }; | |
| cpudvfs-dev@322a8000 { | |
| compatible = "sprd,sharkl5pro-cpudvfs"; | |
| reg = <0x00 0x322a8000 0x00 0x1000>; | |
| enable-syscon = <0x0b 0x04 0x80>; | |
| topdvfs-controller = <0x5b>; | |
| host-cluster-cells = <0x5c 0x5d>; | |
| slave-cluster-cells = <0x5e 0x5f 0x60>; | |
| mpll-cells = <0x61 0x62 0x63>; | |
| phandle = <0xb1>; | |
| lit-core-cluster { | |
| belong-dcdc-cell = <0x00>; | |
| lit_core_cluster_tbl = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x09 0x05 0x05 0x05>; | |
| lit_core_cluster_tbl_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x01 0x02 0x02 0x02 0x00 0x03 0x00 0x01 0x03 0x02 0x03 0x00 0x03 0x00 0x01 0x04 0x03 0x04 0x01 0x01 0x00 0x01 0x05 0x04 0x04 0x00 0x03 0x00 0x02 0x06 0x04 0x04 0x02 0x02 0x00 0x02 0x07 0x04 0x04 0x00 0x03 0x00 0x02 0x08 0x04 0x05 0x03 0x03 0x00 0x02 0x09 0x05 0x05 0x04>; | |
| lit_core_cluster_tbl_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x01 0x02 0x02 0x02 0x00 0x03 0x00 0x01 0x03 0x02 0x03 0x00 0x03 0x00 0x01 0x04 0x03 0x04 0x01 0x01 0x00 0x01 0x05 0x04 0x04 0x00 0x03 0x00 0x02 0x06 0x04 0x04 0x02 0x02 0x00 0x02 0x07 0x04 0x04 0x00 0x03 0x00 0x02 0x08 0x04 0x05 0x03 0x03 0x00 0x02 0x09 0x05 0x05 0x04>; | |
| lit_core_cluster_tbl_T610 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x01 0x03 0x01 0x01 0x01 0x01 0x00 0x02 0x04 0x01 0x01 0x00 0x03 0x00 0x03 0x05 0x04 0x04 0x02 0x02 0x00 0x04 0x06 0x04 0x04 0x00 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x06 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x04 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_tt = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x04 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_ss = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x01 0x03 0x01 0x01 0x01 0x01 0x00 0x02 0x04 0x01 0x01 0x00 0x03 0x00 0x03 0x05 0x04 0x04 0x02 0x02 0x00 0x04 0x06 0x04 0x04 0x00 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x06 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_od = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x01 0x03 0x01 0x01 0x01 0x01 0x00 0x02 0x04 0x01 0x01 0x00 0x03 0x00 0x03 0x05 0x04 0x04 0x02 0x02 0x00 0x04 0x06 0x04 0x04 0x00 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x06 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x04 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x05 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_ss_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x01 0x03 0x01 0x01 0x01 0x01 0x00 0x02 0x04 0x01 0x01 0x00 0x03 0x00 0x03 0x05 0x04 0x04 0x02 0x02 0x00 0x04 0x06 0x04 0x04 0x00 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x06 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T610_od_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x01 0x03 0x01 0x01 0x01 0x01 0x00 0x02 0x04 0x01 0x01 0x00 0x03 0x00 0x03 0x05 0x04 0x04 0x02 0x02 0x00 0x04 0x06 0x04 0x04 0x00 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x07 0x04 0x05 0x03>; | |
| lit_core_cluster_tbl_T618 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x09 0x05 0x05 0x05>; | |
| lit_core_cluster_tbl_T618_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x05 0x09 0x05 0x05 0x05>; | |
| lit_core_cluster_tbl_T618_tt = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x09 0x05 0x05 0x05>; | |
| lit_core_cluster_tbl_T618_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x05 0x09 0x05 0x05 0x05>; | |
| lit_core_cluster_tbl_T618_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x01 0x03 0x01 0x01 0x01 0x01 0x00 0x02 0x04 0x01 0x01 0x00 0x03 0x00 0x03 0x05 0x04 0x04 0x02 0x02 0x00 0x04 0x06 0x04 0x04 0x00 0x03 0x00 0x05 0x07 0x04 0x05 0x03 0x03 0x00 0x06 0x08 0x04 0x05 0x04 0x03 0x00 0x06 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T700 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x05 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T700_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x04 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T700_tt = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x05 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T700_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x00 0x04 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x02 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x04 0x03 0x00 0x04 0x08 0x04 0x05 0x04>; | |
| lit_core_cluster_tbl_T700_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x02 0x01 0x00 0x01 0x01 0x01 0x00 0x03 0x00 0x00 0x02 0x01 0x01 0x00 0x03 0x00 0x00 0x03 0x01 0x01 0x01 0x01 0x00 0x01 0x04 0x01 0x01 0x00 0x03 0x00 0x02 0x05 0x04 0x04 0x02 0x02 0x00 0x03 0x06 0x04 0x04 0x00 0x03 0x00 0x04 0x07 0x04 0x05 0x03 0x03 0x00 0x05 0x08 0x04 0x05 0x04 0x03 0x00 0x05 0x08 0x04 0x05 0x04>; | |
| phandle = <0x5c>; | |
| }; | |
| big-core-cluster { | |
| belong-dcdc-cell = <0x01>; | |
| big_core_cluster_tbl = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x03 0x03 0x00 0x05 0x09 0x05 0x05 0x04>; | |
| big_core_cluster_tbl_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x03 0x04 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x02 0x07 0x04 0x05 0x01 0x03 0x00 0x02 0x08 0x04 0x05 0x02 0x03 0x00 0x02 0x09 0x05 0x05 0x03>; | |
| big_core_cluster_tbl_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x03 0x04 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x02 0x07 0x04 0x05 0x01 0x03 0x00 0x02 0x08 0x04 0x05 0x02 0x03 0x00 0x02 0x09 0x05 0x05 0x03>; | |
| big_core_cluster_tbl_T610 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_tt = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_ss = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_od = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_ss_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T610_od_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x03 0x07 0x04 0x05 0x01>; | |
| big_core_cluster_tbl_T618 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x03 0x03 0x00 0x05 0x09 0x05 0x05 0x04>; | |
| big_core_cluster_tbl_T618_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x03 0x03 0x00 0x05 0x09 0x05 0x05 0x04>; | |
| big_core_cluster_tbl_T618_tt = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x03 0x03 0x00 0x05 0x09 0x05 0x05 0x04>; | |
| big_core_cluster_tbl_T618_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x03 0x03 0x00 0x05 0x09 0x05 0x05 0x04>; | |
| big_core_cluster_tbl_T618_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x03 0x03 0x00 0x04 0x08 0x04 0x05 0x03>; | |
| big_core_cluster_tbl_T700 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T700_ff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T700_tt = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T700_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| big_core_cluster_tbl_T700_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x03 0x01 0x01 0x00 0x03 0x00 0x01 0x05 0x04 0x04 0x00 0x02 0x00 0x02 0x06 0x04 0x04 0x00 0x03 0x00 0x03 0x07 0x04 0x05 0x01 0x03 0x00 0x04 0x08 0x04 0x05 0x02 0x03 0x00 0x04 0x08 0x04 0x05 0x02>; | |
| phandle = <0x5d>; | |
| }; | |
| scu-cluster { | |
| belong-dcdc-cell = <0x00>; | |
| scu_cluster_tbl = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x02 0x01 0x03 0x03 0x00 0x03 0x01 0x04 0x03 0x00 0x04 0x01 0x05 0x03 0x00 0x05 0x01 0x06 0x03 0x00 0x06 0x01 0x07>; | |
| scu_cluster_tbl_ff = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x02 0x01 0x05 0x03 0x00 0x02 0x01 0x06 0x03 0x00 0x02 0x01 0x07>; | |
| scu_cluster_tbl_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x02 0x01 0x05 0x03 0x00 0x02 0x01 0x06 0x03 0x00 0x02 0x01 0x07>; | |
| scu_cluster_tbl_T610 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x01 0x04 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x06 0x01 0x06 0x03 0x00 0x06 0x01 0x06>; | |
| scu_cluster_tbl_T610_ff = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x04 0x01 0x06>; | |
| scu_cluster_tbl_T610_tt = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x04 0x01 0x06>; | |
| scu_cluster_tbl_T610_ss = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x01 0x04 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x06 0x01 0x06 0x03 0x00 0x06 0x01 0x06>; | |
| scu_cluster_tbl_T610_od = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x01 0x04 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x06 0x01 0x06 0x03 0x00 0x06 0x01 0x06>; | |
| scu_cluster_tbl_T610_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x04 0x01 0x06>; | |
| scu_cluster_tbl_T610_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x02 0x01 0x03 0x03 0x00 0x03 0x01 0x04 0x03 0x00 0x04 0x01 0x05 0x03 0x00 0x05 0x01 0x06 0x03 0x00 0x05 0x01 0x06>; | |
| scu_cluster_tbl_T610_ss_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x01 0x04 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x06 0x01 0x06 0x03 0x00 0x06 0x01 0x06>; | |
| scu_cluster_tbl_T610_od_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x01 0x04 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x05 0x01 0x05>; | |
| scu_cluster_tbl_T618 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x02 0x01 0x03 0x03 0x00 0x03 0x01 0x04 0x03 0x00 0x04 0x01 0x05 0x03 0x00 0x05 0x01 0x06 0x03 0x00 0x06 0x01 0x07>; | |
| scu_cluster_tbl_T618_ff = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x05 0x01 0x07>; | |
| scu_cluster_tbl_T618_tt = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x02 0x01 0x03 0x03 0x00 0x03 0x01 0x04 0x03 0x00 0x04 0x01 0x05 0x03 0x00 0x05 0x01 0x06 0x03 0x00 0x06 0x01 0x07>; | |
| scu_cluster_tbl_T618_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x05 0x01 0x07>; | |
| scu_cluster_tbl_T618_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x01 0x01 0x00 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x03 0x01 0x03 0x03 0x00 0x04 0x01 0x04 0x03 0x00 0x05 0x01 0x05 0x03 0x00 0x06 0x01 0x06 0x03 0x00 0x06 0x01 0x06>; | |
| scu_cluster_tbl_T700 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x01 0x01 0x02 0x03 0x00 0x02 0x01 0x03 0x03 0x00 0x03 0x01 0x04 0x03 0x00 0x04 0x01 0x05 0x03 0x00 0x05 0x01 0x06 0x03 0x00 0x05 0x01 0x06>; | |
| scu_cluster_tbl_T700_ff = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x00 0x01 0x03 0x03 0x00 0x01 0x01 0x04 0x03 0x00 0x02 0x01 0x05 0x03 0x00 0x03 0x01 0x06 0x03 0x00 0x04 0x01 0x06>; | |
| scu_cluster_tbl_T700_tt = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x05 0x01 0x06>; | |
| scu_cluster_tbl_T700_ff_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x00 0x01 0x03 0x03 0x00 0x01 0x01 0x04 0x03 0x00 0x02 0x01 0x05 0x03 0x00 0x03 0x01 0x06 0x03 0x00 0x04 0x01 0x06>; | |
| scu_cluster_tbl_T700_tt_65 = <0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x02 0x03 0x00 0x01 0x01 0x03 0x03 0x00 0x02 0x01 0x04 0x03 0x00 0x03 0x01 0x05 0x03 0x00 0x04 0x01 0x06 0x03 0x00 0x05 0x01 0x06>; | |
| phandle = <0x5e>; | |
| }; | |
| periph-cluster { | |
| belong-dcdc-cell = <0x00>; | |
| periph_cluster_tbl = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x06>; | |
| periph_cluster_tbl_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x02>; | |
| periph_cluster_tbl_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x02>; | |
| periph_cluster_tbl_T610 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_tt = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_ss = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x03 0x03 0x01 0x03 0x02 0x00 0x03 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_od = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_tt_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_ss_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T610_od_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T618 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x06>; | |
| periph_cluster_tbl_T618_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T618_tt = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x06>; | |
| periph_cluster_tbl_T618_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T618_tt_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x03 0x03 0x01 0x03 0x02 0x00 0x03 0x03 0x00 0x06>; | |
| periph_cluster_tbl_T700 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T700_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T700_tt = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T700_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x05>; | |
| periph_cluster_tbl_T700_tt_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x05>; | |
| phandle = <0x5f>; | |
| }; | |
| gic-cluster { | |
| belong-dcdc-cell = <0x00>; | |
| gic_cluster_tbl = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T610 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T610_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T610_tt = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T610_ss = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x03 0x03 0x01 0x03 0x02 0x00 0x03 0x03 0x00 0x03>; | |
| gic_cluster_tbl_T610_od = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T610_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T610_tt_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_T610_ss_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_T610_od_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T618 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_T618_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T618_tt = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_T618_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T618_tt_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x03 0x03 0x01 0x03 0x02 0x00 0x03 0x03 0x00 0x03>; | |
| gic_cluster_tbl_T700 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_T700_ff = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T700_tt = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| gic_cluster_tbl_T700_ff_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x01 0x03 0x01 0x01 0x02 0x00 0x01 0x03 0x00 0x01>; | |
| gic_cluster_tbl_T700_tt_65 = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x01 0x02 0x03 0x01 0x02 0x02 0x00 0x02 0x03 0x00 0x02>; | |
| phandle = <0x60>; | |
| }; | |
| mpll-ananke { | |
| mpll-sel-syscon = <0x64 0x98 0xd0>; | |
| phandle = <0x61>; | |
| }; | |
| mpll-prometheus { | |
| mpll-sel-syscon = <0x65 0x44 0xd0>; | |
| phandle = <0x62>; | |
| }; | |
| mpll-scu { | |
| mpll-sel-syscon = <0x64 0xdc 0x68>; | |
| phandle = <0x63>; | |
| }; | |
| }; | |
| apb-busmonitor@32370000 { | |
| compatible = "sprd,apb-busmonitor"; | |
| reg = <0x00 0x32370000 0x00 0x1000>; | |
| interrupts = <0x00 0x66 0x04>; | |
| sprd,target-addr = <0x00 0x00>; | |
| sprd,target-data = <0x00 0x00>; | |
| phandle = <0x129>; | |
| }; | |
| timer@322e0000 { | |
| compatible = "sprd,syst-timer"; | |
| reg = <0x00 0x322e0000 0x00 0x10>; | |
| }; | |
| watchdog@322f0000 { | |
| compatible = "sprd,wdt-r2p0-fiq"; | |
| reg = <0x00 0x322f0000 0x00 0x10000>; | |
| interrupts = <0x00 0x4f 0x04>; | |
| timeout-sec = <0x0c>; | |
| clock-names = "enable\0rtc_enable"; | |
| clocks = <0x0f 0x37 0x0f 0x41>; | |
| }; | |
| hsphy@323b0000 { | |
| compatible = "sprd,sharkl5-phy\0sprd,sharkl5pro-phy"; | |
| sprd,syscon-enable = <0x0b>; | |
| sprd,syscon-anag2 = <0x65>; | |
| sprd,vdd-voltage = <0x325aa0>; | |
| #phy-cells = <0x00>; | |
| phandle = <0x68>; | |
| }; | |
| pinctrl@32450000 { | |
| compatible = "sprd,sharkl5Pro-pinctrl"; | |
| reg = <0x00 0x32450000 0x00 0x3000>; | |
| phandle = <0xb4>; | |
| vbc-iis3-0 { | |
| pins = "SHARKL5PRO_IIS_INF0_SYS_SEL"; | |
| sprd,control = <0x0e>; | |
| phandle = <0x6a>; | |
| }; | |
| vbc-iism0-0 { | |
| pins = "SHARKL5PRO_IIS_INF0_SYS_SEL"; | |
| sprd,control = <0x0f>; | |
| phandle = <0x6b>; | |
| }; | |
| vbc-iis-to-pad { | |
| pins = "SHARKL5PRO_VBC_IIS_INF_SYS_SEL"; | |
| sprd,control = <0x00>; | |
| phandle = <0x6c>; | |
| }; | |
| vbc-iis-to-aon-usb { | |
| pins = "SHARKL5PRO_VBC_IIS_INF_SYS_SEL"; | |
| sprd,control = <0x01>; | |
| phandle = <0x6d>; | |
| }; | |
| vbc-iism0-1 { | |
| pins = "SHARKL5PRO_IIS_INF1_SYS_SEL"; | |
| sprd,control = <0x0f>; | |
| phandle = <0x6e>; | |
| }; | |
| vbc-iism0-3 { | |
| pins = "SHARKL5PRO_IIS_INF3_SYS_SEL"; | |
| sprd,control = <0x0f>; | |
| phandle = <0x6f>; | |
| }; | |
| vbc-iis0-3 { | |
| pins = "SHARKL5PRO_IIS_INF3_SYS_SEL"; | |
| sprd,control = <0x0b>; | |
| phandle = <0x70>; | |
| }; | |
| vbc-iis1-3 { | |
| pins = "SHARKL5PRO_IIS_INF3_SYS_SEL"; | |
| sprd,control = <0x0c>; | |
| phandle = <0x71>; | |
| }; | |
| vbc-iis2-3 { | |
| pins = "SHARKL5PRO_IIS_INF3_SYS_SEL"; | |
| sprd,control = <0x0d>; | |
| phandle = <0x72>; | |
| }; | |
| vbc-iis3-3 { | |
| pins = "SHARKL5PRO_IIS_INF3_SYS_SEL"; | |
| sprd,control = <0x0e>; | |
| phandle = <0x73>; | |
| }; | |
| ap-iis0-3 { | |
| pins = "SHARKL5PRO_IIS_INF3_SYS_SEL"; | |
| sprd,control = <0x00>; | |
| phandle = <0x74>; | |
| }; | |
| }; | |
| djtag@324e0000 { | |
| compatible = "sprd,djtag"; | |
| status = "okay"; | |
| reg = <0x00 0x324e0000 0x00 0x1000>; | |
| syscon-names = "soft_rst"; | |
| syscon = <0x0b 0x130 0x400>; | |
| clock-names = "enable\0tck"; | |
| clocks = <0x0f 0x02 0x0f 0x01>; | |
| hwlocks = <0x2b 0x0a>; | |
| hwlock-names = "djtag"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x12a>; | |
| aon-busmonitor@8 { | |
| compatible = "sprd,sharkl5pro-busmonitor"; | |
| interrupts = <0x00 0x51 0x04>; | |
| reg = <0x08>; | |
| sprd,bm-num = <0x06>; | |
| sprd,bm-name = "AP\0WTLCP\0AUDCP\0PUBCP\0USBOTG\0CM4"; | |
| sprd,bm-type = <0x01 0x01 0x01 0x01 0x01 0x01>; | |
| sprd,bm-dap = <0x00 0x01 0x02 0x03 0x04 0x05>; | |
| sprd,bm-config = <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01>; | |
| sprd,bm-id = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| sprd,bm-ranges = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| }; | |
| modem-dbg-log@324f0000 { | |
| compatible = "sprd,dbg-log-sharkl5\0sprd,dbg-log-sharkl5pro"; | |
| reg = <0x00 0x324f0000 0x00 0x4000>; | |
| sprd,syscon-mm-ahb = <0x11>; | |
| sprd,syscon-dsi-apb = <0x15>; | |
| sprd,ch-name = "TRAINING\0WTL\0MADR\0TPIU\0DBUS\0WCN"; | |
| sprd,ch-index = <0x0f 0x01 0x00 0x02 0x03 0x04>; | |
| sprd,dcfix; | |
| sprd,mm; | |
| sprd,mipi-l5pro = <0x01>; | |
| power-domains = <0x1b>; | |
| status = "okay"; | |
| clock-names = "serdes_eb\0mm_eb\0ana_eb\0dphy_cfg_eb\0dphy_ref_eb\0dsi_csi_test_eb\0cphy_cfg_eb"; | |
| clocks = <0x0f 0x38 0x0f 0x07 0x0f 0x1b 0x0f 0x0e 0x0f 0x0f 0x0f 0x4b 0x0f 0x61>; | |
| vddio-supply = <0x66>; | |
| mipi-switch-en-gpios = <0x67 0x37 0x00>; | |
| mipi-switch-mode-gpios = <0x67 0x08 0x00>; | |
| phandle = <0x12b>; | |
| }; | |
| hwspinlock@327f0000 { | |
| compatible = "sprd,hwspinlock-r3p0"; | |
| reg = <0x00 0x327f0000 0x00 0x10000>; | |
| #hwlock-cells = <0x01>; | |
| clock-names = "enable"; | |
| clocks = <0x0f 0x19>; | |
| phandle = <0x2b>; | |
| }; | |
| usb@5fff0000 { | |
| compatible = "sprd,sharkl5pro-musb\0sprd,sharkl3-musb"; | |
| reg = <0x00 0x5fff0000 0x00 0x2000>; | |
| interrupts = <0x00 0x45 0x04>; | |
| interrupt-names = "mc"; | |
| clocks = <0x0f 0x17>; | |
| clock-names = "core_clk"; | |
| usb-phy = <0x68>; | |
| phy-names = "usb"; | |
| dr-mode = "peripheral"; | |
| multipoint = "true"; | |
| wakeup-source; | |
| phandle = <0x12c>; | |
| }; | |
| socid@402e00e0 { | |
| compatible = "sprd,soc-id"; | |
| chip_id = <0x0b 0xe0 0xffffffff>; | |
| plat_id = <0x0b 0xe8 0xffffffff>; | |
| implement_id = <0x0b 0xf0 0xffffffff>; | |
| manufacture_id = <0x0b 0xf4 0xffffffff>; | |
| version_id = <0x0b 0xf8 0xffffffff>; | |
| phandle = <0x12d>; | |
| }; | |
| }; | |
| agcp { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| vbc@33480000 { | |
| compatible = "unisoc,sharkl5-vbc\0unisoc,sharkl5pro-vbc"; | |
| #sound-dai-cells = <0x01>; | |
| reg = <0x00 0x33480000 0x00 0x1000>; | |
| sprd,syscon-agcp-ahb = <0x69>; | |
| sprd,vbc-phy-offset = <0x32000000>; | |
| pinctrl-names = "vbc_iis3_0\0vbc_iism0_0\0vbc_iis_to_pad\0vbc_iis_to_aon_usb\0vbc_iism0_1\0vbc_iism0_3\0vbc_iis0_3\0vbc_iis1_3\0vbc_iis2_3\0vbc_iis3_3\0ap_iis0_3"; | |
| pinctrl-0 = <0x6a>; | |
| pinctrl-1 = <0x6b>; | |
| pinctrl-2 = <0x6c>; | |
| pinctrl-3 = <0x6d>; | |
| pinctrl-4 = <0x6e>; | |
| pinctrl-5 = <0x6f>; | |
| pinctrl-6 = <0x70>; | |
| pinctrl-7 = <0x71>; | |
| pinctrl-8 = <0x72>; | |
| pinctrl-9 = <0x73>; | |
| pinctrl-10 = <0x74>; | |
| phandle = <0xbc>; | |
| }; | |
| mcdt@33490000 { | |
| compatible = "unisoc,sharkl5-mcdt\0unisoc,sharkl5pro-mcdt"; | |
| reg = <0x00 0x33490000 0x00 0x170>; | |
| interrupts = <0x00 0xb6 0x04>; | |
| sprd,ap-addr-offset = <0x32000000>; | |
| sprd,syscon-agcp-ahb = <0x69>; | |
| }; | |
| dma-controller@33580000 { | |
| compatible = "sprd,sharkl5pro-dma\0sprd,sc9860-dma"; | |
| reg = <0x00 0x33580000 0x00 0x4000>; | |
| interrupts = <0x00 0xb4 0x04>; | |
| #dma-cells = <0x01>; | |
| #dma-channels = <0x20>; | |
| clock-names = "enable\0ashb_eb"; | |
| clocks = <0x75 0x05 0x75 0x0c>; | |
| phandle = <0xa3>; | |
| }; | |
| audio-codec@33750000 { | |
| compatible = "unisoc,audio-codec-dig-agcp"; | |
| reg = <0x00 0x33750000 0x00 0x1000>; | |
| sprd,syscon-agcp-ahb = <0x69>; | |
| phandle = <0x3a>; | |
| }; | |
| agdsp-access { | |
| compatible = "unisoc,agdsp-access"; | |
| sprd,syscon-agcp-ahb = <0x0b>; | |
| sprd,syscon-pmu-apb = <0x02>; | |
| audcp_pmu_sleep_ctrl = <0x02 0xcc 0x20>; | |
| audcp_pmu_slp_status = <0x02 0xd4 0xf000>; | |
| audcp_pmu_pwr_status4 = <0x02 0xb8 0xff000000>; | |
| audcp_pmu_pwr_status3 = <0x02 0x10c 0xff>; | |
| ap_access_ena = <0x0b 0x14c 0x20>; | |
| sprd,ddr-addr-offset = <0x00>; | |
| sprd,auto_agcp_access = <0x00>; | |
| }; | |
| }; | |
| pub { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| dmc-mpu@31030000 { | |
| compatible = "sprd,sharkl5pro-dmc-mpu"; | |
| reg = <0x00 0x31030000 0x00 0x10000>; | |
| interrupts = <0x00 0x6f 0x04>; | |
| syscon-names = "irq_clr\0irq_en"; | |
| mpu-irq-clr-syscon = <0x76 0x32f0 0x200>; | |
| mpu-irq-en-syscon = <0x76 0x32f0 0x100>; | |
| sprd,channel-num = <0x07>; | |
| sprd,mpu-num = <0x10>; | |
| sprd,channel-names = "CPU\0GPU\0DPU/DCAM\0ISP\0AP/VSP/AON\0WTLCP\0PUBCP/AUDCP\0SHARED0\0SHARED1\0SHARED2\0SHARED3\0SHARED4\0SHARED5\0SHARED6\0SHARED7\0SHARED8"; | |
| sprd,ranges = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| sprd,chn-config = <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01>; | |
| sprd,id-config = <0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff 0x00 0x00 0xffff>; | |
| sprd,port-map = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| sprd,ddr-offset = <0x80000000>; | |
| status = "okay"; | |
| phandle = <0x12e>; | |
| }; | |
| ptm@31060000 { | |
| compatible = "sprd,sharkl5pro-ptm"; | |
| reg = <0x00 0x31060000 0x00 0x10000 0x00 0x3c002000 0x00 0x1000 0x00 0x3c003000 0x00 0x1000 0x00 0x3c006000 0x00 0x1000>; | |
| interrupts = <0x00 0x6d 0x04>; | |
| clock-names = "clk_cs\0cs_src"; | |
| clocks = <0x4d 0x22 0x07 0x0f>; | |
| sprd,funnel-port = <0x03>; | |
| sprd,ddr-chn = <0x07>; | |
| sprd,chn-name = "CPU\0GPU\0DPU/DCAM\0ISP\0AP/VSP/AON\0WTLCP\0PUBCP/AUDCP"; | |
| phandle = <0x12f>; | |
| }; | |
| dmc-controller@31050000 { | |
| compatible = "sprd,pub-dmc"; | |
| reg = <0x00 0x3000 0x00 0x100 0x00 0x31050000 0x00 0x7000>; | |
| phandle = <0x130>; | |
| }; | |
| }; | |
| interrupt-controller@12000000 { | |
| compatible = "arm,gic-v3"; | |
| #interrupt-cells = <0x03>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| redistributor-stride = <0x00 0x20000>; | |
| #redistributor-regions = <0x01>; | |
| interrupt-controller; | |
| reg = <0x00 0x12000000 0x00 0x20000 0x00 0x12040000 0x00 0x100000>; | |
| interrupts = <0x01 0x09 0x04>; | |
| phandle = <0x01>; | |
| }; | |
| apahb-gate { | |
| compatible = "sprd,ums512-apahb-gate"; | |
| sprd,syscon = <0x09>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x08>; | |
| }; | |
| clock-controller@20200000 { | |
| compatible = "sprd,ums512-ap-clk"; | |
| reg = <0x00 0x20200000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x06>; | |
| }; | |
| clock-controller@32080000 { | |
| compatible = "sprd,ums512-aonapb-clk"; | |
| reg = <0x00 0x32080000 0x00 0x1000>; | |
| clocks = <0x04 0x77 0x29 0x78>; | |
| clock-names = "ext-26m\0rco-100m\0ext-32k\0ext-4m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x4d>; | |
| }; | |
| pmu-gate { | |
| compatible = "sprd,ums512-pmu-gate"; | |
| sprd,syscon = <0x02>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x131>; | |
| }; | |
| dpll0 { | |
| compatible = "sprd,ums512-g0-pll"; | |
| sprd,syscon = <0x79>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x132>; | |
| }; | |
| mpll1 { | |
| compatible = "sprd,ums512-g2-pll"; | |
| sprd,syscon = <0x65>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x133>; | |
| }; | |
| pll1 { | |
| compatible = "sprd,ums512-g3-pll"; | |
| sprd,syscon = <0x64>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0xa0>; | |
| }; | |
| pll2 { | |
| compatible = "sprd,ums512-gc-pll"; | |
| sprd,syscon = <0x7a>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x07>; | |
| }; | |
| aonapb-gate { | |
| compatible = "sprd,ums512-aon-gate"; | |
| sprd,syscon = <0x0b>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x0f>; | |
| }; | |
| audcpapb-gate { | |
| compatible = "sprd,ums512-audcpapb-gate"; | |
| sprd,syscon = <0x7b>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x134>; | |
| }; | |
| audcpahb-gate { | |
| compatible = "sprd,ums512-audcpahb-gate"; | |
| sprd,syscon = <0x69>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x75>; | |
| }; | |
| funnel@3c002000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x3c002000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x7c>; | |
| phandle = <0x7e>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x7d>; | |
| phandle = <0x88>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etb@3c003000 { | |
| compatible = "arm,coresight-tmc\0arm,primecell"; | |
| reg = <0x00 0x3c003000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| phandle = <0x135>; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x7e>; | |
| phandle = <0x7c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@3e001000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x3e001000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x7f>; | |
| phandle = <0x85>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x80>; | |
| phandle = <0x97>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x81>; | |
| phandle = <0x99>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x82>; | |
| phandle = <0x9b>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x83>; | |
| phandle = <0x9f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etf@3e002000 { | |
| compatible = "arm,coresight-tmc\0arm,primecell"; | |
| reg = <0x00 0x3e002000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x84>; | |
| phandle = <0x89>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x85>; | |
| phandle = <0x7f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etf@3e003000 { | |
| compatible = "arm,coresight-tmc\0arm,primecell"; | |
| reg = <0x00 0x3e003000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x86>; | |
| phandle = <0x8a>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x87>; | |
| phandle = <0x8b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@3e004000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x3e004000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x88>; | |
| phandle = <0x7d>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x89>; | |
| phandle = <0x84>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x8a>; | |
| phandle = <0x86>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@3e005000 { | |
| compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; | |
| reg = <0x00 0x3e005000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "apb_pclk"; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x8b>; | |
| phandle = <0x87>; | |
| }; | |
| }; | |
| }; | |
| in-ports { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| port@0 { | |
| reg = <0x00>; | |
| endpoint { | |
| remote-endpoint = <0x8c>; | |
| phandle = <0x91>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x01>; | |
| endpoint { | |
| remote-endpoint = <0x8d>; | |
| phandle = <0x93>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x02>; | |
| endpoint { | |
| remote-endpoint = <0x8e>; | |
| phandle = <0x95>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x03>; | |
| endpoint { | |
| remote-endpoint = <0x8f>; | |
| phandle = <0x9d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f040000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f040000 0x00 0x1000>; | |
| cpu = <0x90>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x136>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x91>; | |
| phandle = <0x8c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f140000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f140000 0x00 0x1000>; | |
| cpu = <0x92>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x137>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x93>; | |
| phandle = <0x8d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f240000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f240000 0x00 0x1000>; | |
| cpu = <0x94>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x138>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x95>; | |
| phandle = <0x8e>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f340000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f340000 0x00 0x1000>; | |
| cpu = <0x96>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x139>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x97>; | |
| phandle = <0x80>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f440000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f440000 0x00 0x1000>; | |
| cpu = <0x98>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x13a>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x99>; | |
| phandle = <0x81>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f540000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f540000 0x00 0x1000>; | |
| cpu = <0x9a>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x13b>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9b>; | |
| phandle = <0x82>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f640000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f640000 0x00 0x1000>; | |
| cpu = <0x9c>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x13c>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9d>; | |
| phandle = <0x8f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| etm@3f740000 { | |
| compatible = "arm,coresight-etm4x\0arm,primecell"; | |
| reg = <0x00 0x3f740000 0x00 0x1000>; | |
| cpu = <0x9e>; | |
| clocks = <0x04 0x4d 0x22 0x07 0x08>; | |
| clock-names = "apb_pclk\0clk_cs\0cs_src"; | |
| phandle = <0x13d>; | |
| out-ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x9f>; | |
| phandle = <0x83>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gpu-clk { | |
| compatible = "sprd,ums512-gpu-clk"; | |
| sprd,syscon = <0x0c>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x10>; | |
| }; | |
| clock-controller@62100000 { | |
| compatible = "sprd,ums512-mm-clk"; | |
| reg = <0x00 0x62100000 0x00 0x1000>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x13>; | |
| }; | |
| clock-controller@62200000 { | |
| compatible = "sprd,ums512-mm-gate-clk"; | |
| sprd,syscon = <0x11>; | |
| #clock-cells = <0x01>; | |
| phandle = <0x12>; | |
| }; | |
| apapb-gate { | |
| compatible = "sprd,ums512-apapb-gate"; | |
| sprd,syscon = <0x03>; | |
| clocks = <0x04>; | |
| clock-names = "ext-26m"; | |
| #clock-cells = <0x01>; | |
| phandle = <0x05>; | |
| }; | |
| ap-apb { | |
| compatible = "simple-bus"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| sdio@71400000 { | |
| compatible = "sprd,sdhci-r11"; | |
| reg = <0x00 0x71400000 0x00 0x1000>; | |
| interrupts = <0x00 0x0a 0x04>; | |
| clock-names = "sdio\0enable"; | |
| clocks = <0x06 0x15 0x05 0x19>; | |
| assigned-clocks = <0x06 0x15>; | |
| assigned-clock-parents = <0xa0 0x00>; | |
| bus-width = <0x08>; | |
| non-removable; | |
| no-sdio; | |
| no-sd; | |
| cap-mmc-hw-reset; | |
| status = "okay"; | |
| phandle = <0x13e>; | |
| }; | |
| sdio@71100000 { | |
| compatible = "sprd,sdhci-r11"; | |
| reg = <0x00 0x71100000 0x00 0x1000>; | |
| interrupts = <0x00 0x13 0x04>; | |
| clock-names = "sdio\0enable"; | |
| clocks = <0x06 0x13 0x05 0x16>; | |
| assigned-clocks = <0x06 0x13>; | |
| assigned-clock-parents = <0xa0 0x00>; | |
| sd-detect-pol-syscon = <0x0b 0x444 0x04>; | |
| sd-hotplug-protect-en-syscon = <0x0b 0x444 0x08>; | |
| sd-hotplug-debounce-en-syscon = <0x0b 0x444 0x80>; | |
| sd-hotplug-debounce-cn-syscon = <0x0b 0x444 0xff0000>; | |
| bus-width = <0x04>; | |
| no-sdio; | |
| no-mmc; | |
| status = "okay"; | |
| phandle = <0x13f>; | |
| }; | |
| sdio@71200000 { | |
| compatible = "sprd,sdhci-r11"; | |
| reg = <0x00 0x71200000 0x00 0x1000>; | |
| interrupts = <0x00 0x14 0x04>; | |
| clock-names = "sdio\0enable"; | |
| clocks = <0x06 0x14 0x05 0x17>; | |
| assigned-clocks = <0x06 0x14>; | |
| assigned-clock-parents = <0x07 0x17>; | |
| bus-width = <0x04>; | |
| no-sd; | |
| no-mmc; | |
| status = "okay"; | |
| phandle = <0x140>; | |
| }; | |
| }; | |
| }; | |
| sipc-virt { | |
| compatible = "unisoc,sipc-virt-bus"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x141>; | |
| core@5 { | |
| compatible = "sprd,sipc"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x05>; | |
| label = "sipc-lte"; | |
| mboxes = <0xa1 0x02 0x00>; | |
| sprd,smem-info = <0x8e000000 0x8e000000 0x900000>; | |
| phandle = <0x142>; | |
| channel@2 { | |
| compatible = "sprd,spool"; | |
| reg = <0x02>; | |
| label = "imsbr_data"; | |
| sprd,tx-blksize = <0x5f4>; | |
| sprd,tx-blknum = <0x40>; | |
| sprd,rx-blksize = <0x5f4>; | |
| sprd,rx-blknum = <0x40>; | |
| phandle = <0x143>; | |
| }; | |
| channel@3 { | |
| compatible = "sprd,spool"; | |
| reg = <0x03>; | |
| label = "imsbr_ctrl"; | |
| sprd,tx-blksize = <0x80>; | |
| sprd,tx-blknum = <0x40>; | |
| sprd,rx-blksize = <0x80>; | |
| sprd,rx-blknum = <0x40>; | |
| phandle = <0x144>; | |
| }; | |
| channel@4 { | |
| compatible = "sprd,spipe"; | |
| reg = <0x04>; | |
| label = "spipe_lte"; | |
| sprd,ringnr = <0x14>; | |
| sprd,size-rxbuf = <0x1000>; | |
| sprd,size-txbuf = <0x1000>; | |
| phandle = <0x145>; | |
| }; | |
| channel@6 { | |
| compatible = "sprd,spipe"; | |
| reg = <0x06>; | |
| label = "stty_lte"; | |
| sprd,ringnr = <0x20>; | |
| sprd,size-rxbuf = <0x800>; | |
| sprd,size-txbuf = <0x800>; | |
| phandle = <0x146>; | |
| }; | |
| channel@21 { | |
| compatible = "sprd,spipe"; | |
| reg = <0x15>; | |
| label = "sdiag_lte"; | |
| sprd,ringnr = <0x01>; | |
| sprd,size-rxbuf = <0x20000>; | |
| sprd,size-txbuf = <0x8000>; | |
| phandle = <0x147>; | |
| }; | |
| channel@5 { | |
| compatible = "sprd,spool"; | |
| reg = <0x05>; | |
| label = "slog_lte"; | |
| sprd,tx-blksize = <0x00>; | |
| sprd,tx-blknum = <0x00>; | |
| sprd,rx-blksize = <0x1000>; | |
| sprd,rx-blknum = <0x100>; | |
| phandle = <0x148>; | |
| }; | |
| route@0 { | |
| compatible = "sprd,sipx"; | |
| reg = <0x00>; | |
| label = "sipx_lte"; | |
| sprd,dl-pool = <0x800>; | |
| sprd,dl-ack-pool = <0x40>; | |
| sprd,ul-pool = <0x800>; | |
| sprd,ul-ack-pool = <0x400>; | |
| phandle = <0xa2>; | |
| }; | |
| channel@7 { | |
| compatible = "sprd,seth"; | |
| reg = <0x07>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x149>; | |
| }; | |
| channel@8 { | |
| compatible = "sprd,seth"; | |
| reg = <0x08>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x14a>; | |
| }; | |
| channel@9 { | |
| compatible = "sprd,seth"; | |
| reg = <0x09>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x14b>; | |
| }; | |
| channel@18 { | |
| compatible = "sprd,seth"; | |
| reg = <0x12>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x14c>; | |
| }; | |
| channel@19 { | |
| compatible = "sprd,seth"; | |
| reg = <0x13>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x14d>; | |
| }; | |
| channel@20 { | |
| compatible = "sprd,seth"; | |
| reg = <0x14>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x14e>; | |
| }; | |
| channel@24 { | |
| compatible = "sprd,seth"; | |
| reg = <0x18>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x14f>; | |
| }; | |
| channel@25 { | |
| compatible = "sprd,seth"; | |
| reg = <0x19>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x150>; | |
| }; | |
| channel@26 { | |
| compatible = "sprd,seth"; | |
| reg = <0x1a>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x151>; | |
| }; | |
| channel@27 { | |
| compatible = "sprd,seth"; | |
| reg = <0x1b>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x152>; | |
| }; | |
| channel@28 { | |
| compatible = "sprd,seth"; | |
| reg = <0x1c>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x153>; | |
| }; | |
| channel@29 { | |
| compatible = "sprd,seth"; | |
| reg = <0x1d>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x154>; | |
| }; | |
| channel@30 { | |
| compatible = "sprd,seth"; | |
| reg = <0x1e>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x155>; | |
| }; | |
| channel@31 { | |
| compatible = "sprd,seth"; | |
| reg = <0x1f>; | |
| sprd,router = <0xa2>; | |
| sprd,blknum = <0x100>; | |
| phandle = <0x156>; | |
| }; | |
| channel@42 { | |
| compatible = "sprd,pubcp-dvfs"; | |
| sprd,core_id = <0x00>; | |
| sprd,devices-num = <0x01>; | |
| sprd,devices-name = "core_axi"; | |
| sprd,devices-id = <0x00>; | |
| phandle = <0x157>; | |
| }; | |
| }; | |
| core@6 { | |
| compatible = "sprd,sipc"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x06>; | |
| label = "sipc-pmsys"; | |
| mboxes = <0xa1 0x01 0x00 0xa1 0x06 0x01>; | |
| sprd,smem-info = <0xdc00 0x2000bc00 0x2000 0x88000000 0x18000000 0x40000>; | |
| phandle = <0x158>; | |
| channel@4 { | |
| compatible = "sprd,spipe"; | |
| label = "spipe_pm"; | |
| reg = <0x04>; | |
| sprd,ringnr = <0x02>; | |
| sprd,size-rxbuf = <0xb00>; | |
| sprd,size-txbuf = <0x180>; | |
| phandle = <0x159>; | |
| }; | |
| channel@5 { | |
| compatible = "sprd,spipe"; | |
| label = "slog_pm"; | |
| reg = <0x05>; | |
| sprd,ringnr = <0x01>; | |
| sprd,size-rxbuf = <0x500>; | |
| sprd,size-txbuf = <0x00>; | |
| phandle = <0x15a>; | |
| }; | |
| channel@6 { | |
| compatible = "sprd,spipe"; | |
| label = "sctl_pm"; | |
| reg = <0x06>; | |
| sprd,ringnr = <0x01>; | |
| sprd,size-rxbuf = <0x40>; | |
| sprd,size-txbuf = <0x20>; | |
| phandle = <0x15b>; | |
| }; | |
| channel@7 { | |
| compatible = "sprd,spipe"; | |
| label = "data0_gnss"; | |
| reg = <0x07>; | |
| sprd,smem = <0x01>; | |
| sprd,ringnr = <0x01>; | |
| sprd,size-rxbuf = <0x20000>; | |
| sprd,size-txbuf = <0x18000>; | |
| phandle = <0x15c>; | |
| }; | |
| channel@41 { | |
| compatible = "sprd,spipe"; | |
| label = "stime_pm"; | |
| reg = <0x29>; | |
| sprd,ringnr = <0x01>; | |
| sprd,size-rxbuf = <0x40>; | |
| sprd,size-txbuf = <0x80>; | |
| phandle = <0x15d>; | |
| }; | |
| }; | |
| sbridge-log { | |
| compatible = "sprd,slog_bridge"; | |
| sprd,name = "slog_bridge"; | |
| sprd,tx_is_usb = <0x01>; | |
| sprd,tx_dst = <0x00>; | |
| sprd,rx_dst = <0x05>; | |
| sprd,priority = <0x56>; | |
| }; | |
| time_sync { | |
| compatible = "sprd,time-sync"; | |
| }; | |
| }; | |
| sprd-pcm-audio { | |
| compatible = "unisoc,sharkl5-pcm-platform\0unisoc,sharkl5pro-pcm-platform"; | |
| #sound-dai-cells = <0x00>; | |
| dmas = <0xa3 0x01 0xa3 0x02 0xa3 0x03 0xa3 0x04 0xa3 0x11 0xa3 0x12 0xa3 0x0f 0xa3 0x10 0xa3 0x0e 0xa3 0x08 0xa3 0x0c 0xa3 0x09 0xa3 0x0d 0xa3 0x08 0xa3 0x0b 0xa3 0x06 0xa3 0x0e 0xa3 0x0e 0xa3 0x0c 0xa3 0x06>; | |
| dma-names = "normal_p_l\0normal_p_r\0normal_c_l\0normal_c_r\0normal23_p_l\0normal23_p_r\0normal23_c_l\0normal23_c_r\0dspcap_c\0a2dppcm_p\0voice_c\0fast_p\0loop_c\0loop_p\0voip_c\0voip_p\0dspfmcap_c\0dspbtscocap_c\0recognise_c\0voice_pcm_p"; | |
| phandle = <0xb8>; | |
| }; | |
| sprd-compr-audio { | |
| compatible = "unisoc,sharkl5-compress-platform\0unisoc,sharkl5pro-compress-platform"; | |
| #sound-dai-cells = <0x00>; | |
| dmas = <0xa3 0x05 0xa3 0x00>; | |
| dma-names = "compr_dma_stage0\0compr_dma_stage1"; | |
| phandle = <0xba>; | |
| }; | |
| sprd-fe-dai { | |
| compatible = "unisoc,fe-dai"; | |
| #sound-dai-cells = <0x01>; | |
| phandle = <0xb9>; | |
| }; | |
| sprd-routing-pcm { | |
| compatible = "unisoc,pcm-routing"; | |
| #sound-dai-cells = <0x00>; | |
| phandle = <0xbb>; | |
| }; | |
| audio-sipc { | |
| compatible = "unisoc,audio_sipc"; | |
| mboxes = <0xa1 0x05 0x00>; | |
| }; | |
| audio-mem-mgr { | |
| compatible = "unisoc,audio-mem-sharkl5\0unisoc,audio-mem-sharkl5pro"; | |
| ddr32-ap-dsp-map-offset = <0x00>; | |
| sprd,ddr32-dma = <0x87400000 0x300000>; | |
| sprd,ddr32-dspmemdump = <0x87700000 0x80000>; | |
| sprd,cmdaddr = <0x87780000 0x400>; | |
| sprd,smsg-addr = <0x87780400 0xa10>; | |
| sprd,shmaddr-aud-str = <0x87780e10 0x400>; | |
| sprd,shmaddr-dsp-vbc = <0x87781210 0x1400>; | |
| sprd,shmaddr-nxp = <0x87782610 0x400>; | |
| sprd,shmaddr-dsp-smartpa = <0x87782a10 0x1000>; | |
| sprd,shmaddr-reg-dump = <0x87783a10 0x400>; | |
| sprd,iram-ap-base = <0x33800000>; | |
| sprd,iram-dsp-base = <0x1800000>; | |
| sprd,offload-addr = <0x33800000 0x5c00>; | |
| sprd,normal-captue-linklilst-node1 = <0x33805e00 0x200>; | |
| sprd,normal-captue-data = <0x33806000 0x1e00>; | |
| sprd,normal-captue-linklilst-node2 = <0x33807e00 0x200>; | |
| sprd,audcp-aon-iram = <0xa4>; | |
| memory-region = <0xa5 0xa6>; | |
| }; | |
| audio-dsp-dump@0 { | |
| compatible = "unisoc,audio_dsp_log"; | |
| sprd-usemem-type = <0x05>; | |
| sprd-dst = [01]; | |
| sprd-channel = [04]; | |
| sprd-rxblocknum = <0x08>; | |
| sprd-rxblocksize = <0x2000>; | |
| }; | |
| audio-dsp-dump@1 { | |
| compatible = "unisoc,audio_dsp_pcm"; | |
| sprd-usemem-type = <0x05>; | |
| sprd-dst = [01]; | |
| sprd-channel = [03]; | |
| sprd-rxblocknum = <0x08>; | |
| sprd-rxblocksize = <0x2000>; | |
| }; | |
| audio-dsp-dump@2 { | |
| compatible = "unisoc,audio_dsp_mem"; | |
| sprd-usemem-type = <0x09>; | |
| sprd-usemem-bytes = <0x80000>; | |
| sprd-dst = [01]; | |
| sprd-channel = [05]; | |
| sprd,dspdumpmem = <0x33000000 0x10000 0xa400 0x1000 0x89300000 0x5f000>; | |
| }; | |
| audio_pipe_voice { | |
| compatible = "unisoc,audio_pipe_voice"; | |
| sprd,writesync = <0x00>; | |
| sprd,maxuserwritebufsize = <0x00>; | |
| sprd,channel = <0x02>; | |
| }; | |
| audio_pipe_effect { | |
| compatible = "unisoc,audio_pipe_effect"; | |
| sprd,writesync = <0x01>; | |
| sprd,maxuserwritebufsize = <0x400>; | |
| sprd,channel = <0x08>; | |
| }; | |
| audio_pipe_voiceproc { | |
| compatible = "unisoc,audio_pipe_recordproc"; | |
| sprd,writesync = <0x01>; | |
| sprd,maxuserwritebufsize = <0x400>; | |
| sprd,channel = <0x09>; | |
| }; | |
| audio_pipe_bthal { | |
| compatible = "unisoc,audio_pipe_bthal"; | |
| sprd,writesync = <0x00>; | |
| sprd,maxuserwritebufsize = <0x00>; | |
| sprd,channel = <0x0b>; | |
| }; | |
| audiocp_dvfs { | |
| compatible = "unisoc,sharkl5-audcp-dvfs\0unisoc,sharkl5pro-audcp-dvfs"; | |
| sprd,channel = <0x0a>; | |
| }; | |
| audiocp_boot { | |
| compatible = "unisoc,sharkl5-audcp-boot\0unisoc,sharkl5pro-audcp-boot"; | |
| sysshutdown = <0x02 0x60 0x2000000>; | |
| coreshutdown = <0x02 0x5c 0x1000000>; | |
| deepsleep = <0x02 0xcc 0x80000>; | |
| corereset = <0x02 0xb0 0x400>; | |
| sysreset = <0x02 0xb0 0x200>; | |
| reset_sel = <0x02 0x7a4 0xff>; | |
| sysstatus = <0x02 0xb8 0xff000000>; | |
| corestatus = <0x02 0x10c 0xff>; | |
| sleepstatus = <0x02 0xd4 0xf000>; | |
| bootprotect = <0x0b 0x78 0xffff>; | |
| bootvector = <0x0b 0x140 0xffffffff>; | |
| bootaddress_sel = <0x0b 0x144 0x01>; | |
| }; | |
| apipe-pcm { | |
| compatible = "unisoc,apipe"; | |
| }; | |
| apipe-cmd-in { | |
| compatible = "unisoc,apipe"; | |
| }; | |
| apipe-cmd-out { | |
| compatible = "unisoc,apipe"; | |
| }; | |
| ext-26m { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x18cba80>; | |
| clock-output-names = "ext-26m"; | |
| phandle = <0x04>; | |
| }; | |
| ext-32k { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x8000>; | |
| clock-output-names = "ext-32k"; | |
| phandle = <0x29>; | |
| }; | |
| ext-4m { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = "\0=\t"; | |
| clock-output-names = "ext-4m"; | |
| phandle = <0x78>; | |
| }; | |
| rco-100m { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x5f5e100>; | |
| clock-output-names = "rco-100m"; | |
| phandle = <0x77>; | |
| }; | |
| dphy-273m { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x1045a640>; | |
| clock-output-names = "dphy-273m"; | |
| phandle = <0x15e>; | |
| }; | |
| dphy-204m8 { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = "\f5\0"; | |
| clock-output-names = "dphy-204m8"; | |
| phandle = <0x15f>; | |
| }; | |
| efuse@800 { | |
| compatible = "sprd,ums312-cache-efuse\0sprd,ums512-cache-efuse"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x00 0x800 0x00 0x3ff>; | |
| phandle = <0x160>; | |
| uid-start@5c { | |
| reg = <0x5c 0x04>; | |
| phandle = <0x161>; | |
| }; | |
| uid-end@58 { | |
| reg = <0x58 0x04>; | |
| phandle = <0x162>; | |
| }; | |
| thm0-sign@38 { | |
| reg = <0x38 0x01>; | |
| bits = <0x00 0x01>; | |
| phandle = <0x3b>; | |
| }; | |
| thm0-ratio@38 { | |
| reg = <0x38 0x01>; | |
| bits = <0x01 0x07>; | |
| phandle = <0x3c>; | |
| }; | |
| thm0-sen0@39 { | |
| reg = <0x39 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x3d>; | |
| }; | |
| thm0-sen1@41 { | |
| reg = <0x41 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x3e>; | |
| }; | |
| thm0-sen2@40 { | |
| reg = <0x40 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x3f>; | |
| }; | |
| thm0-sen3@43 { | |
| reg = <0x43 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x40>; | |
| }; | |
| thm0-sen4@42 { | |
| reg = <0x42 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x41>; | |
| }; | |
| thm1-sign@3c { | |
| reg = <0x3c 0x01>; | |
| bits = <0x00 0x01>; | |
| phandle = <0x42>; | |
| }; | |
| thm1-ratio@3c { | |
| reg = <0x3c 0x01>; | |
| bits = <0x01 0x07>; | |
| phandle = <0x43>; | |
| }; | |
| thm1-sen0@3d { | |
| reg = <0x3d 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x44>; | |
| }; | |
| thm1-sen1@2f { | |
| reg = <0x2f 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x45>; | |
| }; | |
| thm1-sen2@2e { | |
| reg = <0x2e 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x46>; | |
| }; | |
| thm1-sen3@29 { | |
| reg = <0x29 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x47>; | |
| }; | |
| thm1-sen4@28 { | |
| reg = <0x28 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x48>; | |
| }; | |
| thm1-sen4@2b { | |
| reg = <0x2b 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x49>; | |
| }; | |
| thm2-sign@3e { | |
| reg = <0x3e 0x01>; | |
| bits = <0x00 0x01>; | |
| phandle = <0x4a>; | |
| }; | |
| thm2-ratio@3e { | |
| reg = <0x3e 0x01>; | |
| bits = <0x01 0x07>; | |
| phandle = <0x4b>; | |
| }; | |
| thm2-sen0@3f { | |
| reg = <0x3f 0x01>; | |
| bits = <0x00 0x08>; | |
| phandle = <0x4c>; | |
| }; | |
| cpu-flag@50 { | |
| reg = <0x50 0x04>; | |
| phandle = <0x0e>; | |
| }; | |
| dvfs-bin@17 { | |
| reg = <0x17 0x01>; | |
| bits = <0x00 0x03>; | |
| phandle = <0xb2>; | |
| }; | |
| dvfs-bin@1b { | |
| reg = <0x1b 0x01>; | |
| bits = <0x00 0x03>; | |
| phandle = <0xb3>; | |
| }; | |
| dvfs-bin@13 { | |
| reg = <0x13 0x01>; | |
| bits = <0x00 0x03>; | |
| phandle = <0x163>; | |
| }; | |
| }; | |
| modem@0 { | |
| compatible = "unisoc,modem"; | |
| syscon0 = <0x0b 0xff 0x00>; | |
| syscon1 = <0x02 0xff 0x00>; | |
| syscon2 = <0x0b 0x8c 0x01>; | |
| syscon3 = <0x0b 0xff 0x00>; | |
| syscon4 = <0x0b 0xff 0x00>; | |
| syscon-names = "shutdown\0deepsleep\0corereset\0sysreset\0getstatus"; | |
| sprd,version = <0x02>; | |
| phandle = <0x164>; | |
| }; | |
| modem@1 { | |
| compatible = "unisoc,modem"; | |
| sprd,decoup = "cproc-use-decoup"; | |
| syscon0 = <0x02 0x58 0x2000000>; | |
| syscon1 = <0x02 0xcc 0x40000>; | |
| syscon2 = <0x0b 0x174 0x400>; | |
| syscon3 = <0x02 0xb0 0x02>; | |
| syscon4 = <0x0b 0xff 0x00>; | |
| syscon5 = <0x02 0xb0 0xc000>; | |
| syscon-names = "shutdown\0deepsleep\0corereset\0sysreset\0getstatus\0dspreset"; | |
| sprd,version = <0x02>; | |
| phandle = <0x165>; | |
| }; | |
| cp_dump { | |
| compatible = "sprd,cp_dump"; | |
| sprd,sys-bus-ctrl-sp = <0x0b 0x124 0x01>; | |
| }; | |
| cpus { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x00>; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x90>; | |
| }; | |
| core1 { | |
| cpu = <0x92>; | |
| }; | |
| core2 { | |
| cpu = <0x94>; | |
| }; | |
| core3 { | |
| cpu = <0x96>; | |
| }; | |
| core4 { | |
| cpu = <0x98>; | |
| }; | |
| core5 { | |
| cpu = <0x9a>; | |
| }; | |
| }; | |
| cluster1 { | |
| core0 { | |
| cpu = <0x9c>; | |
| }; | |
| core1 { | |
| cpu = <0x9e>; | |
| }; | |
| }; | |
| }; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a55"; | |
| reg = <0x00 0x00>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa7>; | |
| cpufreq-data-v1 = <0xa8>; | |
| capacity-dmips-mhz = <0x220>; | |
| dynamic-power-coefficient = <0x66>; | |
| #cooling-cells = <0x02>; | |
| sugov_slack_timer; | |
| phandle = <0x90>; | |
| }; | |
| cpu@100 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a55"; | |
| reg = <0x00 0x100>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa7>; | |
| cpufreq-data-v1 = <0xa8>; | |
| capacity-dmips-mhz = <0x220>; | |
| dynamic-power-coefficient = <0x66>; | |
| phandle = <0x92>; | |
| }; | |
| cpu@200 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a55"; | |
| reg = <0x00 0x200>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa7>; | |
| cpufreq-data-v1 = <0xa8>; | |
| capacity-dmips-mhz = <0x220>; | |
| dynamic-power-coefficient = <0x66>; | |
| phandle = <0x94>; | |
| }; | |
| cpu@300 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a55"; | |
| reg = <0x00 0x300>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa7>; | |
| cpufreq-data-v1 = <0xa8>; | |
| capacity-dmips-mhz = <0x220>; | |
| dynamic-power-coefficient = <0x66>; | |
| phandle = <0x96>; | |
| }; | |
| cpu@400 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a55"; | |
| reg = <0x00 0x400>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa7>; | |
| cpufreq-data-v1 = <0xa8>; | |
| capacity-dmips-mhz = <0x220>; | |
| dynamic-power-coefficient = <0x66>; | |
| phandle = <0x98>; | |
| }; | |
| cpu@500 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a55"; | |
| reg = <0x00 0x500>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa7>; | |
| cpufreq-data-v1 = <0xa8>; | |
| capacity-dmips-mhz = <0x220>; | |
| dynamic-power-coefficient = <0x66>; | |
| phandle = <0x9a>; | |
| }; | |
| cpu@600 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a75"; | |
| reg = <0x00 0x600>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa9>; | |
| cpufreq-data-v1 = <0xaa>; | |
| capacity-dmips-mhz = <0x400>; | |
| dynamic-power-coefficient = <0x1f5>; | |
| #cooling-cells = <0x02>; | |
| phandle = <0x9c>; | |
| }; | |
| cpu@700 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a75"; | |
| reg = <0x00 0x700>; | |
| enable-method = "psci"; | |
| cpu-idle-states = <0xa9>; | |
| cpufreq-data-v1 = <0xaa>; | |
| capacity-dmips-mhz = <0x400>; | |
| dynamic-power-coefficient = <0x1f5>; | |
| phandle = <0x9e>; | |
| }; | |
| }; | |
| idle-states { | |
| entry-method = "arm,psci"; | |
| lit_core_pd { | |
| compatible = "arm,idle-state"; | |
| entry-latency-us = <0x3e8>; | |
| exit-latency-us = <0x1f4>; | |
| min-residency-us = <0x9c4>; | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x10000>; | |
| phandle = <0xa7>; | |
| }; | |
| big_core_pd { | |
| compatible = "arm,idle-state"; | |
| entry-latency-us = <0xfa0>; | |
| exit-latency-us = <0xfa0>; | |
| min-residency-us = <0x2710>; | |
| local-timer-stop; | |
| arm,psci-suspend-param = <0x10000>; | |
| phandle = <0xa9>; | |
| }; | |
| }; | |
| power-debug { | |
| compatible = "sprd,power-debug-sharkl5pro"; | |
| sprd,enable = <0x01>; | |
| sprd,scan-interval = <0x1e>; | |
| sprd,sys-ap-ahb = <0x09>; | |
| sprd,sys-ap-apb = <0x03>; | |
| sprd,sys-pmu-apb = <0x02>; | |
| sprd,sys-aon-apb = <0x0b>; | |
| sprd,sys-ap-intc = <0xab 0xac 0xad 0xae 0xaf 0xb0>; | |
| phandle = <0x166>; | |
| }; | |
| debugstat { | |
| compatible = "sprd,debugstat-sharkl5pro"; | |
| phandle = <0x167>; | |
| }; | |
| psci { | |
| compatible = "arm,psci-0.2"; | |
| method = "smc"; | |
| }; | |
| opp-table0 { | |
| sprd,hw-dvfs-device = <0xb1>; | |
| temp-threshold = <0x41>; | |
| nvmem-cell-names = "dvfs_bin"; | |
| nvmem-cells = <0xb2>; | |
| sprd,multi-version; | |
| cpufreq-cluster-cpumask = <0x3f>; | |
| transition_delay_us = <0x1f4>; | |
| operating-points = <0x96000 0xb8a1a 0xbb800 0xb8a1a 0xeadd0 0xb8a1a 0x1174c0 0xb8a1a 0x12c000 0xc042c 0x169d10 0xd59f8 0x177000 0xd9701 0x1a2f20 0xe8b25 0x1bc560 0xf1da1 0x1e8c50 0x100590>; | |
| operating-points-ff = <0x96000 0xb71b0 0xbb800 0xcf850 0xeadd0 0xcf850 0x1174c0 0xcf850 0x12c000 0xcf850 0x169d10 0xf4240 0x177000 0xf4240 0x1a2f20 0xf4240 0x1bc560 0xf4240>; | |
| operating-points-ff-65 = <0x96000 0xb71b0 0xbb800 0xcf850 0xeadd0 0xcf850 0x1174c0 0xcf850 0x12c000 0xcf850 0x169d10 0x100590 0x177000 0x100590 0x1a2f20 0x100590 0x1bc560 0x100590>; | |
| operating-points-T610 = <0x96000 0xb7de5 0xbb800 0xb7de5 0xeadd0 0xb7de5 0x1174c0 0xc7209 0x12c000 0xcec1b 0x169d10 0xe41e7 0x177000 0xe8b25 0x1a2f20 0xf7f49 0x1bc560 0x100590>; | |
| operating-points-T610-ff = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb71b0 0x169d10 0xc4135 0x177000 0xc8a73 0x1a2f20 0xd7e97 0x1bc560 0xe1113>; | |
| operating-points-T610-tt = <0x96000 0xb8a1a 0xbb800 0xb8a1a 0xeadd0 0xb8a1a 0x1174c0 0xb8a1a 0x12c000 0xb8a1a 0x169d10 0xcdfe6 0x177000 0xd2924 0x1a2f20 0xe1d48 0x1bc560 0xeafc4>; | |
| operating-points-T610-ss = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xbaeb9 0x12c000 0xc28cb 0x169d10 0xd7e97 0x177000 0xdc7d5 0x1a2f20 0xebbf9 0x1bc560 0xf4240>; | |
| operating-points-T610-od = <0x96000 0xb7de5 0xbb800 0xb7de5 0xeadd0 0xb7de5 0x1174c0 0xc7209 0x12c000 0xcec1b 0x169d10 0xe41e7 0x177000 0xe8b25 0x1a2f20 0xf7f49 0x1bc560 0x100590>; | |
| operating-points-T610-ff-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb71b0 0x169d10 0xc65d4 0x177000 0xcbb47 0x1a2f20 0xdc7d5 0x1bc560 0xe5a51>; | |
| operating-points-T610-tt-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb964f 0x169d10 0xd10ba 0x177000 0xd59f8 0x1a2f20 0xe6686 0x1bc560 0xef902>; | |
| operating-points-T610-ss-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xbc723 0x12c000 0xc4135 0x169d10 0xdaf6b 0x177000 0xdf8a9 0x1a2f20 0xf0537 0x1bc560 0xf97b3>; | |
| operating-points-T610-od-65 = <0x96000 0xb8a1a 0xbb800 0xb8a1a 0xeadd0 0xb8a1a 0x1174c0 0xc8a73 0x12c000 0xd0485 0x169d10 0xe72bb 0x177000 0xebbf9 0x1a2f20 0xfc887>; | |
| operating-points-T618 = <0x96000 0xb8a1a 0xbb800 0xb8a1a 0xeadd0 0xb8a1a 0x1174c0 0xb8a1a 0x12c000 0xc042c 0x169d10 0xd59f8 0x177000 0xd9701 0x1a2f20 0xe8b25 0x1bc560 0xf1da1 0x1e8c50 0x100590>; | |
| operating-points-T618-ff = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb71b0 0x169d10 0xc96a8 0x177000 0xcd3b1 0x1a2f20 0xdc7d5 0x1bc560 0xe5a51 0x1e8c50 0xf4240>; | |
| operating-points-T618-tt = <0x96000 0xb8a1a 0xbb800 0xb8a1a 0xeadd0 0xb8a1a 0x1174c0 0xb8a1a 0x12c000 0xc042c 0x169d10 0xd59f8 0x177000 0xd9701 0x1a2f20 0xe8b25 0x1bc560 0xf1da1 0x1e8c50 0x100590>; | |
| operating-points-T618-ff-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb71b0 0x169d10 0xcbb47 0x177000 0xd0485 0x1a2f20 0xe1113 0x1bc560 0xea38f 0x1e8c50 0xf97b3>; | |
| operating-points-T618-tt-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xba284 0x12c000 0xc1c96 0x169d10 0xd7e97 0x177000 0xdd40a 0x1a2f20 0xed463 0x1bc560 0xf66df>; | |
| operating-points-T700 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb8a1a 0x169d10 0xcdfe6 0x177000 0xd2924 0x1a2f20 0xe1d48 0x1bc560 0xeafc4>; | |
| operating-points-T700-ff = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb71b0 0x169d10 0xc4135 0x177000 0xc8a73 0x1a2f20 0xd7e97 0x1bc560 0xe1113>; | |
| operating-points-T700-tt = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb8a1a 0x169d10 0xcdfe6 0x177000 0xd2924 0x1a2f20 0xe1d48 0x1bc560 0xeafc4>; | |
| operating-points-T700-ff-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb71b0 0x169d10 0xc65d4 0x177000 0xcbb47 0x1a2f20 0xdc7d5 0x1bc560 0xe5a51>; | |
| operating-points-T700-tt-65 = <0x96000 0xb71b0 0xbb800 0xb71b0 0xeadd0 0xb71b0 0x1174c0 0xb71b0 0x12c000 0xb964f 0x169d10 0xd10ba 0x177000 0xd59f8 0x1a2f20 0xe6686 0x1bc560 0xef902>; | |
| phandle = <0xa8>; | |
| }; | |
| opp-table1 { | |
| sprd,hw-dvfs-device = <0xb1>; | |
| temp-threshold = <0x41>; | |
| nvmem-cell-names = "dvfs_bin"; | |
| nvmem-cells = <0xb3>; | |
| sprd,multi-version; | |
| cpufreq-cluster-cpumask = <0xc0>; | |
| transition_delay_us = <0x1f4>; | |
| operating-points = <0x12c000 0xb71b0 0x169d10 0xcf850 0x177000 0xd4670 0x1a94b0 0xe7ef0 0x1c9080 0xf4240 0x1e8c50 0x100590>; | |
| operating-points-ff = <0x12c000 0xb71b0 0x169d10 0xcf850 0x177000 0xf4240 0x1a94b0 0xf4240 0x1c9080 0xf4240 0x1e8c50 0xf4240>; | |
| operating-points-ff-65 = <0x12c000 0xb71b0 0x169d10 0xc3500 0x177000 0x10c8e0 0x1a94b0 0x10c8e0 0x1c9080 0x10c8e0 0x1e8c50 0x10c8e0>; | |
| operating-points-T610 = <0x12c000 0xc8320 0x169d10 0xe09c0 0x177000 0xe57e0 0x1a94b0 0xf9060 0x1bc560 0x100590>; | |
| operating-points-T610-ff = <0x12c000 0xb71b0 0x169d10 0xc0df0 0x177000 0xc5c10 0x1a94b0 0xd9490 0x1bc560 0xe09c0>; | |
| operating-points-T610-tt = <0x12c000 0xb71b0 0x169d10 0xcaa30 0x177000 0xcf850 0x1a94b0 0xe30d0 0x1bc560 0xea600>; | |
| operating-points-T610-ss = <0x12c000 0xbbfd0 0x169d10 0xd4670 0x177000 0xd9490 0x1a94b0 0xecd10 0x1bc560 0xf4240>; | |
| operating-points-T610-od = <0x12c000 0xc8320 0x169d10 0xe09c0 0x177000 0xe57e0 0x1a94b0 0xf9060 0x1bc560 0x100590>; | |
| operating-points-T610-ff-65 = <0x12c000 0xb71b0 0x169d10 0xc3500 0x177000 0xc8320 0x1a94b0 0xde2b0 0x1bc560 0xe57e0>; | |
| operating-points-T610-tt-65 = <0x12c000 0xb71b0 0x169d10 0xcd140 0x177000 0xd1f60 0x1a94b0 0xe7ef0 0x1bc560 0xef420>; | |
| operating-points-T610-ss-65 = <0x12c000 0xbbfd0 0x169d10 0xd6d80 0x177000 0xdbba0 0x1a94b0 0xf1b30 0x1bc560 0xf9060>; | |
| operating-points-T610-od-65 = <0x12c000 0xcaa30 0x169d10 0xe30d0 0x177000 0xea600 0x1a94b0 0xfde80>; | |
| operating-points-T618 = <0x12c000 0xb71b0 0x169d10 0xcf850 0x177000 0xd4670 0x1a94b0 0xe7ef0 0x1c9080 0xf4240 0x1e8c50 0x100590>; | |
| operating-points-T618-ff = <0x12c000 0xb71b0 0x169d10 0xc3500 0x177000 0xc8320 0x1a94b0 0xdbba0 0x1c9080 0xe7ef0 0x1e8c50 0xf4240>; | |
| operating-points-T618-tt = <0x12c000 0xb71b0 0x169d10 0xcf850 0x177000 0xd4670 0x1a94b0 0xe7ef0 0x1c9080 0xf4240 0x1e8c50 0x100590>; | |
| operating-points-T618-ff-65 = <0x12c000 0xb71b0 0x169d10 0xc3500 0x177000 0xc8320 0x1a94b0 0xde2b0 0x1c9080 0xecd10 0x1e8c50 0xf9060>; | |
| operating-points-T618-tt-65 = <0x12c000 0xb71b0 0x169d10 0xcf850 0x177000 0xd6d80 0x1a94b0 0xea600 0x1c9080 0xf9060>; | |
| operating-points-T700 = <0x12c000 0xb71b0 0x169d10 0xcaa30 0x177000 0xcf850 0x1a94b0 0xe30d0 0x1bc560 0xea600>; | |
| operating-points-T700-ff = <0x12c000 0xb71b0 0x169d10 0xc0df0 0x177000 0xc5c10 0x1a94b0 0xd9490 0x1bc560 0xe09c0>; | |
| operating-points-T700-tt = <0x12c000 0xb71b0 0x169d10 0xcaa30 0x177000 0xcf850 0x1a94b0 0xe30d0 0x1bc560 0xea600>; | |
| operating-points-T700-ff-65 = <0x12c000 0xb71b0 0x169d10 0xc3500 0x177000 0xc8320 0x1a94b0 0xde2b0 0x1bc560 0xe57e0>; | |
| operating-points-T700-tt-65 = <0x12c000 0xb71b0 0x169d10 0xcd140 0x177000 0xd1f60 0x1a94b0 0xe7ef0 0x1bc560 0xef420>; | |
| phandle = <0xaa>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>; | |
| arm,no-tick-in-suspend; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupts = <0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04>; | |
| }; | |
| autotest { | |
| compatible = "sprd,autotest"; | |
| sprd,pinctrl = <0xb4>; | |
| phandle = <0x168>; | |
| }; | |
| sprd-gsp { | |
| compatible = "sprd,gsp-r8p0-sharkl5pro"; | |
| core-cnt = <0x01>; | |
| io-cnt = <0x07>; | |
| cores = <0xb5>; | |
| phandle = <0xbf>; | |
| }; | |
| sp-iram@dc00 { | |
| reg = <0x00 0xdc00 0x00 0x2000>; | |
| phandle = <0x169>; | |
| }; | |
| audcp-iram@a400 { | |
| reg = <0x00 0xa400 0x00 0x1000>; | |
| phandle = <0xa4>; | |
| }; | |
| sprd-headset { | |
| compatible = "unisoc,headset"; | |
| status = "okay"; | |
| sprd,jack-type = <0x01>; | |
| io-channels = <0x33 0x14>; | |
| io-channel-names = "headmic_in_little"; | |
| gpios = <0x31 0x06 0x00>; | |
| sprd,debounce-interval = <0x0a>; | |
| gpio-names = "aud_int_all"; | |
| sprd,3pole-adc-threshold = <0xb86>; | |
| sprd,adc-gnd = <0x148>; | |
| sprd,half-adc-gnd = <0x64>; | |
| sprd,coefficient = <0xd7f28>; | |
| sprd,irq-threshold-button = <0x04>; | |
| nvmem-cells = <0x2e 0xb6>; | |
| nvmem-cell-names = "hp_adc_fir_calib\0hp_adc_sec_calib"; | |
| sprd,spk-route-hp; | |
| phandle = <0xb7>; | |
| sprd,headset-button@0 { | |
| adc-min = <0x00>; | |
| adc-max = <0x1e0>; | |
| code = <0xe2>; | |
| }; | |
| sprd,headset-button@1 { | |
| adc-min = <0x1e1>; | |
| adc-max = <0x3de>; | |
| code = <0x73>; | |
| }; | |
| sprd,headset-button@2 { | |
| adc-min = <0x3df>; | |
| adc-max = <0x9c4>; | |
| code = <0x72>; | |
| }; | |
| }; | |
| sound@0 { | |
| compatible = "unisoc,vbc-v4-codec-sc2730"; | |
| status = "okay"; | |
| sprd-audio-card,name = "sprdphone-sc2730"; | |
| sprd-audio-card,routing = "HPMIC Pin\0HP Mic Jack\0MIC Pin\0Mic Jack\0MIC2 Pin\0Aux Mic Jack\0HeadPhone Jack\0HP Pin\0Ext Spk\0HP Pin\0Ext Spk1\0HP Pin\0Ext Spk\0SPK Pin\0Ext Spk1\0SPK Pin\0Ext Ear\0EAR Pin\0Ext Ear\0SPK Pin\0Ext Ear\0HP Pin"; | |
| sprd-audio-card,headset = <0xb7>; | |
| sprd,syscon-agcp-ahb = <0x69>; | |
| sprd,spk-ext-pa-info = <0x00 0x00 0x00 0x00>; | |
| sprd,spk-ext-pa-gpio = <0x67 0x09 0x01>; | |
| phandle = <0x16a>; | |
| sprd-audio-card,dai-link@0 { | |
| link-name = "FE_NORMAL_AP01"; | |
| stream-name = "FE_ST_NORMAL_AP01"; | |
| ignore-suspend = <0x00>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x00>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@1 { | |
| link-name = "FE_NORMAL_AP23"; | |
| stream-name = "FE_ST_NORMAL_AP23"; | |
| ignore-suspend = <0x00>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x01>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@2 { | |
| link-name = "FE_CAPTURE_DSP"; | |
| stream-name = "FE_ST_CAPTURE_DSP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x02>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@3 { | |
| link-name = "FE_FAST"; | |
| stream-name = "FE_ST_FAST"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x03>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@4 { | |
| link-name = "FE_OFFLOAD"; | |
| stream-name = "FE_ST_OFFLOAD"; | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xba>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x04>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@5 { | |
| link-name = "FE_VOICE"; | |
| stream-name = "FE_ST_VOICE"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x05>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@6 { | |
| link-name = "FE_VOIP"; | |
| stream-name = "FE_ST_VOIP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x06>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@7 { | |
| link-name = "FE_FM"; | |
| stream-name = "FE_ST_FM"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x07>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@8 { | |
| link-name = "FE_FM_C"; | |
| stream-name = "FE_ST_FM_C"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x08>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@9 { | |
| link-name = "FE_VOICE_C"; | |
| stream-name = "FE_ST_VOICE_C"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x09>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@10 { | |
| link-name = "FE_LOOP"; | |
| stream-name = "FE_ST_LOOP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x0a>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@11 { | |
| link-name = "FE_A2DP_OFFLOAD"; | |
| stream-name = "FE_ST_A2DP_OFFLOAD"; | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xba>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x0b>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@12 { | |
| link-name = "FE_A2DP_PCM"; | |
| stream-name = "FE_ST_A2DP_PCM"; | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x0c>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@13 { | |
| link-name = "FE_CAPTURE_FM_DSP"; | |
| stream-name = "FE_ST_CAPTURE_FM_DSP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x0d>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@14 { | |
| link-name = "FE_CAPTURE_BTSCO_DSP"; | |
| stream-name = "FE_ST_CAPTURE_BTSCO_DSP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x0e>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@15 { | |
| link-name = "FE_FM_DSP"; | |
| stream-name = "FE_ST_FM_DSP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x0f>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@16 { | |
| link-name = "FE_DUMP"; | |
| stream-name = "FE_ST_DUMP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x10>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@17 { | |
| link-name = "FE_BTCAP_AP"; | |
| stream-name = "FE_ST_BTCAP_AP"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x11>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@18 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_NORMAL_AP01_CODEC"; | |
| stream-name = "BE_ST_NORMAL_AP01_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x00>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@19 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_NORMAL_AP23_CODEC"; | |
| stream-name = "BE_ST_NORMAL_AP23_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x01>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x01>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@20 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_CAPTURE_DSP_CODEC"; | |
| stream-name = "BE_ST_CAPTURE_DSP_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x02>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@21 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FAST_CODEC"; | |
| stream-name = "BE_ST_FAST_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x03>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@22 { | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| link-name = "BE_OFFLOAD_CODEC"; | |
| stream-name = "BE_ST_OFFLOAD_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x04>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@23 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOICE_CODEC"; | |
| stream-name = "BE_ST_VOICE_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x05>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@24 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOIP_CODEC"; | |
| stream-name = "BE_ST_VOIP_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x06>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@25 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FM_CODEC"; | |
| stream-name = "BE_ST_FM_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x07>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@26 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_LOOP_CODEC"; | |
| stream-name = "BE_ST_LOOP_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x08>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@27 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FM_DSP_CODEC"; | |
| stream-name = "BE_ST_FM_DSP_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x09>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@28 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_NORMAL_AP01_USB"; | |
| stream-name = "BE_ST_NORMAL_AP01_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x0a>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@29 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_NORMAL_AP23_USB"; | |
| stream-name = "BE_ST_NORMAL_AP23_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x0b>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@30 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_CAPTURE_DSP_USB"; | |
| stream-name = "BE_ST_CAPTURE_DSP_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x0c>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@31 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FAST_USB"; | |
| stream-name = "BE_ST_FAST_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x0d>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@32 { | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| link-name = "BE_OFFLOAD_USB"; | |
| stream-name = "BE_ST_OFFLOAD_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x0e>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@33 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOICE_USB"; | |
| stream-name = "BE_ST_VOICE_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x0f>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@34 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOIP_USB"; | |
| stream-name = "BE_ST_VOIP_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x10>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@35 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FM_USB"; | |
| stream-name = "BE_ST_FM_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x11>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@36 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_LOOP_USB"; | |
| stream-name = "BE_ST_LOOP_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x12>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@37 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FM_DSP_USB"; | |
| stream-name = "BE_ST_FM_DSP_USB"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x13>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@38 { | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| link-name = "BE_OFFLOAD_A2DP"; | |
| stream-name = "BE_ST_OFFLOAD_A2DP"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x14>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@39 { | |
| ignore-suspend = <0x00>; | |
| ignore-pmdown-time = <0x00>; | |
| link-name = "BE_PCM_A2DP"; | |
| stream-name = "BE_ST_PCM_A2DP"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x15>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@40 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOICE_BT"; | |
| stream-name = "BE_ST_VOICE_BT"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x16>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@41 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOIP_BT"; | |
| stream-name = "BE_ST_VOIP_BT"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x17>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@42 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_LOOP_BT"; | |
| stream-name = "BE_ST_LOOP_BT"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x18>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@43 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_BT_C"; | |
| stream-name = "BE_ST_BT_C"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x19>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@44 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOICE_C"; | |
| stream-name = "BE_ST_VOICE_C"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x1a>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@45 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FM_C"; | |
| stream-name = "BE_ST_FM_C"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x1b>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@46 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_CAPTURE_FM_DSP"; | |
| stream-name = "BE_ST_CAPTURE_FM_DSP"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x1c>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@47 { | |
| ignore-suspend = <0x00>; | |
| link-name = "BE_CAPTURE_BTSCO_DSP"; | |
| stream-name = "BE_ST_CAPTURE_BTSCO_DSP"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x1d>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@48 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_DUMP"; | |
| stream-name = "BE_DUMP"; | |
| no-pcm = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x1e>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@49 { | |
| link-name = "FE_TEST_CODEC"; | |
| stream-name = "FE_ST_TEST_CODEC"; | |
| ignore-suspend = <0x00>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x13>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@50 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_TEST_CODEC"; | |
| stream-name = "BE_TEST_CODEC"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| dpcm-capture = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x1f>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@51 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_FAST_BTSCO"; | |
| stream-name = "BE_ST_FAST_BTSCO"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x20>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@52 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_NORMAL_AP01_BTSCO"; | |
| stream-name = "BE_ST_NORMAL_AP01_BTSCO"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x21>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@68 { | |
| link-name = "FE_VOICE_PCM_P"; | |
| stream-name = "FE_ST_VOICE_PCM_P"; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| trigger = <0x01 0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x12>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@69 { | |
| ignore-suspend = <0x01>; | |
| link-name = "BE_VOICE_PCM_P"; | |
| stream-name = "BE_ST_VOICE_PCM_P"; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| be-id = <0x00>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x2d>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@90 { | |
| link-name = "FE_MM_P"; | |
| stream-name = "FE_ST_MM_P"; | |
| be-id = <0x00>; | |
| trigger = <0x01 0x01>; | |
| ignore-suspend = <0x01>; | |
| dynamic = <0x01>; | |
| dpcm-playback = <0x01>; | |
| plat { | |
| sound-dai = <0xb8>; | |
| }; | |
| cpu { | |
| sound-dai = <0xb9 0x18>; | |
| }; | |
| codec { | |
| sound-dai = <0x00 0x00>; | |
| }; | |
| }; | |
| sprd-audio-card,dai-link@91 { | |
| link-name = "BE_FAST_P_SMART_AMP"; | |
| stream-name = "BE_ST_FAST_P_SMART_AMP"; | |
| be-id = <0x00>; | |
| ignore-suspend = <0x00>; | |
| no-pcm = <0x01>; | |
| dpcm-playback = <0x01>; | |
| plat { | |
| sound-dai = <0xbb>; | |
| }; | |
| cpu { | |
| sound-dai = <0xbc 0x39>; | |
| }; | |
| codec { | |
| sound-dai = <0xbd 0x00>; | |
| }; | |
| }; | |
| }; | |
| display-subsystem { | |
| compatible = "sprd,display-subsystem"; | |
| ports = <0xbe>; | |
| gsp = <0xbf>; | |
| }; | |
| ion { | |
| compatible = "sprd,ion"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| phandle = <0x16b>; | |
| }; | |
| sprd-map-user { | |
| compatible = "unisoc,map-user"; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| phandle = <0x16c>; | |
| ddrbist-mem@0x80000000 { | |
| reg = <0x00 0x80000000 0x00 0x1000>; | |
| phandle = <0x16d>; | |
| }; | |
| sysdumpinfo-mem@80001000 { | |
| reg = <0x00 0x80001000 0x00 0x1000>; | |
| phandle = <0x16e>; | |
| }; | |
| audio-mem@87400000 { | |
| reg = <0x00 0x87400000 0x00 0x400000>; | |
| phandle = <0xa5>; | |
| }; | |
| sp_ddr-mem@88000000 { | |
| reg = <0x00 0x88000000 0x00 0x300000>; | |
| phandle = <0x16f>; | |
| }; | |
| audiodsp-mem@89000000 { | |
| reg = <0x00 0x89000000 0x00 0x600000>; | |
| phandle = <0xa6>; | |
| }; | |
| cp-mem@89600000 { | |
| reg = <0x00 0x89600000 0x00 0x4900000>; | |
| phandle = <0x170>; | |
| }; | |
| sipc-mem@8e000000 { | |
| reg = <0x00 0x8e000000 0x00 0x900000>; | |
| phandle = <0x171>; | |
| }; | |
| iq-mem@90000000 { | |
| compatible = "sprd,iq-mem"; | |
| reg = <0x00 0x90000000 0x00 0x4000000>; | |
| phandle = <0xc0>; | |
| }; | |
| sml-mem@94000000 { | |
| reg = <0x00 0x94000000 0x00 0x40000>; | |
| phandle = <0x172>; | |
| }; | |
| tos-mem@94040000 { | |
| reg = <0x00 0x94040000 0x00 0x5fc0000>; | |
| phandle = <0x173>; | |
| }; | |
| sh-mem@9a000000 { | |
| reg = <0x00 0x9a000000 0x00 0x100000>; | |
| phandle = <0xd4>; | |
| }; | |
| uboot_log-mem { | |
| reg = <0x00 0x9de80000 0x00 0x80000>; | |
| phandle = <0x174>; | |
| }; | |
| sysdump-uboot@9f000000 { | |
| reg = <0x00 0x9f000000 0x00 0x1000000>; | |
| phandle = <0x175>; | |
| }; | |
| cma_share@f00000000 { | |
| compatible = "shared-dma-pool"; | |
| reg = <0x00 0xf0000000 0x00 0x3000000>; | |
| reusable; | |
| linux,cma-default; | |
| phandle = <0x176>; | |
| }; | |
| rebootescrow@0xfff70000 { | |
| no-map; | |
| reg = <0x00 0xfff70000 0x00 0x10000>; | |
| }; | |
| ramoops@fff80000 { | |
| compatible = "ramoops"; | |
| reg = <0x00 0xfff80000 0x00 0x40000>; | |
| record-size = <0x8000>; | |
| console-size = <0x8000>; | |
| pmsg-size = <0x8000>; | |
| phandle = <0x177>; | |
| }; | |
| }; | |
| sprd-iq { | |
| compatible = "sprd,iq"; | |
| sprd,region = <0xc0>; | |
| sprd,mapping-offs = <0x00>; | |
| }; | |
| rebootescrow@0 { | |
| compatible = "pmem-region"; | |
| reg = <0x00 0xfff70000 0x00 0x10000>; | |
| }; | |
| dpu-dvfs { | |
| compatible = "sprd,hwdvfs-dpu-sharkl5pro"; | |
| sprd,hw-dfs-en = <0x00>; | |
| sprd,work-index-def = <0x04>; | |
| sprd,idle-index-def = <0x01>; | |
| sprd,freq-upd-delay-en = <0x00>; | |
| sprd,freq-upd-hdsk-en = <0x01>; | |
| operating-points = <0x25800 0xaae60 0x2ee00 0xaae60 0x3e800 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0>; | |
| phandle = <0x178>; | |
| }; | |
| vsp-dvfs { | |
| compatible = "sprd,hwdvfs-vsp-sharkl5pro"; | |
| sprd,dvfs-work-freq = <0x16e36000>; | |
| sprd,dvfs-idle-freq = <0xf424000>; | |
| sprd,dvfs-enable-flag = <0x01>; | |
| sprd,freq-upd-delay-en = <0x00>; | |
| sprd,freq-upd-hdsk-en = <0x01>; | |
| operating-points = <0x3e800 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0>; | |
| phandle = <0x179>; | |
| }; | |
| vdsp-dvfs { | |
| compatible = "sprd,hwdvfs-vdsp-sharkl5pro"; | |
| sprd,hw-dfs-en = <0x00>; | |
| sprd,work-index-def = <0x02>; | |
| sprd,idle-index-def = <0x01>; | |
| sprd,freq-upd-delay-en = <0x00>; | |
| sprd,freq-upd-hdsk-en = <0x01>; | |
| operating-points = <0x3e800 0xaae60 0x5dc00 0xaae60 0x7d000 0xaae60 0x96000 0xb71b0 0xbb800 0xb71b0 0xe4840 0xc3500>; | |
| clock-names = "vdsp_twpll\0vdsp_lpll\0vdsp_isppll"; | |
| clocks = <0x07 0x00 0x07 0x15 0x07 0x1a>; | |
| phandle = <0x17a>; | |
| }; | |
| firmware { | |
| android { | |
| compatible = "android,firmware"; | |
| vbmeta { | |
| compatible = "android,vbmeta"; | |
| parts = "vbmeta,boot,vendor_boot,dtbo,l_modem,pm_sys,l_ldsp,l_gdsp,l_agdsp,l_cdsp"; | |
| }; | |
| }; | |
| }; | |
| scene-frequency { | |
| compatible = "sprd,ddr-dvfs"; | |
| freq-num = <0x08>; | |
| phandle = <0x17b>; | |
| }; | |
| sprd-sensorhub { | |
| compatible = "sprd,sharkl5Pro-sensorhub\0sprd,sensor-hub"; | |
| }; | |
| thermal-zones { | |
| phandle = <0x17c>; | |
| soc-thmzone { | |
| polling-delay-passive = <0x64>; | |
| polling-delay = <0x3e8>; | |
| sustainable-power = <0x16a8>; | |
| thermal-sensors = <0xc1 0x00>; | |
| phandle = <0x17d>; | |
| trips { | |
| trip-point@0 { | |
| temperature = <0x11170>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| phandle = <0x17e>; | |
| }; | |
| trip-point@1 { | |
| temperature = <0x14c08>; | |
| hysteresis = <0x3e8>; | |
| type = "passive"; | |
| phandle = <0xc2>; | |
| }; | |
| soc_crit { | |
| temperature = <0x1adb0>; | |
| hysteresis = <0x7d0>; | |
| type = "critical"; | |
| phandle = <0x17f>; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0xc2>; | |
| contribution = <0x400>; | |
| cooling-device = <0x90 0xffffffff 0xffffffff>; | |
| }; | |
| map1 { | |
| trip = <0xc2>; | |
| contribution = <0x2aa>; | |
| cooling-device = <0x9c 0xffffffff 0xffffffff>; | |
| }; | |
| map2 { | |
| trip = <0xc2>; | |
| contribution = <0x400>; | |
| cooling-device = <0xc3 0xffffffff 0xffffffff>; | |
| }; | |
| map3 { | |
| trip = <0xc2>; | |
| contribution = <0x400>; | |
| cooling-device = <0xc4 0xffffffff 0xffffffff>; | |
| }; | |
| map4 { | |
| trip = <0xc2>; | |
| contribution = <0x400>; | |
| cooling-device = <0xc5 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| prometheus6-tzone0 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc6 0x00>; | |
| phandle = <0xd0>; | |
| }; | |
| prometheus6-tzone1 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc6 0x01>; | |
| phandle = <0xd1>; | |
| }; | |
| prometheus7-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc6 0x02>; | |
| phandle = <0xd2>; | |
| }; | |
| ank0-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc6 0x03>; | |
| phandle = <0xca>; | |
| }; | |
| ank1-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc6 0x04>; | |
| phandle = <0xcb>; | |
| }; | |
| gpu-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc7 0x00>; | |
| phandle = <0xd3>; | |
| }; | |
| ank2-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc7 0x01>; | |
| phandle = <0xcc>; | |
| }; | |
| ank3-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc7 0x02>; | |
| phandle = <0xcd>; | |
| }; | |
| ank4-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc7 0x03>; | |
| phandle = <0xce>; | |
| }; | |
| ank5-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc7 0x04>; | |
| phandle = <0xcf>; | |
| }; | |
| cputop-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc7 0x05>; | |
| phandle = <0x180>; | |
| }; | |
| gpuank2-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc8 0x00>; | |
| phandle = <0x181>; | |
| }; | |
| osctsen-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc9 0x00>; | |
| phandle = <0x182>; | |
| }; | |
| outtsen-thmzone { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0xc9 0x01>; | |
| phandle = <0x183>; | |
| }; | |
| }; | |
| virtual-sensor@0 { | |
| compatible = "virtual-thermal"; | |
| #thermal-sensor-cells = <0x01>; | |
| thmzone-cells = <0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3>; | |
| phandle = <0xc1>; | |
| }; | |
| cooling-devices { | |
| cluster0-cooling { | |
| compatible = "sprd,cluster-cooling"; | |
| #cooling-cells = <0x02>; | |
| sprd,efuse-block7 = <0x07>; | |
| sprd,efuse-block15 = <0x0f>; | |
| sprd,leak-core = <0x02 0x55 0x74d>; | |
| sprd,leak-cluster = <0x02 0x55 0x9dc>; | |
| sprd,core-temp-scale = <0x12 0xfffffb00 0x1780e 0xfffe136c>; | |
| sprd,core-voltage-scale = <0x1e0 0xfffffc4b 0x2e2 0xffffff56>; | |
| sprd,cluster-temp-scale = <0x16 0xfffff8e2 0x1d638 0xfff97a5e>; | |
| sprd,cluster-voltage-scale = <0x313 0xfffff9a9 0x4cf 0xfffffed9>; | |
| sprd,efuse-switch = <0x00>; | |
| sprd,hotplug-period = <0x0a>; | |
| sprd,min-cpufreq = "\0\t`"; | |
| sprd,min-cpunum = <0x06>; | |
| sprd,max-temp = <0x15f90>; | |
| sprd,core-base = <0xf6e>; | |
| sprd,cluster-base = <0xf38>; | |
| sprd,dynamic-core = <0x39f 0x3e8 0x3e8>; | |
| sprd,dynamic-cluster = <0xf6 0x3e8 0x3e8>; | |
| phandle = <0xc3>; | |
| }; | |
| cluster1-cooling { | |
| compatible = "sprd,cluster-cooling"; | |
| #cooling-cells = <0x02>; | |
| sprd,efuse-block7 = <0x07>; | |
| sprd,efuse-block15 = <0x0f>; | |
| sprd,leak-core = <0x08 0x55 0x7c0>; | |
| sprd,leak-cluster = <0x08 0x55 0x810>; | |
| sprd,core-temp-scale = <0x12 0xfffffb1b 0x16c58 0xfffd800d>; | |
| sprd,core-voltage-scale = <0x16c 0xfffffd3c 0x23b 0xffffff80>; | |
| sprd,cluster-temp-scale = <0x16 0xfffff8e2 0x1d638 0xfff97a5e>; | |
| sprd,cluster-voltage-scale = <0x313 0xfffff9a9 0x4cf 0xfffffed9>; | |
| sprd,efuse-switch = <0x00>; | |
| sprd,hotplug-period = <0x0a>; | |
| sprd,min-cpufreq = <0x12c000>; | |
| sprd,min-cpunum = <0x00>; | |
| sprd,max-temp = <0x14c08>; | |
| sprd,core-base = <0x2d20>; | |
| sprd,cluster-base = <0xf38>; | |
| sprd,dynamic-core = <0x11cc 0x3e8 0x3e8>; | |
| sprd,dynamic-cluster = <0xf6 0x3e8 0x3e8>; | |
| phandle = <0xc4>; | |
| }; | |
| }; | |
| gpu-cooling-devices { | |
| gpu-cooling0 { | |
| compatible = "sprd,mali-power-model"; | |
| #cooling-cells = <0x02>; | |
| sprd,efuse-block7 = <0x07>; | |
| sprd,efuse-block15 = <0x0f>; | |
| sprd,leak-core = <0x02 0x55 0x74d>; | |
| sprd,leak-cluster = <0x02 0x55 0x9dc>; | |
| sprd,temp-scale = <0x19 0xfffff764 0x2015f 0xfff4b1f8>; | |
| sprd,voltage-scale = <0x321 0xfffff950 0x537 0xfffffebc>; | |
| sprd,hotplug-period = <0x00>; | |
| sprd,core-base = <0x247f>; | |
| sprd,cluster-base = <0x3c6>; | |
| sprd,dynamic-core = <0x1bee 0x352 0x320>; | |
| sprd,dynamic-cluster = <0x17b0 0x300 0x384>; | |
| phandle = <0xc5>; | |
| }; | |
| }; | |
| isp-dvfs { | |
| compatible = "sprd,hwdvfs-isp"; | |
| operating-points = <0x3e800 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0 0x72420 0xb71b0 0x7d000 0xb71b0>; | |
| phandle = <0x184>; | |
| }; | |
| cpp-dvfs { | |
| compatible = "sprd,hwdvfs-cpp"; | |
| operating-points = <0x12c00 0xaae60 0x1f400 0xaae60 0x3e800 0xaae60 0x5dc00 0xb71b0>; | |
| phandle = <0x185>; | |
| }; | |
| jpg-dvfs { | |
| compatible = "sprd,hwdvfs-jpg"; | |
| operating-points = <0x12c00 0xaae60 0x1f400 0xaae60 0x3e800 0xaae60 0x5dc00 0xb71b0>; | |
| phandle = <0x186>; | |
| }; | |
| fd-dvfs { | |
| compatible = "sprd,hwdvfs-fd"; | |
| operating-points = <0x12c00 0xaae60 0x2ee00 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0>; | |
| phandle = <0x187>; | |
| }; | |
| mtx-dvfs { | |
| compatible = "sprd,hwdvfs-mtx"; | |
| operating-points = <0x12c00 0xaae60 0x1f400 0xaae60 0x3e800 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0 0x72420 0xb71b0 0x7d000 0xc3500>; | |
| phandle = <0x188>; | |
| }; | |
| dcam-if-dvfs { | |
| compatible = "sprd,hwdvfs-dcam-if"; | |
| operating-points = <0x2ee00 0xaae60 0x3e800 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0 0x72420 0xb71b0>; | |
| phandle = <0x189>; | |
| }; | |
| dcam-axi-dvfs { | |
| compatible = "sprd,hwdvfs-dcam-axi"; | |
| operating-points = <0x3e800 0xaae60 0x4b000 0xaae60 0x5dc00 0xb71b0 0x72420 0xb71b0>; | |
| phandle = <0x18a>; | |
| }; | |
| mmsys-dvfs { | |
| compatible = "sprd,hwdvfs-mmsys"; | |
| sprd,topdvfs_controller = <0x5b>; | |
| phandle = <0x18b>; | |
| }; | |
| trusty { | |
| compatible = "sprd,trusty-smc-v1"; | |
| irq { | |
| compatible = "sprd,trusty-irq-v1"; | |
| interrupt-templates = <0x01 0x00 0x00 0x00 0x01 0x01 0x01 0x08 0x01 0x01 0x00 0x04>; | |
| interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0xdf 0x02>; | |
| }; | |
| virtio { | |
| compatible = "sprd,trusty-virtio-v1"; | |
| }; | |
| log { | |
| compatible = "sprd,trusty-log-v1"; | |
| }; | |
| sprd-tshm { | |
| compatible = "sprd,tshm"; | |
| memory-region = <0xd4>; | |
| }; | |
| }; | |
| memory@80000000 { | |
| device_type = "memory"; | |
| reg = <0x00 0x80000000 0x00 0x80000000>; | |
| }; | |
| chosen { | |
| stdout-path = "serial1:115200n8"; | |
| bootargs = "earlycon console=ttySPRD1,115200n8 loglevel=1 init=/init root=/dev/ram0 rw printk.devkmsg=on androidboot.boot_devices=soc/soc:ap-apb/71400000.sdio dummy_hcd.num=0 swiotlb=1 initcall_debug=1"; | |
| phandle = <0x18c>; | |
| }; | |
| dvfs-dcdc-cpu0-cfg { | |
| pmic-type-num = <0x00>; | |
| slew-rate = <0x249f>; | |
| tuning-latency-us = <0x00>; | |
| phandle = <0x53>; | |
| }; | |
| dvfs-dcdc-cpu1-cfg { | |
| chnl-i2c-used; | |
| third-pmic-used; | |
| pmic-type-num = <0x02>; | |
| slew-rate = <0xfa0>; | |
| tuning-latency-us = <0x00>; | |
| phandle = <0x54>; | |
| }; | |
| extcon-gpio { | |
| compatible = "linux,extcon-usb-gpio"; | |
| vbus-gpio = <0x31 0x00 0x00>; | |
| phandle = <0x18d>; | |
| }; | |
| __symbols__ { | |
| dpu_qos = "/qos/qos@0"; | |
| dcam_qos = "/qos/mm/qos@0"; | |
| isp_qos = "/qos/mm/qos@1"; | |
| cpp_qos = "/qos/mm/qos@2"; | |
| fd_qos = "/qos/mm/qos@3"; | |
| jpg_qos = "/qos/mm/qos@4"; | |
| mm_qos_threshold = "/qos/mm/qos@5"; | |
| soc = "/soc"; | |
| ap_ahb_regs = "/soc/syscon@20100000"; | |
| pub_apb_regs = "/soc/syscon@31050000"; | |
| top_dvfs_apb_regs = "/soc/syscon@322a0000"; | |
| ap_intc0_regs = "/soc/syscon@32310000"; | |
| ap_intc1_regs = "/soc/syscon@32320000"; | |
| ap_intc2_regs = "/soc/syscon@32330000"; | |
| ap_intc3_regs = "/soc/syscon@32340000"; | |
| ap_intc4_regs = "/soc/syscon@32350000"; | |
| ap_intc5_regs = "/soc/syscon@32360000"; | |
| anlg_phy_g0_regs = "/soc/syscon@32390000"; | |
| anlg_phy_g2_regs = "/soc/syscon@323b0000"; | |
| anlg_phy_g3_regs = "/soc/syscon@323c0000"; | |
| anlg_phy_gc_regs = "/soc/syscon@323e0000"; | |
| anlg_phy_g10_regs = "/soc/syscon@323f0000"; | |
| aon_apb_regs = "/soc/syscon@327d0000"; | |
| pmu_apb_regs = "/soc/syscon@327e0000"; | |
| vsp_pd = "/soc/vsp-power-domain"; | |
| audcp_apb_regs = "/soc/syscon@3350d000"; | |
| audcp_ahb_regs = "/soc/syscon@335e0000"; | |
| gpu_apb_regs = "/soc/syscon@60100000"; | |
| gpu_dvfs_apb_regs = "/soc/syscon@60110000"; | |
| mm_ahb_regs = "/soc/syscon@62200000"; | |
| uart0 = "/soc/apb@70000000/serial@0"; | |
| uart1 = "/soc/apb@70000000/serial@100000"; | |
| i2c0 = "/soc/apb@70000000/i2c@300000"; | |
| i2c1 = "/soc/apb@70000000/i2c@400000"; | |
| i2c2 = "/soc/apb@70000000/i2c@500000"; | |
| i2c3 = "/soc/apb@70000000/i2c@600000"; | |
| i2c4 = "/soc/apb@70000000/i2c@700000"; | |
| spi0 = "/soc/apb@70000000/spi@800000"; | |
| spi1 = "/soc/apb@70000000/spi@900000"; | |
| spi2 = "/soc/apb@70000000/spi@a00000"; | |
| spi3 = "/soc/apb@70000000/spi@b00000"; | |
| apsys_dvfs = "/soc/apb@70000000/apsys-dvfs@1700000"; | |
| ap_apb_regs = "/soc/syscon@71000000"; | |
| ap_dma = "/soc/ap-ahb/dma-controller@20000000"; | |
| vdsp = "/soc/ap-ahb/vdsp@20900000"; | |
| gpu = "/soc/mm/gpu@60000000"; | |
| mm_domain = "/soc/mm/power-domain@327e0024"; | |
| mipi_csi_phy0 = "/soc/mm/mipi-csi-phy0"; | |
| mipi_csi_phy1 = "/soc/mm/mipi-csi-phy1"; | |
| mipi_csi_phy1_m = "/soc/mm/mipi-csi-phy1-m"; | |
| mipi_csi_phy1_s = "/soc/mm/mipi-csi-phy1-s"; | |
| mipi_csi_phy2 = "/soc/mm/mipi-csi-phy2"; | |
| csi0 = "/soc/mm/csi00@62300000"; | |
| csi1 = "/soc/mm/csi01@62400000"; | |
| csi2 = "/soc/mm/csi02@62500000"; | |
| isp = "/soc/mm/isp@62000000"; | |
| iommu_isp = "/soc/mm/iommu@62000000"; | |
| dcam = "/soc/mm/dcam@62900000"; | |
| iommu_dcam = "/soc/mm/iommu@62900000"; | |
| cpp = "/soc/mm/cpp@62800000"; | |
| iommu_cpp = "/soc/mm/iommu@62800000"; | |
| iommu_fd = "/soc/mm/iommu@62a00000"; | |
| jpg = "/soc/mm/jpg-codec@62700000"; | |
| iommu_jpg = "/soc/mm/iommu@62700300"; | |
| dpu = "/soc/mm/dpu@20300000"; | |
| dpu_port = "/soc/mm/dpu@20300000/port"; | |
| dpu_out = "/soc/mm/dpu@20300000/port/endpoint"; | |
| gsp_core0 = "/soc/mm/gsp@20300000"; | |
| iommu_dispc = "/soc/mm/iommu@20300000"; | |
| dsi = "/soc/mm/dsi@20400000"; | |
| dsi_out = "/soc/mm/dsi@20400000/ports/port@0/endpoint"; | |
| dsi_in = "/soc/mm/dsi@20400000/ports/port@1/endpoint"; | |
| panel = "/soc/mm/dsi@20400000/panel"; | |
| panel_in = "/soc/mm/dsi@20400000/panel/port@1/endpoint"; | |
| dphy = "/soc/mm/dphy"; | |
| dphy_out = "/soc/mm/dphy/ports/port@0/endpoint"; | |
| dphy_in = "/soc/mm/dphy/ports/port@1/endpoint"; | |
| vsp = "/soc/mm/video-codec@20500000"; | |
| iommu_vsp = "/soc/mm/iommu@20500000"; | |
| iommu_vdsp_msti = "/soc/mm/iommu@20600000"; | |
| iommu_vdsp_mstd = "/soc/mm/iommu@20700000"; | |
| iommu_vdsp_idma = "/soc/mm/iommu@20800000"; | |
| iommu_vdsp_vdma = "/soc/mm/iommu@20a00000"; | |
| eic_debounce = "/soc/aon/gpio@32000000"; | |
| eic_latch = "/soc/aon/gpio@32000080"; | |
| eic_async = "/soc/aon/gpio@320000a0"; | |
| eic_sync = "/soc/aon/gpio@320000c0"; | |
| aon_i2c0 = "/soc/aon/i2c@32060000"; | |
| ap_gpio = "/soc/aon/gpio@32070000"; | |
| mailbox = "/soc/aon/mailbox@320a0000"; | |
| adi_bus = "/soc/aon/spi@32100000"; | |
| sc2730_pmic = "/soc/aon/spi@32100000/pmic@0"; | |
| pmic_wdt = "/soc/aon/spi@32100000/pmic@0/watchdog@40"; | |
| pmic_eic = "/soc/aon/spi@32100000/pmic@0/gpio@280"; | |
| adc_bcal = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@0"; | |
| adc_scal = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@1"; | |
| pddelta_calib = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@2"; | |
| pdrc_calib = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@6"; | |
| pdref_calib = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@1e"; | |
| fgu_calib = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@3"; | |
| typec_cc1_cal = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@d1"; | |
| typec_cc2_cal = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@d2"; | |
| aud_pabst_vcal = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@20"; | |
| neg_cp_efuse = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@22"; | |
| headset_adc_fir = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@14"; | |
| headset_adc_sec = "/soc/aon/spi@32100000/pmic@0/efuse@300/calib@16"; | |
| pmic_typec = "/soc/aon/spi@32100000/pmic@0/typec@380"; | |
| pmic_fchg = "/soc/aon/spi@32100000/pmic@0/fchg@400"; | |
| pmic_adc = "/soc/aon/spi@32100000/pmic@0/adc@504"; | |
| pmic_fgu = "/soc/aon/spi@32100000/pmic@0/fgu@c00"; | |
| pmic_pd = "/soc/aon/spi@32100000/pmic@0/pd@e00"; | |
| sprd_audio_codec_ana = "/soc/aon/spi@32100000/pmic@0/audio-codec@1000"; | |
| vddcpu = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_CPU"; | |
| vddgpu = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_GPU"; | |
| vddcore = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_CORE"; | |
| vddmodem = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_MODEM"; | |
| vddmem = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_MEM"; | |
| vddmemq = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_MEMQ"; | |
| vddgen0 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_GEN0"; | |
| vddgen1 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_GEN1"; | |
| vddsram = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/DCDC_SRAM"; | |
| avdd18 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_AVDD18"; | |
| vddrf18 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDRF18"; | |
| vddcamio = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDCAMIO"; | |
| vddwcn = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDWCN"; | |
| vddcamd1 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDCAMD1"; | |
| vddcamd0 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDCAMD0"; | |
| vddrf1v25 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDRF1V25"; | |
| avdd12 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_AVDD12"; | |
| vddcama0 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDCAMA0"; | |
| vddcama1 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDCAMA1"; | |
| vddcammot = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDCAMMOT"; | |
| vddsim2 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDSIM2"; | |
| vddemmccore = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDEMMCCORE"; | |
| vddsdcore = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDSDCORE"; | |
| vddsdio = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDSDIO"; | |
| vdd28 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDD28"; | |
| vddwifipa = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDWIFIPA"; | |
| vdd18_dcxo = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDD18_DCXO"; | |
| vddusb33 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDUSB33"; | |
| vddldo0 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDLDO0"; | |
| vddldo1 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDLDO1"; | |
| vddldo2 = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDLDO2"; | |
| vddkpled = "/soc/aon/spi@32100000/pmic@0/power-controller@1800/LDO_VDDKPLED"; | |
| pmic_tsensor = "/soc/aon/spi@32100000/pmic@0/tsensor@1b34"; | |
| osc_tsensor = "/soc/aon/spi@32100000/pmic@0/tsensor@1b34/osc-tsensor@0"; | |
| tout_tsensor = "/soc/aon/spi@32100000/pmic@0/tsensor@1b34/tout-tsensor@1"; | |
| ap_thm0 = "/soc/aon/thermal@32200000"; | |
| ap_thm1 = "/soc/aon/thermal@32210000"; | |
| ap_thm2 = "/soc/aon/thermal@32220000"; | |
| ap_efuse = "/soc/aon/efuse@32240000"; | |
| pwms = "/soc/aon/pwm@32260000"; | |
| sprd_hardware_cpufreq = "/soc/aon/hardware-dvfs-platform"; | |
| topdvfs_controller = "/soc/aon/topdvfsctrl@322a0000"; | |
| dcdc_cpu0 = "/soc/aon/topdvfsctrl@322a0000/dcdc-cpu0"; | |
| dcdc_cpu1 = "/soc/aon/topdvfsctrl@322a0000/dcdc-cpu1"; | |
| dcdc_mm = "/soc/aon/topdvfsctrl@322a0000/dcdc-mm"; | |
| audcp_sys = "/soc/aon/topdvfsctrl@322a0000/dcdc-mm/audcp-sys"; | |
| gpu_sys = "/soc/aon/topdvfsctrl@322a0000/dcdc-mm/gpu-sys"; | |
| mm_sys = "/soc/aon/topdvfsctrl@322a0000/dcdc-mm/mm-sys"; | |
| dcdc_modem = "/soc/aon/topdvfsctrl@322a0000/dcdc-modem"; | |
| pubcp_sys = "/soc/aon/topdvfsctrl@322a0000/dcdc-modem/pubcp-sys"; | |
| wtlcp_sys = "/soc/aon/topdvfsctrl@322a0000/dcdc-modem/wtlcp-sys"; | |
| ap_sys = "/soc/aon/topdvfsctrl@322a0000/dcdc-modem/ap-sys"; | |
| cpudvfs_dev = "/soc/aon/cpudvfs-dev@322a8000"; | |
| lit_core_cluster = "/soc/aon/cpudvfs-dev@322a8000/lit-core-cluster"; | |
| big_core_cluster = "/soc/aon/cpudvfs-dev@322a8000/big-core-cluster"; | |
| scu_cluster = "/soc/aon/cpudvfs-dev@322a8000/scu-cluster"; | |
| periph_cluster = "/soc/aon/cpudvfs-dev@322a8000/periph-cluster"; | |
| gic_cluster = "/soc/aon/cpudvfs-dev@322a8000/gic-cluster"; | |
| mpll_0 = "/soc/aon/cpudvfs-dev@322a8000/mpll-ananke"; | |
| mpll_1 = "/soc/aon/cpudvfs-dev@322a8000/mpll-prometheus"; | |
| mpll_2 = "/soc/aon/cpudvfs-dev@322a8000/mpll-scu"; | |
| apb_bm = "/soc/aon/apb-busmonitor@32370000"; | |
| hsphy = "/soc/aon/hsphy@323b0000"; | |
| pin_controller = "/soc/aon/pinctrl@32450000"; | |
| vbc_iis3_0 = "/soc/aon/pinctrl@32450000/vbc-iis3-0"; | |
| vbc_iism0_0 = "/soc/aon/pinctrl@32450000/vbc-iism0-0"; | |
| vbc_iis_to_pad = "/soc/aon/pinctrl@32450000/vbc-iis-to-pad"; | |
| vbc_iis_to_aon_usb = "/soc/aon/pinctrl@32450000/vbc-iis-to-aon-usb"; | |
| vbc_iism0_1 = "/soc/aon/pinctrl@32450000/vbc-iism0-1"; | |
| vbc_iism0_3 = "/soc/aon/pinctrl@32450000/vbc-iism0-3"; | |
| vbc_iis0_3 = "/soc/aon/pinctrl@32450000/vbc-iis0-3"; | |
| vbc_iis1_3 = "/soc/aon/pinctrl@32450000/vbc-iis1-3"; | |
| vbc_iis2_3 = "/soc/aon/pinctrl@32450000/vbc-iis2-3"; | |
| vbc_iis3_3 = "/soc/aon/pinctrl@32450000/vbc-iis3-3"; | |
| ap_iis0_3 = "/soc/aon/pinctrl@32450000/ap-iis0-3"; | |
| djtag = "/soc/aon/djtag@324e0000"; | |
| modem_dbg_log = "/soc/aon/modem-dbg-log@324f0000"; | |
| hwlock = "/soc/aon/hwspinlock@327f0000"; | |
| usb = "/soc/aon/usb@5fff0000"; | |
| socid = "/soc/aon/socid@402e00e0"; | |
| vbc_v4 = "/soc/agcp/vbc@33480000"; | |
| agcp_dma = "/soc/agcp/dma-controller@33580000"; | |
| sprd_audio_codec_dig = "/soc/agcp/audio-codec@33750000"; | |
| mpu = "/soc/pub/dmc-mpu@31030000"; | |
| ptm_trace = "/soc/pub/ptm@31060000"; | |
| dmc_controller = "/soc/pub/dmc-controller@31050000"; | |
| gic = "/soc/interrupt-controller@12000000"; | |
| apahb_gate = "/soc/apahb-gate"; | |
| ap_clk = "/soc/clock-controller@20200000"; | |
| aon_clk = "/soc/clock-controller@32080000"; | |
| pmu_gate = "/soc/pmu-gate"; | |
| dpll0 = "/soc/dpll0"; | |
| mpll1 = "/soc/mpll1"; | |
| pll1 = "/soc/pll1"; | |
| pll2 = "/soc/pll2"; | |
| aonapb_gate = "/soc/aonapb-gate"; | |
| audcpapb_gate = "/soc/audcpapb-gate"; | |
| audcpahb_gate = "/soc/audcpahb-gate"; | |
| funnel_soc_out_port = "/soc/funnel@3c002000/out-ports/port/endpoint"; | |
| funnel_soc_in_port = "/soc/funnel@3c002000/in-ports/port@1/endpoint"; | |
| soc_etb = "/soc/etb@3c003000"; | |
| etb_in = "/soc/etb@3c003000/in-ports/port/endpoint"; | |
| funnel_corinth_lit_out_port = "/soc/funnel@3e001000/out-ports/port/endpoint"; | |
| funnel_core_in_port3 = "/soc/funnel@3e001000/in-ports/port@0/endpoint"; | |
| funnel_core_in_port4 = "/soc/funnel@3e001000/in-ports/port@1/endpoint"; | |
| funnel_core_in_port5 = "/soc/funnel@3e001000/in-ports/port@2/endpoint"; | |
| funnel_core_in_port7 = "/soc/funnel@3e001000/in-ports/port@3/endpoint"; | |
| corinth_etf_lit_out = "/soc/etf@3e002000/out-ports/port/endpoint"; | |
| corinth_etf_lit_in = "/soc/etf@3e002000/in-ports/port/endpoint"; | |
| corinth_etf_big_out = "/soc/etf@3e003000/out-ports/port/endpoint"; | |
| corinth_etf_big_in = "/soc/etf@3e003000/in-ports/port/endpoint"; | |
| funnel_corinth_out_port = "/soc/funnel@3e004000/out-ports/port/endpoint"; | |
| funnel_corinth_from_lit_in_port = "/soc/funnel@3e004000/in-ports/port@0/endpoint"; | |
| funnel_corinth_from_big_in_port = "/soc/funnel@3e004000/in-ports/port@1/endpoint"; | |
| funnel_corinth_big_out_port = "/soc/funnel@3e005000/out-ports/port/endpoint"; | |
| funnel_core_in_port0 = "/soc/funnel@3e005000/in-ports/port@0/endpoint"; | |
| funnel_core_in_port1 = "/soc/funnel@3e005000/in-ports/port@1/endpoint"; | |
| funnel_core_in_port2 = "/soc/funnel@3e005000/in-ports/port@2/endpoint"; | |
| funnel_core_in_port6 = "/soc/funnel@3e005000/in-ports/port@3/endpoint"; | |
| etm0 = "/soc/etm@3f040000"; | |
| etm0_out = "/soc/etm@3f040000/out-ports/port/endpoint"; | |
| etm1 = "/soc/etm@3f140000"; | |
| etm1_out = "/soc/etm@3f140000/out-ports/port/endpoint"; | |
| etm2 = "/soc/etm@3f240000"; | |
| etm2_out = "/soc/etm@3f240000/out-ports/port/endpoint"; | |
| etm3 = "/soc/etm@3f340000"; | |
| etm3_out = "/soc/etm@3f340000/out-ports/port/endpoint"; | |
| etm4 = "/soc/etm@3f440000"; | |
| etm4_out = "/soc/etm@3f440000/out-ports/port/endpoint"; | |
| etm5 = "/soc/etm@3f540000"; | |
| etm5_out = "/soc/etm@3f540000/out-ports/port/endpoint"; | |
| etm6 = "/soc/etm@3f640000"; | |
| etm6_out = "/soc/etm@3f640000/out-ports/port/endpoint"; | |
| etm7 = "/soc/etm@3f740000"; | |
| etm7_out = "/soc/etm@3f740000/out-ports/port/endpoint"; | |
| gpu_clk = "/soc/gpu-clk"; | |
| mm_clk = "/soc/clock-controller@62100000"; | |
| mm_gate = "/soc/clock-controller@62200000"; | |
| apapb_gate = "/soc/apapb-gate"; | |
| sdio3 = "/soc/ap-apb/sdio@71400000"; | |
| sdio0 = "/soc/ap-apb/sdio@71100000"; | |
| sdio1 = "/soc/ap-apb/sdio@71200000"; | |
| sipc = "/sipc-virt"; | |
| sipc_lte = "/sipc-virt/core@5"; | |
| imsbr_data = "/sipc-virt/core@5/channel@2"; | |
| imsbr_ctrl = "/sipc-virt/core@5/channel@3"; | |
| spipe_lte = "/sipc-virt/core@5/channel@4"; | |
| stty_lte = "/sipc-virt/core@5/channel@6"; | |
| sdiag_lte = "/sipc-virt/core@5/channel@21"; | |
| slog_lte = "/sipc-virt/core@5/channel@5"; | |
| sipx = "/sipc-virt/core@5/route@0"; | |
| seth_ch7 = "/sipc-virt/core@5/channel@7"; | |
| seth_ch8 = "/sipc-virt/core@5/channel@8"; | |
| seth_ch9 = "/sipc-virt/core@5/channel@9"; | |
| seth_ch18 = "/sipc-virt/core@5/channel@18"; | |
| seth_ch19 = "/sipc-virt/core@5/channel@19"; | |
| seth_ch20 = "/sipc-virt/core@5/channel@20"; | |
| seth_ch24 = "/sipc-virt/core@5/channel@24"; | |
| seth_ch25 = "/sipc-virt/core@5/channel@25"; | |
| seth_ch26 = "/sipc-virt/core@5/channel@26"; | |
| seth_ch27 = "/sipc-virt/core@5/channel@27"; | |
| seth_ch28 = "/sipc-virt/core@5/channel@28"; | |
| seth_ch29 = "/sipc-virt/core@5/channel@29"; | |
| seth_ch30 = "/sipc-virt/core@5/channel@30"; | |
| seth_ch31 = "/sipc-virt/core@5/channel@31"; | |
| pubcp_dvfs = "/sipc-virt/core@5/channel@42"; | |
| sipc_sp = "/sipc-virt/core@6"; | |
| spipe_pm = "/sipc-virt/core@6/channel@4"; | |
| slog_pm = "/sipc-virt/core@6/channel@5"; | |
| sctl_pm = "/sipc-virt/core@6/channel@6"; | |
| data0_gnss = "/sipc-virt/core@6/channel@7"; | |
| stime_pm = "/sipc-virt/core@6/channel@41"; | |
| sprd_pcm = "/sprd-pcm-audio"; | |
| sprd_compr = "/sprd-compr-audio"; | |
| sprd_fe_dai = "/sprd-fe-dai"; | |
| sprd_route_pcm = "/sprd-routing-pcm"; | |
| ext_26m = "/ext-26m"; | |
| ext_32k = "/ext-32k"; | |
| ext_4m = "/ext-4m"; | |
| rco_100m = "/rco-100m"; | |
| dphy_273m = "/dphy-273m"; | |
| dphy_204m8 = "/dphy-204m8"; | |
| cache_efuse = "/efuse@800"; | |
| uid_start = "/efuse@800/uid-start@5c"; | |
| uid_end = "/efuse@800/uid-end@58"; | |
| thm0_sign = "/efuse@800/thm0-sign@38"; | |
| thm0_ratio = "/efuse@800/thm0-ratio@38"; | |
| thm0_sen0 = "/efuse@800/thm0-sen0@39"; | |
| thm0_sen1 = "/efuse@800/thm0-sen1@41"; | |
| thm0_sen2 = "/efuse@800/thm0-sen2@40"; | |
| thm0_sen3 = "/efuse@800/thm0-sen3@43"; | |
| thm0_sen4 = "/efuse@800/thm0-sen4@42"; | |
| thm1_sign = "/efuse@800/thm1-sign@3c"; | |
| thm1_ratio = "/efuse@800/thm1-ratio@3c"; | |
| thm1_sen0 = "/efuse@800/thm1-sen0@3d"; | |
| thm1_sen1 = "/efuse@800/thm1-sen1@2f"; | |
| thm1_sen2 = "/efuse@800/thm1-sen2@2e"; | |
| thm1_sen3 = "/efuse@800/thm1-sen3@29"; | |
| thm1_sen4 = "/efuse@800/thm1-sen4@28"; | |
| thm1_sen5 = "/efuse@800/thm1-sen4@2b"; | |
| thm2_sign = "/efuse@800/thm2-sign@3e"; | |
| thm2_ratio = "/efuse@800/thm2-ratio@3e"; | |
| thm2_sen0 = "/efuse@800/thm2-sen0@3f"; | |
| cpu_flag = "/efuse@800/cpu-flag@50"; | |
| dvfs_bin_cpu0 = "/efuse@800/dvfs-bin@17"; | |
| dvfs_bin_cpu1 = "/efuse@800/dvfs-bin@1b"; | |
| dvfs_bin_dsu = "/efuse@800/dvfs-bin@13"; | |
| pmsys = "/modem@0"; | |
| modem = "/modem@1"; | |
| CPU0 = "/cpus/cpu@0"; | |
| CPU1 = "/cpus/cpu@100"; | |
| CPU2 = "/cpus/cpu@200"; | |
| CPU3 = "/cpus/cpu@300"; | |
| CPU4 = "/cpus/cpu@400"; | |
| CPU5 = "/cpus/cpu@500"; | |
| CPU6 = "/cpus/cpu@600"; | |
| CPU7 = "/cpus/cpu@700"; | |
| LIT_CORE_PD = "/idle-states/lit_core_pd"; | |
| BIG_CORE_PD = "/idle-states/big_core_pd"; | |
| power = "/power-debug"; | |
| debug_stat = "/debugstat"; | |
| cpufreq_cluster0_opp = "/opp-table0"; | |
| cpufreq_cluster1_opp = "/opp-table1"; | |
| autotest = "/autotest"; | |
| gsp = "/sprd-gsp"; | |
| iram_reserved = "/sp-iram@dc00"; | |
| audcp_iram_reserved = "/audcp-iram@a400"; | |
| sprd_headset = "/sprd-headset"; | |
| sound_vbc_v4_sprd_codec = "/sound@0"; | |
| ion = "/ion"; | |
| reserved_memory = "/reserved-memory"; | |
| ddrbist_reserved = "/reserved-memory/ddrbist-mem@0x80000000"; | |
| sysdump_reserved = "/reserved-memory/sysdumpinfo-mem@80001000"; | |
| audio_reserved = "/reserved-memory/audio-mem@87400000"; | |
| sp_ddr_reserved = "/reserved-memory/sp_ddr-mem@88000000"; | |
| audiodsp_reserved = "/reserved-memory/audiodsp-mem@89000000"; | |
| cp_reserved = "/reserved-memory/cp-mem@89600000"; | |
| smem_reserved = "/reserved-memory/sipc-mem@8e000000"; | |
| iq_reserved = "/reserved-memory/iq-mem@90000000"; | |
| sml_reserved = "/reserved-memory/sml-mem@94000000"; | |
| tos_reserved = "/reserved-memory/tos-mem@94040000"; | |
| tos_shm_reserved = "/reserved-memory/sh-mem@9a000000"; | |
| uboot_log_reserved = "/reserved-memory/uboot_log-mem"; | |
| uboot_reserved = "/reserved-memory/sysdump-uboot@9f000000"; | |
| cma_reserved = "/reserved-memory/cma_share@f00000000"; | |
| pstore_reserved = "/reserved-memory/ramoops@fff80000"; | |
| dpu_dvfs = "/dpu-dvfs"; | |
| vsp_dvfs = "/vsp-dvfs"; | |
| vdsp_dvfs = "/vdsp-dvfs"; | |
| ddr_dfs = "/scene-frequency"; | |
| thm_zone = "/thermal-zones"; | |
| soc_thmzone = "/thermal-zones/soc-thmzone"; | |
| soc_threshold = "/thermal-zones/soc-thmzone/trips/trip-point@0"; | |
| soc_target = "/thermal-zones/soc-thmzone/trips/trip-point@1"; | |
| soc_crit = "/thermal-zones/soc-thmzone/trips/soc_crit"; | |
| prometheus6_tzone0 = "/thermal-zones/prometheus6-tzone0"; | |
| prometheus6_tzone1 = "/thermal-zones/prometheus6-tzone1"; | |
| prometheus7_thmzone = "/thermal-zones/prometheus7-thmzone"; | |
| ank0_thmzone = "/thermal-zones/ank0-thmzone"; | |
| ank1_thmzone = "/thermal-zones/ank1-thmzone"; | |
| gpu_thmzone = "/thermal-zones/gpu-thmzone"; | |
| ank2_thmzone = "/thermal-zones/ank2-thmzone"; | |
| ank3_thmzone = "/thermal-zones/ank3-thmzone"; | |
| ank4_thmzone = "/thermal-zones/ank4-thmzone"; | |
| ank5_thmzone = "/thermal-zones/ank5-thmzone"; | |
| cputop_thmzone = "/thermal-zones/cputop-thmzone"; | |
| gpuank2_thmzone = "/thermal-zones/gpuank2-thmzone"; | |
| osctsen_thmzone = "/thermal-zones/osctsen-thmzone"; | |
| outtsen_thmzone = "/thermal-zones/outtsen-thmzone"; | |
| virtual_sensor = "/virtual-sensor@0"; | |
| cluster0_cooling = "/cooling-devices/cluster0-cooling"; | |
| cluster1_cooling = "/cooling-devices/cluster1-cooling"; | |
| gpu_cooling0 = "/gpu-cooling-devices/gpu-cooling0"; | |
| isp_dvfs = "/isp-dvfs"; | |
| cpp_dvfs = "/cpp-dvfs"; | |
| jpg_dvfs = "/jpg-dvfs"; | |
| fd_dvfs = "/fd-dvfs"; | |
| mtx_dvfs = "/mtx-dvfs"; | |
| dcam_if_dvfs = "/dcam-if-dvfs"; | |
| dcam_axi_dvfs = "/dcam-axi-dvfs"; | |
| mmsys_dvfs = "/mmsys-dvfs"; | |
| chosen = "/chosen"; | |
| dvfs_dcdc_cpu0_cfg = "/dvfs-dcdc-cpu0-cfg"; | |
| dvfs_dcdc_cpu1_cfg = "/dvfs-dcdc-cpu1-cfg"; | |
| extcon_gpio = "/extcon-gpio"; | |
| }; | |
| }; |
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