Running yosys' cxxrtl backend on blinky

blinky.v

`default_nettype	none
//
module blinky(i_clk, o_led);
`ifdef	SIMULATION
	parameter	WIDTH = 12;
`else
	parameter	WIDTH = 27;
`endif
	input	wire	i_clk;
	output	wire	o_led;

	reg	[WIDTH-1:0]	counter;

	always @(posedge i_clk)
		counter <= counter + 1'b1;

	assign	o_led = counter[WIDTH-1];
endmodule

BlinkyTop.sim.cpp

#include "BlinkyTop.sim.h"

#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \
    defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
#include <backends/cxxrtl/cxxrtl_capi.cc>
#endif

#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)
#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>
#endif

using namespace cxxrtl_yosys;

namespace cxxrtl_design {

} // namespace cxxrtl_design

cxxrtl_toplevel cxxrtl_design_create() {
	return new _cxxrtl_toplevel { std::unique_ptr<cxxrtl_design::p_blinky>(new cxxrtl_design::p_blinky) };
}

BlinkyTop.sim.h

#ifndef CXXRTL_DESIGN_HEADER
#define CXXRTL_DESIGN_HEADER

#include <backends/cxxrtl/cxxrtl_capi.h>

#ifdef __cplusplus
extern "C" {
#endif

cxxrtl_toplevel cxxrtl_design_create();

#ifdef __cplusplus
}
#endif

#ifdef __cplusplus

#include <backends/cxxrtl/cxxrtl.h>

using namespace cxxrtl;

namespace cxxrtl_design {

} // namespace cxxrtl_design

#endif // __cplusplus

#endif

BlinkyTop.sim.ilang

# Generated by Yosys 0.9+2406 (git sha1 UNKNOWN, gcc 9.3.1 -O3 -DNDEBUG -m64 -O3 -fPIC)
autoidx 3
attribute \dynports 1
attribute \top 1
attribute \src "./blinky.v:27.1-42.10"
module \blinky
  parameter \WIDTH 12
  attribute \src "./blinky.v:38.2-39.29"
  wire width 12 $0\counter[11:0]
  attribute \src "./blinky.v:39.14-39.28"
  wire width 12 $add$./blinky.v:39$2_Y
  attribute \src "./blinky.v:36.18-36.25"
  wire width 12 \counter
  attribute \src "./blinky.v:33.13-33.18"
  wire input 1 \i_clk
  attribute \src "./blinky.v:34.14-34.19"
  wire output 2 \o_led
  attribute \src "./blinky.v:39.14-39.28"
  cell $add $add$./blinky.v:39$2
    parameter \A_SIGNED 0
    parameter \A_WIDTH 12
    parameter \B_SIGNED 0
    parameter \B_WIDTH 1
    parameter \Y_WIDTH 12
    connect \A \counter
    connect \B 1'1
    connect \Y $add$./blinky.v:39$2_Y
  end
  attribute \src "./blinky.v:38.2-39.29"
  process $proc$./blinky.v:38$1
    assign { } { }
    assign $0\counter[11:0] $add$./blinky.v:39$2_Y
    sync posedge \i_clk
      update \counter $0\counter[11:0]
  end
  connect \o_led \counter [11]
end

output log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+2406 (git sha1 UNKNOWN, gcc 9.3.1 -O3 -DNDEBUG -m64 -O3 -fPIC)


-- Executing script file `proc.ys' --

1. Executing Verilog-2005 frontend: ./blinky.v
Parsing Verilog input from `./blinky.v' to AST representation.
Generating RTLIL representation for module `\blinky'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \blinky

2.2. Analyzing design hierarchy..
Top module:  \blinky
Removed 0 unused modules.

3. Executing ILANG backend.
Output filename: BlinkyTop.sim.ilang

4. Executing CXXRTL backend.

4.1. Executing FLATTEN pass (flatten design).

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 1 assignment to connection.

4.2.4. Executing PROC_INIT pass (extract init attributes).

4.2.5. Executing PROC_ARST pass (detect async resets in processes).

4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\blinky.$proc$./blinky.v:38$1'.

4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\blinky.\counter' using process `\blinky.$proc$./blinky.v:38$1'.
  created $dff cell `$procdff$3' with positive edge clock.

4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `blinky.$proc$./blinky.v:38$1'.
Cleaned up 0 empty switches.

End of script. Logfile hash: 024f0c9929, CPU: user 0.01s system 0.00s, MEM: 11.35 MB peak
Yosys 0.9+2406 (git sha1 UNKNOWN, gcc 9.3.1 -O3 -DNDEBUG -m64 -O3 -fPIC)
Time spent: 33% 2x read_verilog (0 sec), 14% 2x write_cxxrtl (0 sec), ...

proc.ys

verilog_defines -DSIMULATION
read_verilog ./blinky.v
hierarchy -check -top blinky
write_ilang BlinkyTop.sim.ilang
write_cxxrtl -header BlinkyTop.sim.cpp