simple verilog 8-Bit Nand interface (avalon compatible)

nand_interface.v

module bidir_driver #(parameter width=8) (data_rw, data_r, data_w, oe);
	inout  wire [width-1:0] data_rw;
	input  wire [width-1:0] data_w;
	output wire [width-1:0] data_r;
	
	input wire oe;

	assign data_rw = oe ? data_w : { width {1'bZ} };
	assign data_r  = data_rw;
endmodule

module nand_interface (
// Avalon interface
input ce_i,
input clk_i,
input reset_i,
input read_i,
input write_i,
input address_i,
input  [31:0] writedata_i,
output [31:0] readdata_o,

// Nand interface
inout [7:0] data_io,
output reg ale_o,
output reg ce_n_o,
output reg cle_o,
output reg re_n_o,
output reg we_n_o,
input rb_i
);

wire [7:0] data_i;
wire [7:0] data_o;

wire oe;

integer tmp;

assign readdata_o = data_o | ((!ce_n_o) << 31) | (cle_o << 30) | (ale_o << 29) | ((!re_n_o) << 28) | ((!we_n_o) << 27) | ((!rb_i) << 26);
assign data_i = (writedata_i & 255);

bidir_driver #(.width(8)) mux (.data_rw(data_io), .data_r(data_o), .data_w(data_i), .oe(!we_n_o));

always @(posedge clk_i) begin: GEN_NAND_INTERFACE_LOGIC
	if (reset_i) begin
		ale_o  = 0;
		ce_n_o = 1;
		cle_o  = 0;
		re_n_o = 1;
		we_n_o = 1;
	end
	else begin
		if (ce_i) begin
			if (write_i) begin
				if (writedata_i & (1 << 31)) begin
					ce_n_o = 0;
				end
				else begin
					ce_n_o = 1;
				end
				
				if (writedata_i & (1 << 30)) begin
					cle_o = 1;
				end
				else begin
					cle_o = 0;
				end
				
				if (writedata_i & (1 << 29)) begin
					ale_o = 1;
				end
				else begin
					ale_o = 0;
				end
				
				if (writedata_i & (1 << 28)) begin
					re_n_o = 0;
				end
				else begin
					re_n_o = 1;
				end
				
				if (writedata_i & (1 << 27)) begin
					we_n_o = 0;
				end
				else begin
					we_n_o = 1;
				end
			end
		end
	end
end

endmodule