Last active
January 11, 2018 18:41
-
-
Save maggu2810/aab8fbddd98313f966a0f07405a98625 to your computer and use it in GitHub Desktop.
git diff v4.12 v4.13 -- imx6q-udoo.dts imx6q.dtsi imx6qdl-udoo.dtsi imx6qdl.dtsi
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi | |
index e9a5d0b8c7b0..90a741732f60 100644 | |
--- a/arch/arm/boot/dts/imx6q.dtsi | |
+++ b/arch/arm/boot/dts/imx6q.dtsi | |
@@ -125,7 +125,7 @@ | |
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, | |
<&clks IMX6QDL_CLK_GPU2D_CORE>; | |
clock-names = "bus", "core"; | |
- power-domains = <&gpc 1>; | |
+ power-domains = <&pd_pu>; | |
}; | |
ipu2: ipu@02800000 { | |
@@ -143,10 +143,18 @@ | |
ipu2_csi0: port@0 { | |
reg = <0>; | |
+ | |
+ ipu2_csi0_from_mipi_vc2: endpoint { | |
+ remote-endpoint = <&mipi_vc2_to_ipu2_csi0>; | |
+ }; | |
}; | |
ipu2_csi1: port@1 { | |
reg = <1>; | |
+ | |
+ ipu2_csi1_from_ipu2_csi1_mux: endpoint { | |
+ remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>; | |
+ }; | |
}; | |
ipu2_di0: port@2 { | |
@@ -198,6 +206,11 @@ | |
}; | |
}; | |
+ capture-subsystem { | |
+ compatible = "fsl,imx-capture-subsystem"; | |
+ ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>; | |
+ }; | |
+ | |
display-subsystem { | |
compatible = "fsl,imx-display-subsystem"; | |
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; | |
@@ -246,6 +259,68 @@ | |
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; | |
}; | |
+&gpr { | |
+ ipu1_csi0_mux { | |
+ compatible = "video-mux"; | |
+ mux-controls = <&mux 0>; | |
+ #address-cells = <1>; | |
+ #size-cells = <0>; | |
+ | |
+ port@0 { | |
+ reg = <0>; | |
+ | |
+ ipu1_csi0_mux_from_mipi_vc0: endpoint { | |
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; | |
+ }; | |
+ }; | |
+ | |
+ port@1 { | |
+ reg = <1>; | |
+ | |
+ ipu1_csi0_mux_from_parallel_sensor: endpoint { | |
+ }; | |
+ }; | |
+ | |
+ port@2 { | |
+ reg = <2>; | |
+ | |
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint { | |
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; | |
+ }; | |
+ }; | |
+ }; | |
+ | |
+ ipu2_csi1_mux { | |
+ compatible = "video-mux"; | |
+ mux-controls = <&mux 1>; | |
+ #address-cells = <1>; | |
+ #size-cells = <0>; | |
+ | |
+ port@0 { | |
+ reg = <0>; | |
+ | |
+ ipu2_csi1_mux_from_mipi_vc3: endpoint { | |
+ remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>; | |
+ }; | |
+ }; | |
+ | |
+ port@1 { | |
+ reg = <1>; | |
+ | |
+ ipu2_csi1_mux_from_parallel_sensor: endpoint { | |
+ }; | |
+ }; | |
+ | |
+ port@2 { | |
+ reg = <2>; | |
+ | |
+ ipu2_csi1_mux_to_ipu2_csi1: endpoint { | |
+ remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>; | |
+ }; | |
+ }; | |
+ }; | |
+}; | |
+ | |
&hdmi { | |
compatible = "fsl,imx6q-hdmi"; | |
@@ -266,6 +341,12 @@ | |
}; | |
}; | |
+&ipu1_csi1 { | |
+ ipu1_csi1_from_mipi_vc1: endpoint { | |
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; | |
+ }; | |
+}; | |
+ | |
&ldb { | |
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, | |
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, | |
@@ -312,6 +393,40 @@ | |
}; | |
}; | |
+&mipi_csi { | |
+ port@1 { | |
+ reg = <1>; | |
+ | |
+ mipi_vc0_to_ipu1_csi0_mux: endpoint { | |
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; | |
+ }; | |
+ }; | |
+ | |
+ port@2 { | |
+ reg = <2>; | |
+ | |
+ mipi_vc1_to_ipu1_csi1: endpoint { | |
+ remote-endpoint = <&ipu1_csi1_from_mipi_vc1>; | |
+ }; | |
+ }; | |
+ | |
+ port@3 { | |
+ reg = <3>; | |
+ | |
+ mipi_vc2_to_ipu2_csi0: endpoint { | |
+ remote-endpoint = <&ipu2_csi0_from_mipi_vc2>; | |
+ }; | |
+ }; | |
+ | |
+ port@4 { | |
+ reg = <4>; | |
+ | |
+ mipi_vc3_to_ipu2_csi1_mux: endpoint { | |
+ remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>; | |
+ }; | |
+ }; | |
+}; | |
+ | |
&mipi_dsi { | |
ports { | |
port@2 { | |
@@ -332,6 +447,16 @@ | |
}; | |
}; | |
+&mux { | |
+ mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */ | |
+ <0x04 0x00100000>, /* MIPI_IPU2_MUX */ | |
+ <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ | |
+ <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ | |
+ <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ | |
+ <0x28 0x00000003>, /* DCIC1_MUX_CTL */ | |
+ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ | |
+}; | |
+ | |
&vpu { | |
compatible = "fsl,imx6q-vpu", "cnm,coda960"; | |
}; |
Author
maggu2810
commented
Jan 11, 2018
Related changes:
d72ee3a12b9a ARM: dts: imx6qdl: add capture-subsystem device
2539f517acbd ARM: dts: imx6qdl: Add video multiplexers, mipi_csi, and their connections
b0cb1bd4a380 ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
bc97e88ecd36 ARM: dts: imx6qdl: add multiplexer controls
38281a475480 ARM: dts: imx: Reintroduce 'anatop-enable-bit' where appropriate
e761b82ef222 ARM: dts: imx6: adopt DT to new GPC binding
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment