verilogbug.v

module verilogbug();

reg x = 1;
initial
begin
  if (x === 0) begin
    $display("x === 0 is true");
  end
  else begin
    $display("x === 0 is false");
  end

  if (0 === x) begin
    $display("0 === x is true");
  end
  else begin
    $display("0 === x is false");
  end
end

endmodule