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timingReport
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -a top_level.ncd
Design file: top_level.ncd
Physical constraint file: top_level.pcf
Device,package,speed: xc6slx9,tqg144,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level: summary report, limited to 0 items per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2700 - Timing constraints ignored because advanced analysis with
offsets was specified.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Default period analysis for net "sysClk00 | SETUP | N/A| 9.411ns| N/A| 0
0" | HOLD | 0.415ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Default OFFSET IN BEFORE analysis for clo | SETUP | N/A| 7.235ns| N/A| 0
ck "sysClk000" | | | | |
----------------------------------------------------------------------------------------------------------
Default OFFSET OUT AFTER analysis for clo | MAXDELAY | N/A| 12.695ns| N/A| 0
ck "sysClk000" | | | | |
----------------------------------------------------------------------------------------------------------
Default OFFSET OUT AFTER analysis for clo | MAXDELAY | N/A| 7.501ns| N/A| 0
ck "sysClk180" | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock fx2Clk_in
--------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
--------------+------------+------------+------------+------------+------------------+--------+
fx2Data_io<0> | 4.682(R)| SLOW | -1.024(R)| FAST |sysClk000 | 0.000|
fx2Data_io<1> | 5.617(R)| SLOW | -0.603(R)| FAST |sysClk000 | 0.000|
fx2Data_io<2> | 6.631(R)| SLOW | -0.899(R)| FAST |sysClk000 | 0.000|
fx2Data_io<3> | 5.722(R)| SLOW | -0.876(R)| FAST |sysClk000 | 0.000|
fx2Data_io<4> | 5.990(R)| SLOW | -1.011(R)| FAST |sysClk000 | 0.000|
fx2Data_io<5> | 5.591(R)| SLOW | -1.063(R)| FAST |sysClk000 | 0.000|
fx2Data_io<6> | 6.131(R)| SLOW | -0.936(R)| FAST |sysClk000 | 0.000|
fx2Data_io<7> | 5.359(R)| SLOW | -1.260(R)| FAST |sysClk000 | 0.000|
fx2GotData_in | 7.235(R)| SLOW | -1.128(R)| FAST |sysClk000 | 0.000|
fx2GotRoom_in | 5.926(R)| SLOW | -1.360(R)| FAST |sysClk000 | 0.000|
ramData_io<0> | 4.239(R)| SLOW | -0.806(R)| FAST |sysClk000 | 0.000|
ramData_io<1> | 3.495(R)| SLOW | -0.868(R)| FAST |sysClk000 | 0.000|
ramData_io<2> | 4.044(R)| SLOW | -0.991(R)| FAST |sysClk000 | 0.000|
ramData_io<3> | 3.938(R)| SLOW | -0.835(R)| FAST |sysClk000 | 0.000|
ramData_io<4> | 3.439(R)| SLOW | -0.792(R)| FAST |sysClk000 | 0.000|
ramData_io<5> | 3.850(R)| SLOW | -0.735(R)| FAST |sysClk000 | 0.000|
ramData_io<6> | 3.848(R)| SLOW | -1.001(R)| FAST |sysClk000 | 0.000|
ramData_io<7> | 3.764(R)| SLOW | -0.928(R)| FAST |sysClk000 | 0.000|
ramData_io<8> | 4.010(R)| SLOW | -0.580(R)| FAST |sysClk000 | 0.000|
ramData_io<9> | 3.775(R)| SLOW | -0.629(R)| FAST |sysClk000 | 0.000|
ramData_io<10>| 3.872(R)| SLOW | -0.625(R)| FAST |sysClk000 | 0.000|
ramData_io<11>| 4.221(R)| SLOW | -0.512(R)| FAST |sysClk000 | 0.000|
ramData_io<12>| 5.196(R)| SLOW | -0.874(R)| FAST |sysClk000 | 0.000|
ramData_io<13>| 4.713(R)| SLOW | -1.011(R)| FAST |sysClk000 | 0.000|
ramData_io<14>| 5.029(R)| SLOW | -0.989(R)| FAST |sysClk000 | 0.000|
ramData_io<15>| 5.026(R)| SLOW | -0.949(R)| FAST |sysClk000 | 0.000|
--------------+------------+------------+------------+------------+------------------+--------+
Clock fx2Clk_in to Pad
---------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
---------------+-----------------+------------+-----------------+------------+------------------+--------+
fx2Data_io<0> | 11.591(R)| SLOW | 3.388(R)| FAST |sysClk000 | 0.000|
fx2Data_io<1> | 12.103(R)| SLOW | 3.295(R)| FAST |sysClk000 | 0.000|
fx2Data_io<2> | 11.948(R)| SLOW | 3.673(R)| FAST |sysClk000 | 0.000|
fx2Data_io<3> | 11.552(R)| SLOW | 3.673(R)| FAST |sysClk000 | 0.000|
fx2Data_io<4> | 11.654(R)| SLOW | 3.608(R)| FAST |sysClk000 | 0.000|
fx2Data_io<5> | 11.610(R)| SLOW | 3.608(R)| FAST |sysClk000 | 0.000|
fx2Data_io<6> | 12.025(R)| SLOW | 3.702(R)| FAST |sysClk000 | 0.000|
fx2Data_io<7> | 11.981(R)| SLOW | 3.702(R)| FAST |sysClk000 | 0.000|
fx2FifoSel_out | 10.036(R)| SLOW | 3.197(R)| FAST |sysClk000 | 0.000|
fx2PktEnd_out | 9.370(R)| SLOW | 3.483(R)| FAST |sysClk000 | 0.000|
fx2Read_out | 10.668(R)| SLOW | 3.503(R)| FAST |sysClk000 | 0.000|
fx2Write_out | 11.415(R)| SLOW | 3.527(R)| FAST |sysClk000 | 0.000|
ramAddr_out<0> | 7.440(R)| SLOW | 2.538(R)| FAST |sysClk000 | 0.000|
ramAddr_out<1> | 7.440(R)| SLOW | 2.538(R)| FAST |sysClk000 | 0.000|
ramAddr_out<2> | 7.386(R)| SLOW | 2.484(R)| FAST |sysClk000 | 0.000|
ramAddr_out<3> | 7.386(R)| SLOW | 2.484(R)| FAST |sysClk000 | 0.000|
ramAddr_out<4> | 7.436(R)| SLOW | 2.534(R)| FAST |sysClk000 | 0.000|
ramAddr_out<5> | 7.434(R)| SLOW | 2.532(R)| FAST |sysClk000 | 0.000|
ramAddr_out<6> | 7.434(R)| SLOW | 2.532(R)| FAST |sysClk000 | 0.000|
ramAddr_out<7> | 7.412(R)| SLOW | 2.510(R)| FAST |sysClk000 | 0.000|
ramAddr_out<8> | 7.412(R)| SLOW | 2.510(R)| FAST |sysClk000 | 0.000|
ramAddr_out<9> | 7.421(R)| SLOW | 2.519(R)| FAST |sysClk000 | 0.000|
ramAddr_out<10>| 7.441(R)| SLOW | 2.539(R)| FAST |sysClk000 | 0.000|
ramAddr_out<11>| 7.421(R)| SLOW | 2.519(R)| FAST |sysClk000 | 0.000|
ramBank_out<0> | 7.391(R)| SLOW | 2.489(R)| FAST |sysClk000 | 0.000|
ramBank_out<1> | 7.441(R)| SLOW | 2.539(R)| FAST |sysClk000 | 0.000|
ramClk_out | 7.514(R)| SLOW | 2.617(R)| FAST |sysClk000 | 0.000|
| 7.501(R)| SLOW | 2.500(R)| FAST |sysClk180 | 0.000|
ramCmd_out<0> | 7.245(R)| SLOW | 2.343(R)| FAST |sysClk000 | 0.000|
ramCmd_out<1> | 7.311(R)| SLOW | 2.409(R)| FAST |sysClk000 | 0.000|
ramCmd_out<2> | 7.311(R)| SLOW | 2.409(R)| FAST |sysClk000 | 0.000|
ramData_io<0> | 11.038(R)| SLOW | 3.006(R)| FAST |sysClk000 | 0.000|
ramData_io<1> | 11.038(R)| SLOW | 2.840(R)| FAST |sysClk000 | 0.000|
ramData_io<2> | 10.840(R)| SLOW | 2.884(R)| FAST |sysClk000 | 0.000|
ramData_io<3> | 10.840(R)| SLOW | 2.884(R)| FAST |sysClk000 | 0.000|
ramData_io<4> | 10.399(R)| SLOW | 2.943(R)| FAST |sysClk000 | 0.000|
ramData_io<5> | 10.399(R)| SLOW | 3.033(R)| FAST |sysClk000 | 0.000|
ramData_io<6> | 9.633(R)| SLOW | 3.096(R)| FAST |sysClk000 | 0.000|
ramData_io<7> | 9.919(R)| SLOW | 3.096(R)| FAST |sysClk000 | 0.000|
ramData_io<8> | 12.695(R)| SLOW | 3.444(R)| FAST |sysClk000 | 0.000|
ramData_io<9> | 12.695(R)| SLOW | 3.346(R)| FAST |sysClk000 | 0.000|
ramData_io<10> | 12.680(R)| SLOW | 3.436(R)| FAST |sysClk000 | 0.000|
ramData_io<11> | 12.680(R)| SLOW | 3.416(R)| FAST |sysClk000 | 0.000|
ramData_io<12> | 11.671(R)| SLOW | 2.891(R)| FAST |sysClk000 | 0.000|
ramData_io<13> | 11.671(R)| SLOW | 2.862(R)| FAST |sysClk000 | 0.000|
ramData_io<14> | 11.480(R)| SLOW | 2.872(R)| FAST |sysClk000 | 0.000|
ramData_io<15> | 11.480(R)| SLOW | 2.838(R)| FAST |sysClk000 | 0.000|
---------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock fx2Clk_in
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
fx2Clk_in | 9.411| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 14817 paths, 0 nets, and 2542 connections
Design statistics:
Minimum period: 9.411ns (Maximum frequency: 106.259MHz)
Minimum input required time before clock: 7.235ns
Maximum output delay after clock: 12.695ns
Analysis completed Tue Mar 25 21:07:52 2014
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 394 MB
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