これだと論理合成できないそうです

seripara.v

module seripara (clk, si, res, ena, q);

input si, res, ena, clk;
output [3:0] q;

reg [3:0] q;
reg [1:0] state;

always@(negedge res or posedge clk)
begin

  if (~res)
  begin
    q <= 4'b0000;
    state <= 2'd3;
  end

  if (ena)
  begin
    q[state] = si;
    state = state - 1;
  end

end

endmodule