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Marco Túlio Chella marcotchella

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marcotchella / mux4x1.vhdl
Created December 8, 2021 18:48
Código VHDL para implementacao de Mux 4x 1 e respectivo testbench
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port(
en1 : in std_logic;
en2 : in std_logic;
en3 : in std_logic;
en4 : in std_logic;
sel : in std_logic_vector(1 downto 0);
@marcotchella
marcotchella / or_gate.bat
Created June 14, 2021 19:13
Template VHDL , Testbench , GtkWave
ghdl -a or_gate.vhd
ghdl -a testbench.vhd
ghdl -e testbench
ghdl -r testbench --vcd=or_gate.vcd
gtkwave or_gate.vcd
@marcotchella
marcotchella / jk_flip_flop.vhd
Created March 12, 2020 20:45
library ieee;
use ieee.std_logic_1164.all;
entity JKFF is
port(
j: in std_logic;
k: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic;
@marcotchella
marcotchella / acel_arduino.pde
Created February 16, 2020 19:58
Comunicação entre Arduino e Processing via porta serial. Arduino envia dados que simulam um acelerometro. Processing captura os dados e exibe um retangulo
//sketch processing
import processing.serial.*;
Serial portaArduino;
int lf = 10; //ASCII linefeed
String RecebidaString;
String display;
float ac_x = 0.0;
float ac_y = 0.0;
@marcotchella
marcotchella / mux_4x1.vhd
Created February 13, 2020 11:34
Código em VHDL com implementação de Multiplexador 4 x 1 e respectivo testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4x1_comportamental is
PORT (
a, b, c, d : IN STD_LOGIC;
sel : in std_logic_vector(1 downto 0);
x: OUT STD_LOGIC
);
end mux_4x1_comportamental;
@marcotchella
marcotchella / c_millis.ino
Created December 6, 2019 13:51
função millis para avr em C - atmega328
#include <avr/io.h>
#include <util/delay.h>
#include <util/atomic.h>
#include <avr/interrupt.h>
volatile unsigned long timer1_millis; // faixa de valores vai de 0 a 4.294.967.295 (2^32 - 1)
//--------------------------------------------------------
// rotina de interruoção do TIMER1
ISR(TIMER1_COMPA_vect)
@marcotchella
marcotchella / main.c
Created August 24, 2019 10:24
Modificação firmware Radiosonda Vaisala RS41
// STM32F100 and SI4032 RTTY transmitter
// released under GPL v.2 by anonymous developer
// enjoy and have a nice day
// ver 1.5a
// Codigo original em: https://github.com/df8oe/RS41HUP
// ensaio v00 para avaliar comunicacao pela porta de debug USART3
// implementada rotina para receber e enviar caracteres
// 22/08/2019
@marcotchella
marcotchella / dff.vhd
Created August 8, 2019 11:00
Flip Flop D e Latch - referente apresentação 17 Fundamentos de sistemas Digitais 2019-1
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
entity dff is
port( dado: in std_logic;
clock: in std_logic;
saida: out std_logic
);
@marcotchella
marcotchella / or_gate.vhd
Created June 18, 2019 12:55
template implementação porta OR em VHDL
-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;
entity or_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end or_gate;
@marcotchella
marcotchella / testbench.vhd
Last active June 18, 2019 12:53
template testbench VHDL
-- Testbench for OR gate
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
-- empty
end testbench;
architecture tb of testbench is