coreboot-b13b1ce bootblock Sat Nov 5 22:24:58 PDT 2016 starting...
Exception handlers installed.
Configuring PLL at ff760030 with NF = 99, NR = 2 and NO = 2 (VCO = 1188000KHz, output = 594000KHz)
Configuring PLL at ff760020 with NF = 32, NR = 1 and NO = 2 (VCO = 768000KHz, output = 384000KHz)
Translation table is @ ff700000
Mapping address range [0x00000000:0x00000000) as uncached
Creating new subtable @ff716c00 for [0xff700000:0xff800000)
Mapping address range [0xff700000:0xff718000) as writethrough
Configuring PLL at ff760000 with NF = 75, NR = 1 and NO = 1 (VCO = 1800000KHz, output = 1800000KHz)
SF: Detected GD25Q32(B) with page size 1000, total 400000
CBFS: loading stage @ 0xff70c800 (38760 bytes), entry @ 0xff70c801
coreboot-b13b1ce verstage Sat Nov 5 22:24:58 PDT 2016 starting...
Exception handlers installed.
out: cmd=0x17: 03 f8 17 00 01 00 14 00 00 00 00 00 74 7f 71 ff 64 00 70 ff 0c 00 70 ff bf fa 70 ff
in-header: 03 ed 00 00 10 00 00 00
in-data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1.2 TPM (chip type slb9645tt device-id 0x1A)
TPM: Startup
TPM: command 0x99 returned 0x0
TPM: Asserting physical presence
TPM: command 0x4000000a returned 0x0
TPM: command 0x65 returned 0x0
TPM: flags disable=0, deactivated=0, nvlocked=1
setup_tpm():310: TPM: SetupTPM() succeeded
TPM: tlcl_read(0x1007, 10)
TPM: command 0xcf returned 0x0
out: cmd=0x87: 03 4a 87 00 00 00 04 00 bf fa 70 ff
in-header: 03 d9 00 00 04 00 00 00
in-data: 00 20 00 00
Phase 1
SF: Detected GD25Q32(B) with page size 1000, total 400000
FMAP: Found "FMAP" version 1.0 at ff717000.
FMAP: base = 0 size = 400000 #areas = 22
FMAP: area GBB found
FMAP: offset: 101000
FMAP: size: 978688 bytes
FMAP: GBB at 00101000 (offset 101000)
Phase 2
Phase 3
FMAP: area GBB found
FMAP: offset: 101000
FMAP: size: 978688 bytes
FMAP: GBB at 00101000 (offset 101000)
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 8192 bytes
FMAP: VBLOCK_A at 00200000 (offset 200000)
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 8192 bytes
FMAP: VBLOCK_A at 00200000 (offset 200000)
VB2:vb2_verify_keyblock() Checking key block signature...
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 8192 bytes
FMAP: VBLOCK_A at 00200000 (offset 200000)
FMAP: area VBLOCK_A found
FMAP: offset: 200000
FMAP: size: 8192 bytes
FMAP: VBLOCK_A at 00200000 (offset 200000)
VB2:vb2_verify_fw_preamble() Verifying preamble.
Phase 4
FMAP: area FW_MAIN_A found
FMAP: offset: 202000
FMAP: size: 352256 bytes
FMAP: FW_MAIN_A at 00202000 (offset 202000)
Initialized RK3288 HW crypto for 156220 byte SHA256
VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2
Saving nvdata
out: cmd=0x17: 03 40 17 00 01 00 14 00 01 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20
in-header: 03 fd 00 00 00 00 00 00
in-data:
TPM: command 0x14 returned 0x0
TPM: command 0x14 returned 0x0
TPM: Set global lock
TPM: tlcl_write(0x0, 0)
TPM: command 0xcd returned 0x0
Slot A is selected
CBFS: loading stage @ 0xff70c800 (23416 bytes), entry @ 0xff70c801
coreboot-b13b1ce romstage Sat Nov 5 22:24:58 PDT 2016 starting...
RAM Config: 0.
Starting SDRAM initialization...
Configuring PLL at ff760010 with NF = 400, NR = 9 and NO = 2 (VCO = 1066666KHz, output = 533333KHz)
Finish SDRAM initialization...
Mapping address range [0x00000000:0x80000000) as writeback
Mapping address range [0x10000000:0x10200000) as uncached
CBMEM: root @ 7ffff000 254 entries.
creating vboot_handoff structure
Copying FW preamble
loading ramstage from Slot A
SF: Detected GD25Q32(B) with page size 1000, total 400000
CBFS: loading stage @ 0x200000 (102984 bytes), entry @ 0x200001
coreboot-b13b1ce Sat Nov 5 22:24:58 PDT 2016 booting...
Exception handlers installed.
CBMEM: recovering 4/254 entries from root @ 7ffff000
BS: BS_PRE_DEVICE times (us): entry 21 run 2 exit 1
BS: BS_DEV_INIT_CHIPS times (us): entry 1 run 4 exit 1
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
scan_static_bus for Root Device done
done
BS: BS_DEV_ENUMERATE times (us): entry 2 run 71 exit 1
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0
Setting resources...
Root Device assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 1 run 125 exit 2
Enabling resources...
done.
BS: BS_DEV_ENABLE times (us): entry 1 run 8 exit 2
Initializing devices...
Root Device init
Board ID: 6.
SF: Detected GD25Q32(B) with page size 1000, total 400000
SF: Detected GD25Q32(B) with page size 1000, total 400000
FMAP: Found "FMAP" version 1.0 at 01000000.
FMAP: base = 0 size = 400000 #areas = 22
FMAP: area RW_ELOG found
FMAP: offset: 27c000
FMAP: size: 16384 bytes
FMAP: RW_ELOG at 0027c000 (offset 27c000)
ELOG: FLASH @0x00215248 [SPI 0x0027c000]
ELOG: area is 4096 bytes, full threshold 3072, shrink size 1024
ELOG: Event(17) added with size 13
ELOG: Event(A0) added with size 9
elog_add_boot_reason: Logged dev mode boot
Root Device init 7528 usecs
CPU_CLUSTER: 0 init
LCD framebuffer @10800000
Mapping address range [0x10800000:0x11000000) as uncached
Attempting to setup EDP display.
do not get hpd single, force hpd
Extracted contents:
header: 00 ff ff ff ff ff ff 00
serial number: 0d ae c4 15 00 00 00 00 28 17
version: 01 04
basic params: 95 22 13 78 02
chroma info: ef 05 90 54 52 93 29 25 50 54
established: 00 00 00
standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1: 5e 35 80 96 70 38 14 40 2c 1c 24 00 58 c1 10 00 00 18
descriptor 2: 00 00 00 fe 00 4e 31 35 36 48 47 45 2d 45 41 42 0a 20
descriptor 3: 00 00 00 fe 00 43 4d 4e 0a 20 20 20 20 20 20 20 20 20
descriptor 4: 00 00 00 fe 00 4e 31 35 36 48 47 45 2d 45 41 42 0a 20
extensions: 00
checksum: 1d
Manufacturer: CMN Model 15c4 Serial Number 0
Made week 40 of 2013
EDID version: 1.4
Digital display
6 bits per primary color channel
DisplayPort interface
Maximum image size: 34 cm x 19 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 5e358096703814402c1c240058c110000018
Detailed mode (IN HEX): Clock 136620 KHz, 158 mm x c1 mm
0780 07ac 07c8 0816 hborder 0
0438 043a 043e 044c vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 000000fe004e3135364847452d4541420a20
ASCII string: N156HGE-EAB
Hex of detail: 000000fe00434d4e0a202020202020202020
ASCII string: CMN
Hex of detail: 000000fe004e3135364847452d4541420a20
ASCII string: N156HGE-EAB
Checksum
Checksum: 0x1d (valid)
Configuring PLL at ff760040 with NF = 1346, NR = 59 and NO = 4 (VCO = 547525KHz, output = 136881KHz)
requested signal parameters: lane 0 voltage 0.6V pre_emph 0dB
requested signal parameters: lane 1 voltage 0.6V pre_emph 0dB
using signal parameters: voltage 0.6V pre_emph 0dB
requested signal parameters: lane 0 voltage 0.8V pre_emph 0dB
requested signal parameters: lane 1 voltage 0.8V pre_emph 0dB
using signal parameters: voltage 0.8V pre_emph 0dB
requested signal parameters: lane 0 voltage 1.2V pre_emph 0dB
requested signal parameters: lane 1 voltage 1.2V pre_emph 0dB
using signal parameters: voltage 1.2V pre_emph 0dB
clock recovery reached max voltage
clock recovery failed
link train failed!
edp enable err
CPU_CLUSTER: 0 init 217066 usecs
Devices initialized
Show all devs...After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
BS: BS_DEV_INIT times (us): entry 2 run 224649 exit 1
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE times (us): entry 2 run 10 exit 2
BS: BS_OS_RESUME_CHECK times (us): entry 2 run 3 exit 1
Writing coreboot table at 0x7ffeb000
rom_table_end = 0x7ffeb000
... aligned to 0x7fff0000
0. 0000000000000000-000000007ffeafff: RAM
1. 000000007ffeb000-000000007fffffff: CONFIGURATION TABLES
out: cmd=0x87: 03 aa 87 00 00 00 04 00 e4 c4 20 00
in-header: 03 d9 00 00 04 00 00 00
in-data: 00 20 00 00
Added 9 GPIOS size 264
RAM Config: 0.
Wrote coreboot table at: 7ffeb000, 0x260 bytes, checksum 12ba
coreboot table: 632 bytes.
CBMEM ROOT 0. 7ffff000 00001000
CONSOLE 1. 7ffef000 00010000
TIME STAMP 2. 7ffee000 00001000
VBOOT 3. 7ffed000 00001000
COREBOOT 4. 7ffeb000 00002000
BS: BS_WRITE_TABLES times (us): entry 1 run 633 exit 1
Booting 0xfdb9 byte verified payload at 0x00202024.
Loading segment from rom address 0x010003d4
code (compression=1)
New segment dstaddr 0x43104040 memsize 0x1047670 srcaddr 0x100040c filesize 0xfd81
Loading segment from rom address 0x010003f0
Entry Point 0x43104041
Loading Segment: addr: 0x0000000043104040 memsz: 0x0000000001047670 filesz: 0x000000000000fd81
lb: [0x0000000000200000, 0x0000000000219248)
Post relocation: addr: 0x0000000043104040 memsz: 0x0000000001047670 filesz: 0x000000000000fd81
using LZMA
[ 0x43104040, 43120f54, 0x4414b6b0) <- 0100040c
Clearing Segment: addr: 0x0000000043120f54 memsz: 0x000000000102a75c
dest 43104040, end 4414b6b0, bouncebuffer fffcdb70
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 1 run 85867 exit 1
Jumping to boot code at 43104041
CPU0: stack: ff717580 - ff718000, lowest used address ff7176e8, stack used: 2328 bytes
entry = 43104041
Starting depthcharge on veyron_speedy...
The GBB signature is at 0x43004020 and is: 24 47 42 42
Wipe memory regions:
[0x00000000000000, 0x00000002000000)
[0x00000002000200, 0x00000031f00000)
[0x00000032000000, 0x00000043000000)
[0x0000004414b6b0, 0x0000007ffeb000)
Initializing DWC2 USB controller at 0xff540000.
Initializing DWC2 USB controller at 0xff580000.
Calling VbSelectAndLoadKernel().
cros_ec_init: CrosEC protocol v3 supported (544, 544)
Google ChromeOS EC driver ready, id 'speedy_v1.1.2712-242f6bd'
Clearing the recovery request.
VbEcSoftwareSync(devidx=0)
EC hash:35e04e84ca847cebcb21819b112e56340adc8c345c39c770d469ba0adf197e46
EC-RW hash address, size are 0x433554e8, 32.
Hash = 35e04e84ca847cebcb21819b112e56340adc8c345c39c770d469ba0adf197e46
Expected hash:35e04e84ca847cebcb21819b112e56340adc8c345c39c770d469ba0adf197e46
VbEcSoftwareSync() jumping to EC-RW
Timeout waiting for framing byte.
Received invalid handshake 0
VbEcSoftwareSync() jumped to EC-RW
VbEcSoftwareSync() in RW; done
TPM: TlclRead(0x1008, 13)
1.2 TPM (chip type slb9645tt device-id 0x1A)
TPM: command 0xcf returned 0x0
TPM: command 0x65 returned 0x0
TPM: RollbackKernelRead 30002
Entering VbBootDeveloper()
backlight_update called but not implemented.
leaving VbDisplayScreenFromGBB() with 0
VbAudioOpen() - ticks_per_msec is 1000
VbAudioOpen() - VbExBeep() is limited
VbGetDevMusicNotes: use_short is 0, hdr is 0x0, maxsize is 0
VbGetDevMusicNotes: using 5 default notes
VbAudioOpen() - note count 5
max98090_device_init: Hardware revision: �
max98090_set_sysclk: Clock at 12288000Hz
rockchip_i2s_init: 16, 256, 2
VbBootDeveloper() - trying fixed disk
VbTryLoadKernel() start, get_info_flags=0x2
Man 000090 Snr 1469163228 Product HAG2e� Revision 0.3
VbTryLoadKernel() found 1 disks
VbTryLoadKernel() trying disk 0
Primary GPT header is being ignored
GptNextKernelEntry looking at new prio partition 2
GptNextKernelEntry s1 t0 p2
GptNextKernelEntry looking at new prio partition 4
GptNextKernelEntry s1 t0 p1
GptNextKernelEntry looking at new prio partition 6
GptNextKernelEntry s0 t15 p0
GptNextKernelEntry likes partition 2
Found kernel entry at 20480 size 32768
Checking key block signature...
- sig_size=512, expecting 512 for algorithm 8
- sig_size=256, expecting 256 for algorithm 4
Kernel preamble is good.
- sig_size=256, expecting 256 for algorithm 4
Partition is good.
Same kernel version
Not updating primary GPT: marked to be ignored.
Good_partition >= 0
VbTryLoadKernel() LoadKernel() = 0
backlight_update called but not implemented.
VbDisplayScreenFromGBB(): screen 0 not in the GBB
leaving VbDisplayScreenFromGBB() with 65557
TPM: Lock physical presence
TPM: command 0x4000000a returned 0x0
VbSelectAndLoadKernel() returning 0
Loading FIT.
Image fdt@23 has 43148 bytes.
Image fdt@22 has 44661 bytes.
Image fdt@21 has 43927 bytes.
Image fdt@20 has 43747 bytes.
Image fdt@19 has 36867 bytes.
Image fdt@18 has 44095 bytes.
Image fdt@17 has 45239 bytes.
Image fdt@16 has 44284 bytes.
Image fdt@15 has 37733 bytes.
Image fdt@14 has 46609 bytes.
Image fdt@13 has 43249 bytes.
Image fdt@12 has 46645 bytes.
Image fdt@11 has 44151 bytes.
Image fdt@10 has 44151 bytes.
Image fdt@9 has 40193 bytes.
Image fdt@8 has 33084 bytes.
Image fdt@7 has 31949 bytes.
Image fdt@6 has 40617 bytes.
Image fdt@5 has 40771 bytes.
Image fdt@4 has 40553 bytes.
Image fdt@3 has 37476 bytes.
Image fdt@2 has 12808 bytes.
Image fdt@1 has 13397 bytes.
Image kernel@1 has 4492752 bytes.
Compat preference: google,veyron-speedy-rev6
Config conf@23, kernel kernel@1, fdt fdt@23, compat google,veyron-tiger-rev8 google,veyron-tiger-rev7 google,veyron-tiger-rev6 google,veyron-tiger-rev5 google,veyron-tiger-rev4 google,veyron-tiger-rev3 google,veyron-tiger-rev2 google,veyron-tiger-rev1 google,veyron-tiger-rev0 google,veyron-tiger google,veyron rockchip,rk3288
Config conf@22, kernel kernel@1, fdt fdt@22, compat google,veyron-thea-rev0 google,veyron-thea-rev1 google,veyron-thea-rev2 google,veyron-thea-rev3 google,veyron-thea-rev4 google,veyron-thea google,veyron rockchip,rk3288
Config conf@21, kernel kernel@1, fdt fdt@21, compat google,veyron-speedy-rev9 google,veyron-speedy-rev8 google,veyron-speedy-rev7 google,veyron-speedy-rev6 (match) google,veyron-speedy-rev5 google,veyron-speedy-rev4 google,veyron-speedy-rev3 google,veyron-speedy-rev2 google,veyron-speedy google,veyron rockchip,rk3288
Config conf@20, kernel kernel@1, fdt fdt@20, compat google,veyron-speedy-rev1 google,veyron-speedy google,veyron rockchip,rk3288
Config conf@19, kernel kernel@1, fdt fdt@19, compat google,veyron-rialto-rev3 google,veyron-rialto-rev2 google,veyron-rialto-rev1 google,veyron-rialto-rev0 google,veyron-rialto google,veyron rockchip,rk3288
Config conf@18, kernel kernel@1, fdt fdt@18, compat google,veyron-nicky-rev0 google,veyron-nicky google,veyron rockchip,rk3288
Config conf@17, kernel kernel@1, fdt fdt@17, compat google,veyron-minnie-rev4 google,veyron-minnie-rev3 google,veyron-minnie-rev2 google,veyron-minnie-rev1 google,veyron-minnie-rev0 google,veyron-minnie google,veyron rockchip,rk3288
Config conf@16, kernel kernel@1, fdt fdt@16, compat google,veyron-mighty-rev5 google,veyron-mighty-rev4 google,veyron-mighty-rev3 google,veyron-mighty-rev2 google,veyron-mighty-rev1 google,veyron-mighty google,veyron rockchip,rk3288
Config conf@15, kernel kernel@1, fdt fdt@15, compat google,veyron-mickey-rev8 google,veyron-mickey-rev7 google,veyron-mickey-rev6 google,veyron-mickey-rev5 google,veyron-mickey-rev4 google,veyron-mickey-rev3 google,veyron-mickey-rev2 google,veyron-mickey-rev1 google,veyron-mickey-rev0 google,veyron-mickey google,veyron rockchip,rk3288
Config conf@14, kernel kernel@1, fdt fdt@14, compat google,veyron-jerry-rev7 google,veyron-jerry-rev6 google,veyron-jerry-rev5 google,veyron-jerry-rev4 google,veyron-jerry-rev3 google,veyron-jerry google,veyron rockchip,rk3288
Config conf@13, kernel kernel@1, fdt fdt@13, compat google,veyron-jerry-rev2 google,veyron-jerry google,veyron rockchip,rk3288
Config conf@12, kernel kernel@1, fdt fdt@12, compat google,veyron-jerry-rev10 google,veyron-jerry-rev11 google,veyron-jerry-rev12 google,veyron-jerry-rev13 google,veyron-jerry-rev13 google,veyron-jerry-rev14 google,veyron-jerry-rev15 google,veyron rockchip,rk3288
Config conf@11, kernel kernel@1, fdt fdt@11, compat google,veyron-jaq-rev5 google,veyron-jaq-rev4 google,veyron-jaq-rev3 google,veyron-jaq-rev2 google,veyron-jaq-rev1 google,veyron-jaq google,veyron rockchip,rk3288
Config conf@10, kernel kernel@1, fdt fdt@10, compat google,veyron-gus-rev5 google,veyron-gus-rev4 google,veyron-gus-rev3 google,veyron-gus-rev2 google,veyron-gus-rev1 google,veyron-gus google,veyron rockchip,rk3288
Config conf@9, kernel kernel@1, fdt fdt@9, compat google,veyron-fievel-rev8 google,veyron-fievel-rev7 google,veyron-fievel-rev6 google,veyron-fievel-rev5 google,veyron-fievel-rev4 google,veyron-fievel-rev3 google,veyron-fievel-rev2 google,veyron-fievel-rev1 google,veyron-fievel-rev0 google,veyron-fievel google,veyron rockchip,rk3288
Config conf@8, kernel kernel@1, fdt fdt@8, compat rockchip,rk3288-evb-rk808 rockchip,rk3288
Config conf@7, kernel kernel@1, fdt fdt@7, compat rockchip,rk3288-evb-act8846 rockchip,rk3288
Config conf@6, kernel kernel@1, fdt fdt@6, compat google,veyron-emile-rev8 google,veyron-emile-rev7 google,veyron-emile-rev6 google,veyron-emile-rev5 google,veyron-emile-rev4 google,veyron-emile-rev3 google,veyron-emile-rev2 google,veyron-emile-rev1 google,veyron-emile-rev0 google,veyron-emile google,veyron rockchip,rk3288
Config conf@5, kernel kernel@1, fdt fdt@5, compat google,veyron-danger-rev1 google,veyron-danger google,veyron rockchip,rk3288
Config conf@4, kernel kernel@1, fdt fdt@4, compat google,veyron-danger-rev0 google,veyron-danger google,veyron rockchip,rk3288
Config conf@3, kernel kernel@1, fdt fdt@3, compat google,veyron-brain-rev0 google,veyron-brain google,veyron rockchip,rk3288
Config conf@2, kernel kernel@1, fdt fdt@2, compat radxa,rock rockchip,rk3188
Config conf@1 (default), kernel kernel@1, fdt fdt@1, compat mundoreader,bq-curie2 rockchip,rk3066a
Choosing best match conf@21.
Shutting down all USB controllers.
Exiting depthcharge with code 4 at timestamp: 34219308
Last active
March 3, 2018 12:16
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