Hardware Bit Scan Forwards / Priority Encoder (Written in System Verilog using a parallel binary search-like approach)

bit_scan.sv

/*
The MIT License (MIT)

Copyright (c) 2022 Martin Andronikos

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

/*
Originally created in 2022 for use in LordDecapo's ProcessORC teaching CPU project:
https://github.com/LTDS-Capo/ProcessORC/blob/main/rtl/ALU/ALU_Simple1.sv
For an excellent explanation of the bit hack used (but implemented in hardware) and
of a bunch of other neat tricks watch this video by Creel https://youtu.be/ZRNO-ewsNcQ?t=784
*/

module bit_scan #(
	parameter BITWIDTH = 16,
	parameter BITMASKS = $clog2(BITWIDTH)
)(
	input [BITWIDTH-1:0] data_in,
	output [BITWIDTH-1:0] data_out
);

wire [BITWIDTH-1:0] one_hot = data_in & -data_in;

logic [BITWIDTH-1:0] bitmask [BITMASKS-1:0];
logic [BITMASKS-1:0] masked_region_flags;
genvar curr_mask, curr_bit;
generate
	// for every bitmask
	for(curr_mask=0; curr_mask<BITMASKS; curr_mask=curr_mask+1) begin : outer
		// for every bit in the bitmask
		for(curr_bit=0; curr_bit<BITWIDTH; curr_bit=curr_bit+1) begin : inner
			// if the curr_mask-th bit of the current bit index is set
			// then set the current bit in the current bitmask to 1, else set to 0
			assign bitmask[curr_mask][curr_bit] = (curr_bit&(1<<curr_mask))>>curr_mask;
			// bitmask n pays attention to the n-th bit of the current bit index
		end
		// use the current mask on the input and or-reduce the result to 1 bit
		// then put that bit in the curr_mask-th bit of the output
		assign masked_region_flags[curr_mask] = | (one_hot & bitmask[curr_mask]);
	end
endgenerate

// add 1 to the index to leave all 0s output as an indicator for no 1s in input 
wire [BITMASKS:0] addr_index = {1'b0, masked_region_flags} + {{BITMASKS{1'b0}},1'b1};
// pad the result with 0s to BITWIDTH bits
// if the input had no 1s output a 0, else output the index of the bit
assign data_out = (| data_in) ? {{BITWIDTH-BITMASKS-1{1'b0}}, addr_index} : {BITWIDTH{1'b0}};

endmodule