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Arithmetic bidirectional barrel shifter
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module MATHSHIFTTEST; | |
reg[15:0] ia; | |
reg[3:0] bitcnt; | |
reg lr; | |
wire[15:0] ib; | |
MATHSHIFT mathshift (ia, bitcnt, lr, ib); | |
initial begin | |
$dumpfile("mathshift.vcd"); | |
$dumpvars(0, MATHSHIFTTEST); | |
$monitor("%t: a = %b, bitcnt = %b, lr = %b, b = %b", $time, ia, bitcnt, lr, ib); | |
ia = 16'b1101000000000011; bitcnt = 4'b0000; lr = 0; | |
#2 ia = 16'b1101000000000011; bitcnt = 4'b0011; lr = 1; | |
#2 ia = 16'b0000000000011111; bitcnt = 4'b0001; lr = 0; | |
#2 ia = 16'b0000000000011111; bitcnt = 4'b0101; lr = 0; | |
#2 $finish; | |
end | |
endmodule | |
module MUX (A, B, S, X); | |
input A, B, S; | |
output X; | |
assign X = (S == 1'b0) ? A : B; | |
endmodule | |
module REVERSE #(parameter width = 16,parameter bits = 4) | |
( | |
input[width-1:0] IA, | |
input TF, | |
output[width-1:0] IB | |
); | |
genvar i; | |
generate | |
for(i = 0; i < width; i = i + 1) begin: tiuvs | |
MUX mux(IA[i], IA[width-i-1], TF, IB[i]); | |
end | |
endgenerate | |
endmodule | |
module MATHSHIFT #(parameter width = 16,parameter bits = 4) | |
( | |
input[width-1:0] IA, | |
input[bits-1:0] BITS, | |
input LR, | |
output[width-1:0] IB | |
); | |
wire [width-1:0] WI1;//reverse, do operations, and reverse | |
wire [width-1:0] WI2; | |
REVERSE reverse1(IA, LR, WI1); | |
MATHSHIFTKERNEL mathshiftkernel(WI1, BITS, WI2); | |
REVERSE reverse2(WI2, LR, IB); | |
endmodule | |
module MATHSHIFTKERNEL #(parameter width = 16,parameter bits = 4) | |
( | |
input[width-1:0] IA, | |
input[bits-1:0] BITS, | |
output[width-1:0] IB | |
); | |
wire [width-1:0] WI2D [bits:0];//WI2D[bits:0][width-1:0] | |
genvar i,j;//connecting the input to the wires | |
generate | |
for(j = 0; j < width; j = j + 1) begin: ewsxsdf //initializing first row wire | |
assign WI2D[0][j] = IA[j]; | |
end | |
endgenerate | |
generate | |
for(i = 0; i < bits; i = i + 1) begin: afsdhr //iterating through columns | |
//filling 0 in | |
for(j = 0; j < 2**i; j = j + 1) begin: febasjh //inside column | |
MUX mux(WI2D[i][j],1'b0,BITS[i],WI2D[i+1][j]); | |
end | |
//diagonal carry from previous MUL | |
for(j = 2**i; j < width; j = j + 1) begin: adfasfew //continuation of the same column | |
MUX mux(WI2D[i][j],WI2D[i][j-2**i],BITS[i],WI2D[i+1][j]); | |
end | |
end | |
endgenerate | |
//connecting the wires to the output | |
generate | |
for(j = 0; j < width; j = j + 1) begin: quydsd //initializing first row wire | |
assign IB[j] = WI2D[bits][j]; | |
end | |
endgenerate | |
endmodule | |
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