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July 4, 2019 14:15
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| src/Clash/Primitives/Intel/Fourteennm.hs:419:43: error: | |
| • Expected kind ‘k1 -> *’, but ‘Reset clk’ has kind ‘*’ | |
| • In the second argument of ‘(:::)’, namely ‘Reset clk synchronous’ | |
| In the type signature: | |
| fourteennm_mac# :: forall ax | |
| ay_scan_in | |
| az | |
| bx | |
| by | |
| bz | |
| result_a | |
| result_b | |
| scan_out | |
| load_const_value | |
| clk | |
| gated | |
| synchronous. | |
| (ax <= 27, ay_scan_in <= 27, az <= 26, bx <= 18, by <= 19) => | |
| ("ax_width" ::: SNat ax) | |
| -> ("ay_scan_in_width" ::: SNat ay_scan_in) | |
| -> ("az_width" ::: SNat az) | |
| -> ("bx_width" ::: SNat bx) | |
| -> ("by_width" ::: SNat by) | |
| -> ("bz_width" ::: SNat bz) | |
| -> ("result_a_width" ::: SNat result_a) | |
| -> ("result_b_width" ::: SNat result_b) | |
| -> ("scan_wout_width" ::: SNat scan_out) | |
| -> ("operation_mode" ::: MAC_OperationMode) | |
| -> ("operand_source_max" | |
| ::: MAC_OperandSource) | |
| -> ("operand_source_may" | |
| ::: MAC_OperandSource) | |
| -> ("operand_source_mbx" | |
| ::: MAC_OperandSource) | |
| -> ("operand_source_mby" | |
| ::: MAC_OperandSource) | |
| -> ("preadder_subtract_a" | |
| ::: BoolS) | |
| -> ("preadder_subtract_b" | |
| ::: BoolS) | |
| -> ("signed_max" ::: BoolS) | |
| -> ("signed_may" | |
| ::: BoolS) | |
| -> ("signed_mbx" | |
| ::: BoolS) | |
| -> ("signed_mby" | |
| ::: BoolS) | |
| -> ("ay_use_scan_in" | |
| ::: BoolS) | |
| -> ("by_use_scan_in" | |
| ::: | |
| BoolS) | |
| -> ("delay_scan_out_ay" | |
| ::: | |
| BoolS) | |
| -> ("delay_scan_out_by" | |
| ::: | |
| BoolS) | |
| -> ("use_chainadder" | |
| ::: | |
| BoolS) | |
| -> ("enable_double_accum" | |
| ::: | |
| BoolS) | |
| -> ("load_const_value" | |
| ::: | |
| SNat load_const_value) | |
| -> ("ax_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("ay_scan_in_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("az_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("bx_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("by_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("bz_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("sub_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("negate_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("accumulate_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("accum_pipeline_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("accum_snd_pipeline_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("load_const_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("load_const_pipeline_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("load_const_snd_pipeline_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("output_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("chainout_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("input_pipeline_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("second_pipeline_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("input_systolic_clock" | |
| ::: | |
| MAC_Clock) | |
| -> ("clk" | |
| ::: | |
| Clock clk gated) | |
| -> ("clr" | |
| ::: | |
| Reset clk synchronous) | |
| -> ("sub" | |
| ::: | |
| Signal clk Bit) | |
| -> ("negate" | |
| ::: | |
| Signal clk Bit) | |
| -> ("accumulate" | |
| ::: | |
| Signal clk Bit) | |
| -> ("loadconst" | |
| ::: | |
| Signal clk Bit) | |
| -> ("ax" | |
| ::: | |
| Signal clk (BitVector ax)) | |
| -> ("ay" | |
| ::: | |
| Signal clk (BitVector ay_scan_in)) | |
| -> ("az" | |
| ::: | |
| Signal clk (BitVector az)) | |
| -> ("bx" | |
| ::: | |
| Signal clk (BitVector bx)) | |
| -> ("by" | |
| ::: | |
| Signal clk (BitVector by)) | |
| -> ("bz" | |
| ::: | |
| Signal clk (BitVector bz)) | |
| -> ("coefsela" | |
| ::: | |
| Signal clk (BitVector 3)) | |
| -> ("coefselb" | |
| ::: | |
| Signal clk (BitVector 3)) | |
| -> ("scanin" | |
| ::: | |
| Signal clk (BitVector ay_scan_in)) | |
| -> ("chainin" | |
| ::: | |
| Signal clk (BitVector 64)) | |
| -> ("resulta" | |
| ::: | |
| Signal clk (BitVector result_a), | |
| "resultb" | |
| ::: | |
| Signal clk (BitVector result_b), | |
| "scanout" | |
| ::: | |
| Signal clk (BitVector scan_out), | |
| "chainout" | |
| ::: | |
| Signal clk (BitVector 64)) | |
| | | |
| 419 | -> ("clr" ::: Reset clk synchronous) |
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