log

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run.tcl
# read_verilog top.v
# set_property -name top -value top -objects [current_fileset -sim]
# set_property -name xsim.elaborate.xelab.more_options -value {-L xpm} -objects [current_fileset -sim]
# save_project_as sim project -force
# set_property RUNTIME all [current_fileset -sim]
# launch_simulation -step compile
Command: launch_simulation -step compile
INFO: [Vivado 12-12493] Simulation top is 'top'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/opt/Xilinx/Vivado/2022.2/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'top' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/martijn/code/vl_logic_issue/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
# launch_simulation -step elaborate
Command: launch_simulation -step elaborate
INFO: [Vivado 12-12493] Simulation top is 'top'
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log -L xpm
Vivado Simulator v2022.2
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log -L xpm 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-3355] formal port 'src_clk' of type 'vl_logic' does not match with actual type 'wire' [/home/martijn/code/vl_logic_issue/top.v:16]
ERROR: [VRFC 10-3355] formal port 'dest_clk' of type 'vl_logic' does not match with actual type 'wire' [/home/martijn/code/vl_logic_issue/top.v:17]
ERROR: [VRFC 10-3355] formal port 'src_in_bin' of type 'vl_logic_vector' does not match with actual type 'wire' [/home/martijn/code/vl_logic_issue/top.v:18]
ERROR: [VRFC 10-3355] formal port 'dest_out_bin' of type 'vl_logic_vector' does not match with actual type 'wire' [/home/martijn/code/vl_logic_issue/top.v:19]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/martijn/code/vl_logic_issue/project/sim.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

    while executing
"launch_simulation -step elaborate"
    (file "run.tcl" line 10)
INFO: [Common 17-206] Exiting Vivado at Wed Apr 19 20:43:00 2023...