R2 first boot emmc

emmc.txt

[USBD] USB PRB0 LineState: 0

[USBD] USB cable/ No Cable inserted!

[PLFM] Keep stay in USB Mode
Platform initialization is ok
wait for frequency meter finish, CLK26CALI = 0x81
mt_pll_post_init: mt_get_cpu_freq = 1040000Khz
wait for frequency meter finish, CLK26CALI = 0x90
mt_pll_post_init: mt_get_bus_freq = 273000Khz
wait for frequency meter finish, CLK26CALI = 0x81
mt_pll_post_init: mt_get_mem_freq = 133250Khz
[PWRAP] pwrap_init_preloader
[PWRAP] pwrap_init
pwrap_init_sistrobe [Read Test] fail,index=12,rdata=B54Bata=2D52
[PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=13,rdata=B54B
[PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=14,rdata=B54B
[PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=15,rdata=B54B
[PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=16,rdata=B54B
[PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=17,rdata=B54B
[PWRAP] _pwrap_init_sistrobe [Read Test] fail,index=18,rdata=B54B
[PWRAP] _pwrap_init_sistrobe [Read Test] fai[pmic6323_init] Done...................
mt7623 disable long press reset ->>>>>
mt7623 disable long press reset <<<<<-
mt7623 VPA supplied by 1.0V to MT7530 ->
mt7623 VPA supplied by 1.0V to MT7530 <-
mt7623 enables RG_VGP1_EN for LCM ->
mt7623 enables RG_VGP1_EN for LCM <-
MT7623 E2 setting =>
MT7623 E2 setting <=
[PLFM] Init I2C: OK(0)
[PLFM] Init PWRAP: OK(0)
[PLFM] Init PMIC: OK(0)
[PLFM] chip[CA00]

[BLDR] [Support SD/eMMC] Build Time: 20170905-120917
==== Dump RGU Reg ========
RGU MODEafter set KP enable: KP_SEL = 0x0 !
MTK_PMIC_RST_KEY is used for this project!
[RTC] get_frequet=3967
[RTC] get_freque ouput=5
[RTC] get_freque[RTC] get_frequeut=0x0, ouput=0
[RTC] bbpu = 0xD, con = 0x426
[RTC] powerkey1 = 0xA357, powerkey2 = 0x67D2
 0x201, spar0 = 0x40, spar1 = 0x800
[RTC] new_spare0 = 0x0, new_spare1 = 0x1, new_spare2 = 0x1, new_spare3 = 0x1
[RTC] bbpu = 0xD, con = 0x426, cali = 0x300
pl pmic powerkey Release
[PLFM] Power key boot!
[RTC] rtc_bbpu_power_on done
[EMI] mcp_dram_num:0,discrete_dram_num:1,enable_combo_dis:0
[EMI] PCDDR3
[Check]mt_get_mdl_number 0x0
[EMI] eMMC/NAND ID = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
[EMI] MDL number = 0
[EMI] emi_set eMMC/NAND ID = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
[EMI][Vcore]0x21te1  byte2  byte3
-----------------------------
0    0    0    0    0    
1    0    0    0    0    
2    0    1    0    0    
3    0    1    0    0    
4    0    1    0    0    
5    0    1    0    0    
6    0    1    0    0    
7    0    1    0    0    
8    0    1    0    0    
9    0    1    0    0    
10    0    1    0    0    
11    0    1    0    0    
12    0    1    0    0    
13    0    1    0    0    
14    0    1    0    0    
15    0    1    0    0    
pass ----------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0   0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0   Load u-boot from eMMC...
[PLFM] Init Boot Device: OK(0)

[PART] blksz: 512B
[PART] [0x0000000000000000-0x000000000003FFFF] "PRELOADER" (512 blocks) 
[PART] [0x0000000000000000-0x000000000003FFFF] "MBR" (512 blocks) 
[PART] [0x0000000000040000-0x00000000000BFFFF] "UBOOT" (1024 blocks) 
[PART] [0x00000000000C0000-0x00000000000FFFFF] "CONFIG" (512 blocks) 
[PART] [0x0000000000100000-0x000000000013FFFF] "FACTORY" (512 blocks) 
[PART] [0x0000000000140000-0x000000000213FFFF] "BOOTIMG" (65536 blocks) 
[PART] 0 
[PART]partition flags 0x0 
[PART]partition name 0x8 
[bean] part->startblk(0x200) bdev->blksz(0x200) part->part_id(8) hdr(0xFFB50000)
[BlkDev.c 101 ]partition block size 0x200 ,blks:0xE90000
[BlkDev.c 101 ]partition block erase size 0x200 

[PART] load "ze:80000000
[PLFM] md_type[0] = 249 
[PLFM] md_type[1] = 250 

[PLFM] boot reason: 0
[PLFM] boot mode: 0
[PLFM] META COM0: 0
[PLFM] <0xFFB7CC10>: 0x0
[PLFM] boot time: 1995ms
[PLFM] DDR reserve mode: enable = 0, success = 0

[BLDR] jump to 0x81E00000
[BLDR] <0x81E00000>=0xEA0000B8
[BLDR] <0x81E00004>=0xE59FF014