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| .amdgcn_target "amdgcn-amd-amdhsa-hcc-gfx900" | |
| .globl default_function_kernel0 | |
| .p2align 8 | |
| .type default_function_kernel0,@function | |
| default_function_kernel0: | |
| s_load_dwordx2 s[2:3], s[4:5], 0x0 | |
| s_load_dwordx2 s[8:9], s[4:5], 0x8 | |
| v_lshlrev_b32_e32 v15, 2, v1 | |
| s_load_dwordx2 s[4:5], s[4:5], 0x10 | |
| v_add_u32_e32 v3, v15, v0 | |
| s_movk_i32 s11, 0x200 | |
| v_mul_u32_u24_e32 v6, 24, v1 | |
| s_lshl_b32 s12, s6, 3 | |
| s_lshl_b32 s13, s7, 8 | |
| v_lshlrev_b32_e32 v13, 1, v6 | |
| v_cmp_gt_i32_e64 s[0:1], 1, v1 | |
| v_lshl_add_u32 v2, v3, 1, s11 | |
| v_lshrrev_b32_e32 v14, 3, v3 | |
| v_and_b32_e32 v3, 7, v3 | |
| v_lshlrev_b32_e32 v4, 1, v0 | |
| v_lshlrev_b32_e32 v1, 18, v1 | |
| s_add_i32 s6, s12, s13 | |
| v_add3_u32 v1, s6, v1, v4 | |
| v_lshl_or_b32 v4, v14, 4, v3 | |
| v_or_b32_e32 v7, 2, v13 | |
| v_or_b32_e32 v8, 4, v13 | |
| v_or_b32_e32 v9, 6, v13 | |
| v_or_b32_e32 v10, 8, v13 | |
| v_or_b32_e32 v11, 10, v13 | |
| v_or_b32_e32 v12, 12, v13 | |
| v_lshlrev_b32_e32 v5, 2, v0 | |
| v_add_u32_e32 v6, s11, v13 | |
| v_or_b32_e32 v13, 14, v13 | |
| v_lshl_add_u32 v14, v14, 8, s12 | |
| v_add_u32_e32 v0, s13, v0 | |
| s_movk_i32 s12, 0xe100 | |
| v_add3_u32 v0, v0, v15, s12 | |
| s_add_i32 s10, s7, -1 | |
| v_lshlrev_b32_e32 v4, 1, v4 | |
| v_add_u32_e32 v7, s11, v7 | |
| v_add_u32_e32 v8, s11, v8 | |
| v_add_u32_e32 v9, s11, v9 | |
| v_add_u32_e32 v10, s11, v10 | |
| v_add_u32_e32 v11, s11, v11 | |
| v_add_u32_e32 v12, s11, v12 | |
| v_add_u32_e32 v13, s11, v13 | |
| s_add_i32 s6, s7, 1 | |
| v_mov_b32_e32 v15, -1 | |
| v_mov_b32_e32 v16, 0 | |
| s_movk_i32 s12, 0x2000 | |
| s_branch BB0_2 | |
| BB0_1: | |
| s_or_b64 exec, exec, s[14:15] | |
| v_add_u32_e32 v16, 1, v16 | |
| v_cmp_eq_u32_e32 vcc, 32, v16 | |
| v_add_u32_e32 v0, s12, v0 | |
| s_and_b64 vcc, exec, vcc | |
| v_add_u32_e32 v15, 1, v15 | |
| s_cbranch_vccnz BB0_20 | |
| BB0_2: | |
| v_mov_b32_e32 v24, 0 | |
| v_mov_b32_e32 v17, 0 | |
| v_mov_b32_e32 v18, v0 | |
| v_mov_b32_e32 v19, v14 | |
| s_branch BB0_4 | |
| BB0_3: | |
| v_add_u32_e32 v17, 1, v17 | |
| v_cmp_eq_u32_e32 vcc, 16, v17 | |
| v_add_u32_e32 v19, 0x1000, v19 | |
| s_and_b64 vcc, exec, vcc | |
| v_add_u32_e32 v18, 16, v18 | |
| s_cbranch_vccnz BB0_18 | |
| BB0_4: | |
| v_mov_b32_e32 v20, 0 | |
| v_mov_b32_e32 v21, v15 | |
| v_mov_b32_e32 v22, v18 | |
| s_branch BB0_6 | |
| BB0_5: | |
| s_or_b64 exec, exec, s[14:15] | |
| v_add_u32_e32 v20, 0x30000, v20 | |
| v_cmp_eq_u32_e32 vcc, 0x90000, v20 | |
| v_add_u32_e32 v22, s12, v22 | |
| s_and_b64 vcc, exec, vcc | |
| v_add_u32_e32 v21, 1, v21 | |
| s_cbranch_vccnz BB0_3 | |
| BB0_6: | |
| s_waitcnt vmcnt(0) lgkmcnt(0) | |
| s_barrier | |
| v_or_b32_e32 v23, s10, v21 | |
| v_cmp_gt_u32_e32 vcc, 32, v23 | |
| s_and_b64 vcc, exec, vcc | |
| v_mov_b32_e32 v23, 0 | |
| s_cbranch_vccz BB0_8 | |
| v_add_u32_e32 v25, 0xfffffe00, v22 | |
| v_ashrrev_i32_e32 v26, 31, v25 | |
| v_lshlrev_b64 v[25:26], 1, v[25:26] | |
| v_mov_b32_e32 v23, s3 | |
| v_add_co_u32_e32 v25, vcc, s2, v25 | |
| v_addc_co_u32_e32 v26, vcc, v23, v26, vcc | |
| global_load_ushort v23, v[25:26], off | |
| BB0_8: | |
| v_add_u32_e32 v25, v19, v20 | |
| v_or_b32_e32 v26, v25, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v2, v23 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_mov_b32_e32 v23, s9 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 | |
| v_add_u32_e32 v23, s11, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:64 | |
| v_add_u32_e32 v23, 0x400, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:128 | |
| v_add_u32_e32 v23, 0x600, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:192 | |
| v_add_u32_e32 v23, 0x800, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:256 | |
| v_add_u32_e32 v23, 0xa00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:320 | |
| v_add_u32_e32 v23, 0xc00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:384 | |
| v_add_u32_e32 v23, 0xe00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:448 | |
| s_waitcnt lgkmcnt(0) | |
| s_barrier | |
| s_and_saveexec_b64 s[14:15], s[0:1] | |
| s_cbranch_execz BB0_10 | |
| BB0_9: | |
| ds_read2_b32 v[30:31], v5 offset1:8 | |
| ds_read_u16 v23, v6 | |
| ds_read2_b64 v[26:29], v6 offset0:2 offset1:3 | |
| ds_read_u16 v32, v7 | |
| ds_read_u16 v33, v8 | |
| ds_read_u16 v34, v9 | |
| s_waitcnt lgkmcnt(4) | |
| s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 | |
| v_pk_fma_f16 v23, v23, v30, v24 op_sel_hi:[0,1,1] | |
| ds_read_u16 v30, v10 | |
| s_waitcnt lgkmcnt(3) | |
| v_pk_fma_f16 v31, v32, v31, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:16 offset1:24 | |
| ds_read_u16 v35, v11 | |
| s_waitcnt lgkmcnt(1) | |
| v_pk_fma_f16 v23, v33, v23, v31 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v31, v34, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:32 offset1:40 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v30, v23, v31 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v30, v35, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read_u16 v31, v12 | |
| ds_read_u16 v32, v13 | |
| ds_read2_b32 v[23:24], v5 offset0:48 offset1:56 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v31, v23, v30 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v30, v32, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:64 offset1:72 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v26, v23, v30 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v26, v26, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:80 offset1:88 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v27, v23, v26 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v26, v27, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:96 offset1:104 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v28, v23, v26 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v26, v28, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:112 offset1:120 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v29, v23, v26 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v24, v29, v24, v23 op_sel:[1,0,0] | |
| BB0_10: | |
| s_or_b64 exec, exec, s[14:15] | |
| s_barrier | |
| v_or_b32_e32 v23, s7, v21 | |
| v_cmp_gt_u32_e32 vcc, 32, v23 | |
| s_and_b64 vcc, exec, vcc | |
| v_mov_b32_e32 v23, 0 | |
| s_cbranch_vccz BB0_12 | |
| v_add_u32_e32 v26, 0xffffff00, v22 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s3 | |
| v_add_co_u32_e32 v26, vcc, s2, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| BB0_12: | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v2, v23 | |
| v_add_u32_e32 v23, 0x10000, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 | |
| v_add_u32_e32 v23, 0x10200, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:64 | |
| v_add_u32_e32 v23, 0x10400, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:128 | |
| v_add_u32_e32 v23, 0x10600, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:192 | |
| v_add_u32_e32 v23, 0x10800, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:256 | |
| v_add_u32_e32 v23, 0x10a00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:320 | |
| v_add_u32_e32 v23, 0x10c00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:384 | |
| v_add_u32_e32 v23, 0x10e00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:448 | |
| s_waitcnt lgkmcnt(0) | |
| s_barrier | |
| s_and_saveexec_b64 s[14:15], s[0:1] | |
| s_cbranch_execz BB0_14 | |
| BB0_13: | |
| ds_read2_b32 v[30:31], v5 offset1:8 | |
| ds_read_u16 v23, v6 | |
| ds_read2_b64 v[26:29], v6 offset0:2 offset1:3 | |
| ds_read_u16 v32, v7 | |
| ds_read_u16 v33, v8 | |
| ds_read_u16 v34, v9 | |
| s_waitcnt lgkmcnt(4) | |
| s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 | |
| v_pk_fma_f16 v23, v23, v30, v24 op_sel_hi:[0,1,1] | |
| ds_read_u16 v30, v10 | |
| s_waitcnt lgkmcnt(3) | |
| v_pk_fma_f16 v31, v32, v31, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:16 offset1:24 | |
| ds_read_u16 v35, v11 | |
| s_waitcnt lgkmcnt(1) | |
| v_pk_fma_f16 v23, v33, v23, v31 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v31, v34, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:32 offset1:40 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v30, v23, v31 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v30, v35, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read_u16 v31, v12 | |
| ds_read_u16 v32, v13 | |
| ds_read2_b32 v[23:24], v5 offset0:48 offset1:56 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v31, v23, v30 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v30, v32, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:64 offset1:72 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v26, v23, v30 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v26, v26, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:80 offset1:88 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v27, v23, v26 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v26, v27, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:96 offset1:104 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v28, v23, v26 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v26, v28, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:112 offset1:120 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v29, v23, v26 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v24, v29, v24, v23 op_sel:[1,0,0] | |
| BB0_14: | |
| s_or_b64 exec, exec, s[14:15] | |
| s_barrier | |
| v_or_b32_e32 v23, s6, v21 | |
| v_cmp_lt_u32_e32 vcc, 31, v23 | |
| s_and_b64 vcc, exec, vcc | |
| v_mov_b32_e32 v23, 0 | |
| s_cbranch_vccnz BB0_16 | |
| v_ashrrev_i32_e32 v23, 31, v22 | |
| v_lshlrev_b64 v[26:27], 1, v[22:23] | |
| v_mov_b32_e32 v23, s3 | |
| v_add_co_u32_e32 v26, vcc, s2, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| BB0_16: | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v2, v23 | |
| v_add_u32_e32 v23, 0x20000, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 | |
| v_add_u32_e32 v23, 0x20200, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:64 | |
| v_add_u32_e32 v23, 0x20400, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:128 | |
| v_add_u32_e32 v23, 0x20600, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:192 | |
| v_add_u32_e32 v23, 0x20800, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:256 | |
| v_add_u32_e32 v23, 0x20a00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:320 | |
| v_add_u32_e32 v23, 0x20c00, v25 | |
| v_or_b32_e32 v26, v23, v3 | |
| v_ashrrev_i32_e32 v27, 31, v26 | |
| v_lshlrev_b64 v[26:27], 1, v[26:27] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v26, vcc, s8, v26 | |
| v_addc_co_u32_e32 v27, vcc, v23, v27, vcc | |
| global_load_ushort v23, v[26:27], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:384 | |
| v_add_u32_e32 v23, 0x20e00, v25 | |
| v_or_b32_e32 v25, v23, v3 | |
| v_ashrrev_i32_e32 v26, 31, v25 | |
| v_lshlrev_b64 v[25:26], 1, v[25:26] | |
| v_mov_b32_e32 v23, s9 | |
| v_add_co_u32_e32 v25, vcc, s8, v25 | |
| v_addc_co_u32_e32 v26, vcc, v23, v26, vcc | |
| global_load_ushort v23, v[25:26], off | |
| s_waitcnt vmcnt(0) | |
| ds_write_b16 v4, v23 offset:448 | |
| s_waitcnt lgkmcnt(0) | |
| s_barrier | |
| s_and_saveexec_b64 s[14:15], s[0:1] | |
| s_cbranch_execz BB0_5 | |
| BB0_17: | |
| ds_read2_b32 v[29:30], v5 offset1:8 | |
| ds_read_u16 v23, v6 | |
| ds_read2_b64 v[25:28], v6 offset0:2 offset1:3 | |
| ds_read_u16 v31, v7 | |
| ds_read_u16 v32, v8 | |
| ds_read_u16 v33, v9 | |
| s_waitcnt lgkmcnt(4) | |
| s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 | |
| v_pk_fma_f16 v23, v23, v29, v24 op_sel_hi:[0,1,1] | |
| ds_read_u16 v29, v10 | |
| s_waitcnt lgkmcnt(3) | |
| v_pk_fma_f16 v30, v31, v30, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:16 offset1:24 | |
| ds_read_u16 v34, v11 | |
| s_waitcnt lgkmcnt(1) | |
| v_pk_fma_f16 v23, v32, v23, v30 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v30, v33, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:32 offset1:40 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v29, v23, v30 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v29, v34, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read_u16 v30, v12 | |
| ds_read_u16 v31, v13 | |
| ds_read2_b32 v[23:24], v5 offset0:48 offset1:56 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v30, v23, v29 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v29, v31, v24, v23 op_sel_hi:[0,1,1] | |
| ds_read2_b32 v[23:24], v5 offset0:64 offset1:72 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v25, v23, v29 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v25, v25, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:80 offset1:88 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v26, v23, v25 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v25, v26, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:96 offset1:104 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v27, v23, v25 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v25, v27, v24, v23 op_sel:[1,0,0] | |
| ds_read2_b32 v[23:24], v5 offset0:112 offset1:120 | |
| s_waitcnt lgkmcnt(0) | |
| v_pk_fma_f16 v23, v28, v23, v25 op_sel_hi:[0,1,1] | |
| v_pk_fma_f16 v24, v28, v24, v23 op_sel:[1,0,0] | |
| s_branch BB0_5 | |
| BB0_18: | |
| s_and_saveexec_b64 s[14:15], s[0:1] | |
| s_cbranch_execz BB0_1 | |
| BB0_19: | |
| v_lshl_add_u32 v17, v16, 13, v1 | |
| v_ashrrev_i32_e32 v18, 31, v17 | |
| v_lshlrev_b64 v[17:18], 1, v[17:18] | |
| v_mov_b32_e32 v19, s5 | |
| v_add_co_u32_e32 v17, vcc, s4, v17 | |
| v_addc_co_u32_e32 v18, vcc, v19, v18, vcc | |
| v_mov_b32_e32 v19, 0xffff | |
| v_bfi_b32 v19, v19, v24, v24 | |
| global_store_dword v[17:18], v19, off | |
| s_branch BB0_1 | |
| BB0_20: | |
| s_endpgm | |
| .section .rodata,#alloc | |
| .p2align 6 | |
| .amdhsa_kernel default_function_kernel0 | |
| .amdhsa_group_segment_fixed_size 560 | |
| .amdhsa_private_segment_fixed_size 0 | |
| .amdhsa_user_sgpr_private_segment_buffer 1 | |
| .amdhsa_user_sgpr_dispatch_ptr 0 | |
| .amdhsa_user_sgpr_queue_ptr 0 | |
| .amdhsa_user_sgpr_kernarg_segment_ptr 1 | |
| .amdhsa_user_sgpr_dispatch_id 0 | |
| .amdhsa_user_sgpr_flat_scratch_init 0 | |
| .amdhsa_user_sgpr_private_segment_size 0 | |
| .amdhsa_system_sgpr_private_segment_wavefront_offset 0 | |
| .amdhsa_system_sgpr_workgroup_id_x 1 | |
| .amdhsa_system_sgpr_workgroup_id_y 0 | |
| .amdhsa_system_sgpr_workgroup_id_z 1 | |
| .amdhsa_system_sgpr_workgroup_info 0 | |
| .amdhsa_system_vgpr_workitem_id 1 | |
| .amdhsa_next_free_vgpr 36 | |
| .amdhsa_next_free_sgpr 16 | |
| .amdhsa_reserve_flat_scratch 0 | |
| .amdhsa_float_round_mode_32 0 | |
| .amdhsa_float_round_mode_16_64 0 | |
| .amdhsa_float_denorm_mode_32 0 | |
| .amdhsa_float_denorm_mode_16_64 3 | |
| .amdhsa_dx10_clamp 1 | |
| .amdhsa_ieee_mode 1 | |
| .amdhsa_fp16_overflow 0 | |
| .amdhsa_exception_fp_ieee_invalid_op 0 | |
| .amdhsa_exception_fp_denorm_src 0 | |
| .amdhsa_exception_fp_ieee_div_zero 0 | |
| .amdhsa_exception_fp_ieee_overflow 0 | |
| .amdhsa_exception_fp_ieee_underflow 0 | |
| .amdhsa_exception_fp_ieee_inexact 0 | |
| .amdhsa_exception_int_div_zero 0 | |
| .end_amdhsa_kernel | |
| .text | |
| .Lfunc_end0: | |
| .size default_function_kernel0, .Lfunc_end0-default_function_kernel0 | |
| .ident "clang version 12.0.0 (/src/external/llvm-project/clang dac2bfceaa8d4a90257dc8a6d58f268e172ce00e)" | |
| .section ".note.GNU-stack" | |
| .amdgpu_metadata | |
| --- | |
| amdhsa.kernels: | |
| - .args: | |
| - .access: read_only | |
| .address_space: global | |
| .offset: 0 | |
| .size: 8 | |
| .value_kind: global_buffer | |
| .value_type: f16 | |
| - .access: read_only | |
| .address_space: global | |
| .offset: 8 | |
| .size: 8 | |
| .value_kind: global_buffer | |
| .value_type: f16 | |
| - .address_space: global | |
| .offset: 16 | |
| .size: 8 | |
| .value_kind: global_buffer | |
| .value_type: f16 | |
| .group_segment_fixed_size: 560 | |
| .kernarg_segment_align: 8 | |
| .kernarg_segment_size: 24 | |
| .language: OpenCL C | |
| .language_version: | |
| - 2 | |
| - 0 | |
| .max_flat_workgroup_size: 1024 | |
| .name: default_function_kernel0 | |
| .private_segment_fixed_size: 0 | |
| .sgpr_count: 18 | |
| .sgpr_spill_count: 0 | |
| .symbol: default_function_kernel0.kd | |
| .vgpr_count: 36 | |
| .vgpr_spill_count: 0 | |
| .wavefront_size: 64 | |
| amdhsa.version: | |
| - 1 | |
| - 0 | |
| ... | |
| .end_amdgpu_metadata |
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