Very hacky vcd output.

main.rs

use kaze::*;
use vcd::*;
use std::io;
use std::{fs::File, io::ErrorKind::InvalidInput};

fn main() -> std::io::Result<()> {
    let mut file = File::create("foo.vcd")?;

    // Create a context, which will contain our module(s)
    let c = Context::new();
    let mut writer = vcd::Writer::new(&mut file);
    // Write the header
    writer.timescale(1, TimescaleUnit::US)?;
    writer.add_module("top")?;
    let clock = writer.add_wire(1, "clk")?;
    let reset = writer.add_wire(1, "reset")?;
    let count = writer.add_wire(32, "count")?;
    writer.upscope()?;
    writer.enddefinitions()?;

    // Write the initial values
    writer.begin(SimulationCommand::Dumpvars)?;
    writer.change_scalar(clock, Value::V0)?;
    writer.change_scalar(reset, Value::V0)?;
    //writer.change_scalar(count, Value::V0)?;
    writer.end()?;

    // Create a module
    let counter = counter_module(&c);

    // Generate Rust simulator code
    sim::generate(counter, std::io::stdout())?;

    // Generate Verilog code
    //verilog::generate(counter, std::io::stdout())?;

    let mut cm = CounterModule::new();
    cm.reset();

    for t in 1..100 {
        
        cm.posedge_clk();
        writer.timestamp(t)?;
        if t == 10 {
            writer.change_scalar(reset, Value::V0)?;
            cm.reset();
        } else {
            writer.change_scalar(reset, Value::V1)?;
        }
        cm.prop();
        writer.change_scalar(clock, if t % 2 == 0 {Value::V0} else {Value::V1})?;
        let c = get_value(&cm.count);
        //for i in &c {
        //    print!("{}", i);
        //}
        //println!();
        writer.change_vector(count, &c )?;
        //println!("Current count: {}", cm.count);
        
    }

    Ok(())
}

fn get_value(count: &u32) -> Vec<Value> {
    let mut v = Vec::new();
    for i in 0..31 {
        if count & (1 << i) == 1 << i {
            v.push(Value::V1)
        } else {
            v.push(Value::V0)
        }
    }
    v.reverse();
    v
}

fn counter_module<'a>(c: &'a Context<'a>) -> &Module<'a> {
    let m = c.module("CounterModule");

    let r = m.reg("r", 32);
    r.default_value(0u32);
    r.drive_next(r.value + m.lit(0x1u32, 32));
    m.output("count", r.value);

    m
}

#[derive(Default)]
pub struct CounterModule {      
    // Outputs
    pub count: u32, // 32 bit(s)

    // Regs
    __reg_r_0: u32, // 32 bit(s)
    __reg_r_0_next: u32,
}

impl CounterModule {
    pub fn new() -> CounterModule {
        CounterModule::default()
    }

    pub fn reset(&mut self) {
        self.__reg_r_0 = 0x0u32;
    }

    pub fn posedge_clk(&mut self) {
        self.__reg_r_0 = self.__reg_r_0_next;
    }

    pub fn prop(&mut self) {
        self.count = self.__reg_r_0;
        let __temp_0 = self.__reg_r_0.wrapping_add(0x1u32);
        self.__reg_r_0_next = __temp_0;
    }
}