Created
January 30, 2016 22:09
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Results of static branch prediction attempts
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| model name : Intel(R) Core(TM) i5 CPU M 520 @ 2.40GHz | |
| c.f. https://github.com/mattgodbolt/agner | |
| ****************************************************************************** | |
| Ahead not taken | |
| ****************************************************************************** | |
| Processor 0 | |
| Clock Core cyc Instruct BrTaken BrMispred | |
| 548996 517178 1501711 0 3 | |
| 500608 500606 1501707 0 2 | |
| 500608 500609 1501707 0 2 | |
| 500592 500590 1501707 0 1 | |
| 500592 500590 1501707 0 1 | |
| 500592 500592 1501707 0 1 | |
| 500588 500588 1501707 0 1 | |
| 500592 500590 1501707 0 1 | |
| Processor 0 | |
| Clock BaClrClr BaClrBad BaClrEly BaClrL8 | |
| 510136 0 0 98 0 | |
| 500608 0 0 103 0 | |
| 500608 0 0 103 0 | |
| 500588 0 0 103 0 | |
| 500592 0 0 103 0 | |
| 500592 0 0 103 0 | |
| 500592 0 0 103 0 | |
| 500588 0 0 103 0 | |
| ****************************************************************************** | |
| Behind not taken | |
| ****************************************************************************** | |
| Processor 0 | |
| Clock Core cyc Instruct BrTaken BrMispred | |
| 526048 521058 1501710 0 1004 | |
| 500608 500607 1501707 0 2 | |
| 500608 500609 1501707 0 2 | |
| 500592 500592 1501707 0 1 | |
| 500588 500590 1501707 0 1 | |
| 500592 500592 1501707 0 1 | |
| 500588 500592 1501707 0 1 | |
| 500592 500590 1501707 0 1 | |
| Processor 0 | |
| Clock BaClrClr BaClrBad BaClrEly BaClrL8 | |
| 526500 1001 0 111 0 | |
| 500604 0 0 103 0 | |
| 523152 37 0 158 0 | |
| 500604 0 0 104 0 | |
| 500592 0 0 103 0 | |
| 500592 0 0 103 0 | |
| 500592 0 0 103 0 | |
| 518688 35 0 133 0 | |
| ****************************************************************************** | |
| Ahead taken | |
| ****************************************************************************** | |
| Processor 0 | |
| Clock Core cyc Instruct BrTaken BrMispred | |
| 460040 454621 1301710 0 1004 | |
| 433940 433943 1301707 0 2 | |
| 433920 433922 1301707 0 1 | |
| 433924 433925 1301707 0 1 | |
| 433920 433925 1301707 0 1 | |
| 433920 433922 1301707 0 1 | |
| 433924 433925 1301707 0 1 | |
| 433924 433925 1301707 0 1 | |
| Processor 0 | |
| Clock BaClrClr BaClrBad BaClrEly BaClrL8 | |
| 461380 5 0 99152 0 | |
| 445468 60 0 100440 0 | |
| 433924 0 0 100125 0 | |
| 433920 0 0 100125 0 | |
| 433920 0 0 100125 0 | |
| 433924 0 0 100125 0 | |
| 433920 0 0 100125 0 | |
| 433924 0 0 100125 0 | |
| ****************************************************************************** | |
| Behind taken | |
| ****************************************************************************** | |
| Processor 0 | |
| Clock Core cyc Instruct BrTaken BrMispred | |
| 335464 329620 900510 0 10 | |
| 300308 300347 900507 0 2 | |
| 300284 300321 900507 0 1 | |
| 300284 300322 900507 0 1 | |
| 300288 300322 900507 0 1 | |
| 300288 300324 900507 0 1 | |
| 300292 300327 900507 0 1 | |
| 300288 300327 900507 0 1 | |
| Processor 0 | |
| Clock BaClrClr BaClrBad BaClrEly BaClrL8 | |
| 334928 1002 0 103467 0 | |
| 300344 0 0 100333 0 | |
| 300324 0 0 100331 0 | |
| 300320 0 0 100331 0 | |
| 300320 0 0 100331 0 | |
| 300324 0 0 100331 0 | |
| 300324 0 0 100331 0 | |
| 300324 0 0 100331 0 |
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