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mattico/stm32h743.mmap.diff

Created June 7, 2021 01:58
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stm32h743.mmap.diff
--- ./mmaps_old/stm32h743.mmap 2021-06-06 20:39:56.330000000 -0500
+++ mmaps_new/stm32h743.mmap 2021-06-06 20:39:04.720000000 -0500
@@ -21366,48 +21366,48 @@
0x58027054 B REGISTER M2FECR (rw): RAMECC monitor 2 failing error code register
0x58027054 C FIELD 00w32 FEC (ro): ECC failing code
0x5C001000 A PERIPHERAL DBGMCU
-0x5C001000 B REGISTER IDC (ro): Identity code
+0x5C001000 B REGISTER IDC (ro): DBGMCU Identity Code Register
0x5C001000 C FIELD 00w12 DEV_ID: Device ID
-0x5C001000 C FIELD 16w16 REV_ID: Revision ID
-0x5C001004 B REGISTER CR (rw): Configuration register
-0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow debug in D1 Sleep mode
-0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow debug in D1 Stop mode
-0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow debug in D1 Standby mode
-0x5C001004 C FIELD 20w01 TRACECLKEN: Trace clock enable enable
-0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable enable
-0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable enable
+0x5C001000 C FIELD 16w16 REV_ID: Revision
+0x5C001004 B REGISTER CR (rw): DBGMCU Configuration Register
+0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow D1 domain debug in Sleep mode
+0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow D1 domain debug in Stop mode
+0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow D1 domain debug in Standby mode
+0x5C001004 C FIELD 20w01 TRACECLKEN: Trace port clock enable
+0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable
+0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable
0x5C001004 C FIELD 28w01 TRGOEN: External trigger output enable
-0x5C001034 B REGISTER APB3FZ1 (rw): APB3 peripheral freeze register
-0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug mode
-0x5C00103C B REGISTER APB1LFZ1 (rw): APB1L peripheral freeze register
-0x5C00103C C FIELD 00w01 TIM2: TIM2 stop in debug mode
-0x5C00103C C FIELD 01w01 TIM3: TIM3 stop in debug mode
-0x5C00103C C FIELD 02w01 TIM4: TIM4 stop in debug mode
-0x5C00103C C FIELD 03w01 TIM5: TIM5 stop in debug mode
-0x5C00103C C FIELD 04w01 TIM6: TIM6 stop in debug mode
-0x5C00103C C FIELD 05w01 TIM7: TIM7 stop in debug mode
-0x5C00103C C FIELD 06w01 TIM12: TIM12 stop in debug mode
-0x5C00103C C FIELD 07w01 TIM13: TIM13 stop in debug mode
-0x5C00103C C FIELD 08w01 TIM14: TIM14 stop in debug mode
-0x5C00103C C FIELD 09w01 LPTIM1: LPTIM1 stop in debug mode
-0x5C00103C C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop in debug mode
-0x5C00104C B REGISTER APB2FZ1 (rw): APB2 peripheral freeze register
-0x5C00104C C FIELD 00w01 TIM1: TIM1 stop in debug mode
-0x5C00104C C FIELD 01w01 TIM8: TIM8 stop in debug mode
-0x5C00104C C FIELD 16w01 TIM15: TIM15 stop in debug mode
-0x5C00104C C FIELD 17w01 TIM16: TIM16 stop in debug mode
-0x5C00104C C FIELD 18w01 TIM17: TIM17 stop in debug mode
-0x5C00104C C FIELD 29w01 HRTIM: HRTIM stop in debug mode
-0x5C001054 B REGISTER APB4FZ1 (rw): APB4 peripheral freeze register
-0x5C001054 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop in debug mode
-0x5C001054 C FIELD 09w01 LPTIM2: LPTIM2 stop in debug mode
-0x5C001054 C FIELD 10w01 LPTIM3: LPTIM3 stop in debug mode
-0x5C001054 C FIELD 11w01 LPTIM4: LPTIM4 stop in debug mode
-0x5C001054 C FIELD 12w01 LPTIM5: LPTIM5 stop in debug mode
-0x5C001054 C FIELD 16w01 RTC: RTC stop in debug mode
-0x5C001054 C FIELD 18w01 IWDG1: Independent watchdog for D1 stop in debug mode
+0x5C001034 B REGISTER APB3FZ1 (rw): DBGMCU APB3 peripheral freeze register
+0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C00103C B REGISTER APB1LFZ1 (rw): DBGMCU APB1L peripheral freeze register
+0x5C00103C C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C00103C C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C00103C C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C00103C C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C00103C C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C00103C C FIELD 05w01 DBG_TIM7: TIM7 stop in debug
+0x5C00103C C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C00103C C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C00103C C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C00103C C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C00103C C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C00103C C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C00103C C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C00104C B REGISTER APB2FZ1 (rw): DBGMCU APB2 peripheral freeze register
+0x5C00104C C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C00104C C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C00104C C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C00104C C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C00104C C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C00104C C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001054 B REGISTER APB4FZ1 (rw): DBGMCU APB4 peripheral freeze register
+0x5C001054 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001054 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001054 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001054 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001054 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001054 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001054 C FIELD 18w01 DBG_IWDG1: Independent watchdog for D1 stop in debug
0xE000E008 A PERIPHERAL SCB_ACTRL
0xE000E008 B REGISTER ACTRL (rw): Auxiliary control register
0xE000E008 C FIELD 02w01 DISFOLD: DISFOLD
@@ -21718,7 +21718,7 @@
0xE000ED20 B REGISTER SHPR3 (rw): System handler priority registers
0xE000ED20 C FIELD 16w08 PRI_14: Priority of system handler 14
0xE000ED20 C FIELD 24w08 PRI_15: Priority of system handler 15
-0xE000ED24 B REGISTER SHCRS (rw): System handler control and state register
+0xE000ED24 B REGISTER SHCSR (rw): System handler control and state register
0xE000ED24 C FIELD 00w01 MEMFAULTACT: Memory management fault exception active bit
0xE000ED24 C FIELD 01w01 BUSFAULTACT: Bus fault exception active bit
0xE000ED24 C FIELD 03w01 USGFAULTACT: Usage fault exception active bit
@@ -21795,7 +21795,7 @@
0xE000ED90 C FIELD 00w01 SEPARATE: Separate flag
0xE000ED90 C FIELD 08w08 DREGION: Number of MPU data regions
0xE000ED90 C FIELD 16w08 IREGION: Number of MPU instruction regions
-0xE000ED94 B REGISTER MPU_CTRL (ro): MPU control register
+0xE000ED94 B REGISTER MPU_CTRL (rw): MPU control register
0xE000ED94 C FIELD 00w01 ENABLE: Enables the MPU
0xE000ED94 C FIELD 01w01 HFNMIENA: Enables the operation of MPU during hard fault
0xE000ED94 C FIELD 02w01 PRIVDEFENA: Enable priviliged software access to default memory map
Raw
stm32h743v.mmap.diff
--- ./mmaps_old/stm32h743v.mmap 2021-06-06 20:39:56.550000000 -0500
+++ mmaps_new/stm32h743v.mmap 2021-06-06 20:39:04.720000000 -0500
@@ -21372,48 +21372,48 @@
0x58027054 B REGISTER M2FECR (rw): RAMECC monitor 2 failing error code register
0x58027054 C FIELD 00w32 FEC (ro): ECC failing code
0x5C001000 A PERIPHERAL DBGMCU
-0x5C001000 B REGISTER IDC (ro): Identity code
+0x5C001000 B REGISTER IDC (ro): DBGMCU Identity Code Register
0x5C001000 C FIELD 00w12 DEV_ID: Device ID
-0x5C001000 C FIELD 16w16 REV_ID: Revision ID
-0x5C001004 B REGISTER CR (rw): Configuration register
-0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow debug in D1 Sleep mode
-0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow debug in D1 Stop mode
-0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow debug in D1 Standby mode
-0x5C001004 C FIELD 20w01 TRACECLKEN: Trace clock enable enable
-0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable enable
-0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable enable
+0x5C001000 C FIELD 16w16 REV_ID: Revision
+0x5C001004 B REGISTER CR (rw): DBGMCU Configuration Register
+0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow D1 domain debug in Sleep mode
+0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow D1 domain debug in Stop mode
+0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow D1 domain debug in Standby mode
+0x5C001004 C FIELD 20w01 TRACECLKEN: Trace port clock enable
+0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable
+0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable
0x5C001004 C FIELD 28w01 TRGOEN: External trigger output enable
-0x5C001034 B REGISTER APB3FZ1 (rw): APB3 peripheral freeze register
-0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug mode
-0x5C00103C B REGISTER APB1LFZ1 (rw): APB1L peripheral freeze register
-0x5C00103C C FIELD 00w01 TIM2: TIM2 stop in debug mode
-0x5C00103C C FIELD 01w01 TIM3: TIM3 stop in debug mode
-0x5C00103C C FIELD 02w01 TIM4: TIM4 stop in debug mode
-0x5C00103C C FIELD 03w01 TIM5: TIM5 stop in debug mode
-0x5C00103C C FIELD 04w01 TIM6: TIM6 stop in debug mode
-0x5C00103C C FIELD 05w01 TIM7: TIM7 stop in debug mode
-0x5C00103C C FIELD 06w01 TIM12: TIM12 stop in debug mode
-0x5C00103C C FIELD 07w01 TIM13: TIM13 stop in debug mode
-0x5C00103C C FIELD 08w01 TIM14: TIM14 stop in debug mode
-0x5C00103C C FIELD 09w01 LPTIM1: LPTIM1 stop in debug mode
-0x5C00103C C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop in debug mode
-0x5C00104C B REGISTER APB2FZ1 (rw): APB2 peripheral freeze register
-0x5C00104C C FIELD 00w01 TIM1: TIM1 stop in debug mode
-0x5C00104C C FIELD 01w01 TIM8: TIM8 stop in debug mode
-0x5C00104C C FIELD 16w01 TIM15: TIM15 stop in debug mode
-0x5C00104C C FIELD 17w01 TIM16: TIM16 stop in debug mode
-0x5C00104C C FIELD 18w01 TIM17: TIM17 stop in debug mode
-0x5C00104C C FIELD 29w01 HRTIM: HRTIM stop in debug mode
-0x5C001054 B REGISTER APB4FZ1 (rw): APB4 peripheral freeze register
-0x5C001054 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop in debug mode
-0x5C001054 C FIELD 09w01 LPTIM2: LPTIM2 stop in debug mode
-0x5C001054 C FIELD 10w01 LPTIM3: LPTIM3 stop in debug mode
-0x5C001054 C FIELD 11w01 LPTIM4: LPTIM4 stop in debug mode
-0x5C001054 C FIELD 12w01 LPTIM5: LPTIM5 stop in debug mode
-0x5C001054 C FIELD 16w01 RTC: RTC stop in debug mode
-0x5C001054 C FIELD 18w01 IWDG1: Independent watchdog for D1 stop in debug mode
+0x5C001034 B REGISTER APB3FZ1 (rw): DBGMCU APB3 peripheral freeze register
+0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C00103C B REGISTER APB1LFZ1 (rw): DBGMCU APB1L peripheral freeze register
+0x5C00103C C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C00103C C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C00103C C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C00103C C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C00103C C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C00103C C FIELD 05w01 DBG_TIM7: TIM7 stop in debug
+0x5C00103C C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C00103C C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C00103C C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C00103C C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C00103C C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C00103C C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C00103C C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C00104C B REGISTER APB2FZ1 (rw): DBGMCU APB2 peripheral freeze register
+0x5C00104C C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C00104C C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C00104C C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C00104C C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C00104C C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C00104C C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001054 B REGISTER APB4FZ1 (rw): DBGMCU APB4 peripheral freeze register
+0x5C001054 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001054 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001054 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001054 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001054 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001054 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001054 C FIELD 18w01 DBG_IWDG1: Independent watchdog for D1 stop in debug
0xE000E008 A PERIPHERAL SCB_ACTRL
0xE000E008 B REGISTER ACTRL (rw): Auxiliary control register
0xE000E008 C FIELD 02w01 DISFOLD: DISFOLD
@@ -21724,7 +21724,7 @@
0xE000ED20 B REGISTER SHPR3 (rw): System handler priority registers
0xE000ED20 C FIELD 16w08 PRI_14: Priority of system handler 14
0xE000ED20 C FIELD 24w08 PRI_15: Priority of system handler 15
-0xE000ED24 B REGISTER SHCRS (rw): System handler control and state register
+0xE000ED24 B REGISTER SHCSR (rw): System handler control and state register
0xE000ED24 C FIELD 00w01 MEMFAULTACT: Memory management fault exception active bit
0xE000ED24 C FIELD 01w01 BUSFAULTACT: Bus fault exception active bit
0xE000ED24 C FIELD 03w01 USGFAULTACT: Usage fault exception active bit
@@ -21801,7 +21801,7 @@
0xE000ED90 C FIELD 00w01 SEPARATE: Separate flag
0xE000ED90 C FIELD 08w08 DREGION: Number of MPU data regions
0xE000ED90 C FIELD 16w08 IREGION: Number of MPU instruction regions
-0xE000ED94 B REGISTER MPU_CTRL (ro): MPU control register
+0xE000ED94 B REGISTER MPU_CTRL (rw): MPU control register
0xE000ED94 C FIELD 00w01 ENABLE: Enables the MPU
0xE000ED94 C FIELD 01w01 HFNMIENA: Enables the operation of MPU during hard fault
0xE000ED94 C FIELD 02w01 PRIVDEFENA: Enable priviliged software access to default memory map
Raw
stm32h747cm4.mmap.diff
--- ./mmaps_old/stm32h747cm4.mmap 2021-06-06 20:39:56.480000000 -0500
+++ mmaps_new/stm32h747cm4.mmap 2021-06-06 20:39:04.720000000 -0500
@@ -91,7 +91,7 @@
0x4000001C C FIELD 11w01 OC4PE: OC4PE
0x4000001C C FIELD 12w03 OC4M: OC4M
0x4000001C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000001C C FIELD 15w01 OC4CE: O24CE
+0x4000001C C FIELD 15w01 OC4CE: OC4CE
0x4000001C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000001C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000020 B REGISTER CCER (rw): capture/compare enable register
@@ -226,7 +226,7 @@
0x4000041C C FIELD 11w01 OC4PE: OC4PE
0x4000041C C FIELD 12w03 OC4M: OC4M
0x4000041C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000041C C FIELD 15w01 OC4CE: O24CE
+0x4000041C C FIELD 15w01 OC4CE: OC4CE
0x4000041C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000041C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000420 B REGISTER CCER (rw): capture/compare enable register
@@ -367,7 +367,7 @@
0x4000081C C FIELD 11w01 OC4PE: OC4PE
0x4000081C C FIELD 12w03 OC4M: OC4M
0x4000081C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000081C C FIELD 15w01 OC4CE: O24CE
+0x4000081C C FIELD 15w01 OC4CE: OC4CE
0x4000081C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000081C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000820 B REGISTER CCER (rw): capture/compare enable register
@@ -508,7 +508,7 @@
0x40000C1C C FIELD 11w01 OC4PE: OC4PE
0x40000C1C C FIELD 12w03 OC4M: OC4M
0x40000C1C C FIELD 12w04 IC4F: Input capture 4 filter
-0x40000C1C C FIELD 15w01 OC4CE: O24CE
+0x40000C1C C FIELD 15w01 OC4CE: OC4CE
0x40000C1C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x40000C1C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000C20 B REGISTER CCER (rw): capture/compare enable register
@@ -691,7 +691,7 @@
0x4000181C C FIELD 11w01 OC4PE: OC4PE
0x4000181C C FIELD 12w03 OC4M: OC4M
0x4000181C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000181C C FIELD 15w01 O24CE: O24CE
+0x4000181C C FIELD 15w01 OC4CE: OC4CE
0x4000181C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000181C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40001820 B REGISTER CCER (rw): capture/compare enable register
@@ -832,7 +832,7 @@
0x40001C1C C FIELD 11w01 OC4PE: OC4PE
0x40001C1C C FIELD 12w03 OC4M: OC4M
0x40001C1C C FIELD 12w04 IC4F: Input capture 4 filter
-0x40001C1C C FIELD 15w01 O24CE: O24CE
+0x40001C1C C FIELD 15w01 OC4CE: OC4CE
0x40001C1C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x40001C1C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40001C20 B REGISTER CCER (rw): capture/compare enable register
@@ -973,7 +973,7 @@
0x4000201C C FIELD 11w01 OC4PE: OC4PE
0x4000201C C FIELD 12w03 OC4M: OC4M
0x4000201C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000201C C FIELD 15w01 O24CE: O24CE
+0x4000201C C FIELD 15w01 OC4CE: OC4CE
0x4000201C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000201C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40002020 B REGISTER CCER (rw): capture/compare enable register
@@ -5527,498 +5527,493 @@
0x40016048 C FIELD 24w03 DLYM4L: Delay line for first microphone of pair 4
0x40016048 C FIELD 28w03 DLYM4R: Delay line for second microphone of pair 4
0x40017000 A PERIPHERAL DFSDM
-0x40017000 B REGISTER DFSDM_CHCFG0R1 (rw): DFSDM channel configuration 0 register 1
-0x40017000 C FIELD 00w02 SITP: Serial interface type for channel 0
-0x40017000 C FIELD 02w02 SPICKSEL: SPI clock select for channel 0
-0x40017000 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 0
-0x40017000 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 0
-0x40017000 C FIELD 07w01 CHEN: Channel 0 enable
-0x40017000 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017000 C FIELD 12w02 DATMPX: Input data multiplexer for channel 0
-0x40017000 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017000 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017000 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017000 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017004 B REGISTER DFSDM_CHCFG1R1 (rw): DFSDM channel configuration 1 register 1
-0x40017004 C FIELD 00w02 SITP: Serial interface type for channel 1
-0x40017004 C FIELD 02w02 SPICKSEL: SPI clock select for channel 1
-0x40017004 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 1
-0x40017004 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 1
-0x40017004 C FIELD 07w01 CHEN: Channel 1 enable
-0x40017004 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017004 C FIELD 12w02 DATMPX: Input data multiplexer for channel 1
-0x40017004 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017004 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017004 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017004 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017008 B REGISTER DFSDM_CHCFG2R1 (rw): DFSDM channel configuration 2 register 1
-0x40017008 C FIELD 00w02 SITP: Serial interface type for channel 2
-0x40017008 C FIELD 02w02 SPICKSEL: SPI clock select for channel 2
-0x40017008 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 2
-0x40017008 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 2
-0x40017008 C FIELD 07w01 CHEN: Channel 2 enable
-0x40017008 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017008 C FIELD 12w02 DATMPX: Input data multiplexer for channel 2
-0x40017008 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017008 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017008 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017008 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001700C B REGISTER DFSDM_CHCFG3R1 (rw): DFSDM channel configuration 3 register 1
-0x4001700C C FIELD 00w02 SITP: Serial interface type for channel 3
-0x4001700C C FIELD 02w02 SPICKSEL: SPI clock select for channel 3
-0x4001700C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 3
-0x4001700C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 3
-0x4001700C C FIELD 07w01 CHEN: Channel 3 enable
-0x4001700C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001700C C FIELD 12w02 DATMPX: Input data multiplexer for channel 3
-0x4001700C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001700C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001700C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001700C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017010 B REGISTER DFSDM_CHCFG4R1 (rw): DFSDM channel configuration 4 register 1
-0x40017010 C FIELD 00w02 SITP: Serial interface type for channel 4
-0x40017010 C FIELD 02w02 SPICKSEL: SPI clock select for channel 4
-0x40017010 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 4
-0x40017010 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 4
-0x40017010 C FIELD 07w01 CHEN: Channel 4 enable
-0x40017010 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017010 C FIELD 12w02 DATMPX: Input data multiplexer for channel 4
-0x40017010 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017010 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017010 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017010 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017014 B REGISTER DFSDM_CHCFG5R1 (rw): DFSDM channel configuration 5 register 1
-0x40017014 C FIELD 00w02 SITP: Serial interface type for channel 5
-0x40017014 C FIELD 02w02 SPICKSEL: SPI clock select for channel 5
-0x40017014 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 5
-0x40017014 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 5
-0x40017014 C FIELD 07w01 CHEN: Channel 5 enable
-0x40017014 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017014 C FIELD 12w02 DATMPX: Input data multiplexer for channel 5
-0x40017014 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017014 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017014 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017014 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017018 B REGISTER DFSDM_CHCFG6R1 (rw): DFSDM channel configuration 6 register 1
-0x40017018 C FIELD 00w02 SITP: Serial interface type for channel 6
-0x40017018 C FIELD 02w02 SPICKSEL: SPI clock select for channel 6
-0x40017018 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 6
-0x40017018 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 6
-0x40017018 C FIELD 07w01 CHEN: Channel 6 enable
-0x40017018 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017018 C FIELD 12w02 DATMPX: Input data multiplexer for channel 6
-0x40017018 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017018 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017018 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017018 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001701C B REGISTER DFSDM_CHCFG7R1 (rw): DFSDM channel configuration 7 register 1
-0x4001701C C FIELD 00w02 SITP: Serial interface type for channel 7
-0x4001701C C FIELD 02w02 SPICKSEL: SPI clock select for channel 7
-0x4001701C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 7
-0x4001701C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 7
-0x4001701C C FIELD 07w01 CHEN: Channel 7 enable
-0x4001701C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001701C C FIELD 12w02 DATMPX: Input data multiplexer for channel 7
-0x4001701C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001701C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001701C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001701C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017020 B REGISTER DFSDM_CHCFG0R2 (rw): DFSDM channel configuration 0 register 2
-0x40017020 C FIELD 03w05 DTRBS: Data right bit-shift for channel 0
-0x40017020 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 0
-0x40017024 B REGISTER DFSDM_CHCFG1R2 (rw): DFSDM channel configuration 1 register 2
-0x40017024 C FIELD 03w05 DTRBS: Data right bit-shift for channel 1
-0x40017024 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 1
-0x40017028 B REGISTER DFSDM_CHCFG2R2 (rw): DFSDM channel configuration 2 register 2
-0x40017028 C FIELD 03w05 DTRBS: Data right bit-shift for channel 2
-0x40017028 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 2
-0x4001702C B REGISTER DFSDM_CHCFG3R2 (rw): DFSDM channel configuration 3 register 2
-0x4001702C C FIELD 03w05 DTRBS: Data right bit-shift for channel 3
-0x4001702C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 3
-0x40017030 B REGISTER DFSDM_CHCFG4R2 (rw): DFSDM channel configuration 4 register 2
-0x40017030 C FIELD 03w05 DTRBS: Data right bit-shift for channel 4
-0x40017030 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 4
-0x40017034 B REGISTER DFSDM_CHCFG5R2 (rw): DFSDM channel configuration 5 register 2
-0x40017034 C FIELD 03w05 DTRBS: Data right bit-shift for channel 5
-0x40017034 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 5
-0x40017038 B REGISTER DFSDM_CHCFG6R2 (rw): DFSDM channel configuration 6 register 2
-0x40017038 C FIELD 03w05 DTRBS: Data right bit-shift for channel 6
-0x40017038 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 6
-0x4001703C B REGISTER DFSDM_CHCFG7R2 (rw): DFSDM channel configuration 7 register 2
-0x4001703C C FIELD 03w05 DTRBS: Data right bit-shift for channel 7
-0x4001703C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 7
-0x40017040 B REGISTER DFSDM_AWSCD0R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017040 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 0
-0x40017040 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 0
-0x40017040 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 0
-0x40017040 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 0
-0x40017044 B REGISTER DFSDM_AWSCD1R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017044 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 1
-0x40017044 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 1
-0x40017044 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 1
-0x40017044 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 1
-0x40017048 B REGISTER DFSDM_AWSCD2R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017048 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 2
-0x40017048 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 2
-0x40017048 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 2
-0x40017048 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 2
-0x4001704C B REGISTER DFSDM_AWSCD3R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001704C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 3
-0x4001704C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 3
-0x4001704C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 3
-0x4001704C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 3
-0x40017050 B REGISTER DFSDM_AWSCD4R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017050 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 4
-0x40017050 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 4
-0x40017050 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 4
-0x40017050 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 4
-0x40017054 B REGISTER DFSDM_AWSCD5R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017054 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 5
-0x40017054 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 5
-0x40017054 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 5
-0x40017054 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 5
-0x40017058 B REGISTER DFSDM_AWSCD6R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017058 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 6
-0x40017058 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 6
-0x40017058 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 6
-0x40017058 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 6
-0x4001705C B REGISTER DFSDM_AWSCD7R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001705C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 7
-0x4001705C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 7
-0x4001705C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 7
-0x4001705C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 7
-0x40017060 B REGISTER DFSDM_CHWDAT0R (ro): DFSDM channel watchdog filter data register
-0x40017060 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017064 B REGISTER DFSDM_CHWDAT1R (ro): DFSDM channel watchdog filter data register
-0x40017064 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017068 B REGISTER DFSDM_CHWDAT2R (ro): DFSDM channel watchdog filter data register
-0x40017068 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001706C B REGISTER DFSDM_CHWDAT3R (ro): DFSDM channel watchdog filter data register
-0x4001706C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017070 B REGISTER DFSDM_CHWDAT4R (ro): DFSDM channel watchdog filter data register
-0x40017070 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017074 B REGISTER DFSDM_CHWDAT5R (ro): DFSDM channel watchdog filter data register
-0x40017074 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017078 B REGISTER DFSDM_CHWDAT6R (ro): DFSDM channel watchdog filter data register
-0x40017078 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001707C B REGISTER DFSDM_CHWDAT7R (ro): DFSDM channel watchdog filter data register
-0x4001707C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017080 B REGISTER DFSDM_CHDATIN0R (rw): DFSDM channel data input register
-0x40017080 C FIELD 00w16 INDAT0: Input data for channel 0
-0x40017080 C FIELD 16w16 INDAT1: Input data for channel 1
-0x40017084 B REGISTER DFSDM_CHDATIN1R (rw): DFSDM channel data input register
-0x40017084 C FIELD 00w16 INDAT0: Input data for channel 1
-0x40017084 C FIELD 16w16 INDAT1: Input data for channel 2
-0x40017088 B REGISTER DFSDM_CHDATIN2R (rw): DFSDM channel data input register
-0x40017088 C FIELD 00w16 INDAT0: Input data for channel 2
-0x40017088 C FIELD 16w16 INDAT1: Input data for channel 3
-0x4001708C B REGISTER DFSDM_CHDATIN3R (rw): DFSDM channel data input register
-0x4001708C C FIELD 00w16 INDAT0: Input data for channel 3
-0x4001708C C FIELD 16w16 INDAT1: Input data for channel 4
-0x40017090 B REGISTER DFSDM_CHDATIN4R (rw): DFSDM channel data input register
-0x40017090 C FIELD 00w16 INDAT0: Input data for channel 4
-0x40017090 C FIELD 16w16 INDAT1: Input data for channel 5
-0x40017094 B REGISTER DFSDM_CHDATIN5R (rw): DFSDM channel data input register
-0x40017094 C FIELD 00w16 INDAT0: Input data for channel 5
-0x40017094 C FIELD 16w16 INDAT1: Input data for channel 6
-0x40017098 B REGISTER DFSDM_CHDATIN6R (rw): DFSDM channel data input register
-0x40017098 C FIELD 00w16 INDAT0: Input data for channel 6
-0x40017098 C FIELD 16w16 INDAT1: Input data for channel 7
-0x4001709C B REGISTER DFSDM_CHDATIN7R (rw): DFSDM channel data input register
-0x4001709C C FIELD 00w16 INDAT0: Input data for channel 7
-0x4001709C C FIELD 16w16 INDAT1: Input data for channel 8
-0x400170A0 B REGISTER DFSDM0_CR1 (rw): DFSDM control register 1
-0x400170A0 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A0 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A0 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A0 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A0 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A0 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A0 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A0 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A0 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A0 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A0 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A0 C FIELD 24w03 RCH: Regular channel selection
-0x400170A0 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A0 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A4 B REGISTER DFSDM1_CR1 (rw): DFSDM control register 1
-0x400170A4 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A4 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A4 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A4 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A4 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A4 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A4 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A4 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A4 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A4 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A4 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A4 C FIELD 24w03 RCH: Regular channel selection
-0x400170A4 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A4 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A8 B REGISTER DFSDM2_CR1 (rw): DFSDM control register 1
-0x400170A8 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A8 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A8 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A8 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A8 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A8 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A8 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A8 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A8 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A8 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A8 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A8 C FIELD 24w03 RCH: Regular channel selection
-0x400170A8 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A8 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170AC B REGISTER DFSDM3_CR1 (rw): DFSDM control register 1
-0x400170AC C FIELD 00w01 DFEN: DFSDM enable
-0x400170AC C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170AC C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170AC C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170AC C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170AC C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170AC C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170AC C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170AC C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170AC C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170AC C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170AC C FIELD 24w03 RCH: Regular channel selection
-0x400170AC C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170AC C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170B0 B REGISTER DFSDM0_CR2 (rw): DFSDM control register 2
-0x400170B0 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B0 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B0 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B0 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B0 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B0 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B0 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B0 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B0 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B4 B REGISTER DFSDM1_CR2 (rw): DFSDM control register 2
-0x400170B4 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B4 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B4 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B4 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B4 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B4 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B4 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B4 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B4 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B8 B REGISTER DFSDM2_CR2 (rw): DFSDM control register 2
-0x400170B8 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B8 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B8 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B8 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B8 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B8 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B8 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B8 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B8 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170BC B REGISTER DFSDM3_CR2 (rw): DFSDM control register 2
-0x400170BC C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170BC C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170BC C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170BC C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170BC C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170BC C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170BC C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170BC C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170BC C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170C0 B REGISTER DFSDM0_ISR (ro): DFSDM interrupt and status register
-0x400170C0 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C0 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C0 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C0 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C0 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C0 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C0 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C0 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C0 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C4 B REGISTER DFSDM1_ISR (ro): DFSDM interrupt and status register
-0x400170C4 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C4 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C4 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C4 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C4 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C4 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C4 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C4 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C4 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C8 B REGISTER DFSDM2_ISR (ro): DFSDM interrupt and status register
-0x400170C8 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C8 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C8 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C8 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C8 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C8 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C8 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C8 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C8 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170CC B REGISTER DFSDM3_ISR (ro): DFSDM interrupt and status register
-0x400170CC C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170CC C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170CC C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170CC C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170CC C FIELD 04w01 AWDF: Analog watchdog
-0x400170CC C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170CC C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170CC C FIELD 16w08 CKABF: Clock absence flag
-0x400170CC C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170D0 B REGISTER DFSDM0_ICR (rw): DFSDM interrupt flag clear register
-0x400170D0 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D0 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D0 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D0 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D4 B REGISTER DFSDM1_ICR (rw): DFSDM interrupt flag clear register
-0x400170D4 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D4 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D4 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D4 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D8 B REGISTER DFSDM2_ICR (rw): DFSDM interrupt flag clear register
-0x400170D8 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D8 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D8 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D8 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170DC B REGISTER DFSDM3_ICR (rw): DFSDM interrupt flag clear register
-0x400170DC C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170DC C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170DC C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170DC C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170E0 B REGISTER DFSDM0_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E0 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E4 B REGISTER DFSDM1_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E4 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E8 B REGISTER DFSDM2_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E8 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170EC B REGISTER DFSDM3_JCHGR (rw): DFSDM injected channel group selection register
-0x400170EC C FIELD 00w08 JCHG: Injected channel group selection
-0x400170F0 B REGISTER DFSDM0_FCR (rw): DFSDM filter control register
-0x400170F0 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F0 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F0 C FIELD 29w03 FORD: Sinc filter order
-0x400170F4 B REGISTER DFSDM1_FCR (rw): DFSDM filter control register
-0x400170F4 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F4 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F4 C FIELD 29w03 FORD: Sinc filter order
-0x400170F8 B REGISTER DFSDM2_FCR (rw): DFSDM filter control register
-0x400170F8 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F8 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F8 C FIELD 29w03 FORD: Sinc filter order
-0x400170FC B REGISTER DFSDM3_FCR (rw): DFSDM filter control register
-0x400170FC C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170FC C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170FC C FIELD 29w03 FORD: Sinc filter order
-0x40017100 B REGISTER DFSDM0_JDATAR (ro): DFSDM data register for injected group
-0x40017100 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017100 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017104 B REGISTER DFSDM1_JDATAR (ro): DFSDM data register for injected group
-0x40017104 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017104 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017108 B REGISTER DFSDM2_JDATAR (ro): DFSDM data register for injected group
-0x40017108 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017108 C FIELD 08w24 JDATA: Injected group conversion data
-0x4001710C B REGISTER DFSDM3_JDATAR (ro): DFSDM data register for injected group
-0x4001710C C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x4001710C C FIELD 08w24 JDATA: Injected group conversion data
-0x40017110 B REGISTER DFSDM0_RDATAR (ro): DFSDM data register for the regular channel
-0x40017110 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017110 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017110 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017114 B REGISTER DFSDM1_RDATAR (ro): DFSDM data register for the regular channel
-0x40017114 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017114 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017114 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017118 B REGISTER DFSDM2_RDATAR (ro): DFSDM data register for the regular channel
-0x40017118 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017118 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017118 C FIELD 08w24 RDATA: Regular channel conversion data
-0x4001711C B REGISTER DFSDM3_RDATAR (ro): DFSDM data register for the regular channel
+0x40017000 B REGISTER CH0CFGR1 (rw): channel configuration y register
+0x40017000 C FIELD 00w02 SITP: SITP
+0x40017000 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017000 C FIELD 05w01 SCDEN: SCDEN
+0x40017000 C FIELD 06w01 CKABEN: CKABEN
+0x40017000 C FIELD 07w01 CHEN: CHEN
+0x40017000 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017000 C FIELD 12w02 DATMPX: DATMPX
+0x40017000 C FIELD 14w02 DATPACK: DATPACK
+0x40017000 C FIELD 16w08 CKOUTDIV: CKOUTDIV
+0x40017000 C FIELD 30w01 CKOUTSRC: CKOUTSRC
+0x40017000 C FIELD 31w01 DFSDMEN: DFSDMEN
+0x40017004 B REGISTER CH0CFGR2 (rw): channel configuration y register
+0x40017004 C FIELD 03w05 DTRBS: DTRBS
+0x40017004 C FIELD 08w24 OFFSET: OFFSET
+0x40017008 B REGISTER CH0AWSCDR (rw): analog watchdog and short-circuit detector register
+0x40017008 C FIELD 00w08 SCDT: SCDT
+0x40017008 C FIELD 12w04 BKSCD: BKSCD
+0x40017008 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017008 C FIELD 22w02 AWFORD: AWFORD
+0x4001700C B REGISTER CH0WDATR (rw): channel watchdog filter data register
+0x4001700C C FIELD 00w16 WDATA: WDATA
+0x40017010 B REGISTER CH0DATINR (rw): channel data input register
+0x40017010 C FIELD 00w16 INDAT0: INDAT0
+0x40017010 C FIELD 16w16 INDAT1: INDAT1
+0x40017014 B REGISTER CH0DLYR (rw): channel y delay register
+0x40017014 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017020 B REGISTER CH1CFGR1 (rw): CH1CFGR1
+0x40017020 C FIELD 00w02 SITP: SITP
+0x40017020 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017020 C FIELD 05w01 SCDEN: SCDEN
+0x40017020 C FIELD 06w01 CKABEN: CKABEN
+0x40017020 C FIELD 07w01 CHEN: CHEN
+0x40017020 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017020 C FIELD 12w02 DATMPX: DATMPX
+0x40017020 C FIELD 14w02 DATPACK: DATPACK
+0x40017024 B REGISTER CH1CFGR2 (rw): CH1CFGR2
+0x40017024 C FIELD 03w05 DTRBS: DTRBS
+0x40017024 C FIELD 08w24 OFFSET: OFFSET
+0x40017028 B REGISTER CH1AWSCDR (rw): CH1AWSCDR
+0x40017028 C FIELD 00w08 SCDT: SCDT
+0x40017028 C FIELD 12w04 BKSCD: BKSCD
+0x40017028 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017028 C FIELD 22w02 AWFORD: AWFORD
+0x4001702C B REGISTER CH1WDATR (rw): CH1WDATR
+0x4001702C C FIELD 00w16 WDATA: WDATA
+0x40017030 B REGISTER CH1DATINR (rw): CH1DATINR
+0x40017030 C FIELD 00w16 INDAT0: INDAT0
+0x40017030 C FIELD 16w16 INDAT1: INDAT1
+0x40017034 B REGISTER CH1DLYR (rw): channel y delay register
+0x40017034 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017040 B REGISTER CH2CFGR1 (rw): CH2CFGR1
+0x40017040 C FIELD 00w02 SITP: SITP
+0x40017040 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017040 C FIELD 05w01 SCDEN: SCDEN
+0x40017040 C FIELD 06w01 CKABEN: CKABEN
+0x40017040 C FIELD 07w01 CHEN: CHEN
+0x40017040 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017040 C FIELD 12w02 DATMPX: DATMPX
+0x40017040 C FIELD 14w02 DATPACK: DATPACK
+0x40017044 B REGISTER CH2CFGR2 (rw): CH2CFGR2
+0x40017044 C FIELD 03w05 DTRBS: DTRBS
+0x40017044 C FIELD 08w24 OFFSET: OFFSET
+0x40017048 B REGISTER CH2AWSCDR (rw): CH2AWSCDR
+0x40017048 C FIELD 00w08 SCDT: SCDT
+0x40017048 C FIELD 12w04 BKSCD: BKSCD
+0x40017048 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017048 C FIELD 22w02 AWFORD: AWFORD
+0x4001704C B REGISTER CH2WDATR (rw): CH2WDATR
+0x4001704C C FIELD 00w16 WDATA: WDATA
+0x40017050 B REGISTER CH2DATINR (rw): CH2DATINR
+0x40017050 C FIELD 00w16 INDAT0: INDAT0
+0x40017050 C FIELD 16w16 INDAT1: INDAT1
+0x40017054 B REGISTER CH2DLYR (rw): channel y delay register
+0x40017054 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017060 B REGISTER CH3CFGR1 (rw): CH3CFGR1
+0x40017060 C FIELD 00w02 SITP: SITP
+0x40017060 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017060 C FIELD 05w01 SCDEN: SCDEN
+0x40017060 C FIELD 06w01 CKABEN: CKABEN
+0x40017060 C FIELD 07w01 CHEN: CHEN
+0x40017060 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017060 C FIELD 12w02 DATMPX: DATMPX
+0x40017060 C FIELD 14w02 DATPACK: DATPACK
+0x40017064 B REGISTER CH3CFGR2 (rw): CH3CFGR2
+0x40017064 C FIELD 03w05 DTRBS: DTRBS
+0x40017064 C FIELD 08w24 OFFSET: OFFSET
+0x40017068 B REGISTER CH3AWSCDR (rw): CH3AWSCDR
+0x40017068 C FIELD 00w08 SCDT: SCDT
+0x40017068 C FIELD 12w04 BKSCD: BKSCD
+0x40017068 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017068 C FIELD 22w02 AWFORD: AWFORD
+0x4001706C B REGISTER CH3WDATR (rw): CH3WDATR
+0x4001706C C FIELD 00w16 WDATA: WDATA
+0x40017070 B REGISTER CH3DATINR (rw): CH3DATINR
+0x40017070 C FIELD 00w16 INDAT0: INDAT0
+0x40017070 C FIELD 16w16 INDAT1: INDAT1
+0x40017074 B REGISTER CH3DLYR (rw): channel y delay register
+0x40017074 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017080 B REGISTER CH4CFGR1 (rw): CH4CFGR1
+0x40017080 C FIELD 00w02 SITP: SITP
+0x40017080 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017080 C FIELD 05w01 SCDEN: SCDEN
+0x40017080 C FIELD 06w01 CKABEN: CKABEN
+0x40017080 C FIELD 07w01 CHEN: CHEN
+0x40017080 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017080 C FIELD 12w02 DATMPX: DATMPX
+0x40017080 C FIELD 14w02 DATPACK: DATPACK
+0x40017084 B REGISTER CH4CFGR2 (rw): CH4CFGR2
+0x40017084 C FIELD 03w05 DTRBS: DTRBS
+0x40017084 C FIELD 08w24 OFFSET: OFFSET
+0x40017088 B REGISTER CH4AWSCDR (rw): CH4AWSCDR
+0x40017088 C FIELD 00w08 SCDT: SCDT
+0x40017088 C FIELD 12w04 BKSCD: BKSCD
+0x40017088 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017088 C FIELD 22w02 AWFORD: AWFORD
+0x4001708C B REGISTER CH4WDATR (rw): CH4WDATR
+0x4001708C C FIELD 00w16 WDATA: WDATA
+0x40017090 B REGISTER CH4DATINR (rw): CH4DATINR
+0x40017090 C FIELD 00w16 INDAT0: INDAT0
+0x40017090 C FIELD 16w16 INDAT1: INDAT1
+0x40017094 B REGISTER CH4DLYR (rw): channel y delay register
+0x40017094 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170A0 B REGISTER CH5CFGR1 (rw): CH5CFGR1
+0x400170A0 C FIELD 00w02 SITP: SITP
+0x400170A0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170A0 C FIELD 05w01 SCDEN: SCDEN
+0x400170A0 C FIELD 06w01 CKABEN: CKABEN
+0x400170A0 C FIELD 07w01 CHEN: CHEN
+0x400170A0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170A0 C FIELD 12w02 DATMPX: DATMPX
+0x400170A0 C FIELD 14w02 DATPACK: DATPACK
+0x400170A4 B REGISTER CH5CFGR2 (rw): CH5CFGR2
+0x400170A4 C FIELD 03w05 DTRBS: DTRBS
+0x400170A4 C FIELD 08w24 OFFSET: OFFSET
+0x400170A8 B REGISTER CH5AWSCDR (rw): CH5AWSCDR
+0x400170A8 C FIELD 00w08 SCDT: SCDT
+0x400170A8 C FIELD 12w04 BKSCD: BKSCD
+0x400170A8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170A8 C FIELD 22w02 AWFORD: AWFORD
+0x400170AC B REGISTER CH5WDATR (rw): CH5WDATR
+0x400170AC C FIELD 00w16 WDATA: WDATA
+0x400170B0 B REGISTER CH5DATINR (rw): CH5DATINR
+0x400170B0 C FIELD 00w16 INDAT0: INDAT0
+0x400170B0 C FIELD 16w16 INDAT1: INDAT1
+0x400170B4 B REGISTER CH5DLYR (rw): channel y delay register
+0x400170B4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170C0 B REGISTER CH6CFGR1 (rw): CH6CFGR1
+0x400170C0 C FIELD 00w02 SITP: SITP
+0x400170C0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170C0 C FIELD 05w01 SCDEN: SCDEN
+0x400170C0 C FIELD 06w01 CKABEN: CKABEN
+0x400170C0 C FIELD 07w01 CHEN: CHEN
+0x400170C0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170C0 C FIELD 12w02 DATMPX: DATMPX
+0x400170C0 C FIELD 14w02 DATPACK: DATPACK
+0x400170C4 B REGISTER CH6CFGR2 (rw): CH6CFGR2
+0x400170C4 C FIELD 03w05 DTRBS: DTRBS
+0x400170C4 C FIELD 08w24 OFFSET: OFFSET
+0x400170C8 B REGISTER CH6AWSCDR (rw): CH6AWSCDR
+0x400170C8 C FIELD 00w08 SCDT: SCDT
+0x400170C8 C FIELD 12w04 BKSCD: BKSCD
+0x400170C8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170C8 C FIELD 22w02 AWFORD: AWFORD
+0x400170CC B REGISTER CH6WDATR (rw): CH6WDATR
+0x400170CC C FIELD 00w16 WDATA: WDATA
+0x400170D0 B REGISTER CH6DATINR (rw): CH6DATINR
+0x400170D0 C FIELD 00w16 INDAT0: INDAT0
+0x400170D0 C FIELD 16w16 INDAT1: INDAT1
+0x400170D4 B REGISTER CH6DLYR (rw): channel y delay register
+0x400170D4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170E0 B REGISTER CH7CFGR1 (rw): CH7CFGR1
+0x400170E0 C FIELD 00w02 SITP: SITP
+0x400170E0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170E0 C FIELD 05w01 SCDEN: SCDEN
+0x400170E0 C FIELD 06w01 CKABEN: CKABEN
+0x400170E0 C FIELD 07w01 CHEN: CHEN
+0x400170E0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170E0 C FIELD 12w02 DATMPX: DATMPX
+0x400170E0 C FIELD 14w02 DATPACK: DATPACK
+0x400170E4 B REGISTER CH7CFGR2 (rw): CH7CFGR2
+0x400170E4 C FIELD 03w05 DTRBS: DTRBS
+0x400170E4 C FIELD 08w24 OFFSET: OFFSET
+0x400170E8 B REGISTER CH7AWSCDR (rw): CH7AWSCDR
+0x400170E8 C FIELD 00w08 SCDT: SCDT
+0x400170E8 C FIELD 12w04 BKSCD: BKSCD
+0x400170E8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170E8 C FIELD 22w02 AWFORD: AWFORD
+0x400170EC B REGISTER CH7WDATR (rw): CH7WDATR
+0x400170EC C FIELD 00w16 WDATA: WDATA
+0x400170F0 B REGISTER CH7DATINR (rw): CH7DATINR
+0x400170F0 C FIELD 00w16 INDAT0: INDAT0
+0x400170F0 C FIELD 16w16 INDAT1: INDAT1
+0x400170F4 B REGISTER CH7DLYR (rw): channel y delay register
+0x400170F4 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017100 B REGISTER DFSDM_FLT0CR1 (rw): control register 1
+0x40017100 C FIELD 00w01 DFEN: DFSDM enable
+0x40017100 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017100 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017100 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017100 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017100 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017100 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017100 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017100 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017100 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017100 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017100 C FIELD 24w03 RCH: Regular channel selection
+0x40017100 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017100 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017104 B REGISTER DFSDM_FLT0CR2 (rw): control register 2
+0x40017104 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017104 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017104 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017104 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017104 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017104 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017104 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017104 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017104 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017108 B REGISTER DFSDM_FLT0ISR (ro): interrupt and status register
+0x40017108 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017108 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017108 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017108 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017108 C FIELD 04w01 AWDF: Analog watchdog
+0x40017108 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017108 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017108 C FIELD 16w08 CKABF: Clock absence flag
+0x40017108 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001710C B REGISTER DFSDM_FLT0ICR (rw): interrupt flag clear register
+0x4001710C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001710C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001710C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001710C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017110 B REGISTER DFSDM_FLT0JCHGR (rw): injected channel group selection register
+0x40017110 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017114 B REGISTER DFSDM_FLT0FCR (rw): filter control register
+0x40017114 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017114 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017114 C FIELD 29w03 FORD: Sinc filter order
+0x40017118 B REGISTER DFSDM_FLT0JDATAR (ro): data register for injected group
+0x40017118 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017118 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001711C B REGISTER DFSDM_FLT0RDATAR (ro): data register for the regular channel
0x4001711C C FIELD 00w03 RDATACH: Regular channel most recently converted
0x4001711C C FIELD 04w01 RPEND: Regular channel pending data
0x4001711C C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017120 B REGISTER DFSDM0_AWHTR (rw): DFSDM analog watchdog high threshold register
+0x40017120 B REGISTER DFSDM_FLT0AWHTR (rw): analog watchdog high threshold register
0x40017120 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
0x40017120 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017124 B REGISTER DFSDM1_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017124 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017124 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017128 B REGISTER DFSDM2_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017128 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017128 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x4001712C B REGISTER DFSDM3_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x4001712C C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x4001712C C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017130 B REGISTER DFSDM0_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017130 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017130 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017134 B REGISTER DFSDM1_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017134 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017134 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017138 B REGISTER DFSDM2_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017138 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017138 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x4001713C B REGISTER DFSDM3_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x4001713C C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x4001713C C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017140 B REGISTER DFSDM0_AWSR (ro): DFSDM analog watchdog status register
-0x40017140 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017140 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017144 B REGISTER DFSDM1_AWSR (ro): DFSDM analog watchdog status register
-0x40017144 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017144 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017148 B REGISTER DFSDM2_AWSR (ro): DFSDM analog watchdog status register
-0x40017148 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017148 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x4001714C B REGISTER DFSDM3_AWSR (ro): DFSDM analog watchdog status register
-0x4001714C C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x4001714C C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017150 B REGISTER DFSDM0_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017150 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017150 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017154 B REGISTER DFSDM1_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017154 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017154 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017158 B REGISTER DFSDM2_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017158 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017158 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x4001715C B REGISTER DFSDM3_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x4001715C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x4001715C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017160 B REGISTER DFSDM0_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017160 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017160 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017164 B REGISTER DFSDM1_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017164 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017164 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017168 B REGISTER DFSDM2_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017168 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017168 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x4001716C B REGISTER DFSDM3_EXMAX (ro): DFSDM Extremes detector maximum register
-0x4001716C C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x4001716C C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017170 B REGISTER DFSDM0_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017170 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017170 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017174 B REGISTER DFSDM1_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017174 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017174 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017178 B REGISTER DFSDM2_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017178 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017178 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x4001717C B REGISTER DFSDM3_EXMIN (ro): DFSDM Extremes detector minimum register
-0x4001717C C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x4001717C C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017180 B REGISTER DFSDM0_CNVTIMR (ro): DFSDM conversion timer register
-0x40017180 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017184 B REGISTER DFSDM1_CNVTIMR (ro): DFSDM conversion timer register
-0x40017184 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017188 B REGISTER DFSDM2_CNVTIMR (ro): DFSDM conversion timer register
-0x40017188 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x4001718C B REGISTER DFSDM3_CNVTIMR (ro): DFSDM conversion timer register
-0x4001718C C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
+0x40017124 B REGISTER DFSDM_FLT0AWLTR (rw): analog watchdog low threshold register
+0x40017124 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017124 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017128 B REGISTER DFSDM_FLT0AWSR (ro): analog watchdog status register
+0x40017128 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017128 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001712C B REGISTER DFSDM_FLT0AWCFR (rw): analog watchdog clear flag register
+0x4001712C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001712C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017130 B REGISTER DFSDM_FLT0EXMAX (ro): Extremes detector maximum register
+0x40017130 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017130 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017134 B REGISTER DFSDM_FLT0EXMIN (ro): Extremes detector minimum register
+0x40017134 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017134 C FIELD 08w24 EXMIN: EXMIN
+0x40017138 B REGISTER DFSDM_FLT0CNVTIMR (ro): conversion timer register
+0x40017138 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017180 B REGISTER DFSDM_FLT1CR1 (rw): control register 1
+0x40017180 C FIELD 00w01 DFEN: DFSDM enable
+0x40017180 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017180 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017180 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017180 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017180 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017180 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017180 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017180 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017180 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017180 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017180 C FIELD 24w03 RCH: Regular channel selection
+0x40017180 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017180 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017184 B REGISTER DFSDM_FLT1CR2 (rw): control register 2
+0x40017184 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017184 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017184 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017184 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017184 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017184 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017184 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017184 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017184 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017188 B REGISTER DFSDM_FLT1ISR (ro): interrupt and status register
+0x40017188 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017188 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017188 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017188 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017188 C FIELD 04w01 AWDF: Analog watchdog
+0x40017188 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017188 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017188 C FIELD 16w08 CKABF: Clock absence flag
+0x40017188 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001718C B REGISTER DFSDM_FLT1ICR (rw): interrupt flag clear register
+0x4001718C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001718C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001718C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001718C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017190 B REGISTER DFSDM_FLT1CHGR (rw): injected channel group selection register
+0x40017190 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017194 B REGISTER DFSDM_FLT1FCR (rw): filter control register
+0x40017194 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017194 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017194 C FIELD 29w03 FORD: Sinc filter order
+0x40017198 B REGISTER DFSDM_FLT1JDATAR (ro): data register for injected group
+0x40017198 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017198 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001719C B REGISTER DFSDM_FLT1RDATAR (ro): data register for the regular channel
+0x4001719C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001719C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001719C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400171A0 B REGISTER DFSDM_FLT1AWHTR (rw): analog watchdog high threshold register
+0x400171A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400171A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400171A4 B REGISTER DFSDM_FLT1AWLTR (rw): analog watchdog low threshold register
+0x400171A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400171A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400171A8 B REGISTER DFSDM_FLT1AWSR (ro): analog watchdog status register
+0x400171A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400171A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400171AC B REGISTER DFSDM_FLT1AWCFR (rw): analog watchdog clear flag register
+0x400171AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400171AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400171B0 B REGISTER DFSDM_FLT1EXMAX (ro): Extremes detector maximum register
+0x400171B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400171B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400171B4 B REGISTER DFSDM_FLT1EXMIN (ro): Extremes detector minimum register
+0x400171B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400171B4 C FIELD 08w24 EXMIN: EXMIN
+0x400171B8 B REGISTER DFSDM_FLT1CNVTIMR (ro): conversion timer register
+0x400171B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017200 B REGISTER DFSDM_FLT2CR1 (rw): control register 1
+0x40017200 C FIELD 00w01 DFEN: DFSDM enable
+0x40017200 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017200 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017200 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017200 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017200 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017200 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017200 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017200 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017200 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017200 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017200 C FIELD 24w03 RCH: Regular channel selection
+0x40017200 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017200 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017204 B REGISTER DFSDM_FLT2CR2 (rw): control register 2
+0x40017204 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017204 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017204 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017204 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017204 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017204 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017204 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017204 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017204 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017208 B REGISTER DFSDM_FLT2ISR (ro): interrupt and status register
+0x40017208 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017208 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017208 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017208 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017208 C FIELD 04w01 AWDF: Analog watchdog
+0x40017208 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017208 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017208 C FIELD 16w08 CKABF: Clock absence flag
+0x40017208 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001720C B REGISTER DFSDM_FLT2ICR (rw): interrupt flag clear register
+0x4001720C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001720C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001720C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001720C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017210 B REGISTER DFSDM_FLT2JCHGR (rw): injected channel group selection register
+0x40017210 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017214 B REGISTER DFSDM_FLT2FCR (rw): filter control register
+0x40017214 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017214 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017214 C FIELD 29w03 FORD: Sinc filter order
+0x40017218 B REGISTER DFSDM_FLT2JDATAR (ro): data register for injected group
+0x40017218 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017218 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001721C B REGISTER DFSDM_FLT2RDATAR (ro): data register for the regular channel
+0x4001721C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001721C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001721C C FIELD 08w24 RDATA: Regular channel conversion data
+0x40017220 B REGISTER DFSDM_FLT2AWHTR (rw): analog watchdog high threshold register
+0x40017220 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x40017220 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x40017224 B REGISTER DFSDM_FLT2AWLTR (rw): analog watchdog low threshold register
+0x40017224 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017224 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017228 B REGISTER DFSDM_FLT2AWSR (ro): analog watchdog status register
+0x40017228 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017228 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001722C B REGISTER DFSDM_FLT2AWCFR (rw): analog watchdog clear flag register
+0x4001722C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001722C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017230 B REGISTER DFSDM_FLT2EXMAX (ro): Extremes detector maximum register
+0x40017230 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017230 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017234 B REGISTER DFSDM_FLT2EXMIN (ro): Extremes detector minimum register
+0x40017234 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017234 C FIELD 08w24 EXMIN: EXMIN
+0x40017238 B REGISTER DFSDM_FLT2CNVTIMR (ro): conversion timer register
+0x40017238 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017280 B REGISTER DFSDM_FLT3CR1 (rw): control register 1
+0x40017280 C FIELD 00w01 DFEN: DFSDM enable
+0x40017280 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017280 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017280 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017280 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017280 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017280 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017280 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017280 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017280 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017280 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017280 C FIELD 24w03 RCH: Regular channel selection
+0x40017280 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017280 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017284 B REGISTER DFSDM_FLT3CR2 (rw): control register 2
+0x40017284 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017284 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017284 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017284 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017284 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017284 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017284 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017284 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017284 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017288 B REGISTER DFSDM_FLT3ISR (ro): interrupt and status register
+0x40017288 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017288 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017288 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017288 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017288 C FIELD 04w01 AWDF: Analog watchdog
+0x40017288 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017288 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017288 C FIELD 16w08 CKABF: Clock absence flag
+0x40017288 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001728C B REGISTER DFSDM_FLT3ICR (rw): interrupt flag clear register
+0x4001728C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001728C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001728C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001728C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017290 B REGISTER DFSDM_FLT3JCHGR (rw): injected channel group selection register
+0x40017290 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017294 B REGISTER DFSDM_FLT3FCR (rw): filter control register
+0x40017294 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017294 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017294 C FIELD 29w03 FORD: Sinc filter order
+0x40017298 B REGISTER DFSDM_FLT3JDATAR (ro): data register for injected group
+0x40017298 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017298 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001729C B REGISTER DFSDM_FLT3RDATAR (ro): data register for the regular channel
+0x4001729C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001729C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001729C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400172A0 B REGISTER DFSDM_FLT3AWHTR (rw): analog watchdog high threshold register
+0x400172A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400172A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400172A4 B REGISTER DFSDM_FLT3AWLTR (rw): analog watchdog low threshold register
+0x400172A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400172A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400172A8 B REGISTER DFSDM_FLT3AWSR (ro): analog watchdog status register
+0x400172A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400172A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400172AC B REGISTER DFSDM_FLT3AWCFR (rw): analog watchdog clear flag register
+0x400172AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400172AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400172B0 B REGISTER DFSDM_FLT3EXMAX (ro): Extremes detector maximum register
+0x400172B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400172B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400172B4 B REGISTER DFSDM_FLT3EXMIN (ro): Extremes detector minimum register
+0x400172B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400172B4 C FIELD 08w24 EXMIN: EXMIN
+0x400172B8 B REGISTER DFSDM_FLT3CNVTIMR (ro): conversion timer register
+0x400172B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
0x40017400 A PERIPHERAL HRTIM_Master
0x40017400 B REGISTER MCR (rw): Master Timer Control Register
0x40017400 C FIELD 00w03 CK_PSC: HRTIM Master Clock prescaler
@@ -17241,6 +17236,7 @@
0x58000404 C FIELD 06w01 PB8FMP: PB(8) Fast Mode Plus
0x58000404 C FIELD 07w01 PB9FMP: PB(9) Fm+
0x58000404 C FIELD 08w01 BOOSTE: Booster Enable
+0x58000404 C FIELD 09w01 BOOSTVDDSEL: Analog switch supply voltage selection
0x58000404 C FIELD 21w03 EPIS: Ethernet PHY Interface Selection
0x58000404 C FIELD 24w01 PA0SO: PA0 Switch Open
0x58000404 C FIELD 25w01 PA1SO: PA1 Switch Open
@@ -17266,6 +17262,19 @@
0x58000414 C FIELD 04w04 EXTI13: EXTI x configuration (x = 12 to 15)
0x58000414 C FIELD 08w04 EXTI14: EXTI x configuration (x = 12 to 15)
0x58000414 C FIELD 12w04 EXTI15: EXTI x configuration (x = 12 to 15)
+0x58000418 B REGISTER CFGR (rw): configuration register
+0x58000418 C FIELD 00w01 CM4L: CM4L
+0x58000418 C FIELD 02w01 PVDL: PVDL
+0x58000418 C FIELD 03w01 FLASHL: FLASHL
+0x58000418 C FIELD 06w01 CM7L: CM7L
+0x58000418 C FIELD 07w01 BKRAML: BKRAML
+0x58000418 C FIELD 09w01 SRAM4L: SRAM4L
+0x58000418 C FIELD 10w01 SRAM3L: SRAM3L
+0x58000418 C FIELD 11w01 SRAM2L: SRAM2L
+0x58000418 C FIELD 12w01 SRAM1L: SRAM1L
+0x58000418 C FIELD 13w01 DTCML: DTCML
+0x58000418 C FIELD 14w01 ITCML: ITCML
+0x58000418 C FIELD 15w01 AXISRAML: AXISRAML
0x58000420 B REGISTER CCCSR (rw): compensation cell control/status register
0x58000420 C FIELD 00w01 EN: enable
0x58000420 C FIELD 01w01 CS: Code selection
@@ -17277,23 +17286,28 @@
0x58000428 B REGISTER CCCR (rw): SYSCFG compensation cell code register
0x58000428 C FIELD 00w04 NCC: NMOS compensation code
0x58000428 C FIELD 04w04 PCC: PMOS compensation code
-0x5800042C B REGISTER PWRCR (rw): SYSCFG Power Control Register
-0x5800042C C FIELD 00w01 ODEN: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode. This bit must be written only in VOS1 voltage scaling mode
+0x5800042C B REGISTER PWRCR (rw): SYSCFG power control register
+0x5800042C C FIELD 00w01 ODEN: Overdrive enable
0x58000524 B REGISTER PKGR (ro): SYSCFG package register
0x58000524 C FIELD 00w04 PKG: Package
0x58000700 B REGISTER UR0 (ro): SYSCFG user register 0
0x58000700 C FIELD 00w01 BKS: Bank Swap
0x58000700 C FIELD 16w08 RDP: Readout protection
-0x58000708 B REGISTER UR2 (rw): SYSCFG user register 2
-0x58000708 C FIELD 00w02 BORH: BOR_LVL Brownout Reset Threshold Level
-0x58000708 C FIELD 16w16 BOOT_ADD0: Boot Address 0
+0x58000704 B REGISTER UR1 (rw): SYSCFG user register 1
+0x58000704 C FIELD 00w01 BCM4: Boot Cortex-M4
+0x58000704 C FIELD 16w01 BCM7: Boot Cortex-M7
+0x58000708 B REGISTER UR2: SYSCFG user register 2
+0x58000708 C FIELD 00w02 BORH (ro): BOR_LVL Brownout Reset Threshold Level
+0x58000708 C FIELD 16w16 BCM7_ADD0 (rw): Cortex-M7 Boot Address 0
0x5800070C B REGISTER UR3 (rw): SYSCFG user register 3
-0x5800070C C FIELD 16w16 BOOT_ADD1: Boot Address 1
-0x58000710 B REGISTER UR4 (ro): SYSCFG user register 4
-0x58000710 C FIELD 16w01 MEPAD_1: Mass Erase Protected Area Disabled for bank 1
+0x5800070C C FIELD 00w16 BCM4_ADD1: Cortex-M4 Boot Address 0
+0x5800070C C FIELD 16w16 BCM7_ADD1: Cortex-M7 Boot Address 1
+0x58000710 B REGISTER UR4: SYSCFG user register 4
+0x58000710 C FIELD 00w16 BCM4_ADD1 (rw): Mass Erase Protected Area Disabled for bank 1
+0x58000710 C FIELD 16w01 MEPAD_1 (ro): Boot Cortex-M4 Address 1
0x58000714 B REGISTER UR5 (ro): SYSCFG user register 5
0x58000714 C FIELD 00w01 MESAD_1: Mass erase secured area disabled for bank 1
-0x58000714 C FIELD 16w08 WRPN_1: Write protection for flash bank 1
+0x58000714 C FIELD 16w08 WRPS_1: Write protection for flash bank 1
0x58000718 B REGISTER UR6 (ro): SYSCFG user register 6
0x58000718 C FIELD 00w12 PA_BEG_1: Protected area start address for bank 1
0x58000718 C FIELD 16w12 PA_END_1: Protected area end address for bank 1
@@ -17304,7 +17318,7 @@
0x58000720 C FIELD 00w01 MEPAD_2: Mass erase protected area disabled for bank 2
0x58000720 C FIELD 16w01 MESAD_2: Mass erase secured area disabled for bank 2
0x58000724 B REGISTER UR9 (ro): SYSCFG user register 9
-0x58000724 C FIELD 00w08 WRPN_2: Write protection for flash bank 2
+0x58000724 C FIELD 00w08 WRPS_2: Write protection for flash bank 2
0x58000724 C FIELD 16w12 PA_BEG_2: Protected area start address for bank 2
0x58000728 B REGISTER UR10 (ro): SYSCFG user register 10
0x58000728 C FIELD 00w12 PA_END_2: Protected area end address for bank 2
@@ -17313,14 +17327,17 @@
0x5800072C C FIELD 00w12 SA_END_2: Secured area end address for bank 2
0x5800072C C FIELD 16w01 IWDG1M: Independent Watchdog 1 mode
0x58000730 B REGISTER UR12 (ro): SYSCFG user register 12
+0x58000730 C FIELD 00w01 IWDG2M: Independent Watchdog 2 mode
0x58000730 C FIELD 16w01 SECURE: Secure mode
0x58000734 B REGISTER UR13 (ro): SYSCFG user register 13
0x58000734 C FIELD 00w02 SDRS: Secured DTCM RAM Size
0x58000734 C FIELD 16w01 D1SBRST: D1 Standby reset
0x58000738 B REGISTER UR14 (rw): SYSCFG user register 14
0x58000738 C FIELD 00w01 D1STPRST: D1 Stop Reset
-0x5800073C B REGISTER UR15 (ro): SYSCFG user register 15
-0x5800073C C FIELD 16w01 FZIWDGSTB: Freeze independent watchdog in Standby mode
+0x58000738 C FIELD 16w01 D2SBRST: D2 Standby Reset
+0x5800073C B REGISTER UR15: SYSCFG user register 15
+0x5800073C C FIELD 00w01 D2STPRST (rw): D2 Stop Reset
+0x5800073C C FIELD 16w01 FZIWDGSTB (ro): Freeze independent watchdog in Standby mode
0x58000740 B REGISTER UR16 (ro): SYSCFG user register 16
0x58000740 C FIELD 00w01 FZIWDGSTP: Freeze independent watchdog in Stop mode
0x58000740 C FIELD 16w01 PKP: Private key programmed
@@ -22159,86 +22176,88 @@
0x58027054 B REGISTER M2FECR (rw): RAMECC monitor 2 failing error code register
0x58027054 C FIELD 00w32 FEC (ro): ECC failing code
0x5C001000 A PERIPHERAL DBGMCU
-0x5C001000 B REGISTER IDC (ro): Identity code
+0x5C001000 B REGISTER IDC (ro): DBGMCU Identity Code Register
0x5C001000 C FIELD 00w12 DEV_ID: Device ID
-0x5C001000 C FIELD 16w16 REV_ID: Revision ID
-0x5C001004 B REGISTER CR (rw): Configuration register
-0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow debug in D1 Sleep mode
-0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow debug in D1 Stop mode
-0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow debug in D1 Standby mode
-0x5C001004 C FIELD 03w01 DBGSLEEP_D2: Allow debug in D2 Sleep mode
-0x5C001004 C FIELD 04w01 DBGSTOP_D2: Allow debug in D2 Stop mode
-0x5C001004 C FIELD 05w01 DBGSTBY_D2: Allow debug in D2 Standby mode
-0x5C001004 C FIELD 20w01 TRACECLKEN: Trace clock enable enable
-0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable enable
-0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable enable
+0x5C001000 C FIELD 16w16 REV_ID: Revision
+0x5C001004 B REGISTER CR (rw): DBGMCU Configuration Register
+0x5C001004 C FIELD 00w01 DBGSLPD1: Allow D1 domain debug in Sleep mode
+0x5C001004 C FIELD 01w01 DBGSTPD1: Allow D1 domain debug in Stop mode
+0x5C001004 C FIELD 02w01 DBGSTBD1: Allow D1 domain debug in Standby mode
+0x5C001004 C FIELD 03w01 DBGSLPD2: Allow D2 domain debug in Sleep mode
+0x5C001004 C FIELD 04w01 DBGSTPD2: Allow D2 domain debug in Stop mode
+0x5C001004 C FIELD 05w01 DBGSTBD2: Allow D2 domain debug in Standby mode
+0x5C001004 C FIELD 07w01 DBGSTPD3: Allow debug in D3 Stop mode
+0x5C001004 C FIELD 08w01 DBGSTBD3: Allow debug in D3 Standby mode
+0x5C001004 C FIELD 20w01 TRACECLKEN: Trace port clock enable
+0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable
+0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable
0x5C001004 C FIELD 28w01 TRGOEN: External trigger output enable
-0x5C001034 B REGISTER APB3FZ1 (rw): APB3 peripheral freeze register
-0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug mode
-0x5C001038 B REGISTER APB3FZ2 (rw): APB3 peripheral freeze register CPU2
-0x5C001038 C FIELD 06w01 WWDG1: WWDG1 stop when Cortex-M4 in debug mode
-0x5C00103C B REGISTER APB1LFZ1 (rw): APB1L peripheral freeze register
-0x5C00103C C FIELD 00w01 TIM2: TIM2 stop in debug mode
-0x5C00103C C FIELD 01w01 TIM3: TIM3 stop in debug mode
-0x5C00103C C FIELD 02w01 TIM4: TIM4 stop in debug mode
-0x5C00103C C FIELD 03w01 TIM5: TIM5 stop in debug mode
-0x5C00103C C FIELD 04w01 TIM6: TIM6 stop in debug mode
-0x5C00103C C FIELD 05w01 TIM7: TIM7 stop in debug mode
-0x5C00103C C FIELD 06w01 TIM12: TIM12 stop in debug mode
-0x5C00103C C FIELD 07w01 TIM13: TIM13 stop in debug mode
-0x5C00103C C FIELD 08w01 TIM14: TIM14 stop in debug mode
-0x5C00103C C FIELD 09w01 LPTIM1: LPTIM1 stop in debug mode
-0x5C00103C C FIELD 11w01 WWDG2: WWDG2 stop when Cortex-M7 in debug mode
-0x5C00103C C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop in debug mode
-0x5C001040 B REGISTER APB1LFZ2 (rw): APB1L peripheral freeze register CPU2
-0x5C001040 C FIELD 00w01 TIM2: TIM2 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 01w01 TIM3: TIM3 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 02w01 TIM4: TIM4 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 03w01 TIM5: TIM5 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 04w01 TIM6: TIM6 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 05w01 TIM7: TIM7 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 06w01 TIM12: TIM12 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 07w01 TIM13: TIM13 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 08w01 TIM14: TIM14 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 09w01 LPTIM1: LPTIM1 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 11w01 WWDG2: WWDG2 stop in when Cortex-M4 when Cortex-M4 in debug mode
-0x5C001040 C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001048 B REGISTER APB2FZ2 (rw): APB2 peripheral freeze register CPU2
-0x5C001048 C FIELD 00w01 TIM1: TIM1 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 01w01 TIM8: TIM8 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 16w01 TIM15: TIM15 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 17w01 TIM16: TIM16 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 18w01 TIM17: TIM17 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 29w01 HRTIM: HRTIM stop when Cortex-M4 in debug mode
-0x5C00104C B REGISTER APB2FZ1 (rw): APB2 peripheral freeze register
-0x5C00104C C FIELD 00w01 TIM1: TIM1 stop in debug mode
-0x5C00104C C FIELD 01w01 TIM8: TIM8 stop in debug mode
-0x5C00104C C FIELD 16w01 TIM15: TIM15 stop in debug mode
-0x5C00104C C FIELD 17w01 TIM16: TIM16 stop in debug mode
-0x5C00104C C FIELD 18w01 TIM17: TIM17 stop in debug mode
-0x5C00104C C FIELD 29w01 HRTIM: HRTIM stop in debug mode
-0x5C001054 B REGISTER APB4FZ1 (rw): APB4 peripheral freeze register
-0x5C001054 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop in debug mode
-0x5C001054 C FIELD 09w01 LPTIM2: LPTIM2 stop in debug mode
-0x5C001054 C FIELD 10w01 LPTIM3: LPTIM3 stop in debug mode
-0x5C001054 C FIELD 11w01 LPTIM4: LPTIM4 stop in debug mode
-0x5C001054 C FIELD 12w01 LPTIM5: LPTIM5 stop in debug mode
-0x5C001054 C FIELD 16w01 RTC: RTC stop in debug mode
-0x5C001054 C FIELD 18w01 IWDG1: Independent watchdog for D1 stop in debug mode
-0x5C001054 C FIELD 19w01 IWDG2: Independent watchdog for D2 stop when Cortex-M7 in debug mode
-0x5C001058 B REGISTER APB4FZ2 (rw): APB4 peripheral freeze register CPU2
-0x5C001058 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 09w01 LPTIM2: LPTIM2 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 10w01 LPTIM3: LPTIM3 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 11w01 LPTIM4: LPTIM4 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 12w01 LPTIM5: LPTIM5 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 16w01 RTC: RTC stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 18w01 WDGLSD1: LS watchdog for D1 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 19w01 WDGLSD2: LS watchdog for D2 stop when Cortex-M4 in debug mode
+0x5C001034 B REGISTER APB3FZ1 (rw): DBGMCU APB3 peripheral freeze register CPU1
+0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C001038 B REGISTER APB3FZ2 (rw): DBGMCU APB3 peripheral freeze register CPU2
+0x5C001038 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C00103C B REGISTER APB1LFZ1 (rw): DBGMCU APB1L peripheral freeze register
+0x5C00103C C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C00103C C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C00103C C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C00103C C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C00103C C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C00103C C FIELD 05w01 DBG_TIM7: TIM7 stop in debug
+0x5C00103C C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C00103C C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C00103C C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C00103C C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C00103C C FIELD 11w01 DBG_WWDG2: WWDG2 stop in debug
+0x5C00103C C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C00103C C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C00103C C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C001040 B REGISTER APB1LFZ2 (rw): DBGMCU APB1L peripheral freeze register CPU2
+0x5C001040 C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C001040 C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C001040 C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C001040 C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C001040 C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C001040 C FIELD 05w01 DBG_TIM7: TIM4 stop in debug
+0x5C001040 C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C001040 C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C001040 C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C001040 C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C001040 C FIELD 11w01 DBG_WWDG2: WWDG2 stop in debug
+0x5C001040 C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C001040 C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C001040 C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C00104C B REGISTER APB2FZ1 (rw): DBGMCU APB2 peripheral freeze register
+0x5C00104C C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C00104C C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C00104C C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C00104C C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C00104C C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C00104C C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001050 B REGISTER APB2FZ2 (rw): DBGMCU APB2 peripheral freeze register CPU2
+0x5C001050 C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C001050 C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C001050 C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C001050 C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C001050 C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C001050 C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001054 B REGISTER APB4FZ1 (rw): DBGMCU APB4 peripheral freeze register
+0x5C001054 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001054 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001054 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001054 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001054 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001054 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001054 C FIELD 18w01 DBG_WDGLSD1: Independent watchdog for D1 stop in debug
+0x5C001054 C FIELD 19w01 DBG_WDGLSD2: Independent watchdog for D2 stop in debug
+0x5C001058 B REGISTER APB4FZ2 (rw): DBGMCU APB4 peripheral freeze register CPU2
+0x5C001058 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001058 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001058 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001058 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001058 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001058 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001058 C FIELD 18w01 DBG_WDGLSD1: LS watchdog for D1 stop in debug
+0x5C001058 C FIELD 19w01 DBG_WDGLSD2: LS watchdog for D2 stop in debug
0xE000E008 A PERIPHERAL SCB_ACTRL
0xE000E008 B REGISTER ACTRL (rw): Auxiliary control register
0xE000E008 C FIELD 02w01 DISFOLD: DISFOLD
@@ -22539,7 +22558,7 @@
0xE000ED20 B REGISTER SHPR3 (rw): System handler priority registers
0xE000ED20 C FIELD 16w08 PRI_14: Priority of system handler 14
0xE000ED20 C FIELD 24w08 PRI_15: Priority of system handler 15
-0xE000ED24 B REGISTER SHCRS (rw): System handler control and state register
+0xE000ED24 B REGISTER SHCSR (rw): System handler control and state register
0xE000ED24 C FIELD 00w01 MEMFAULTACT: Memory management fault exception active bit
0xE000ED24 C FIELD 01w01 BUSFAULTACT: Bus fault exception active bit
0xE000ED24 C FIELD 03w01 USGFAULTACT: Usage fault exception active bit
@@ -22616,7 +22635,7 @@
0xE000ED90 C FIELD 00w01 SEPARATE: Separate flag
0xE000ED90 C FIELD 08w08 DREGION: Number of MPU data regions
0xE000ED90 C FIELD 16w08 IREGION: Number of MPU instruction regions
-0xE000ED94 B REGISTER MPU_CTRL (ro): MPU control register
+0xE000ED94 B REGISTER MPU_CTRL (rw): MPU control register
0xE000ED94 C FIELD 00w01 ENABLE: Enables the MPU
0xE000ED94 C FIELD 01w01 HFNMIENA: Enables the operation of MPU during hard fault
0xE000ED94 C FIELD 02w01 PRIVDEFENA: Enable priviliged software access to default memory map
Raw
stm32h747cm7.mmap.diff
--- ./mmaps_old/stm32h747cm7.mmap 2021-06-06 20:39:56.380000000 -0500
+++ mmaps_new/stm32h747cm7.mmap 2021-06-06 20:39:04.730000000 -0500
@@ -91,7 +91,7 @@
0x4000001C C FIELD 11w01 OC4PE: OC4PE
0x4000001C C FIELD 12w03 OC4M: OC4M
0x4000001C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000001C C FIELD 15w01 OC4CE: O24CE
+0x4000001C C FIELD 15w01 OC4CE: OC4CE
0x4000001C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000001C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000020 B REGISTER CCER (rw): capture/compare enable register
@@ -226,7 +226,7 @@
0x4000041C C FIELD 11w01 OC4PE: OC4PE
0x4000041C C FIELD 12w03 OC4M: OC4M
0x4000041C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000041C C FIELD 15w01 OC4CE: O24CE
+0x4000041C C FIELD 15w01 OC4CE: OC4CE
0x4000041C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000041C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000420 B REGISTER CCER (rw): capture/compare enable register
@@ -367,7 +367,7 @@
0x4000081C C FIELD 11w01 OC4PE: OC4PE
0x4000081C C FIELD 12w03 OC4M: OC4M
0x4000081C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000081C C FIELD 15w01 OC4CE: O24CE
+0x4000081C C FIELD 15w01 OC4CE: OC4CE
0x4000081C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000081C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000820 B REGISTER CCER (rw): capture/compare enable register
@@ -508,7 +508,7 @@
0x40000C1C C FIELD 11w01 OC4PE: OC4PE
0x40000C1C C FIELD 12w03 OC4M: OC4M
0x40000C1C C FIELD 12w04 IC4F: Input capture 4 filter
-0x40000C1C C FIELD 15w01 OC4CE: O24CE
+0x40000C1C C FIELD 15w01 OC4CE: OC4CE
0x40000C1C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x40000C1C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000C20 B REGISTER CCER (rw): capture/compare enable register
@@ -691,7 +691,7 @@
0x4000181C C FIELD 11w01 OC4PE: OC4PE
0x4000181C C FIELD 12w03 OC4M: OC4M
0x4000181C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000181C C FIELD 15w01 O24CE: O24CE
+0x4000181C C FIELD 15w01 OC4CE: OC4CE
0x4000181C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000181C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40001820 B REGISTER CCER (rw): capture/compare enable register
@@ -832,7 +832,7 @@
0x40001C1C C FIELD 11w01 OC4PE: OC4PE
0x40001C1C C FIELD 12w03 OC4M: OC4M
0x40001C1C C FIELD 12w04 IC4F: Input capture 4 filter
-0x40001C1C C FIELD 15w01 O24CE: O24CE
+0x40001C1C C FIELD 15w01 OC4CE: OC4CE
0x40001C1C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x40001C1C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40001C20 B REGISTER CCER (rw): capture/compare enable register
@@ -973,7 +973,7 @@
0x4000201C C FIELD 11w01 OC4PE: OC4PE
0x4000201C C FIELD 12w03 OC4M: OC4M
0x4000201C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000201C C FIELD 15w01 O24CE: O24CE
+0x4000201C C FIELD 15w01 OC4CE: OC4CE
0x4000201C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000201C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40002020 B REGISTER CCER (rw): capture/compare enable register
@@ -5527,498 +5527,493 @@
0x40016048 C FIELD 24w03 DLYM4L: Delay line for first microphone of pair 4
0x40016048 C FIELD 28w03 DLYM4R: Delay line for second microphone of pair 4
0x40017000 A PERIPHERAL DFSDM
-0x40017000 B REGISTER DFSDM_CHCFG0R1 (rw): DFSDM channel configuration 0 register 1
-0x40017000 C FIELD 00w02 SITP: Serial interface type for channel 0
-0x40017000 C FIELD 02w02 SPICKSEL: SPI clock select for channel 0
-0x40017000 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 0
-0x40017000 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 0
-0x40017000 C FIELD 07w01 CHEN: Channel 0 enable
-0x40017000 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017000 C FIELD 12w02 DATMPX: Input data multiplexer for channel 0
-0x40017000 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017000 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017000 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017000 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017004 B REGISTER DFSDM_CHCFG1R1 (rw): DFSDM channel configuration 1 register 1
-0x40017004 C FIELD 00w02 SITP: Serial interface type for channel 1
-0x40017004 C FIELD 02w02 SPICKSEL: SPI clock select for channel 1
-0x40017004 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 1
-0x40017004 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 1
-0x40017004 C FIELD 07w01 CHEN: Channel 1 enable
-0x40017004 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017004 C FIELD 12w02 DATMPX: Input data multiplexer for channel 1
-0x40017004 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017004 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017004 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017004 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017008 B REGISTER DFSDM_CHCFG2R1 (rw): DFSDM channel configuration 2 register 1
-0x40017008 C FIELD 00w02 SITP: Serial interface type for channel 2
-0x40017008 C FIELD 02w02 SPICKSEL: SPI clock select for channel 2
-0x40017008 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 2
-0x40017008 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 2
-0x40017008 C FIELD 07w01 CHEN: Channel 2 enable
-0x40017008 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017008 C FIELD 12w02 DATMPX: Input data multiplexer for channel 2
-0x40017008 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017008 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017008 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017008 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001700C B REGISTER DFSDM_CHCFG3R1 (rw): DFSDM channel configuration 3 register 1
-0x4001700C C FIELD 00w02 SITP: Serial interface type for channel 3
-0x4001700C C FIELD 02w02 SPICKSEL: SPI clock select for channel 3
-0x4001700C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 3
-0x4001700C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 3
-0x4001700C C FIELD 07w01 CHEN: Channel 3 enable
-0x4001700C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001700C C FIELD 12w02 DATMPX: Input data multiplexer for channel 3
-0x4001700C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001700C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001700C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001700C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017010 B REGISTER DFSDM_CHCFG4R1 (rw): DFSDM channel configuration 4 register 1
-0x40017010 C FIELD 00w02 SITP: Serial interface type for channel 4
-0x40017010 C FIELD 02w02 SPICKSEL: SPI clock select for channel 4
-0x40017010 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 4
-0x40017010 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 4
-0x40017010 C FIELD 07w01 CHEN: Channel 4 enable
-0x40017010 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017010 C FIELD 12w02 DATMPX: Input data multiplexer for channel 4
-0x40017010 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017010 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017010 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017010 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017014 B REGISTER DFSDM_CHCFG5R1 (rw): DFSDM channel configuration 5 register 1
-0x40017014 C FIELD 00w02 SITP: Serial interface type for channel 5
-0x40017014 C FIELD 02w02 SPICKSEL: SPI clock select for channel 5
-0x40017014 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 5
-0x40017014 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 5
-0x40017014 C FIELD 07w01 CHEN: Channel 5 enable
-0x40017014 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017014 C FIELD 12w02 DATMPX: Input data multiplexer for channel 5
-0x40017014 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017014 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017014 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017014 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017018 B REGISTER DFSDM_CHCFG6R1 (rw): DFSDM channel configuration 6 register 1
-0x40017018 C FIELD 00w02 SITP: Serial interface type for channel 6
-0x40017018 C FIELD 02w02 SPICKSEL: SPI clock select for channel 6
-0x40017018 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 6
-0x40017018 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 6
-0x40017018 C FIELD 07w01 CHEN: Channel 6 enable
-0x40017018 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017018 C FIELD 12w02 DATMPX: Input data multiplexer for channel 6
-0x40017018 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017018 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017018 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017018 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001701C B REGISTER DFSDM_CHCFG7R1 (rw): DFSDM channel configuration 7 register 1
-0x4001701C C FIELD 00w02 SITP: Serial interface type for channel 7
-0x4001701C C FIELD 02w02 SPICKSEL: SPI clock select for channel 7
-0x4001701C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 7
-0x4001701C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 7
-0x4001701C C FIELD 07w01 CHEN: Channel 7 enable
-0x4001701C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001701C C FIELD 12w02 DATMPX: Input data multiplexer for channel 7
-0x4001701C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001701C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001701C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001701C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017020 B REGISTER DFSDM_CHCFG0R2 (rw): DFSDM channel configuration 0 register 2
-0x40017020 C FIELD 03w05 DTRBS: Data right bit-shift for channel 0
-0x40017020 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 0
-0x40017024 B REGISTER DFSDM_CHCFG1R2 (rw): DFSDM channel configuration 1 register 2
-0x40017024 C FIELD 03w05 DTRBS: Data right bit-shift for channel 1
-0x40017024 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 1
-0x40017028 B REGISTER DFSDM_CHCFG2R2 (rw): DFSDM channel configuration 2 register 2
-0x40017028 C FIELD 03w05 DTRBS: Data right bit-shift for channel 2
-0x40017028 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 2
-0x4001702C B REGISTER DFSDM_CHCFG3R2 (rw): DFSDM channel configuration 3 register 2
-0x4001702C C FIELD 03w05 DTRBS: Data right bit-shift for channel 3
-0x4001702C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 3
-0x40017030 B REGISTER DFSDM_CHCFG4R2 (rw): DFSDM channel configuration 4 register 2
-0x40017030 C FIELD 03w05 DTRBS: Data right bit-shift for channel 4
-0x40017030 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 4
-0x40017034 B REGISTER DFSDM_CHCFG5R2 (rw): DFSDM channel configuration 5 register 2
-0x40017034 C FIELD 03w05 DTRBS: Data right bit-shift for channel 5
-0x40017034 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 5
-0x40017038 B REGISTER DFSDM_CHCFG6R2 (rw): DFSDM channel configuration 6 register 2
-0x40017038 C FIELD 03w05 DTRBS: Data right bit-shift for channel 6
-0x40017038 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 6
-0x4001703C B REGISTER DFSDM_CHCFG7R2 (rw): DFSDM channel configuration 7 register 2
-0x4001703C C FIELD 03w05 DTRBS: Data right bit-shift for channel 7
-0x4001703C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 7
-0x40017040 B REGISTER DFSDM_AWSCD0R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017040 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 0
-0x40017040 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 0
-0x40017040 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 0
-0x40017040 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 0
-0x40017044 B REGISTER DFSDM_AWSCD1R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017044 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 1
-0x40017044 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 1
-0x40017044 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 1
-0x40017044 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 1
-0x40017048 B REGISTER DFSDM_AWSCD2R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017048 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 2
-0x40017048 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 2
-0x40017048 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 2
-0x40017048 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 2
-0x4001704C B REGISTER DFSDM_AWSCD3R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001704C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 3
-0x4001704C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 3
-0x4001704C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 3
-0x4001704C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 3
-0x40017050 B REGISTER DFSDM_AWSCD4R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017050 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 4
-0x40017050 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 4
-0x40017050 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 4
-0x40017050 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 4
-0x40017054 B REGISTER DFSDM_AWSCD5R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017054 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 5
-0x40017054 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 5
-0x40017054 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 5
-0x40017054 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 5
-0x40017058 B REGISTER DFSDM_AWSCD6R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017058 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 6
-0x40017058 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 6
-0x40017058 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 6
-0x40017058 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 6
-0x4001705C B REGISTER DFSDM_AWSCD7R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001705C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 7
-0x4001705C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 7
-0x4001705C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 7
-0x4001705C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 7
-0x40017060 B REGISTER DFSDM_CHWDAT0R (ro): DFSDM channel watchdog filter data register
-0x40017060 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017064 B REGISTER DFSDM_CHWDAT1R (ro): DFSDM channel watchdog filter data register
-0x40017064 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017068 B REGISTER DFSDM_CHWDAT2R (ro): DFSDM channel watchdog filter data register
-0x40017068 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001706C B REGISTER DFSDM_CHWDAT3R (ro): DFSDM channel watchdog filter data register
-0x4001706C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017070 B REGISTER DFSDM_CHWDAT4R (ro): DFSDM channel watchdog filter data register
-0x40017070 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017074 B REGISTER DFSDM_CHWDAT5R (ro): DFSDM channel watchdog filter data register
-0x40017074 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017078 B REGISTER DFSDM_CHWDAT6R (ro): DFSDM channel watchdog filter data register
-0x40017078 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001707C B REGISTER DFSDM_CHWDAT7R (ro): DFSDM channel watchdog filter data register
-0x4001707C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017080 B REGISTER DFSDM_CHDATIN0R (rw): DFSDM channel data input register
-0x40017080 C FIELD 00w16 INDAT0: Input data for channel 0
-0x40017080 C FIELD 16w16 INDAT1: Input data for channel 1
-0x40017084 B REGISTER DFSDM_CHDATIN1R (rw): DFSDM channel data input register
-0x40017084 C FIELD 00w16 INDAT0: Input data for channel 1
-0x40017084 C FIELD 16w16 INDAT1: Input data for channel 2
-0x40017088 B REGISTER DFSDM_CHDATIN2R (rw): DFSDM channel data input register
-0x40017088 C FIELD 00w16 INDAT0: Input data for channel 2
-0x40017088 C FIELD 16w16 INDAT1: Input data for channel 3
-0x4001708C B REGISTER DFSDM_CHDATIN3R (rw): DFSDM channel data input register
-0x4001708C C FIELD 00w16 INDAT0: Input data for channel 3
-0x4001708C C FIELD 16w16 INDAT1: Input data for channel 4
-0x40017090 B REGISTER DFSDM_CHDATIN4R (rw): DFSDM channel data input register
-0x40017090 C FIELD 00w16 INDAT0: Input data for channel 4
-0x40017090 C FIELD 16w16 INDAT1: Input data for channel 5
-0x40017094 B REGISTER DFSDM_CHDATIN5R (rw): DFSDM channel data input register
-0x40017094 C FIELD 00w16 INDAT0: Input data for channel 5
-0x40017094 C FIELD 16w16 INDAT1: Input data for channel 6
-0x40017098 B REGISTER DFSDM_CHDATIN6R (rw): DFSDM channel data input register
-0x40017098 C FIELD 00w16 INDAT0: Input data for channel 6
-0x40017098 C FIELD 16w16 INDAT1: Input data for channel 7
-0x4001709C B REGISTER DFSDM_CHDATIN7R (rw): DFSDM channel data input register
-0x4001709C C FIELD 00w16 INDAT0: Input data for channel 7
-0x4001709C C FIELD 16w16 INDAT1: Input data for channel 8
-0x400170A0 B REGISTER DFSDM0_CR1 (rw): DFSDM control register 1
-0x400170A0 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A0 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A0 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A0 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A0 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A0 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A0 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A0 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A0 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A0 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A0 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A0 C FIELD 24w03 RCH: Regular channel selection
-0x400170A0 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A0 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A4 B REGISTER DFSDM1_CR1 (rw): DFSDM control register 1
-0x400170A4 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A4 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A4 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A4 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A4 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A4 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A4 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A4 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A4 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A4 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A4 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A4 C FIELD 24w03 RCH: Regular channel selection
-0x400170A4 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A4 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A8 B REGISTER DFSDM2_CR1 (rw): DFSDM control register 1
-0x400170A8 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A8 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A8 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A8 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A8 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A8 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A8 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A8 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A8 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A8 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A8 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A8 C FIELD 24w03 RCH: Regular channel selection
-0x400170A8 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A8 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170AC B REGISTER DFSDM3_CR1 (rw): DFSDM control register 1
-0x400170AC C FIELD 00w01 DFEN: DFSDM enable
-0x400170AC C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170AC C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170AC C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170AC C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170AC C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170AC C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170AC C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170AC C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170AC C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170AC C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170AC C FIELD 24w03 RCH: Regular channel selection
-0x400170AC C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170AC C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170B0 B REGISTER DFSDM0_CR2 (rw): DFSDM control register 2
-0x400170B0 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B0 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B0 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B0 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B0 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B0 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B0 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B0 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B0 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B4 B REGISTER DFSDM1_CR2 (rw): DFSDM control register 2
-0x400170B4 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B4 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B4 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B4 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B4 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B4 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B4 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B4 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B4 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B8 B REGISTER DFSDM2_CR2 (rw): DFSDM control register 2
-0x400170B8 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B8 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B8 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B8 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B8 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B8 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B8 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B8 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B8 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170BC B REGISTER DFSDM3_CR2 (rw): DFSDM control register 2
-0x400170BC C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170BC C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170BC C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170BC C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170BC C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170BC C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170BC C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170BC C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170BC C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170C0 B REGISTER DFSDM0_ISR (ro): DFSDM interrupt and status register
-0x400170C0 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C0 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C0 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C0 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C0 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C0 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C0 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C0 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C0 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C4 B REGISTER DFSDM1_ISR (ro): DFSDM interrupt and status register
-0x400170C4 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C4 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C4 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C4 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C4 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C4 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C4 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C4 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C4 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C8 B REGISTER DFSDM2_ISR (ro): DFSDM interrupt and status register
-0x400170C8 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C8 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C8 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C8 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C8 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C8 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C8 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C8 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C8 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170CC B REGISTER DFSDM3_ISR (ro): DFSDM interrupt and status register
-0x400170CC C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170CC C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170CC C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170CC C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170CC C FIELD 04w01 AWDF: Analog watchdog
-0x400170CC C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170CC C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170CC C FIELD 16w08 CKABF: Clock absence flag
-0x400170CC C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170D0 B REGISTER DFSDM0_ICR (rw): DFSDM interrupt flag clear register
-0x400170D0 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D0 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D0 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D0 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D4 B REGISTER DFSDM1_ICR (rw): DFSDM interrupt flag clear register
-0x400170D4 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D4 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D4 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D4 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D8 B REGISTER DFSDM2_ICR (rw): DFSDM interrupt flag clear register
-0x400170D8 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D8 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D8 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D8 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170DC B REGISTER DFSDM3_ICR (rw): DFSDM interrupt flag clear register
-0x400170DC C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170DC C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170DC C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170DC C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170E0 B REGISTER DFSDM0_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E0 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E4 B REGISTER DFSDM1_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E4 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E8 B REGISTER DFSDM2_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E8 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170EC B REGISTER DFSDM3_JCHGR (rw): DFSDM injected channel group selection register
-0x400170EC C FIELD 00w08 JCHG: Injected channel group selection
-0x400170F0 B REGISTER DFSDM0_FCR (rw): DFSDM filter control register
-0x400170F0 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F0 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F0 C FIELD 29w03 FORD: Sinc filter order
-0x400170F4 B REGISTER DFSDM1_FCR (rw): DFSDM filter control register
-0x400170F4 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F4 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F4 C FIELD 29w03 FORD: Sinc filter order
-0x400170F8 B REGISTER DFSDM2_FCR (rw): DFSDM filter control register
-0x400170F8 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F8 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F8 C FIELD 29w03 FORD: Sinc filter order
-0x400170FC B REGISTER DFSDM3_FCR (rw): DFSDM filter control register
-0x400170FC C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170FC C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170FC C FIELD 29w03 FORD: Sinc filter order
-0x40017100 B REGISTER DFSDM0_JDATAR (ro): DFSDM data register for injected group
-0x40017100 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017100 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017104 B REGISTER DFSDM1_JDATAR (ro): DFSDM data register for injected group
-0x40017104 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017104 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017108 B REGISTER DFSDM2_JDATAR (ro): DFSDM data register for injected group
-0x40017108 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017108 C FIELD 08w24 JDATA: Injected group conversion data
-0x4001710C B REGISTER DFSDM3_JDATAR (ro): DFSDM data register for injected group
-0x4001710C C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x4001710C C FIELD 08w24 JDATA: Injected group conversion data
-0x40017110 B REGISTER DFSDM0_RDATAR (ro): DFSDM data register for the regular channel
-0x40017110 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017110 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017110 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017114 B REGISTER DFSDM1_RDATAR (ro): DFSDM data register for the regular channel
-0x40017114 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017114 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017114 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017118 B REGISTER DFSDM2_RDATAR (ro): DFSDM data register for the regular channel
-0x40017118 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017118 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017118 C FIELD 08w24 RDATA: Regular channel conversion data
-0x4001711C B REGISTER DFSDM3_RDATAR (ro): DFSDM data register for the regular channel
+0x40017000 B REGISTER CH0CFGR1 (rw): channel configuration y register
+0x40017000 C FIELD 00w02 SITP: SITP
+0x40017000 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017000 C FIELD 05w01 SCDEN: SCDEN
+0x40017000 C FIELD 06w01 CKABEN: CKABEN
+0x40017000 C FIELD 07w01 CHEN: CHEN
+0x40017000 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017000 C FIELD 12w02 DATMPX: DATMPX
+0x40017000 C FIELD 14w02 DATPACK: DATPACK
+0x40017000 C FIELD 16w08 CKOUTDIV: CKOUTDIV
+0x40017000 C FIELD 30w01 CKOUTSRC: CKOUTSRC
+0x40017000 C FIELD 31w01 DFSDMEN: DFSDMEN
+0x40017004 B REGISTER CH0CFGR2 (rw): channel configuration y register
+0x40017004 C FIELD 03w05 DTRBS: DTRBS
+0x40017004 C FIELD 08w24 OFFSET: OFFSET
+0x40017008 B REGISTER CH0AWSCDR (rw): analog watchdog and short-circuit detector register
+0x40017008 C FIELD 00w08 SCDT: SCDT
+0x40017008 C FIELD 12w04 BKSCD: BKSCD
+0x40017008 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017008 C FIELD 22w02 AWFORD: AWFORD
+0x4001700C B REGISTER CH0WDATR (rw): channel watchdog filter data register
+0x4001700C C FIELD 00w16 WDATA: WDATA
+0x40017010 B REGISTER CH0DATINR (rw): channel data input register
+0x40017010 C FIELD 00w16 INDAT0: INDAT0
+0x40017010 C FIELD 16w16 INDAT1: INDAT1
+0x40017014 B REGISTER CH0DLYR (rw): channel y delay register
+0x40017014 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017020 B REGISTER CH1CFGR1 (rw): CH1CFGR1
+0x40017020 C FIELD 00w02 SITP: SITP
+0x40017020 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017020 C FIELD 05w01 SCDEN: SCDEN
+0x40017020 C FIELD 06w01 CKABEN: CKABEN
+0x40017020 C FIELD 07w01 CHEN: CHEN
+0x40017020 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017020 C FIELD 12w02 DATMPX: DATMPX
+0x40017020 C FIELD 14w02 DATPACK: DATPACK
+0x40017024 B REGISTER CH1CFGR2 (rw): CH1CFGR2
+0x40017024 C FIELD 03w05 DTRBS: DTRBS
+0x40017024 C FIELD 08w24 OFFSET: OFFSET
+0x40017028 B REGISTER CH1AWSCDR (rw): CH1AWSCDR
+0x40017028 C FIELD 00w08 SCDT: SCDT
+0x40017028 C FIELD 12w04 BKSCD: BKSCD
+0x40017028 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017028 C FIELD 22w02 AWFORD: AWFORD
+0x4001702C B REGISTER CH1WDATR (rw): CH1WDATR
+0x4001702C C FIELD 00w16 WDATA: WDATA
+0x40017030 B REGISTER CH1DATINR (rw): CH1DATINR
+0x40017030 C FIELD 00w16 INDAT0: INDAT0
+0x40017030 C FIELD 16w16 INDAT1: INDAT1
+0x40017034 B REGISTER CH1DLYR (rw): channel y delay register
+0x40017034 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017040 B REGISTER CH2CFGR1 (rw): CH2CFGR1
+0x40017040 C FIELD 00w02 SITP: SITP
+0x40017040 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017040 C FIELD 05w01 SCDEN: SCDEN
+0x40017040 C FIELD 06w01 CKABEN: CKABEN
+0x40017040 C FIELD 07w01 CHEN: CHEN
+0x40017040 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017040 C FIELD 12w02 DATMPX: DATMPX
+0x40017040 C FIELD 14w02 DATPACK: DATPACK
+0x40017044 B REGISTER CH2CFGR2 (rw): CH2CFGR2
+0x40017044 C FIELD 03w05 DTRBS: DTRBS
+0x40017044 C FIELD 08w24 OFFSET: OFFSET
+0x40017048 B REGISTER CH2AWSCDR (rw): CH2AWSCDR
+0x40017048 C FIELD 00w08 SCDT: SCDT
+0x40017048 C FIELD 12w04 BKSCD: BKSCD
+0x40017048 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017048 C FIELD 22w02 AWFORD: AWFORD
+0x4001704C B REGISTER CH2WDATR (rw): CH2WDATR
+0x4001704C C FIELD 00w16 WDATA: WDATA
+0x40017050 B REGISTER CH2DATINR (rw): CH2DATINR
+0x40017050 C FIELD 00w16 INDAT0: INDAT0
+0x40017050 C FIELD 16w16 INDAT1: INDAT1
+0x40017054 B REGISTER CH2DLYR (rw): channel y delay register
+0x40017054 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017060 B REGISTER CH3CFGR1 (rw): CH3CFGR1
+0x40017060 C FIELD 00w02 SITP: SITP
+0x40017060 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017060 C FIELD 05w01 SCDEN: SCDEN
+0x40017060 C FIELD 06w01 CKABEN: CKABEN
+0x40017060 C FIELD 07w01 CHEN: CHEN
+0x40017060 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017060 C FIELD 12w02 DATMPX: DATMPX
+0x40017060 C FIELD 14w02 DATPACK: DATPACK
+0x40017064 B REGISTER CH3CFGR2 (rw): CH3CFGR2
+0x40017064 C FIELD 03w05 DTRBS: DTRBS
+0x40017064 C FIELD 08w24 OFFSET: OFFSET
+0x40017068 B REGISTER CH3AWSCDR (rw): CH3AWSCDR
+0x40017068 C FIELD 00w08 SCDT: SCDT
+0x40017068 C FIELD 12w04 BKSCD: BKSCD
+0x40017068 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017068 C FIELD 22w02 AWFORD: AWFORD
+0x4001706C B REGISTER CH3WDATR (rw): CH3WDATR
+0x4001706C C FIELD 00w16 WDATA: WDATA
+0x40017070 B REGISTER CH3DATINR (rw): CH3DATINR
+0x40017070 C FIELD 00w16 INDAT0: INDAT0
+0x40017070 C FIELD 16w16 INDAT1: INDAT1
+0x40017074 B REGISTER CH3DLYR (rw): channel y delay register
+0x40017074 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017080 B REGISTER CH4CFGR1 (rw): CH4CFGR1
+0x40017080 C FIELD 00w02 SITP: SITP
+0x40017080 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017080 C FIELD 05w01 SCDEN: SCDEN
+0x40017080 C FIELD 06w01 CKABEN: CKABEN
+0x40017080 C FIELD 07w01 CHEN: CHEN
+0x40017080 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017080 C FIELD 12w02 DATMPX: DATMPX
+0x40017080 C FIELD 14w02 DATPACK: DATPACK
+0x40017084 B REGISTER CH4CFGR2 (rw): CH4CFGR2
+0x40017084 C FIELD 03w05 DTRBS: DTRBS
+0x40017084 C FIELD 08w24 OFFSET: OFFSET
+0x40017088 B REGISTER CH4AWSCDR (rw): CH4AWSCDR
+0x40017088 C FIELD 00w08 SCDT: SCDT
+0x40017088 C FIELD 12w04 BKSCD: BKSCD
+0x40017088 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017088 C FIELD 22w02 AWFORD: AWFORD
+0x4001708C B REGISTER CH4WDATR (rw): CH4WDATR
+0x4001708C C FIELD 00w16 WDATA: WDATA
+0x40017090 B REGISTER CH4DATINR (rw): CH4DATINR
+0x40017090 C FIELD 00w16 INDAT0: INDAT0
+0x40017090 C FIELD 16w16 INDAT1: INDAT1
+0x40017094 B REGISTER CH4DLYR (rw): channel y delay register
+0x40017094 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170A0 B REGISTER CH5CFGR1 (rw): CH5CFGR1
+0x400170A0 C FIELD 00w02 SITP: SITP
+0x400170A0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170A0 C FIELD 05w01 SCDEN: SCDEN
+0x400170A0 C FIELD 06w01 CKABEN: CKABEN
+0x400170A0 C FIELD 07w01 CHEN: CHEN
+0x400170A0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170A0 C FIELD 12w02 DATMPX: DATMPX
+0x400170A0 C FIELD 14w02 DATPACK: DATPACK
+0x400170A4 B REGISTER CH5CFGR2 (rw): CH5CFGR2
+0x400170A4 C FIELD 03w05 DTRBS: DTRBS
+0x400170A4 C FIELD 08w24 OFFSET: OFFSET
+0x400170A8 B REGISTER CH5AWSCDR (rw): CH5AWSCDR
+0x400170A8 C FIELD 00w08 SCDT: SCDT
+0x400170A8 C FIELD 12w04 BKSCD: BKSCD
+0x400170A8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170A8 C FIELD 22w02 AWFORD: AWFORD
+0x400170AC B REGISTER CH5WDATR (rw): CH5WDATR
+0x400170AC C FIELD 00w16 WDATA: WDATA
+0x400170B0 B REGISTER CH5DATINR (rw): CH5DATINR
+0x400170B0 C FIELD 00w16 INDAT0: INDAT0
+0x400170B0 C FIELD 16w16 INDAT1: INDAT1
+0x400170B4 B REGISTER CH5DLYR (rw): channel y delay register
+0x400170B4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170C0 B REGISTER CH6CFGR1 (rw): CH6CFGR1
+0x400170C0 C FIELD 00w02 SITP: SITP
+0x400170C0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170C0 C FIELD 05w01 SCDEN: SCDEN
+0x400170C0 C FIELD 06w01 CKABEN: CKABEN
+0x400170C0 C FIELD 07w01 CHEN: CHEN
+0x400170C0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170C0 C FIELD 12w02 DATMPX: DATMPX
+0x400170C0 C FIELD 14w02 DATPACK: DATPACK
+0x400170C4 B REGISTER CH6CFGR2 (rw): CH6CFGR2
+0x400170C4 C FIELD 03w05 DTRBS: DTRBS
+0x400170C4 C FIELD 08w24 OFFSET: OFFSET
+0x400170C8 B REGISTER CH6AWSCDR (rw): CH6AWSCDR
+0x400170C8 C FIELD 00w08 SCDT: SCDT
+0x400170C8 C FIELD 12w04 BKSCD: BKSCD
+0x400170C8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170C8 C FIELD 22w02 AWFORD: AWFORD
+0x400170CC B REGISTER CH6WDATR (rw): CH6WDATR
+0x400170CC C FIELD 00w16 WDATA: WDATA
+0x400170D0 B REGISTER CH6DATINR (rw): CH6DATINR
+0x400170D0 C FIELD 00w16 INDAT0: INDAT0
+0x400170D0 C FIELD 16w16 INDAT1: INDAT1
+0x400170D4 B REGISTER CH6DLYR (rw): channel y delay register
+0x400170D4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170E0 B REGISTER CH7CFGR1 (rw): CH7CFGR1
+0x400170E0 C FIELD 00w02 SITP: SITP
+0x400170E0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170E0 C FIELD 05w01 SCDEN: SCDEN
+0x400170E0 C FIELD 06w01 CKABEN: CKABEN
+0x400170E0 C FIELD 07w01 CHEN: CHEN
+0x400170E0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170E0 C FIELD 12w02 DATMPX: DATMPX
+0x400170E0 C FIELD 14w02 DATPACK: DATPACK
+0x400170E4 B REGISTER CH7CFGR2 (rw): CH7CFGR2
+0x400170E4 C FIELD 03w05 DTRBS: DTRBS
+0x400170E4 C FIELD 08w24 OFFSET: OFFSET
+0x400170E8 B REGISTER CH7AWSCDR (rw): CH7AWSCDR
+0x400170E8 C FIELD 00w08 SCDT: SCDT
+0x400170E8 C FIELD 12w04 BKSCD: BKSCD
+0x400170E8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170E8 C FIELD 22w02 AWFORD: AWFORD
+0x400170EC B REGISTER CH7WDATR (rw): CH7WDATR
+0x400170EC C FIELD 00w16 WDATA: WDATA
+0x400170F0 B REGISTER CH7DATINR (rw): CH7DATINR
+0x400170F0 C FIELD 00w16 INDAT0: INDAT0
+0x400170F0 C FIELD 16w16 INDAT1: INDAT1
+0x400170F4 B REGISTER CH7DLYR (rw): channel y delay register
+0x400170F4 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017100 B REGISTER DFSDM_FLT0CR1 (rw): control register 1
+0x40017100 C FIELD 00w01 DFEN: DFSDM enable
+0x40017100 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017100 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017100 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017100 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017100 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017100 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017100 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017100 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017100 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017100 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017100 C FIELD 24w03 RCH: Regular channel selection
+0x40017100 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017100 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017104 B REGISTER DFSDM_FLT0CR2 (rw): control register 2
+0x40017104 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017104 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017104 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017104 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017104 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017104 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017104 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017104 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017104 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017108 B REGISTER DFSDM_FLT0ISR (ro): interrupt and status register
+0x40017108 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017108 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017108 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017108 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017108 C FIELD 04w01 AWDF: Analog watchdog
+0x40017108 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017108 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017108 C FIELD 16w08 CKABF: Clock absence flag
+0x40017108 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001710C B REGISTER DFSDM_FLT0ICR (rw): interrupt flag clear register
+0x4001710C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001710C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001710C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001710C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017110 B REGISTER DFSDM_FLT0JCHGR (rw): injected channel group selection register
+0x40017110 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017114 B REGISTER DFSDM_FLT0FCR (rw): filter control register
+0x40017114 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017114 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017114 C FIELD 29w03 FORD: Sinc filter order
+0x40017118 B REGISTER DFSDM_FLT0JDATAR (ro): data register for injected group
+0x40017118 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017118 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001711C B REGISTER DFSDM_FLT0RDATAR (ro): data register for the regular channel
0x4001711C C FIELD 00w03 RDATACH: Regular channel most recently converted
0x4001711C C FIELD 04w01 RPEND: Regular channel pending data
0x4001711C C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017120 B REGISTER DFSDM0_AWHTR (rw): DFSDM analog watchdog high threshold register
+0x40017120 B REGISTER DFSDM_FLT0AWHTR (rw): analog watchdog high threshold register
0x40017120 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
0x40017120 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017124 B REGISTER DFSDM1_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017124 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017124 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017128 B REGISTER DFSDM2_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017128 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017128 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x4001712C B REGISTER DFSDM3_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x4001712C C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x4001712C C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017130 B REGISTER DFSDM0_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017130 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017130 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017134 B REGISTER DFSDM1_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017134 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017134 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017138 B REGISTER DFSDM2_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017138 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017138 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x4001713C B REGISTER DFSDM3_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x4001713C C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x4001713C C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017140 B REGISTER DFSDM0_AWSR (ro): DFSDM analog watchdog status register
-0x40017140 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017140 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017144 B REGISTER DFSDM1_AWSR (ro): DFSDM analog watchdog status register
-0x40017144 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017144 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017148 B REGISTER DFSDM2_AWSR (ro): DFSDM analog watchdog status register
-0x40017148 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017148 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x4001714C B REGISTER DFSDM3_AWSR (ro): DFSDM analog watchdog status register
-0x4001714C C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x4001714C C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017150 B REGISTER DFSDM0_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017150 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017150 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017154 B REGISTER DFSDM1_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017154 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017154 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017158 B REGISTER DFSDM2_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017158 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017158 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x4001715C B REGISTER DFSDM3_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x4001715C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x4001715C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017160 B REGISTER DFSDM0_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017160 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017160 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017164 B REGISTER DFSDM1_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017164 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017164 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017168 B REGISTER DFSDM2_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017168 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017168 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x4001716C B REGISTER DFSDM3_EXMAX (ro): DFSDM Extremes detector maximum register
-0x4001716C C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x4001716C C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017170 B REGISTER DFSDM0_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017170 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017170 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017174 B REGISTER DFSDM1_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017174 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017174 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017178 B REGISTER DFSDM2_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017178 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017178 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x4001717C B REGISTER DFSDM3_EXMIN (ro): DFSDM Extremes detector minimum register
-0x4001717C C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x4001717C C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017180 B REGISTER DFSDM0_CNVTIMR (ro): DFSDM conversion timer register
-0x40017180 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017184 B REGISTER DFSDM1_CNVTIMR (ro): DFSDM conversion timer register
-0x40017184 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017188 B REGISTER DFSDM2_CNVTIMR (ro): DFSDM conversion timer register
-0x40017188 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x4001718C B REGISTER DFSDM3_CNVTIMR (ro): DFSDM conversion timer register
-0x4001718C C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
+0x40017124 B REGISTER DFSDM_FLT0AWLTR (rw): analog watchdog low threshold register
+0x40017124 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017124 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017128 B REGISTER DFSDM_FLT0AWSR (ro): analog watchdog status register
+0x40017128 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017128 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001712C B REGISTER DFSDM_FLT0AWCFR (rw): analog watchdog clear flag register
+0x4001712C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001712C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017130 B REGISTER DFSDM_FLT0EXMAX (ro): Extremes detector maximum register
+0x40017130 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017130 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017134 B REGISTER DFSDM_FLT0EXMIN (ro): Extremes detector minimum register
+0x40017134 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017134 C FIELD 08w24 EXMIN: EXMIN
+0x40017138 B REGISTER DFSDM_FLT0CNVTIMR (ro): conversion timer register
+0x40017138 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017180 B REGISTER DFSDM_FLT1CR1 (rw): control register 1
+0x40017180 C FIELD 00w01 DFEN: DFSDM enable
+0x40017180 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017180 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017180 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017180 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017180 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017180 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017180 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017180 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017180 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017180 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017180 C FIELD 24w03 RCH: Regular channel selection
+0x40017180 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017180 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017184 B REGISTER DFSDM_FLT1CR2 (rw): control register 2
+0x40017184 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017184 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017184 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017184 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017184 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017184 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017184 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017184 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017184 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017188 B REGISTER DFSDM_FLT1ISR (ro): interrupt and status register
+0x40017188 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017188 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017188 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017188 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017188 C FIELD 04w01 AWDF: Analog watchdog
+0x40017188 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017188 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017188 C FIELD 16w08 CKABF: Clock absence flag
+0x40017188 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001718C B REGISTER DFSDM_FLT1ICR (rw): interrupt flag clear register
+0x4001718C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001718C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001718C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001718C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017190 B REGISTER DFSDM_FLT1CHGR (rw): injected channel group selection register
+0x40017190 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017194 B REGISTER DFSDM_FLT1FCR (rw): filter control register
+0x40017194 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017194 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017194 C FIELD 29w03 FORD: Sinc filter order
+0x40017198 B REGISTER DFSDM_FLT1JDATAR (ro): data register for injected group
+0x40017198 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017198 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001719C B REGISTER DFSDM_FLT1RDATAR (ro): data register for the regular channel
+0x4001719C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001719C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001719C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400171A0 B REGISTER DFSDM_FLT1AWHTR (rw): analog watchdog high threshold register
+0x400171A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400171A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400171A4 B REGISTER DFSDM_FLT1AWLTR (rw): analog watchdog low threshold register
+0x400171A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400171A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400171A8 B REGISTER DFSDM_FLT1AWSR (ro): analog watchdog status register
+0x400171A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400171A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400171AC B REGISTER DFSDM_FLT1AWCFR (rw): analog watchdog clear flag register
+0x400171AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400171AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400171B0 B REGISTER DFSDM_FLT1EXMAX (ro): Extremes detector maximum register
+0x400171B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400171B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400171B4 B REGISTER DFSDM_FLT1EXMIN (ro): Extremes detector minimum register
+0x400171B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400171B4 C FIELD 08w24 EXMIN: EXMIN
+0x400171B8 B REGISTER DFSDM_FLT1CNVTIMR (ro): conversion timer register
+0x400171B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017200 B REGISTER DFSDM_FLT2CR1 (rw): control register 1
+0x40017200 C FIELD 00w01 DFEN: DFSDM enable
+0x40017200 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017200 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017200 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017200 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017200 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017200 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017200 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017200 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017200 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017200 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017200 C FIELD 24w03 RCH: Regular channel selection
+0x40017200 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017200 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017204 B REGISTER DFSDM_FLT2CR2 (rw): control register 2
+0x40017204 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017204 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017204 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017204 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017204 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017204 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017204 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017204 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017204 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017208 B REGISTER DFSDM_FLT2ISR (ro): interrupt and status register
+0x40017208 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017208 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017208 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017208 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017208 C FIELD 04w01 AWDF: Analog watchdog
+0x40017208 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017208 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017208 C FIELD 16w08 CKABF: Clock absence flag
+0x40017208 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001720C B REGISTER DFSDM_FLT2ICR (rw): interrupt flag clear register
+0x4001720C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001720C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001720C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001720C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017210 B REGISTER DFSDM_FLT2JCHGR (rw): injected channel group selection register
+0x40017210 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017214 B REGISTER DFSDM_FLT2FCR (rw): filter control register
+0x40017214 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017214 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017214 C FIELD 29w03 FORD: Sinc filter order
+0x40017218 B REGISTER DFSDM_FLT2JDATAR (ro): data register for injected group
+0x40017218 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017218 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001721C B REGISTER DFSDM_FLT2RDATAR (ro): data register for the regular channel
+0x4001721C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001721C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001721C C FIELD 08w24 RDATA: Regular channel conversion data
+0x40017220 B REGISTER DFSDM_FLT2AWHTR (rw): analog watchdog high threshold register
+0x40017220 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x40017220 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x40017224 B REGISTER DFSDM_FLT2AWLTR (rw): analog watchdog low threshold register
+0x40017224 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017224 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017228 B REGISTER DFSDM_FLT2AWSR (ro): analog watchdog status register
+0x40017228 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017228 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001722C B REGISTER DFSDM_FLT2AWCFR (rw): analog watchdog clear flag register
+0x4001722C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001722C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017230 B REGISTER DFSDM_FLT2EXMAX (ro): Extremes detector maximum register
+0x40017230 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017230 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017234 B REGISTER DFSDM_FLT2EXMIN (ro): Extremes detector minimum register
+0x40017234 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017234 C FIELD 08w24 EXMIN: EXMIN
+0x40017238 B REGISTER DFSDM_FLT2CNVTIMR (ro): conversion timer register
+0x40017238 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017280 B REGISTER DFSDM_FLT3CR1 (rw): control register 1
+0x40017280 C FIELD 00w01 DFEN: DFSDM enable
+0x40017280 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017280 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017280 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017280 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017280 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017280 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017280 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017280 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017280 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017280 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017280 C FIELD 24w03 RCH: Regular channel selection
+0x40017280 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017280 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017284 B REGISTER DFSDM_FLT3CR2 (rw): control register 2
+0x40017284 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017284 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017284 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017284 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017284 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017284 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017284 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017284 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017284 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017288 B REGISTER DFSDM_FLT3ISR (ro): interrupt and status register
+0x40017288 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017288 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017288 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017288 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017288 C FIELD 04w01 AWDF: Analog watchdog
+0x40017288 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017288 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017288 C FIELD 16w08 CKABF: Clock absence flag
+0x40017288 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001728C B REGISTER DFSDM_FLT3ICR (rw): interrupt flag clear register
+0x4001728C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001728C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001728C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001728C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017290 B REGISTER DFSDM_FLT3JCHGR (rw): injected channel group selection register
+0x40017290 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017294 B REGISTER DFSDM_FLT3FCR (rw): filter control register
+0x40017294 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017294 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017294 C FIELD 29w03 FORD: Sinc filter order
+0x40017298 B REGISTER DFSDM_FLT3JDATAR (ro): data register for injected group
+0x40017298 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017298 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001729C B REGISTER DFSDM_FLT3RDATAR (ro): data register for the regular channel
+0x4001729C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001729C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001729C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400172A0 B REGISTER DFSDM_FLT3AWHTR (rw): analog watchdog high threshold register
+0x400172A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400172A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400172A4 B REGISTER DFSDM_FLT3AWLTR (rw): analog watchdog low threshold register
+0x400172A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400172A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400172A8 B REGISTER DFSDM_FLT3AWSR (ro): analog watchdog status register
+0x400172A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400172A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400172AC B REGISTER DFSDM_FLT3AWCFR (rw): analog watchdog clear flag register
+0x400172AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400172AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400172B0 B REGISTER DFSDM_FLT3EXMAX (ro): Extremes detector maximum register
+0x400172B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400172B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400172B4 B REGISTER DFSDM_FLT3EXMIN (ro): Extremes detector minimum register
+0x400172B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400172B4 C FIELD 08w24 EXMIN: EXMIN
+0x400172B8 B REGISTER DFSDM_FLT3CNVTIMR (ro): conversion timer register
+0x400172B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
0x40017400 A PERIPHERAL HRTIM_Master
0x40017400 B REGISTER MCR (rw): Master Timer Control Register
0x40017400 C FIELD 00w03 CK_PSC: HRTIM Master Clock prescaler
@@ -17277,6 +17272,7 @@
0x58000404 C FIELD 06w01 PB8FMP: PB(8) Fast Mode Plus
0x58000404 C FIELD 07w01 PB9FMP: PB(9) Fm+
0x58000404 C FIELD 08w01 BOOSTE: Booster Enable
+0x58000404 C FIELD 09w01 BOOSTVDDSEL: Analog switch supply voltage selection
0x58000404 C FIELD 21w03 EPIS: Ethernet PHY Interface Selection
0x58000404 C FIELD 24w01 PA0SO: PA0 Switch Open
0x58000404 C FIELD 25w01 PA1SO: PA1 Switch Open
@@ -17302,6 +17298,19 @@
0x58000414 C FIELD 04w04 EXTI13: EXTI x configuration (x = 12 to 15)
0x58000414 C FIELD 08w04 EXTI14: EXTI x configuration (x = 12 to 15)
0x58000414 C FIELD 12w04 EXTI15: EXTI x configuration (x = 12 to 15)
+0x58000418 B REGISTER CFGR (rw): configuration register
+0x58000418 C FIELD 00w01 CM4L: CM4L
+0x58000418 C FIELD 02w01 PVDL: PVDL
+0x58000418 C FIELD 03w01 FLASHL: FLASHL
+0x58000418 C FIELD 06w01 CM7L: CM7L
+0x58000418 C FIELD 07w01 BKRAML: BKRAML
+0x58000418 C FIELD 09w01 SRAM4L: SRAM4L
+0x58000418 C FIELD 10w01 SRAM3L: SRAM3L
+0x58000418 C FIELD 11w01 SRAM2L: SRAM2L
+0x58000418 C FIELD 12w01 SRAM1L: SRAM1L
+0x58000418 C FIELD 13w01 DTCML: DTCML
+0x58000418 C FIELD 14w01 ITCML: ITCML
+0x58000418 C FIELD 15w01 AXISRAML: AXISRAML
0x58000420 B REGISTER CCCSR (rw): compensation cell control/status register
0x58000420 C FIELD 00w01 EN: enable
0x58000420 C FIELD 01w01 CS: Code selection
@@ -17313,23 +17322,28 @@
0x58000428 B REGISTER CCCR (rw): SYSCFG compensation cell code register
0x58000428 C FIELD 00w04 NCC: NMOS compensation code
0x58000428 C FIELD 04w04 PCC: PMOS compensation code
-0x5800042C B REGISTER PWRCR (rw): SYSCFG Power Control Register
-0x5800042C C FIELD 00w01 ODEN: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode. This bit must be written only in VOS1 voltage scaling mode
+0x5800042C B REGISTER PWRCR (rw): SYSCFG power control register
+0x5800042C C FIELD 00w01 ODEN: Overdrive enable
0x58000524 B REGISTER PKGR (ro): SYSCFG package register
0x58000524 C FIELD 00w04 PKG: Package
0x58000700 B REGISTER UR0 (ro): SYSCFG user register 0
0x58000700 C FIELD 00w01 BKS: Bank Swap
0x58000700 C FIELD 16w08 RDP: Readout protection
-0x58000708 B REGISTER UR2 (rw): SYSCFG user register 2
-0x58000708 C FIELD 00w02 BORH: BOR_LVL Brownout Reset Threshold Level
-0x58000708 C FIELD 16w16 BOOT_ADD0: Boot Address 0
+0x58000704 B REGISTER UR1 (rw): SYSCFG user register 1
+0x58000704 C FIELD 00w01 BCM4: Boot Cortex-M4
+0x58000704 C FIELD 16w01 BCM7: Boot Cortex-M7
+0x58000708 B REGISTER UR2: SYSCFG user register 2
+0x58000708 C FIELD 00w02 BORH (ro): BOR_LVL Brownout Reset Threshold Level
+0x58000708 C FIELD 16w16 BCM7_ADD0 (rw): Cortex-M7 Boot Address 0
0x5800070C B REGISTER UR3 (rw): SYSCFG user register 3
-0x5800070C C FIELD 16w16 BOOT_ADD1: Boot Address 1
-0x58000710 B REGISTER UR4 (ro): SYSCFG user register 4
-0x58000710 C FIELD 16w01 MEPAD_1: Mass Erase Protected Area Disabled for bank 1
+0x5800070C C FIELD 00w16 BCM4_ADD1: Cortex-M4 Boot Address 0
+0x5800070C C FIELD 16w16 BCM7_ADD1: Cortex-M7 Boot Address 1
+0x58000710 B REGISTER UR4: SYSCFG user register 4
+0x58000710 C FIELD 00w16 BCM4_ADD1 (rw): Mass Erase Protected Area Disabled for bank 1
+0x58000710 C FIELD 16w01 MEPAD_1 (ro): Boot Cortex-M4 Address 1
0x58000714 B REGISTER UR5 (ro): SYSCFG user register 5
0x58000714 C FIELD 00w01 MESAD_1: Mass erase secured area disabled for bank 1
-0x58000714 C FIELD 16w08 WRPN_1: Write protection for flash bank 1
+0x58000714 C FIELD 16w08 WRPS_1: Write protection for flash bank 1
0x58000718 B REGISTER UR6 (ro): SYSCFG user register 6
0x58000718 C FIELD 00w12 PA_BEG_1: Protected area start address for bank 1
0x58000718 C FIELD 16w12 PA_END_1: Protected area end address for bank 1
@@ -17340,7 +17354,7 @@
0x58000720 C FIELD 00w01 MEPAD_2: Mass erase protected area disabled for bank 2
0x58000720 C FIELD 16w01 MESAD_2: Mass erase secured area disabled for bank 2
0x58000724 B REGISTER UR9 (ro): SYSCFG user register 9
-0x58000724 C FIELD 00w08 WRPN_2: Write protection for flash bank 2
+0x58000724 C FIELD 00w08 WRPS_2: Write protection for flash bank 2
0x58000724 C FIELD 16w12 PA_BEG_2: Protected area start address for bank 2
0x58000728 B REGISTER UR10 (ro): SYSCFG user register 10
0x58000728 C FIELD 00w12 PA_END_2: Protected area end address for bank 2
@@ -17349,14 +17363,17 @@
0x5800072C C FIELD 00w12 SA_END_2: Secured area end address for bank 2
0x5800072C C FIELD 16w01 IWDG1M: Independent Watchdog 1 mode
0x58000730 B REGISTER UR12 (ro): SYSCFG user register 12
+0x58000730 C FIELD 00w01 IWDG2M: Independent Watchdog 2 mode
0x58000730 C FIELD 16w01 SECURE: Secure mode
0x58000734 B REGISTER UR13 (ro): SYSCFG user register 13
0x58000734 C FIELD 00w02 SDRS: Secured DTCM RAM Size
0x58000734 C FIELD 16w01 D1SBRST: D1 Standby reset
0x58000738 B REGISTER UR14 (rw): SYSCFG user register 14
0x58000738 C FIELD 00w01 D1STPRST: D1 Stop Reset
-0x5800073C B REGISTER UR15 (ro): SYSCFG user register 15
-0x5800073C C FIELD 16w01 FZIWDGSTB: Freeze independent watchdog in Standby mode
+0x58000738 C FIELD 16w01 D2SBRST: D2 Standby Reset
+0x5800073C B REGISTER UR15: SYSCFG user register 15
+0x5800073C C FIELD 00w01 D2STPRST (rw): D2 Stop Reset
+0x5800073C C FIELD 16w01 FZIWDGSTB (ro): Freeze independent watchdog in Standby mode
0x58000740 B REGISTER UR16 (ro): SYSCFG user register 16
0x58000740 C FIELD 00w01 FZIWDGSTP: Freeze independent watchdog in Stop mode
0x58000740 C FIELD 16w01 PKP: Private key programmed
@@ -22195,86 +22212,88 @@
0x58027054 B REGISTER M2FECR (rw): RAMECC monitor 2 failing error code register
0x58027054 C FIELD 00w32 FEC (ro): ECC failing code
0x5C001000 A PERIPHERAL DBGMCU
-0x5C001000 B REGISTER IDC (ro): Identity code
+0x5C001000 B REGISTER IDC (ro): DBGMCU Identity Code Register
0x5C001000 C FIELD 00w12 DEV_ID: Device ID
-0x5C001000 C FIELD 16w16 REV_ID: Revision ID
-0x5C001004 B REGISTER CR (rw): Configuration register
-0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow debug in D1 Sleep mode
-0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow debug in D1 Stop mode
-0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow debug in D1 Standby mode
-0x5C001004 C FIELD 03w01 DBGSLEEP_D2: Allow debug in D2 Sleep mode
-0x5C001004 C FIELD 04w01 DBGSTOP_D2: Allow debug in D2 Stop mode
-0x5C001004 C FIELD 05w01 DBGSTBY_D2: Allow debug in D2 Standby mode
-0x5C001004 C FIELD 20w01 TRACECLKEN: Trace clock enable enable
-0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable enable
-0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable enable
+0x5C001000 C FIELD 16w16 REV_ID: Revision
+0x5C001004 B REGISTER CR (rw): DBGMCU Configuration Register
+0x5C001004 C FIELD 00w01 DBGSLPD1: Allow D1 domain debug in Sleep mode
+0x5C001004 C FIELD 01w01 DBGSTPD1: Allow D1 domain debug in Stop mode
+0x5C001004 C FIELD 02w01 DBGSTBD1: Allow D1 domain debug in Standby mode
+0x5C001004 C FIELD 03w01 DBGSLPD2: Allow D2 domain debug in Sleep mode
+0x5C001004 C FIELD 04w01 DBGSTPD2: Allow D2 domain debug in Stop mode
+0x5C001004 C FIELD 05w01 DBGSTBD2: Allow D2 domain debug in Standby mode
+0x5C001004 C FIELD 07w01 DBGSTPD3: Allow debug in D3 Stop mode
+0x5C001004 C FIELD 08w01 DBGSTBD3: Allow debug in D3 Standby mode
+0x5C001004 C FIELD 20w01 TRACECLKEN: Trace port clock enable
+0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable
+0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable
0x5C001004 C FIELD 28w01 TRGOEN: External trigger output enable
-0x5C001034 B REGISTER APB3FZ1 (rw): APB3 peripheral freeze register
-0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug mode
-0x5C001038 B REGISTER APB3FZ2 (rw): APB3 peripheral freeze register CPU2
-0x5C001038 C FIELD 06w01 WWDG1: WWDG1 stop when Cortex-M4 in debug mode
-0x5C00103C B REGISTER APB1LFZ1 (rw): APB1L peripheral freeze register
-0x5C00103C C FIELD 00w01 TIM2: TIM2 stop in debug mode
-0x5C00103C C FIELD 01w01 TIM3: TIM3 stop in debug mode
-0x5C00103C C FIELD 02w01 TIM4: TIM4 stop in debug mode
-0x5C00103C C FIELD 03w01 TIM5: TIM5 stop in debug mode
-0x5C00103C C FIELD 04w01 TIM6: TIM6 stop in debug mode
-0x5C00103C C FIELD 05w01 TIM7: TIM7 stop in debug mode
-0x5C00103C C FIELD 06w01 TIM12: TIM12 stop in debug mode
-0x5C00103C C FIELD 07w01 TIM13: TIM13 stop in debug mode
-0x5C00103C C FIELD 08w01 TIM14: TIM14 stop in debug mode
-0x5C00103C C FIELD 09w01 LPTIM1: LPTIM1 stop in debug mode
-0x5C00103C C FIELD 11w01 WWDG2: WWDG2 stop when Cortex-M7 in debug mode
-0x5C00103C C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop in debug mode
-0x5C001040 B REGISTER APB1LFZ2 (rw): APB1L peripheral freeze register CPU2
-0x5C001040 C FIELD 00w01 TIM2: TIM2 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 01w01 TIM3: TIM3 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 02w01 TIM4: TIM4 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 03w01 TIM5: TIM5 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 04w01 TIM6: TIM6 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 05w01 TIM7: TIM7 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 06w01 TIM12: TIM12 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 07w01 TIM13: TIM13 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 08w01 TIM14: TIM14 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 09w01 LPTIM1: LPTIM1 stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 11w01 WWDG2: WWDG2 stop in when Cortex-M4 when Cortex-M4 in debug mode
-0x5C001040 C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001040 C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001048 B REGISTER APB2FZ2 (rw): APB2 peripheral freeze register CPU2
-0x5C001048 C FIELD 00w01 TIM1: TIM1 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 01w01 TIM8: TIM8 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 16w01 TIM15: TIM15 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 17w01 TIM16: TIM16 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 18w01 TIM17: TIM17 stop when Cortex-M4 in debug mode
-0x5C001048 C FIELD 29w01 HRTIM: HRTIM stop when Cortex-M4 in debug mode
-0x5C00104C B REGISTER APB2FZ1 (rw): APB2 peripheral freeze register
-0x5C00104C C FIELD 00w01 TIM1: TIM1 stop in debug mode
-0x5C00104C C FIELD 01w01 TIM8: TIM8 stop in debug mode
-0x5C00104C C FIELD 16w01 TIM15: TIM15 stop in debug mode
-0x5C00104C C FIELD 17w01 TIM16: TIM16 stop in debug mode
-0x5C00104C C FIELD 18w01 TIM17: TIM17 stop in debug mode
-0x5C00104C C FIELD 29w01 HRTIM: HRTIM stop in debug mode
-0x5C001054 B REGISTER APB4FZ1 (rw): APB4 peripheral freeze register
-0x5C001054 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop in debug mode
-0x5C001054 C FIELD 09w01 LPTIM2: LPTIM2 stop in debug mode
-0x5C001054 C FIELD 10w01 LPTIM3: LPTIM3 stop in debug mode
-0x5C001054 C FIELD 11w01 LPTIM4: LPTIM4 stop in debug mode
-0x5C001054 C FIELD 12w01 LPTIM5: LPTIM5 stop in debug mode
-0x5C001054 C FIELD 16w01 RTC: RTC stop in debug mode
-0x5C001054 C FIELD 18w01 IWDG1: Independent watchdog for D1 stop in debug mode
-0x5C001054 C FIELD 19w01 IWDG2: Independent watchdog for D2 stop when Cortex-M7 in debug mode
-0x5C001058 B REGISTER APB4FZ2 (rw): APB4 peripheral freeze register CPU2
-0x5C001058 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 09w01 LPTIM2: LPTIM2 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 10w01 LPTIM3: LPTIM3 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 11w01 LPTIM4: LPTIM4 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 12w01 LPTIM5: LPTIM5 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 16w01 RTC: RTC stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 18w01 WDGLSD1: LS watchdog for D1 stop when Cortex-M4 in debug mode
-0x5C001058 C FIELD 19w01 WDGLSD2: LS watchdog for D2 stop when Cortex-M4 in debug mode
+0x5C001034 B REGISTER APB3FZ1 (rw): DBGMCU APB3 peripheral freeze register CPU1
+0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C001038 B REGISTER APB3FZ2 (rw): DBGMCU APB3 peripheral freeze register CPU2
+0x5C001038 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C00103C B REGISTER APB1LFZ1 (rw): DBGMCU APB1L peripheral freeze register
+0x5C00103C C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C00103C C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C00103C C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C00103C C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C00103C C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C00103C C FIELD 05w01 DBG_TIM7: TIM7 stop in debug
+0x5C00103C C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C00103C C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C00103C C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C00103C C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C00103C C FIELD 11w01 DBG_WWDG2: WWDG2 stop in debug
+0x5C00103C C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C00103C C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C00103C C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C001040 B REGISTER APB1LFZ2 (rw): DBGMCU APB1L peripheral freeze register CPU2
+0x5C001040 C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C001040 C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C001040 C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C001040 C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C001040 C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C001040 C FIELD 05w01 DBG_TIM7: TIM4 stop in debug
+0x5C001040 C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C001040 C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C001040 C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C001040 C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C001040 C FIELD 11w01 DBG_WWDG2: WWDG2 stop in debug
+0x5C001040 C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C001040 C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C001040 C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C00104C B REGISTER APB2FZ1 (rw): DBGMCU APB2 peripheral freeze register
+0x5C00104C C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C00104C C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C00104C C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C00104C C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C00104C C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C00104C C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001050 B REGISTER APB2FZ2 (rw): DBGMCU APB2 peripheral freeze register CPU2
+0x5C001050 C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C001050 C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C001050 C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C001050 C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C001050 C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C001050 C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001054 B REGISTER APB4FZ1 (rw): DBGMCU APB4 peripheral freeze register
+0x5C001054 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001054 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001054 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001054 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001054 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001054 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001054 C FIELD 18w01 DBG_WDGLSD1: Independent watchdog for D1 stop in debug
+0x5C001054 C FIELD 19w01 DBG_WDGLSD2: Independent watchdog for D2 stop in debug
+0x5C001058 B REGISTER APB4FZ2 (rw): DBGMCU APB4 peripheral freeze register CPU2
+0x5C001058 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001058 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001058 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001058 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001058 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001058 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001058 C FIELD 18w01 DBG_WDGLSD1: LS watchdog for D1 stop in debug
+0x5C001058 C FIELD 19w01 DBG_WDGLSD2: LS watchdog for D2 stop in debug
0xE000E008 A PERIPHERAL SCB_ACTRL
0xE000E008 B REGISTER ACTRL (rw): Auxiliary control register
0xE000E008 C FIELD 02w01 DISFOLD: DISFOLD
@@ -22575,7 +22594,7 @@
0xE000ED20 B REGISTER SHPR3 (rw): System handler priority registers
0xE000ED20 C FIELD 16w08 PRI_14: Priority of system handler 14
0xE000ED20 C FIELD 24w08 PRI_15: Priority of system handler 15
-0xE000ED24 B REGISTER SHCRS (rw): System handler control and state register
+0xE000ED24 B REGISTER SHCSR (rw): System handler control and state register
0xE000ED24 C FIELD 00w01 MEMFAULTACT: Memory management fault exception active bit
0xE000ED24 C FIELD 01w01 BUSFAULTACT: Bus fault exception active bit
0xE000ED24 C FIELD 03w01 USGFAULTACT: Usage fault exception active bit
@@ -22652,7 +22671,7 @@
0xE000ED90 C FIELD 00w01 SEPARATE: Separate flag
0xE000ED90 C FIELD 08w08 DREGION: Number of MPU data regions
0xE000ED90 C FIELD 16w08 IREGION: Number of MPU instruction regions
-0xE000ED94 B REGISTER MPU_CTRL (ro): MPU control register
+0xE000ED94 B REGISTER MPU_CTRL (rw): MPU control register
0xE000ED94 C FIELD 00w01 ENABLE: Enables the MPU
0xE000ED94 C FIELD 01w01 HFNMIENA: Enables the operation of MPU during hard fault
0xE000ED94 C FIELD 02w01 PRIVDEFENA: Enable priviliged software access to default memory map
Raw
stm32h753.mmap.diff
--- ./mmaps_old/stm32h753.mmap 2021-06-06 20:39:56.400000000 -0500
+++ mmaps_new/stm32h753.mmap 2021-06-06 20:39:04.730000000 -0500
@@ -5517,498 +5517,493 @@
0x40016048 C FIELD 24w03 DLYM4L: Delay line for first microphone of pair 4
0x40016048 C FIELD 28w03 DLYM4R: Delay line for second microphone of pair 4
0x40017000 A PERIPHERAL DFSDM
-0x40017000 B REGISTER DFSDM_CHCFG0R1 (rw): DFSDM channel configuration 0 register 1
-0x40017000 C FIELD 00w02 SITP: Serial interface type for channel 0
-0x40017000 C FIELD 02w02 SPICKSEL: SPI clock select for channel 0
-0x40017000 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 0
-0x40017000 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 0
-0x40017000 C FIELD 07w01 CHEN: Channel 0 enable
-0x40017000 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017000 C FIELD 12w02 DATMPX: Input data multiplexer for channel 0
-0x40017000 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017000 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017000 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017000 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017004 B REGISTER DFSDM_CHCFG1R1 (rw): DFSDM channel configuration 1 register 1
-0x40017004 C FIELD 00w02 SITP: Serial interface type for channel 1
-0x40017004 C FIELD 02w02 SPICKSEL: SPI clock select for channel 1
-0x40017004 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 1
-0x40017004 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 1
-0x40017004 C FIELD 07w01 CHEN: Channel 1 enable
-0x40017004 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017004 C FIELD 12w02 DATMPX: Input data multiplexer for channel 1
-0x40017004 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017004 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017004 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017004 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017008 B REGISTER DFSDM_CHCFG2R1 (rw): DFSDM channel configuration 2 register 1
-0x40017008 C FIELD 00w02 SITP: Serial interface type for channel 2
-0x40017008 C FIELD 02w02 SPICKSEL: SPI clock select for channel 2
-0x40017008 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 2
-0x40017008 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 2
-0x40017008 C FIELD 07w01 CHEN: Channel 2 enable
-0x40017008 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017008 C FIELD 12w02 DATMPX: Input data multiplexer for channel 2
-0x40017008 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017008 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017008 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017008 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001700C B REGISTER DFSDM_CHCFG3R1 (rw): DFSDM channel configuration 3 register 1
-0x4001700C C FIELD 00w02 SITP: Serial interface type for channel 3
-0x4001700C C FIELD 02w02 SPICKSEL: SPI clock select for channel 3
-0x4001700C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 3
-0x4001700C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 3
-0x4001700C C FIELD 07w01 CHEN: Channel 3 enable
-0x4001700C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001700C C FIELD 12w02 DATMPX: Input data multiplexer for channel 3
-0x4001700C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001700C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001700C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001700C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017010 B REGISTER DFSDM_CHCFG4R1 (rw): DFSDM channel configuration 4 register 1
-0x40017010 C FIELD 00w02 SITP: Serial interface type for channel 4
-0x40017010 C FIELD 02w02 SPICKSEL: SPI clock select for channel 4
-0x40017010 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 4
-0x40017010 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 4
-0x40017010 C FIELD 07w01 CHEN: Channel 4 enable
-0x40017010 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017010 C FIELD 12w02 DATMPX: Input data multiplexer for channel 4
-0x40017010 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017010 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017010 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017010 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017014 B REGISTER DFSDM_CHCFG5R1 (rw): DFSDM channel configuration 5 register 1
-0x40017014 C FIELD 00w02 SITP: Serial interface type for channel 5
-0x40017014 C FIELD 02w02 SPICKSEL: SPI clock select for channel 5
-0x40017014 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 5
-0x40017014 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 5
-0x40017014 C FIELD 07w01 CHEN: Channel 5 enable
-0x40017014 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017014 C FIELD 12w02 DATMPX: Input data multiplexer for channel 5
-0x40017014 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017014 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017014 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017014 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017018 B REGISTER DFSDM_CHCFG6R1 (rw): DFSDM channel configuration 6 register 1
-0x40017018 C FIELD 00w02 SITP: Serial interface type for channel 6
-0x40017018 C FIELD 02w02 SPICKSEL: SPI clock select for channel 6
-0x40017018 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 6
-0x40017018 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 6
-0x40017018 C FIELD 07w01 CHEN: Channel 6 enable
-0x40017018 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017018 C FIELD 12w02 DATMPX: Input data multiplexer for channel 6
-0x40017018 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017018 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017018 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017018 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001701C B REGISTER DFSDM_CHCFG7R1 (rw): DFSDM channel configuration 7 register 1
-0x4001701C C FIELD 00w02 SITP: Serial interface type for channel 7
-0x4001701C C FIELD 02w02 SPICKSEL: SPI clock select for channel 7
-0x4001701C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 7
-0x4001701C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 7
-0x4001701C C FIELD 07w01 CHEN: Channel 7 enable
-0x4001701C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001701C C FIELD 12w02 DATMPX: Input data multiplexer for channel 7
-0x4001701C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001701C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001701C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001701C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017020 B REGISTER DFSDM_CHCFG0R2 (rw): DFSDM channel configuration 0 register 2
-0x40017020 C FIELD 03w05 DTRBS: Data right bit-shift for channel 0
-0x40017020 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 0
-0x40017024 B REGISTER DFSDM_CHCFG1R2 (rw): DFSDM channel configuration 1 register 2
-0x40017024 C FIELD 03w05 DTRBS: Data right bit-shift for channel 1
-0x40017024 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 1
-0x40017028 B REGISTER DFSDM_CHCFG2R2 (rw): DFSDM channel configuration 2 register 2
-0x40017028 C FIELD 03w05 DTRBS: Data right bit-shift for channel 2
-0x40017028 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 2
-0x4001702C B REGISTER DFSDM_CHCFG3R2 (rw): DFSDM channel configuration 3 register 2
-0x4001702C C FIELD 03w05 DTRBS: Data right bit-shift for channel 3
-0x4001702C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 3
-0x40017030 B REGISTER DFSDM_CHCFG4R2 (rw): DFSDM channel configuration 4 register 2
-0x40017030 C FIELD 03w05 DTRBS: Data right bit-shift for channel 4
-0x40017030 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 4
-0x40017034 B REGISTER DFSDM_CHCFG5R2 (rw): DFSDM channel configuration 5 register 2
-0x40017034 C FIELD 03w05 DTRBS: Data right bit-shift for channel 5
-0x40017034 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 5
-0x40017038 B REGISTER DFSDM_CHCFG6R2 (rw): DFSDM channel configuration 6 register 2
-0x40017038 C FIELD 03w05 DTRBS: Data right bit-shift for channel 6
-0x40017038 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 6
-0x4001703C B REGISTER DFSDM_CHCFG7R2 (rw): DFSDM channel configuration 7 register 2
-0x4001703C C FIELD 03w05 DTRBS: Data right bit-shift for channel 7
-0x4001703C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 7
-0x40017040 B REGISTER DFSDM_AWSCD0R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017040 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 0
-0x40017040 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 0
-0x40017040 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 0
-0x40017040 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 0
-0x40017044 B REGISTER DFSDM_AWSCD1R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017044 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 1
-0x40017044 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 1
-0x40017044 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 1
-0x40017044 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 1
-0x40017048 B REGISTER DFSDM_AWSCD2R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017048 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 2
-0x40017048 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 2
-0x40017048 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 2
-0x40017048 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 2
-0x4001704C B REGISTER DFSDM_AWSCD3R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001704C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 3
-0x4001704C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 3
-0x4001704C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 3
-0x4001704C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 3
-0x40017050 B REGISTER DFSDM_AWSCD4R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017050 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 4
-0x40017050 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 4
-0x40017050 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 4
-0x40017050 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 4
-0x40017054 B REGISTER DFSDM_AWSCD5R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017054 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 5
-0x40017054 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 5
-0x40017054 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 5
-0x40017054 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 5
-0x40017058 B REGISTER DFSDM_AWSCD6R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017058 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 6
-0x40017058 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 6
-0x40017058 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 6
-0x40017058 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 6
-0x4001705C B REGISTER DFSDM_AWSCD7R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001705C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 7
-0x4001705C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 7
-0x4001705C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 7
-0x4001705C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 7
-0x40017060 B REGISTER DFSDM_CHWDAT0R (ro): DFSDM channel watchdog filter data register
-0x40017060 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017064 B REGISTER DFSDM_CHWDAT1R (ro): DFSDM channel watchdog filter data register
-0x40017064 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017068 B REGISTER DFSDM_CHWDAT2R (ro): DFSDM channel watchdog filter data register
-0x40017068 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001706C B REGISTER DFSDM_CHWDAT3R (ro): DFSDM channel watchdog filter data register
-0x4001706C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017070 B REGISTER DFSDM_CHWDAT4R (ro): DFSDM channel watchdog filter data register
-0x40017070 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017074 B REGISTER DFSDM_CHWDAT5R (ro): DFSDM channel watchdog filter data register
-0x40017074 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017078 B REGISTER DFSDM_CHWDAT6R (ro): DFSDM channel watchdog filter data register
-0x40017078 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001707C B REGISTER DFSDM_CHWDAT7R (ro): DFSDM channel watchdog filter data register
-0x4001707C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017080 B REGISTER DFSDM_CHDATIN0R (rw): DFSDM channel data input register
-0x40017080 C FIELD 00w16 INDAT0: Input data for channel 0
-0x40017080 C FIELD 16w16 INDAT1: Input data for channel 1
-0x40017084 B REGISTER DFSDM_CHDATIN1R (rw): DFSDM channel data input register
-0x40017084 C FIELD 00w16 INDAT0: Input data for channel 1
-0x40017084 C FIELD 16w16 INDAT1: Input data for channel 2
-0x40017088 B REGISTER DFSDM_CHDATIN2R (rw): DFSDM channel data input register
-0x40017088 C FIELD 00w16 INDAT0: Input data for channel 2
-0x40017088 C FIELD 16w16 INDAT1: Input data for channel 3
-0x4001708C B REGISTER DFSDM_CHDATIN3R (rw): DFSDM channel data input register
-0x4001708C C FIELD 00w16 INDAT0: Input data for channel 3
-0x4001708C C FIELD 16w16 INDAT1: Input data for channel 4
-0x40017090 B REGISTER DFSDM_CHDATIN4R (rw): DFSDM channel data input register
-0x40017090 C FIELD 00w16 INDAT0: Input data for channel 4
-0x40017090 C FIELD 16w16 INDAT1: Input data for channel 5
-0x40017094 B REGISTER DFSDM_CHDATIN5R (rw): DFSDM channel data input register
-0x40017094 C FIELD 00w16 INDAT0: Input data for channel 5
-0x40017094 C FIELD 16w16 INDAT1: Input data for channel 6
-0x40017098 B REGISTER DFSDM_CHDATIN6R (rw): DFSDM channel data input register
-0x40017098 C FIELD 00w16 INDAT0: Input data for channel 6
-0x40017098 C FIELD 16w16 INDAT1: Input data for channel 7
-0x4001709C B REGISTER DFSDM_CHDATIN7R (rw): DFSDM channel data input register
-0x4001709C C FIELD 00w16 INDAT0: Input data for channel 7
-0x4001709C C FIELD 16w16 INDAT1: Input data for channel 8
-0x400170A0 B REGISTER DFSDM0_CR1 (rw): DFSDM control register 1
-0x400170A0 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A0 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A0 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A0 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A0 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A0 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A0 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A0 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A0 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A0 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A0 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A0 C FIELD 24w03 RCH: Regular channel selection
-0x400170A0 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A0 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A4 B REGISTER DFSDM1_CR1 (rw): DFSDM control register 1
-0x400170A4 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A4 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A4 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A4 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A4 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A4 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A4 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A4 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A4 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A4 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A4 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A4 C FIELD 24w03 RCH: Regular channel selection
-0x400170A4 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A4 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A8 B REGISTER DFSDM2_CR1 (rw): DFSDM control register 1
-0x400170A8 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A8 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A8 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A8 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A8 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A8 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A8 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A8 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A8 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A8 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A8 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A8 C FIELD 24w03 RCH: Regular channel selection
-0x400170A8 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A8 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170AC B REGISTER DFSDM3_CR1 (rw): DFSDM control register 1
-0x400170AC C FIELD 00w01 DFEN: DFSDM enable
-0x400170AC C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170AC C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170AC C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170AC C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170AC C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170AC C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170AC C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170AC C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170AC C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170AC C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170AC C FIELD 24w03 RCH: Regular channel selection
-0x400170AC C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170AC C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170B0 B REGISTER DFSDM0_CR2 (rw): DFSDM control register 2
-0x400170B0 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B0 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B0 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B0 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B0 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B0 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B0 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B0 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B0 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B4 B REGISTER DFSDM1_CR2 (rw): DFSDM control register 2
-0x400170B4 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B4 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B4 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B4 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B4 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B4 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B4 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B4 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B4 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B8 B REGISTER DFSDM2_CR2 (rw): DFSDM control register 2
-0x400170B8 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B8 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B8 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B8 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B8 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B8 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B8 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B8 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B8 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170BC B REGISTER DFSDM3_CR2 (rw): DFSDM control register 2
-0x400170BC C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170BC C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170BC C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170BC C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170BC C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170BC C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170BC C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170BC C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170BC C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170C0 B REGISTER DFSDM0_ISR (ro): DFSDM interrupt and status register
-0x400170C0 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C0 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C0 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C0 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C0 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C0 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C0 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C0 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C0 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C4 B REGISTER DFSDM1_ISR (ro): DFSDM interrupt and status register
-0x400170C4 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C4 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C4 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C4 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C4 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C4 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C4 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C4 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C4 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C8 B REGISTER DFSDM2_ISR (ro): DFSDM interrupt and status register
-0x400170C8 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C8 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C8 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C8 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C8 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C8 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C8 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C8 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C8 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170CC B REGISTER DFSDM3_ISR (ro): DFSDM interrupt and status register
-0x400170CC C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170CC C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170CC C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170CC C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170CC C FIELD 04w01 AWDF: Analog watchdog
-0x400170CC C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170CC C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170CC C FIELD 16w08 CKABF: Clock absence flag
-0x400170CC C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170D0 B REGISTER DFSDM0_ICR (rw): DFSDM interrupt flag clear register
-0x400170D0 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D0 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D0 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D0 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D4 B REGISTER DFSDM1_ICR (rw): DFSDM interrupt flag clear register
-0x400170D4 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D4 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D4 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D4 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D8 B REGISTER DFSDM2_ICR (rw): DFSDM interrupt flag clear register
-0x400170D8 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D8 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D8 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D8 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170DC B REGISTER DFSDM3_ICR (rw): DFSDM interrupt flag clear register
-0x400170DC C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170DC C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170DC C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170DC C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170E0 B REGISTER DFSDM0_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E0 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E4 B REGISTER DFSDM1_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E4 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E8 B REGISTER DFSDM2_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E8 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170EC B REGISTER DFSDM3_JCHGR (rw): DFSDM injected channel group selection register
-0x400170EC C FIELD 00w08 JCHG: Injected channel group selection
-0x400170F0 B REGISTER DFSDM0_FCR (rw): DFSDM filter control register
-0x400170F0 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F0 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F0 C FIELD 29w03 FORD: Sinc filter order
-0x400170F4 B REGISTER DFSDM1_FCR (rw): DFSDM filter control register
-0x400170F4 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F4 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F4 C FIELD 29w03 FORD: Sinc filter order
-0x400170F8 B REGISTER DFSDM2_FCR (rw): DFSDM filter control register
-0x400170F8 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F8 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F8 C FIELD 29w03 FORD: Sinc filter order
-0x400170FC B REGISTER DFSDM3_FCR (rw): DFSDM filter control register
-0x400170FC C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170FC C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170FC C FIELD 29w03 FORD: Sinc filter order
-0x40017100 B REGISTER DFSDM0_JDATAR (ro): DFSDM data register for injected group
-0x40017100 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017100 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017104 B REGISTER DFSDM1_JDATAR (ro): DFSDM data register for injected group
-0x40017104 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017104 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017108 B REGISTER DFSDM2_JDATAR (ro): DFSDM data register for injected group
-0x40017108 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017108 C FIELD 08w24 JDATA: Injected group conversion data
-0x4001710C B REGISTER DFSDM3_JDATAR (ro): DFSDM data register for injected group
-0x4001710C C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x4001710C C FIELD 08w24 JDATA: Injected group conversion data
-0x40017110 B REGISTER DFSDM0_RDATAR (ro): DFSDM data register for the regular channel
-0x40017110 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017110 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017110 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017114 B REGISTER DFSDM1_RDATAR (ro): DFSDM data register for the regular channel
-0x40017114 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017114 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017114 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017118 B REGISTER DFSDM2_RDATAR (ro): DFSDM data register for the regular channel
-0x40017118 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017118 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017118 C FIELD 08w24 RDATA: Regular channel conversion data
-0x4001711C B REGISTER DFSDM3_RDATAR (ro): DFSDM data register for the regular channel
+0x40017000 B REGISTER CH0CFGR1 (rw): channel configuration y register
+0x40017000 C FIELD 00w02 SITP: SITP
+0x40017000 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017000 C FIELD 05w01 SCDEN: SCDEN
+0x40017000 C FIELD 06w01 CKABEN: CKABEN
+0x40017000 C FIELD 07w01 CHEN: CHEN
+0x40017000 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017000 C FIELD 12w02 DATMPX: DATMPX
+0x40017000 C FIELD 14w02 DATPACK: DATPACK
+0x40017000 C FIELD 16w08 CKOUTDIV: CKOUTDIV
+0x40017000 C FIELD 30w01 CKOUTSRC: CKOUTSRC
+0x40017000 C FIELD 31w01 DFSDMEN: DFSDMEN
+0x40017004 B REGISTER CH0CFGR2 (rw): channel configuration y register
+0x40017004 C FIELD 03w05 DTRBS: DTRBS
+0x40017004 C FIELD 08w24 OFFSET: OFFSET
+0x40017008 B REGISTER CH0AWSCDR (rw): analog watchdog and short-circuit detector register
+0x40017008 C FIELD 00w08 SCDT: SCDT
+0x40017008 C FIELD 12w04 BKSCD: BKSCD
+0x40017008 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017008 C FIELD 22w02 AWFORD: AWFORD
+0x4001700C B REGISTER CH0WDATR (rw): channel watchdog filter data register
+0x4001700C C FIELD 00w16 WDATA: WDATA
+0x40017010 B REGISTER CH0DATINR (rw): channel data input register
+0x40017010 C FIELD 00w16 INDAT0: INDAT0
+0x40017010 C FIELD 16w16 INDAT1: INDAT1
+0x40017014 B REGISTER CH0DLYR (rw): channel y delay register
+0x40017014 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017020 B REGISTER CH1CFGR1 (rw): CH1CFGR1
+0x40017020 C FIELD 00w02 SITP: SITP
+0x40017020 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017020 C FIELD 05w01 SCDEN: SCDEN
+0x40017020 C FIELD 06w01 CKABEN: CKABEN
+0x40017020 C FIELD 07w01 CHEN: CHEN
+0x40017020 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017020 C FIELD 12w02 DATMPX: DATMPX
+0x40017020 C FIELD 14w02 DATPACK: DATPACK
+0x40017024 B REGISTER CH1CFGR2 (rw): CH1CFGR2
+0x40017024 C FIELD 03w05 DTRBS: DTRBS
+0x40017024 C FIELD 08w24 OFFSET: OFFSET
+0x40017028 B REGISTER CH1AWSCDR (rw): CH1AWSCDR
+0x40017028 C FIELD 00w08 SCDT: SCDT
+0x40017028 C FIELD 12w04 BKSCD: BKSCD
+0x40017028 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017028 C FIELD 22w02 AWFORD: AWFORD
+0x4001702C B REGISTER CH1WDATR (rw): CH1WDATR
+0x4001702C C FIELD 00w16 WDATA: WDATA
+0x40017030 B REGISTER CH1DATINR (rw): CH1DATINR
+0x40017030 C FIELD 00w16 INDAT0: INDAT0
+0x40017030 C FIELD 16w16 INDAT1: INDAT1
+0x40017034 B REGISTER CH1DLYR (rw): channel y delay register
+0x40017034 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017040 B REGISTER CH2CFGR1 (rw): CH2CFGR1
+0x40017040 C FIELD 00w02 SITP: SITP
+0x40017040 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017040 C FIELD 05w01 SCDEN: SCDEN
+0x40017040 C FIELD 06w01 CKABEN: CKABEN
+0x40017040 C FIELD 07w01 CHEN: CHEN
+0x40017040 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017040 C FIELD 12w02 DATMPX: DATMPX
+0x40017040 C FIELD 14w02 DATPACK: DATPACK
+0x40017044 B REGISTER CH2CFGR2 (rw): CH2CFGR2
+0x40017044 C FIELD 03w05 DTRBS: DTRBS
+0x40017044 C FIELD 08w24 OFFSET: OFFSET
+0x40017048 B REGISTER CH2AWSCDR (rw): CH2AWSCDR
+0x40017048 C FIELD 00w08 SCDT: SCDT
+0x40017048 C FIELD 12w04 BKSCD: BKSCD
+0x40017048 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017048 C FIELD 22w02 AWFORD: AWFORD
+0x4001704C B REGISTER CH2WDATR (rw): CH2WDATR
+0x4001704C C FIELD 00w16 WDATA: WDATA
+0x40017050 B REGISTER CH2DATINR (rw): CH2DATINR
+0x40017050 C FIELD 00w16 INDAT0: INDAT0
+0x40017050 C FIELD 16w16 INDAT1: INDAT1
+0x40017054 B REGISTER CH2DLYR (rw): channel y delay register
+0x40017054 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017060 B REGISTER CH3CFGR1 (rw): CH3CFGR1
+0x40017060 C FIELD 00w02 SITP: SITP
+0x40017060 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017060 C FIELD 05w01 SCDEN: SCDEN
+0x40017060 C FIELD 06w01 CKABEN: CKABEN
+0x40017060 C FIELD 07w01 CHEN: CHEN
+0x40017060 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017060 C FIELD 12w02 DATMPX: DATMPX
+0x40017060 C FIELD 14w02 DATPACK: DATPACK
+0x40017064 B REGISTER CH3CFGR2 (rw): CH3CFGR2
+0x40017064 C FIELD 03w05 DTRBS: DTRBS
+0x40017064 C FIELD 08w24 OFFSET: OFFSET
+0x40017068 B REGISTER CH3AWSCDR (rw): CH3AWSCDR
+0x40017068 C FIELD 00w08 SCDT: SCDT
+0x40017068 C FIELD 12w04 BKSCD: BKSCD
+0x40017068 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017068 C FIELD 22w02 AWFORD: AWFORD
+0x4001706C B REGISTER CH3WDATR (rw): CH3WDATR
+0x4001706C C FIELD 00w16 WDATA: WDATA
+0x40017070 B REGISTER CH3DATINR (rw): CH3DATINR
+0x40017070 C FIELD 00w16 INDAT0: INDAT0
+0x40017070 C FIELD 16w16 INDAT1: INDAT1
+0x40017074 B REGISTER CH3DLYR (rw): channel y delay register
+0x40017074 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017080 B REGISTER CH4CFGR1 (rw): CH4CFGR1
+0x40017080 C FIELD 00w02 SITP: SITP
+0x40017080 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017080 C FIELD 05w01 SCDEN: SCDEN
+0x40017080 C FIELD 06w01 CKABEN: CKABEN
+0x40017080 C FIELD 07w01 CHEN: CHEN
+0x40017080 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017080 C FIELD 12w02 DATMPX: DATMPX
+0x40017080 C FIELD 14w02 DATPACK: DATPACK
+0x40017084 B REGISTER CH4CFGR2 (rw): CH4CFGR2
+0x40017084 C FIELD 03w05 DTRBS: DTRBS
+0x40017084 C FIELD 08w24 OFFSET: OFFSET
+0x40017088 B REGISTER CH4AWSCDR (rw): CH4AWSCDR
+0x40017088 C FIELD 00w08 SCDT: SCDT
+0x40017088 C FIELD 12w04 BKSCD: BKSCD
+0x40017088 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017088 C FIELD 22w02 AWFORD: AWFORD
+0x4001708C B REGISTER CH4WDATR (rw): CH4WDATR
+0x4001708C C FIELD 00w16 WDATA: WDATA
+0x40017090 B REGISTER CH4DATINR (rw): CH4DATINR
+0x40017090 C FIELD 00w16 INDAT0: INDAT0
+0x40017090 C FIELD 16w16 INDAT1: INDAT1
+0x40017094 B REGISTER CH4DLYR (rw): channel y delay register
+0x40017094 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170A0 B REGISTER CH5CFGR1 (rw): CH5CFGR1
+0x400170A0 C FIELD 00w02 SITP: SITP
+0x400170A0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170A0 C FIELD 05w01 SCDEN: SCDEN
+0x400170A0 C FIELD 06w01 CKABEN: CKABEN
+0x400170A0 C FIELD 07w01 CHEN: CHEN
+0x400170A0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170A0 C FIELD 12w02 DATMPX: DATMPX
+0x400170A0 C FIELD 14w02 DATPACK: DATPACK
+0x400170A4 B REGISTER CH5CFGR2 (rw): CH5CFGR2
+0x400170A4 C FIELD 03w05 DTRBS: DTRBS
+0x400170A4 C FIELD 08w24 OFFSET: OFFSET
+0x400170A8 B REGISTER CH5AWSCDR (rw): CH5AWSCDR
+0x400170A8 C FIELD 00w08 SCDT: SCDT
+0x400170A8 C FIELD 12w04 BKSCD: BKSCD
+0x400170A8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170A8 C FIELD 22w02 AWFORD: AWFORD
+0x400170AC B REGISTER CH5WDATR (rw): CH5WDATR
+0x400170AC C FIELD 00w16 WDATA: WDATA
+0x400170B0 B REGISTER CH5DATINR (rw): CH5DATINR
+0x400170B0 C FIELD 00w16 INDAT0: INDAT0
+0x400170B0 C FIELD 16w16 INDAT1: INDAT1
+0x400170B4 B REGISTER CH5DLYR (rw): channel y delay register
+0x400170B4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170C0 B REGISTER CH6CFGR1 (rw): CH6CFGR1
+0x400170C0 C FIELD 00w02 SITP: SITP
+0x400170C0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170C0 C FIELD 05w01 SCDEN: SCDEN
+0x400170C0 C FIELD 06w01 CKABEN: CKABEN
+0x400170C0 C FIELD 07w01 CHEN: CHEN
+0x400170C0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170C0 C FIELD 12w02 DATMPX: DATMPX
+0x400170C0 C FIELD 14w02 DATPACK: DATPACK
+0x400170C4 B REGISTER CH6CFGR2 (rw): CH6CFGR2
+0x400170C4 C FIELD 03w05 DTRBS: DTRBS
+0x400170C4 C FIELD 08w24 OFFSET: OFFSET
+0x400170C8 B REGISTER CH6AWSCDR (rw): CH6AWSCDR
+0x400170C8 C FIELD 00w08 SCDT: SCDT
+0x400170C8 C FIELD 12w04 BKSCD: BKSCD
+0x400170C8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170C8 C FIELD 22w02 AWFORD: AWFORD
+0x400170CC B REGISTER CH6WDATR (rw): CH6WDATR
+0x400170CC C FIELD 00w16 WDATA: WDATA
+0x400170D0 B REGISTER CH6DATINR (rw): CH6DATINR
+0x400170D0 C FIELD 00w16 INDAT0: INDAT0
+0x400170D0 C FIELD 16w16 INDAT1: INDAT1
+0x400170D4 B REGISTER CH6DLYR (rw): channel y delay register
+0x400170D4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170E0 B REGISTER CH7CFGR1 (rw): CH7CFGR1
+0x400170E0 C FIELD 00w02 SITP: SITP
+0x400170E0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170E0 C FIELD 05w01 SCDEN: SCDEN
+0x400170E0 C FIELD 06w01 CKABEN: CKABEN
+0x400170E0 C FIELD 07w01 CHEN: CHEN
+0x400170E0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170E0 C FIELD 12w02 DATMPX: DATMPX
+0x400170E0 C FIELD 14w02 DATPACK: DATPACK
+0x400170E4 B REGISTER CH7CFGR2 (rw): CH7CFGR2
+0x400170E4 C FIELD 03w05 DTRBS: DTRBS
+0x400170E4 C FIELD 08w24 OFFSET: OFFSET
+0x400170E8 B REGISTER CH7AWSCDR (rw): CH7AWSCDR
+0x400170E8 C FIELD 00w08 SCDT: SCDT
+0x400170E8 C FIELD 12w04 BKSCD: BKSCD
+0x400170E8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170E8 C FIELD 22w02 AWFORD: AWFORD
+0x400170EC B REGISTER CH7WDATR (rw): CH7WDATR
+0x400170EC C FIELD 00w16 WDATA: WDATA
+0x400170F0 B REGISTER CH7DATINR (rw): CH7DATINR
+0x400170F0 C FIELD 00w16 INDAT0: INDAT0
+0x400170F0 C FIELD 16w16 INDAT1: INDAT1
+0x400170F4 B REGISTER CH7DLYR (rw): channel y delay register
+0x400170F4 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017100 B REGISTER DFSDM_FLT0CR1 (rw): control register 1
+0x40017100 C FIELD 00w01 DFEN: DFSDM enable
+0x40017100 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017100 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017100 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017100 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017100 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017100 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017100 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017100 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017100 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017100 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017100 C FIELD 24w03 RCH: Regular channel selection
+0x40017100 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017100 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017104 B REGISTER DFSDM_FLT0CR2 (rw): control register 2
+0x40017104 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017104 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017104 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017104 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017104 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017104 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017104 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017104 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017104 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017108 B REGISTER DFSDM_FLT0ISR (ro): interrupt and status register
+0x40017108 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017108 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017108 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017108 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017108 C FIELD 04w01 AWDF: Analog watchdog
+0x40017108 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017108 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017108 C FIELD 16w08 CKABF: Clock absence flag
+0x40017108 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001710C B REGISTER DFSDM_FLT0ICR (rw): interrupt flag clear register
+0x4001710C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001710C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001710C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001710C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017110 B REGISTER DFSDM_FLT0JCHGR (rw): injected channel group selection register
+0x40017110 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017114 B REGISTER DFSDM_FLT0FCR (rw): filter control register
+0x40017114 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017114 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017114 C FIELD 29w03 FORD: Sinc filter order
+0x40017118 B REGISTER DFSDM_FLT0JDATAR (ro): data register for injected group
+0x40017118 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017118 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001711C B REGISTER DFSDM_FLT0RDATAR (ro): data register for the regular channel
0x4001711C C FIELD 00w03 RDATACH: Regular channel most recently converted
0x4001711C C FIELD 04w01 RPEND: Regular channel pending data
0x4001711C C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017120 B REGISTER DFSDM0_AWHTR (rw): DFSDM analog watchdog high threshold register
+0x40017120 B REGISTER DFSDM_FLT0AWHTR (rw): analog watchdog high threshold register
0x40017120 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
0x40017120 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017124 B REGISTER DFSDM1_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017124 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017124 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017128 B REGISTER DFSDM2_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017128 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017128 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x4001712C B REGISTER DFSDM3_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x4001712C C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x4001712C C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017130 B REGISTER DFSDM0_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017130 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017130 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017134 B REGISTER DFSDM1_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017134 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017134 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017138 B REGISTER DFSDM2_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017138 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017138 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x4001713C B REGISTER DFSDM3_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x4001713C C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x4001713C C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017140 B REGISTER DFSDM0_AWSR (ro): DFSDM analog watchdog status register
-0x40017140 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017140 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017144 B REGISTER DFSDM1_AWSR (ro): DFSDM analog watchdog status register
-0x40017144 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017144 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017148 B REGISTER DFSDM2_AWSR (ro): DFSDM analog watchdog status register
-0x40017148 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017148 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x4001714C B REGISTER DFSDM3_AWSR (ro): DFSDM analog watchdog status register
-0x4001714C C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x4001714C C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017150 B REGISTER DFSDM0_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017150 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017150 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017154 B REGISTER DFSDM1_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017154 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017154 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017158 B REGISTER DFSDM2_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017158 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017158 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x4001715C B REGISTER DFSDM3_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x4001715C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x4001715C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017160 B REGISTER DFSDM0_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017160 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017160 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017164 B REGISTER DFSDM1_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017164 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017164 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017168 B REGISTER DFSDM2_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017168 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017168 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x4001716C B REGISTER DFSDM3_EXMAX (ro): DFSDM Extremes detector maximum register
-0x4001716C C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x4001716C C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017170 B REGISTER DFSDM0_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017170 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017170 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017174 B REGISTER DFSDM1_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017174 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017174 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017178 B REGISTER DFSDM2_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017178 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017178 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x4001717C B REGISTER DFSDM3_EXMIN (ro): DFSDM Extremes detector minimum register
-0x4001717C C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x4001717C C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017180 B REGISTER DFSDM0_CNVTIMR (ro): DFSDM conversion timer register
-0x40017180 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017184 B REGISTER DFSDM1_CNVTIMR (ro): DFSDM conversion timer register
-0x40017184 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017188 B REGISTER DFSDM2_CNVTIMR (ro): DFSDM conversion timer register
-0x40017188 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x4001718C B REGISTER DFSDM3_CNVTIMR (ro): DFSDM conversion timer register
-0x4001718C C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
+0x40017124 B REGISTER DFSDM_FLT0AWLTR (rw): analog watchdog low threshold register
+0x40017124 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017124 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017128 B REGISTER DFSDM_FLT0AWSR (ro): analog watchdog status register
+0x40017128 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017128 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001712C B REGISTER DFSDM_FLT0AWCFR (rw): analog watchdog clear flag register
+0x4001712C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001712C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017130 B REGISTER DFSDM_FLT0EXMAX (ro): Extremes detector maximum register
+0x40017130 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017130 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017134 B REGISTER DFSDM_FLT0EXMIN (ro): Extremes detector minimum register
+0x40017134 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017134 C FIELD 08w24 EXMIN: EXMIN
+0x40017138 B REGISTER DFSDM_FLT0CNVTIMR (ro): conversion timer register
+0x40017138 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017180 B REGISTER DFSDM_FLT1CR1 (rw): control register 1
+0x40017180 C FIELD 00w01 DFEN: DFSDM enable
+0x40017180 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017180 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017180 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017180 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017180 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017180 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017180 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017180 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017180 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017180 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017180 C FIELD 24w03 RCH: Regular channel selection
+0x40017180 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017180 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017184 B REGISTER DFSDM_FLT1CR2 (rw): control register 2
+0x40017184 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017184 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017184 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017184 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017184 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017184 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017184 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017184 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017184 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017188 B REGISTER DFSDM_FLT1ISR (ro): interrupt and status register
+0x40017188 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017188 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017188 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017188 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017188 C FIELD 04w01 AWDF: Analog watchdog
+0x40017188 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017188 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017188 C FIELD 16w08 CKABF: Clock absence flag
+0x40017188 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001718C B REGISTER DFSDM_FLT1ICR (rw): interrupt flag clear register
+0x4001718C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001718C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001718C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001718C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017190 B REGISTER DFSDM_FLT1CHGR (rw): injected channel group selection register
+0x40017190 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017194 B REGISTER DFSDM_FLT1FCR (rw): filter control register
+0x40017194 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017194 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017194 C FIELD 29w03 FORD: Sinc filter order
+0x40017198 B REGISTER DFSDM_FLT1JDATAR (ro): data register for injected group
+0x40017198 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017198 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001719C B REGISTER DFSDM_FLT1RDATAR (ro): data register for the regular channel
+0x4001719C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001719C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001719C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400171A0 B REGISTER DFSDM_FLT1AWHTR (rw): analog watchdog high threshold register
+0x400171A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400171A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400171A4 B REGISTER DFSDM_FLT1AWLTR (rw): analog watchdog low threshold register
+0x400171A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400171A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400171A8 B REGISTER DFSDM_FLT1AWSR (ro): analog watchdog status register
+0x400171A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400171A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400171AC B REGISTER DFSDM_FLT1AWCFR (rw): analog watchdog clear flag register
+0x400171AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400171AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400171B0 B REGISTER DFSDM_FLT1EXMAX (ro): Extremes detector maximum register
+0x400171B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400171B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400171B4 B REGISTER DFSDM_FLT1EXMIN (ro): Extremes detector minimum register
+0x400171B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400171B4 C FIELD 08w24 EXMIN: EXMIN
+0x400171B8 B REGISTER DFSDM_FLT1CNVTIMR (ro): conversion timer register
+0x400171B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017200 B REGISTER DFSDM_FLT2CR1 (rw): control register 1
+0x40017200 C FIELD 00w01 DFEN: DFSDM enable
+0x40017200 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017200 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017200 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017200 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017200 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017200 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017200 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017200 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017200 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017200 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017200 C FIELD 24w03 RCH: Regular channel selection
+0x40017200 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017200 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017204 B REGISTER DFSDM_FLT2CR2 (rw): control register 2
+0x40017204 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017204 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017204 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017204 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017204 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017204 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017204 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017204 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017204 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017208 B REGISTER DFSDM_FLT2ISR (ro): interrupt and status register
+0x40017208 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017208 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017208 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017208 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017208 C FIELD 04w01 AWDF: Analog watchdog
+0x40017208 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017208 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017208 C FIELD 16w08 CKABF: Clock absence flag
+0x40017208 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001720C B REGISTER DFSDM_FLT2ICR (rw): interrupt flag clear register
+0x4001720C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001720C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001720C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001720C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017210 B REGISTER DFSDM_FLT2JCHGR (rw): injected channel group selection register
+0x40017210 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017214 B REGISTER DFSDM_FLT2FCR (rw): filter control register
+0x40017214 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017214 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017214 C FIELD 29w03 FORD: Sinc filter order
+0x40017218 B REGISTER DFSDM_FLT2JDATAR (ro): data register for injected group
+0x40017218 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017218 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001721C B REGISTER DFSDM_FLT2RDATAR (ro): data register for the regular channel
+0x4001721C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001721C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001721C C FIELD 08w24 RDATA: Regular channel conversion data
+0x40017220 B REGISTER DFSDM_FLT2AWHTR (rw): analog watchdog high threshold register
+0x40017220 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x40017220 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x40017224 B REGISTER DFSDM_FLT2AWLTR (rw): analog watchdog low threshold register
+0x40017224 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017224 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017228 B REGISTER DFSDM_FLT2AWSR (ro): analog watchdog status register
+0x40017228 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017228 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001722C B REGISTER DFSDM_FLT2AWCFR (rw): analog watchdog clear flag register
+0x4001722C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001722C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017230 B REGISTER DFSDM_FLT2EXMAX (ro): Extremes detector maximum register
+0x40017230 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017230 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017234 B REGISTER DFSDM_FLT2EXMIN (ro): Extremes detector minimum register
+0x40017234 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017234 C FIELD 08w24 EXMIN: EXMIN
+0x40017238 B REGISTER DFSDM_FLT2CNVTIMR (ro): conversion timer register
+0x40017238 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017280 B REGISTER DFSDM_FLT3CR1 (rw): control register 1
+0x40017280 C FIELD 00w01 DFEN: DFSDM enable
+0x40017280 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017280 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017280 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017280 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017280 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017280 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017280 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017280 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017280 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017280 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017280 C FIELD 24w03 RCH: Regular channel selection
+0x40017280 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017280 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017284 B REGISTER DFSDM_FLT3CR2 (rw): control register 2
+0x40017284 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017284 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017284 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017284 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017284 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017284 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017284 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017284 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017284 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017288 B REGISTER DFSDM_FLT3ISR (ro): interrupt and status register
+0x40017288 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017288 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017288 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017288 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017288 C FIELD 04w01 AWDF: Analog watchdog
+0x40017288 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017288 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017288 C FIELD 16w08 CKABF: Clock absence flag
+0x40017288 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001728C B REGISTER DFSDM_FLT3ICR (rw): interrupt flag clear register
+0x4001728C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001728C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001728C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001728C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017290 B REGISTER DFSDM_FLT3JCHGR (rw): injected channel group selection register
+0x40017290 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017294 B REGISTER DFSDM_FLT3FCR (rw): filter control register
+0x40017294 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017294 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017294 C FIELD 29w03 FORD: Sinc filter order
+0x40017298 B REGISTER DFSDM_FLT3JDATAR (ro): data register for injected group
+0x40017298 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017298 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001729C B REGISTER DFSDM_FLT3RDATAR (ro): data register for the regular channel
+0x4001729C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001729C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001729C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400172A0 B REGISTER DFSDM_FLT3AWHTR (rw): analog watchdog high threshold register
+0x400172A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400172A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400172A4 B REGISTER DFSDM_FLT3AWLTR (rw): analog watchdog low threshold register
+0x400172A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400172A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400172A8 B REGISTER DFSDM_FLT3AWSR (ro): analog watchdog status register
+0x400172A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400172A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400172AC B REGISTER DFSDM_FLT3AWCFR (rw): analog watchdog clear flag register
+0x400172AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400172AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400172B0 B REGISTER DFSDM_FLT3EXMAX (ro): Extremes detector maximum register
+0x400172B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400172B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400172B4 B REGISTER DFSDM_FLT3EXMIN (ro): Extremes detector minimum register
+0x400172B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400172B4 C FIELD 08w24 EXMIN: EXMIN
+0x400172B8 B REGISTER DFSDM_FLT3CNVTIMR (ro): conversion timer register
+0x400172B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
0x40017400 A PERIPHERAL HRTIM_Master
0x40017400 B REGISTER MCR (rw): Master Timer Control Register
0x40017400 C FIELD 00w03 CK_PSC: HRTIM Master Clock prescaler
@@ -21613,48 +21608,48 @@
0x58027054 B REGISTER M2FECR (rw): RAMECC monitor 2 failing error code register
0x58027054 C FIELD 00w32 FEC (ro): ECC failing code
0x5C001000 A PERIPHERAL DBGMCU
-0x5C001000 B REGISTER IDC (ro): Identity code
+0x5C001000 B REGISTER IDC (ro): DBGMCU Identity Code Register
0x5C001000 C FIELD 00w12 DEV_ID: Device ID
-0x5C001000 C FIELD 16w16 REV_ID: Revision ID
-0x5C001004 B REGISTER CR (rw): Configuration register
-0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow debug in D1 Sleep mode
-0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow debug in D1 Stop mode
-0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow debug in D1 Standby mode
-0x5C001004 C FIELD 20w01 TRACECLKEN: Trace clock enable enable
-0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable enable
-0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable enable
+0x5C001000 C FIELD 16w16 REV_ID: Revision
+0x5C001004 B REGISTER CR (rw): DBGMCU Configuration Register
+0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow D1 domain debug in Sleep mode
+0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow D1 domain debug in Stop mode
+0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow D1 domain debug in Standby mode
+0x5C001004 C FIELD 20w01 TRACECLKEN: Trace port clock enable
+0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable
+0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable
0x5C001004 C FIELD 28w01 TRGOEN: External trigger output enable
-0x5C001034 B REGISTER APB3FZ1 (rw): APB3 peripheral freeze register
-0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug mode
-0x5C00103C B REGISTER APB1LFZ1 (rw): APB1L peripheral freeze register
-0x5C00103C C FIELD 00w01 TIM2: TIM2 stop in debug mode
-0x5C00103C C FIELD 01w01 TIM3: TIM3 stop in debug mode
-0x5C00103C C FIELD 02w01 TIM4: TIM4 stop in debug mode
-0x5C00103C C FIELD 03w01 TIM5: TIM5 stop in debug mode
-0x5C00103C C FIELD 04w01 TIM6: TIM6 stop in debug mode
-0x5C00103C C FIELD 05w01 TIM7: TIM7 stop in debug mode
-0x5C00103C C FIELD 06w01 TIM12: TIM12 stop in debug mode
-0x5C00103C C FIELD 07w01 TIM13: TIM13 stop in debug mode
-0x5C00103C C FIELD 08w01 TIM14: TIM14 stop in debug mode
-0x5C00103C C FIELD 09w01 LPTIM1: LPTIM1 stop in debug mode
-0x5C00103C C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop in debug mode
-0x5C00104C B REGISTER APB2FZ1 (rw): APB2 peripheral freeze register
-0x5C00104C C FIELD 00w01 TIM1: TIM1 stop in debug mode
-0x5C00104C C FIELD 01w01 TIM8: TIM8 stop in debug mode
-0x5C00104C C FIELD 16w01 TIM15: TIM15 stop in debug mode
-0x5C00104C C FIELD 17w01 TIM16: TIM16 stop in debug mode
-0x5C00104C C FIELD 18w01 TIM17: TIM17 stop in debug mode
-0x5C00104C C FIELD 29w01 HRTIM: HRTIM stop in debug mode
-0x5C001054 B REGISTER APB4FZ1 (rw): APB4 peripheral freeze register
-0x5C001054 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop in debug mode
-0x5C001054 C FIELD 09w01 LPTIM2: LPTIM2 stop in debug mode
-0x5C001054 C FIELD 10w01 LPTIM3: LPTIM3 stop in debug mode
-0x5C001054 C FIELD 11w01 LPTIM4: LPTIM4 stop in debug mode
-0x5C001054 C FIELD 12w01 LPTIM5: LPTIM5 stop in debug mode
-0x5C001054 C FIELD 16w01 RTC: RTC stop in debug mode
-0x5C001054 C FIELD 18w01 IWDG1: Independent watchdog for D1 stop in debug mode
+0x5C001034 B REGISTER APB3FZ1 (rw): DBGMCU APB3 peripheral freeze register
+0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C00103C B REGISTER APB1LFZ1 (rw): DBGMCU APB1L peripheral freeze register
+0x5C00103C C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C00103C C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C00103C C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C00103C C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C00103C C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C00103C C FIELD 05w01 DBG_TIM7: TIM7 stop in debug
+0x5C00103C C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C00103C C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C00103C C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C00103C C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C00103C C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C00103C C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C00103C C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C00104C B REGISTER APB2FZ1 (rw): DBGMCU APB2 peripheral freeze register
+0x5C00104C C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C00104C C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C00104C C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C00104C C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C00104C C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C00104C C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001054 B REGISTER APB4FZ1 (rw): DBGMCU APB4 peripheral freeze register
+0x5C001054 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001054 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001054 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001054 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001054 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001054 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001054 C FIELD 18w01 DBG_WDGLSD1: Independent watchdog for D1 stop in debug
0xE000E008 A PERIPHERAL SCB_ACTRL
0xE000E008 B REGISTER ACTRL (rw): Auxiliary control register
0xE000E008 C FIELD 02w01 DISFOLD: DISFOLD
@@ -21965,7 +21960,7 @@
0xE000ED20 B REGISTER SHPR3 (rw): System handler priority registers
0xE000ED20 C FIELD 16w08 PRI_14: Priority of system handler 14
0xE000ED20 C FIELD 24w08 PRI_15: Priority of system handler 15
-0xE000ED24 B REGISTER SHCRS (rw): System handler control and state register
+0xE000ED24 B REGISTER SHCSR (rw): System handler control and state register
0xE000ED24 C FIELD 00w01 MEMFAULTACT: Memory management fault exception active bit
0xE000ED24 C FIELD 01w01 BUSFAULTACT: Bus fault exception active bit
0xE000ED24 C FIELD 03w01 USGFAULTACT: Usage fault exception active bit
@@ -22042,7 +22037,7 @@
0xE000ED90 C FIELD 00w01 SEPARATE: Separate flag
0xE000ED90 C FIELD 08w08 DREGION: Number of MPU data regions
0xE000ED90 C FIELD 16w08 IREGION: Number of MPU instruction regions
-0xE000ED94 B REGISTER MPU_CTRL (ro): MPU control register
+0xE000ED94 B REGISTER MPU_CTRL (rw): MPU control register
0xE000ED94 C FIELD 00w01 ENABLE: Enables the MPU
0xE000ED94 C FIELD 01w01 HFNMIENA: Enables the operation of MPU during hard fault
0xE000ED94 C FIELD 02w01 PRIVDEFENA: Enable priviliged software access to default memory map
Raw
stm32h753v.mmap.diff
--- ./mmaps_old/stm32h753v.mmap 2021-06-06 20:39:56.600000000 -0500
+++ mmaps_new/stm32h753v.mmap 2021-06-06 20:39:04.730000000 -0500
@@ -5517,498 +5517,493 @@
0x40016048 C FIELD 24w03 DLYM4L: Delay line for first microphone of pair 4
0x40016048 C FIELD 28w03 DLYM4R: Delay line for second microphone of pair 4
0x40017000 A PERIPHERAL DFSDM
-0x40017000 B REGISTER DFSDM_CHCFG0R1 (rw): DFSDM channel configuration 0 register 1
-0x40017000 C FIELD 00w02 SITP: Serial interface type for channel 0
-0x40017000 C FIELD 02w02 SPICKSEL: SPI clock select for channel 0
-0x40017000 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 0
-0x40017000 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 0
-0x40017000 C FIELD 07w01 CHEN: Channel 0 enable
-0x40017000 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017000 C FIELD 12w02 DATMPX: Input data multiplexer for channel 0
-0x40017000 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017000 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017000 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017000 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017004 B REGISTER DFSDM_CHCFG1R1 (rw): DFSDM channel configuration 1 register 1
-0x40017004 C FIELD 00w02 SITP: Serial interface type for channel 1
-0x40017004 C FIELD 02w02 SPICKSEL: SPI clock select for channel 1
-0x40017004 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 1
-0x40017004 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 1
-0x40017004 C FIELD 07w01 CHEN: Channel 1 enable
-0x40017004 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017004 C FIELD 12w02 DATMPX: Input data multiplexer for channel 1
-0x40017004 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017004 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017004 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017004 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017008 B REGISTER DFSDM_CHCFG2R1 (rw): DFSDM channel configuration 2 register 1
-0x40017008 C FIELD 00w02 SITP: Serial interface type for channel 2
-0x40017008 C FIELD 02w02 SPICKSEL: SPI clock select for channel 2
-0x40017008 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 2
-0x40017008 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 2
-0x40017008 C FIELD 07w01 CHEN: Channel 2 enable
-0x40017008 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017008 C FIELD 12w02 DATMPX: Input data multiplexer for channel 2
-0x40017008 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017008 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017008 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017008 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001700C B REGISTER DFSDM_CHCFG3R1 (rw): DFSDM channel configuration 3 register 1
-0x4001700C C FIELD 00w02 SITP: Serial interface type for channel 3
-0x4001700C C FIELD 02w02 SPICKSEL: SPI clock select for channel 3
-0x4001700C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 3
-0x4001700C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 3
-0x4001700C C FIELD 07w01 CHEN: Channel 3 enable
-0x4001700C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001700C C FIELD 12w02 DATMPX: Input data multiplexer for channel 3
-0x4001700C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001700C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001700C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001700C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017010 B REGISTER DFSDM_CHCFG4R1 (rw): DFSDM channel configuration 4 register 1
-0x40017010 C FIELD 00w02 SITP: Serial interface type for channel 4
-0x40017010 C FIELD 02w02 SPICKSEL: SPI clock select for channel 4
-0x40017010 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 4
-0x40017010 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 4
-0x40017010 C FIELD 07w01 CHEN: Channel 4 enable
-0x40017010 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017010 C FIELD 12w02 DATMPX: Input data multiplexer for channel 4
-0x40017010 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017010 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017010 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017010 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017014 B REGISTER DFSDM_CHCFG5R1 (rw): DFSDM channel configuration 5 register 1
-0x40017014 C FIELD 00w02 SITP: Serial interface type for channel 5
-0x40017014 C FIELD 02w02 SPICKSEL: SPI clock select for channel 5
-0x40017014 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 5
-0x40017014 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 5
-0x40017014 C FIELD 07w01 CHEN: Channel 5 enable
-0x40017014 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017014 C FIELD 12w02 DATMPX: Input data multiplexer for channel 5
-0x40017014 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017014 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017014 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017014 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017018 B REGISTER DFSDM_CHCFG6R1 (rw): DFSDM channel configuration 6 register 1
-0x40017018 C FIELD 00w02 SITP: Serial interface type for channel 6
-0x40017018 C FIELD 02w02 SPICKSEL: SPI clock select for channel 6
-0x40017018 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 6
-0x40017018 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 6
-0x40017018 C FIELD 07w01 CHEN: Channel 6 enable
-0x40017018 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017018 C FIELD 12w02 DATMPX: Input data multiplexer for channel 6
-0x40017018 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017018 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017018 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017018 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001701C B REGISTER DFSDM_CHCFG7R1 (rw): DFSDM channel configuration 7 register 1
-0x4001701C C FIELD 00w02 SITP: Serial interface type for channel 7
-0x4001701C C FIELD 02w02 SPICKSEL: SPI clock select for channel 7
-0x4001701C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 7
-0x4001701C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 7
-0x4001701C C FIELD 07w01 CHEN: Channel 7 enable
-0x4001701C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001701C C FIELD 12w02 DATMPX: Input data multiplexer for channel 7
-0x4001701C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001701C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001701C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001701C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017020 B REGISTER DFSDM_CHCFG0R2 (rw): DFSDM channel configuration 0 register 2
-0x40017020 C FIELD 03w05 DTRBS: Data right bit-shift for channel 0
-0x40017020 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 0
-0x40017024 B REGISTER DFSDM_CHCFG1R2 (rw): DFSDM channel configuration 1 register 2
-0x40017024 C FIELD 03w05 DTRBS: Data right bit-shift for channel 1
-0x40017024 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 1
-0x40017028 B REGISTER DFSDM_CHCFG2R2 (rw): DFSDM channel configuration 2 register 2
-0x40017028 C FIELD 03w05 DTRBS: Data right bit-shift for channel 2
-0x40017028 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 2
-0x4001702C B REGISTER DFSDM_CHCFG3R2 (rw): DFSDM channel configuration 3 register 2
-0x4001702C C FIELD 03w05 DTRBS: Data right bit-shift for channel 3
-0x4001702C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 3
-0x40017030 B REGISTER DFSDM_CHCFG4R2 (rw): DFSDM channel configuration 4 register 2
-0x40017030 C FIELD 03w05 DTRBS: Data right bit-shift for channel 4
-0x40017030 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 4
-0x40017034 B REGISTER DFSDM_CHCFG5R2 (rw): DFSDM channel configuration 5 register 2
-0x40017034 C FIELD 03w05 DTRBS: Data right bit-shift for channel 5
-0x40017034 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 5
-0x40017038 B REGISTER DFSDM_CHCFG6R2 (rw): DFSDM channel configuration 6 register 2
-0x40017038 C FIELD 03w05 DTRBS: Data right bit-shift for channel 6
-0x40017038 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 6
-0x4001703C B REGISTER DFSDM_CHCFG7R2 (rw): DFSDM channel configuration 7 register 2
-0x4001703C C FIELD 03w05 DTRBS: Data right bit-shift for channel 7
-0x4001703C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 7
-0x40017040 B REGISTER DFSDM_AWSCD0R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017040 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 0
-0x40017040 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 0
-0x40017040 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 0
-0x40017040 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 0
-0x40017044 B REGISTER DFSDM_AWSCD1R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017044 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 1
-0x40017044 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 1
-0x40017044 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 1
-0x40017044 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 1
-0x40017048 B REGISTER DFSDM_AWSCD2R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017048 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 2
-0x40017048 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 2
-0x40017048 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 2
-0x40017048 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 2
-0x4001704C B REGISTER DFSDM_AWSCD3R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001704C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 3
-0x4001704C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 3
-0x4001704C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 3
-0x4001704C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 3
-0x40017050 B REGISTER DFSDM_AWSCD4R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017050 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 4
-0x40017050 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 4
-0x40017050 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 4
-0x40017050 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 4
-0x40017054 B REGISTER DFSDM_AWSCD5R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017054 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 5
-0x40017054 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 5
-0x40017054 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 5
-0x40017054 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 5
-0x40017058 B REGISTER DFSDM_AWSCD6R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017058 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 6
-0x40017058 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 6
-0x40017058 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 6
-0x40017058 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 6
-0x4001705C B REGISTER DFSDM_AWSCD7R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001705C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 7
-0x4001705C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 7
-0x4001705C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 7
-0x4001705C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 7
-0x40017060 B REGISTER DFSDM_CHWDAT0R (ro): DFSDM channel watchdog filter data register
-0x40017060 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017064 B REGISTER DFSDM_CHWDAT1R (ro): DFSDM channel watchdog filter data register
-0x40017064 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017068 B REGISTER DFSDM_CHWDAT2R (ro): DFSDM channel watchdog filter data register
-0x40017068 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001706C B REGISTER DFSDM_CHWDAT3R (ro): DFSDM channel watchdog filter data register
-0x4001706C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017070 B REGISTER DFSDM_CHWDAT4R (ro): DFSDM channel watchdog filter data register
-0x40017070 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017074 B REGISTER DFSDM_CHWDAT5R (ro): DFSDM channel watchdog filter data register
-0x40017074 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017078 B REGISTER DFSDM_CHWDAT6R (ro): DFSDM channel watchdog filter data register
-0x40017078 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001707C B REGISTER DFSDM_CHWDAT7R (ro): DFSDM channel watchdog filter data register
-0x4001707C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017080 B REGISTER DFSDM_CHDATIN0R (rw): DFSDM channel data input register
-0x40017080 C FIELD 00w16 INDAT0: Input data for channel 0
-0x40017080 C FIELD 16w16 INDAT1: Input data for channel 1
-0x40017084 B REGISTER DFSDM_CHDATIN1R (rw): DFSDM channel data input register
-0x40017084 C FIELD 00w16 INDAT0: Input data for channel 1
-0x40017084 C FIELD 16w16 INDAT1: Input data for channel 2
-0x40017088 B REGISTER DFSDM_CHDATIN2R (rw): DFSDM channel data input register
-0x40017088 C FIELD 00w16 INDAT0: Input data for channel 2
-0x40017088 C FIELD 16w16 INDAT1: Input data for channel 3
-0x4001708C B REGISTER DFSDM_CHDATIN3R (rw): DFSDM channel data input register
-0x4001708C C FIELD 00w16 INDAT0: Input data for channel 3
-0x4001708C C FIELD 16w16 INDAT1: Input data for channel 4
-0x40017090 B REGISTER DFSDM_CHDATIN4R (rw): DFSDM channel data input register
-0x40017090 C FIELD 00w16 INDAT0: Input data for channel 4
-0x40017090 C FIELD 16w16 INDAT1: Input data for channel 5
-0x40017094 B REGISTER DFSDM_CHDATIN5R (rw): DFSDM channel data input register
-0x40017094 C FIELD 00w16 INDAT0: Input data for channel 5
-0x40017094 C FIELD 16w16 INDAT1: Input data for channel 6
-0x40017098 B REGISTER DFSDM_CHDATIN6R (rw): DFSDM channel data input register
-0x40017098 C FIELD 00w16 INDAT0: Input data for channel 6
-0x40017098 C FIELD 16w16 INDAT1: Input data for channel 7
-0x4001709C B REGISTER DFSDM_CHDATIN7R (rw): DFSDM channel data input register
-0x4001709C C FIELD 00w16 INDAT0: Input data for channel 7
-0x4001709C C FIELD 16w16 INDAT1: Input data for channel 8
-0x400170A0 B REGISTER DFSDM0_CR1 (rw): DFSDM control register 1
-0x400170A0 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A0 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A0 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A0 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A0 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A0 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A0 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A0 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A0 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A0 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A0 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A0 C FIELD 24w03 RCH: Regular channel selection
-0x400170A0 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A0 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A4 B REGISTER DFSDM1_CR1 (rw): DFSDM control register 1
-0x400170A4 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A4 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A4 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A4 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A4 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A4 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A4 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A4 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A4 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A4 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A4 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A4 C FIELD 24w03 RCH: Regular channel selection
-0x400170A4 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A4 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A8 B REGISTER DFSDM2_CR1 (rw): DFSDM control register 1
-0x400170A8 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A8 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A8 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A8 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A8 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A8 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A8 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A8 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A8 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A8 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A8 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A8 C FIELD 24w03 RCH: Regular channel selection
-0x400170A8 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A8 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170AC B REGISTER DFSDM3_CR1 (rw): DFSDM control register 1
-0x400170AC C FIELD 00w01 DFEN: DFSDM enable
-0x400170AC C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170AC C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170AC C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170AC C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170AC C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170AC C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170AC C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170AC C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170AC C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170AC C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170AC C FIELD 24w03 RCH: Regular channel selection
-0x400170AC C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170AC C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170B0 B REGISTER DFSDM0_CR2 (rw): DFSDM control register 2
-0x400170B0 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B0 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B0 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B0 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B0 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B0 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B0 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B0 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B0 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B4 B REGISTER DFSDM1_CR2 (rw): DFSDM control register 2
-0x400170B4 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B4 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B4 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B4 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B4 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B4 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B4 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B4 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B4 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B8 B REGISTER DFSDM2_CR2 (rw): DFSDM control register 2
-0x400170B8 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B8 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B8 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B8 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B8 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B8 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B8 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B8 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B8 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170BC B REGISTER DFSDM3_CR2 (rw): DFSDM control register 2
-0x400170BC C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170BC C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170BC C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170BC C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170BC C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170BC C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170BC C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170BC C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170BC C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170C0 B REGISTER DFSDM0_ISR (ro): DFSDM interrupt and status register
-0x400170C0 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C0 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C0 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C0 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C0 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C0 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C0 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C0 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C0 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C4 B REGISTER DFSDM1_ISR (ro): DFSDM interrupt and status register
-0x400170C4 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C4 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C4 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C4 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C4 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C4 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C4 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C4 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C4 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C8 B REGISTER DFSDM2_ISR (ro): DFSDM interrupt and status register
-0x400170C8 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C8 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C8 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C8 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C8 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C8 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C8 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C8 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C8 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170CC B REGISTER DFSDM3_ISR (ro): DFSDM interrupt and status register
-0x400170CC C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170CC C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170CC C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170CC C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170CC C FIELD 04w01 AWDF: Analog watchdog
-0x400170CC C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170CC C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170CC C FIELD 16w08 CKABF: Clock absence flag
-0x400170CC C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170D0 B REGISTER DFSDM0_ICR (rw): DFSDM interrupt flag clear register
-0x400170D0 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D0 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D0 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D0 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D4 B REGISTER DFSDM1_ICR (rw): DFSDM interrupt flag clear register
-0x400170D4 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D4 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D4 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D4 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D8 B REGISTER DFSDM2_ICR (rw): DFSDM interrupt flag clear register
-0x400170D8 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D8 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D8 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D8 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170DC B REGISTER DFSDM3_ICR (rw): DFSDM interrupt flag clear register
-0x400170DC C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170DC C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170DC C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170DC C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170E0 B REGISTER DFSDM0_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E0 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E4 B REGISTER DFSDM1_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E4 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E8 B REGISTER DFSDM2_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E8 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170EC B REGISTER DFSDM3_JCHGR (rw): DFSDM injected channel group selection register
-0x400170EC C FIELD 00w08 JCHG: Injected channel group selection
-0x400170F0 B REGISTER DFSDM0_FCR (rw): DFSDM filter control register
-0x400170F0 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F0 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F0 C FIELD 29w03 FORD: Sinc filter order
-0x400170F4 B REGISTER DFSDM1_FCR (rw): DFSDM filter control register
-0x400170F4 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F4 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F4 C FIELD 29w03 FORD: Sinc filter order
-0x400170F8 B REGISTER DFSDM2_FCR (rw): DFSDM filter control register
-0x400170F8 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F8 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F8 C FIELD 29w03 FORD: Sinc filter order
-0x400170FC B REGISTER DFSDM3_FCR (rw): DFSDM filter control register
-0x400170FC C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170FC C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170FC C FIELD 29w03 FORD: Sinc filter order
-0x40017100 B REGISTER DFSDM0_JDATAR (ro): DFSDM data register for injected group
-0x40017100 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017100 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017104 B REGISTER DFSDM1_JDATAR (ro): DFSDM data register for injected group
-0x40017104 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017104 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017108 B REGISTER DFSDM2_JDATAR (ro): DFSDM data register for injected group
-0x40017108 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017108 C FIELD 08w24 JDATA: Injected group conversion data
-0x4001710C B REGISTER DFSDM3_JDATAR (ro): DFSDM data register for injected group
-0x4001710C C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x4001710C C FIELD 08w24 JDATA: Injected group conversion data
-0x40017110 B REGISTER DFSDM0_RDATAR (ro): DFSDM data register for the regular channel
-0x40017110 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017110 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017110 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017114 B REGISTER DFSDM1_RDATAR (ro): DFSDM data register for the regular channel
-0x40017114 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017114 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017114 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017118 B REGISTER DFSDM2_RDATAR (ro): DFSDM data register for the regular channel
-0x40017118 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017118 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017118 C FIELD 08w24 RDATA: Regular channel conversion data
-0x4001711C B REGISTER DFSDM3_RDATAR (ro): DFSDM data register for the regular channel
+0x40017000 B REGISTER CH0CFGR1 (rw): channel configuration y register
+0x40017000 C FIELD 00w02 SITP: SITP
+0x40017000 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017000 C FIELD 05w01 SCDEN: SCDEN
+0x40017000 C FIELD 06w01 CKABEN: CKABEN
+0x40017000 C FIELD 07w01 CHEN: CHEN
+0x40017000 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017000 C FIELD 12w02 DATMPX: DATMPX
+0x40017000 C FIELD 14w02 DATPACK: DATPACK
+0x40017000 C FIELD 16w08 CKOUTDIV: CKOUTDIV
+0x40017000 C FIELD 30w01 CKOUTSRC: CKOUTSRC
+0x40017000 C FIELD 31w01 DFSDMEN: DFSDMEN
+0x40017004 B REGISTER CH0CFGR2 (rw): channel configuration y register
+0x40017004 C FIELD 03w05 DTRBS: DTRBS
+0x40017004 C FIELD 08w24 OFFSET: OFFSET
+0x40017008 B REGISTER CH0AWSCDR (rw): analog watchdog and short-circuit detector register
+0x40017008 C FIELD 00w08 SCDT: SCDT
+0x40017008 C FIELD 12w04 BKSCD: BKSCD
+0x40017008 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017008 C FIELD 22w02 AWFORD: AWFORD
+0x4001700C B REGISTER CH0WDATR (rw): channel watchdog filter data register
+0x4001700C C FIELD 00w16 WDATA: WDATA
+0x40017010 B REGISTER CH0DATINR (rw): channel data input register
+0x40017010 C FIELD 00w16 INDAT0: INDAT0
+0x40017010 C FIELD 16w16 INDAT1: INDAT1
+0x40017014 B REGISTER CH0DLYR (rw): channel y delay register
+0x40017014 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017020 B REGISTER CH1CFGR1 (rw): CH1CFGR1
+0x40017020 C FIELD 00w02 SITP: SITP
+0x40017020 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017020 C FIELD 05w01 SCDEN: SCDEN
+0x40017020 C FIELD 06w01 CKABEN: CKABEN
+0x40017020 C FIELD 07w01 CHEN: CHEN
+0x40017020 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017020 C FIELD 12w02 DATMPX: DATMPX
+0x40017020 C FIELD 14w02 DATPACK: DATPACK
+0x40017024 B REGISTER CH1CFGR2 (rw): CH1CFGR2
+0x40017024 C FIELD 03w05 DTRBS: DTRBS
+0x40017024 C FIELD 08w24 OFFSET: OFFSET
+0x40017028 B REGISTER CH1AWSCDR (rw): CH1AWSCDR
+0x40017028 C FIELD 00w08 SCDT: SCDT
+0x40017028 C FIELD 12w04 BKSCD: BKSCD
+0x40017028 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017028 C FIELD 22w02 AWFORD: AWFORD
+0x4001702C B REGISTER CH1WDATR (rw): CH1WDATR
+0x4001702C C FIELD 00w16 WDATA: WDATA
+0x40017030 B REGISTER CH1DATINR (rw): CH1DATINR
+0x40017030 C FIELD 00w16 INDAT0: INDAT0
+0x40017030 C FIELD 16w16 INDAT1: INDAT1
+0x40017034 B REGISTER CH1DLYR (rw): channel y delay register
+0x40017034 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017040 B REGISTER CH2CFGR1 (rw): CH2CFGR1
+0x40017040 C FIELD 00w02 SITP: SITP
+0x40017040 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017040 C FIELD 05w01 SCDEN: SCDEN
+0x40017040 C FIELD 06w01 CKABEN: CKABEN
+0x40017040 C FIELD 07w01 CHEN: CHEN
+0x40017040 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017040 C FIELD 12w02 DATMPX: DATMPX
+0x40017040 C FIELD 14w02 DATPACK: DATPACK
+0x40017044 B REGISTER CH2CFGR2 (rw): CH2CFGR2
+0x40017044 C FIELD 03w05 DTRBS: DTRBS
+0x40017044 C FIELD 08w24 OFFSET: OFFSET
+0x40017048 B REGISTER CH2AWSCDR (rw): CH2AWSCDR
+0x40017048 C FIELD 00w08 SCDT: SCDT
+0x40017048 C FIELD 12w04 BKSCD: BKSCD
+0x40017048 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017048 C FIELD 22w02 AWFORD: AWFORD
+0x4001704C B REGISTER CH2WDATR (rw): CH2WDATR
+0x4001704C C FIELD 00w16 WDATA: WDATA
+0x40017050 B REGISTER CH2DATINR (rw): CH2DATINR
+0x40017050 C FIELD 00w16 INDAT0: INDAT0
+0x40017050 C FIELD 16w16 INDAT1: INDAT1
+0x40017054 B REGISTER CH2DLYR (rw): channel y delay register
+0x40017054 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017060 B REGISTER CH3CFGR1 (rw): CH3CFGR1
+0x40017060 C FIELD 00w02 SITP: SITP
+0x40017060 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017060 C FIELD 05w01 SCDEN: SCDEN
+0x40017060 C FIELD 06w01 CKABEN: CKABEN
+0x40017060 C FIELD 07w01 CHEN: CHEN
+0x40017060 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017060 C FIELD 12w02 DATMPX: DATMPX
+0x40017060 C FIELD 14w02 DATPACK: DATPACK
+0x40017064 B REGISTER CH3CFGR2 (rw): CH3CFGR2
+0x40017064 C FIELD 03w05 DTRBS: DTRBS
+0x40017064 C FIELD 08w24 OFFSET: OFFSET
+0x40017068 B REGISTER CH3AWSCDR (rw): CH3AWSCDR
+0x40017068 C FIELD 00w08 SCDT: SCDT
+0x40017068 C FIELD 12w04 BKSCD: BKSCD
+0x40017068 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017068 C FIELD 22w02 AWFORD: AWFORD
+0x4001706C B REGISTER CH3WDATR (rw): CH3WDATR
+0x4001706C C FIELD 00w16 WDATA: WDATA
+0x40017070 B REGISTER CH3DATINR (rw): CH3DATINR
+0x40017070 C FIELD 00w16 INDAT0: INDAT0
+0x40017070 C FIELD 16w16 INDAT1: INDAT1
+0x40017074 B REGISTER CH3DLYR (rw): channel y delay register
+0x40017074 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017080 B REGISTER CH4CFGR1 (rw): CH4CFGR1
+0x40017080 C FIELD 00w02 SITP: SITP
+0x40017080 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x40017080 C FIELD 05w01 SCDEN: SCDEN
+0x40017080 C FIELD 06w01 CKABEN: CKABEN
+0x40017080 C FIELD 07w01 CHEN: CHEN
+0x40017080 C FIELD 08w01 CHINSEL: CHINSEL
+0x40017080 C FIELD 12w02 DATMPX: DATMPX
+0x40017080 C FIELD 14w02 DATPACK: DATPACK
+0x40017084 B REGISTER CH4CFGR2 (rw): CH4CFGR2
+0x40017084 C FIELD 03w05 DTRBS: DTRBS
+0x40017084 C FIELD 08w24 OFFSET: OFFSET
+0x40017088 B REGISTER CH4AWSCDR (rw): CH4AWSCDR
+0x40017088 C FIELD 00w08 SCDT: SCDT
+0x40017088 C FIELD 12w04 BKSCD: BKSCD
+0x40017088 C FIELD 16w05 AWFOSR: AWFOSR
+0x40017088 C FIELD 22w02 AWFORD: AWFORD
+0x4001708C B REGISTER CH4WDATR (rw): CH4WDATR
+0x4001708C C FIELD 00w16 WDATA: WDATA
+0x40017090 B REGISTER CH4DATINR (rw): CH4DATINR
+0x40017090 C FIELD 00w16 INDAT0: INDAT0
+0x40017090 C FIELD 16w16 INDAT1: INDAT1
+0x40017094 B REGISTER CH4DLYR (rw): channel y delay register
+0x40017094 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170A0 B REGISTER CH5CFGR1 (rw): CH5CFGR1
+0x400170A0 C FIELD 00w02 SITP: SITP
+0x400170A0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170A0 C FIELD 05w01 SCDEN: SCDEN
+0x400170A0 C FIELD 06w01 CKABEN: CKABEN
+0x400170A0 C FIELD 07w01 CHEN: CHEN
+0x400170A0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170A0 C FIELD 12w02 DATMPX: DATMPX
+0x400170A0 C FIELD 14w02 DATPACK: DATPACK
+0x400170A4 B REGISTER CH5CFGR2 (rw): CH5CFGR2
+0x400170A4 C FIELD 03w05 DTRBS: DTRBS
+0x400170A4 C FIELD 08w24 OFFSET: OFFSET
+0x400170A8 B REGISTER CH5AWSCDR (rw): CH5AWSCDR
+0x400170A8 C FIELD 00w08 SCDT: SCDT
+0x400170A8 C FIELD 12w04 BKSCD: BKSCD
+0x400170A8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170A8 C FIELD 22w02 AWFORD: AWFORD
+0x400170AC B REGISTER CH5WDATR (rw): CH5WDATR
+0x400170AC C FIELD 00w16 WDATA: WDATA
+0x400170B0 B REGISTER CH5DATINR (rw): CH5DATINR
+0x400170B0 C FIELD 00w16 INDAT0: INDAT0
+0x400170B0 C FIELD 16w16 INDAT1: INDAT1
+0x400170B4 B REGISTER CH5DLYR (rw): channel y delay register
+0x400170B4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170C0 B REGISTER CH6CFGR1 (rw): CH6CFGR1
+0x400170C0 C FIELD 00w02 SITP: SITP
+0x400170C0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170C0 C FIELD 05w01 SCDEN: SCDEN
+0x400170C0 C FIELD 06w01 CKABEN: CKABEN
+0x400170C0 C FIELD 07w01 CHEN: CHEN
+0x400170C0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170C0 C FIELD 12w02 DATMPX: DATMPX
+0x400170C0 C FIELD 14w02 DATPACK: DATPACK
+0x400170C4 B REGISTER CH6CFGR2 (rw): CH6CFGR2
+0x400170C4 C FIELD 03w05 DTRBS: DTRBS
+0x400170C4 C FIELD 08w24 OFFSET: OFFSET
+0x400170C8 B REGISTER CH6AWSCDR (rw): CH6AWSCDR
+0x400170C8 C FIELD 00w08 SCDT: SCDT
+0x400170C8 C FIELD 12w04 BKSCD: BKSCD
+0x400170C8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170C8 C FIELD 22w02 AWFORD: AWFORD
+0x400170CC B REGISTER CH6WDATR (rw): CH6WDATR
+0x400170CC C FIELD 00w16 WDATA: WDATA
+0x400170D0 B REGISTER CH6DATINR (rw): CH6DATINR
+0x400170D0 C FIELD 00w16 INDAT0: INDAT0
+0x400170D0 C FIELD 16w16 INDAT1: INDAT1
+0x400170D4 B REGISTER CH6DLYR (rw): channel y delay register
+0x400170D4 C FIELD 00w06 PLSSKP: PLSSKP
+0x400170E0 B REGISTER CH7CFGR1 (rw): CH7CFGR1
+0x400170E0 C FIELD 00w02 SITP: SITP
+0x400170E0 C FIELD 02w02 SPICKSEL: SPICKSEL
+0x400170E0 C FIELD 05w01 SCDEN: SCDEN
+0x400170E0 C FIELD 06w01 CKABEN: CKABEN
+0x400170E0 C FIELD 07w01 CHEN: CHEN
+0x400170E0 C FIELD 08w01 CHINSEL: CHINSEL
+0x400170E0 C FIELD 12w02 DATMPX: DATMPX
+0x400170E0 C FIELD 14w02 DATPACK: DATPACK
+0x400170E4 B REGISTER CH7CFGR2 (rw): CH7CFGR2
+0x400170E4 C FIELD 03w05 DTRBS: DTRBS
+0x400170E4 C FIELD 08w24 OFFSET: OFFSET
+0x400170E8 B REGISTER CH7AWSCDR (rw): CH7AWSCDR
+0x400170E8 C FIELD 00w08 SCDT: SCDT
+0x400170E8 C FIELD 12w04 BKSCD: BKSCD
+0x400170E8 C FIELD 16w05 AWFOSR: AWFOSR
+0x400170E8 C FIELD 22w02 AWFORD: AWFORD
+0x400170EC B REGISTER CH7WDATR (rw): CH7WDATR
+0x400170EC C FIELD 00w16 WDATA: WDATA
+0x400170F0 B REGISTER CH7DATINR (rw): CH7DATINR
+0x400170F0 C FIELD 00w16 INDAT0: INDAT0
+0x400170F0 C FIELD 16w16 INDAT1: INDAT1
+0x400170F4 B REGISTER CH7DLYR (rw): channel y delay register
+0x400170F4 C FIELD 00w06 PLSSKP: PLSSKP
+0x40017100 B REGISTER DFSDM_FLT0CR1 (rw): control register 1
+0x40017100 C FIELD 00w01 DFEN: DFSDM enable
+0x40017100 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017100 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017100 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017100 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017100 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017100 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017100 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017100 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017100 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017100 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017100 C FIELD 24w03 RCH: Regular channel selection
+0x40017100 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017100 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017104 B REGISTER DFSDM_FLT0CR2 (rw): control register 2
+0x40017104 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017104 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017104 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017104 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017104 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017104 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017104 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017104 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017104 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017108 B REGISTER DFSDM_FLT0ISR (ro): interrupt and status register
+0x40017108 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017108 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017108 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017108 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017108 C FIELD 04w01 AWDF: Analog watchdog
+0x40017108 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017108 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017108 C FIELD 16w08 CKABF: Clock absence flag
+0x40017108 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001710C B REGISTER DFSDM_FLT0ICR (rw): interrupt flag clear register
+0x4001710C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001710C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001710C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001710C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017110 B REGISTER DFSDM_FLT0JCHGR (rw): injected channel group selection register
+0x40017110 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017114 B REGISTER DFSDM_FLT0FCR (rw): filter control register
+0x40017114 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017114 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017114 C FIELD 29w03 FORD: Sinc filter order
+0x40017118 B REGISTER DFSDM_FLT0JDATAR (ro): data register for injected group
+0x40017118 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017118 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001711C B REGISTER DFSDM_FLT0RDATAR (ro): data register for the regular channel
0x4001711C C FIELD 00w03 RDATACH: Regular channel most recently converted
0x4001711C C FIELD 04w01 RPEND: Regular channel pending data
0x4001711C C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017120 B REGISTER DFSDM0_AWHTR (rw): DFSDM analog watchdog high threshold register
+0x40017120 B REGISTER DFSDM_FLT0AWHTR (rw): analog watchdog high threshold register
0x40017120 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
0x40017120 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017124 B REGISTER DFSDM1_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017124 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017124 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017128 B REGISTER DFSDM2_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017128 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017128 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x4001712C B REGISTER DFSDM3_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x4001712C C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x4001712C C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017130 B REGISTER DFSDM0_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017130 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017130 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017134 B REGISTER DFSDM1_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017134 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017134 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017138 B REGISTER DFSDM2_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017138 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017138 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x4001713C B REGISTER DFSDM3_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x4001713C C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x4001713C C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017140 B REGISTER DFSDM0_AWSR (ro): DFSDM analog watchdog status register
-0x40017140 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017140 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017144 B REGISTER DFSDM1_AWSR (ro): DFSDM analog watchdog status register
-0x40017144 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017144 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017148 B REGISTER DFSDM2_AWSR (ro): DFSDM analog watchdog status register
-0x40017148 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017148 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x4001714C B REGISTER DFSDM3_AWSR (ro): DFSDM analog watchdog status register
-0x4001714C C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x4001714C C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017150 B REGISTER DFSDM0_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017150 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017150 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017154 B REGISTER DFSDM1_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017154 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017154 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017158 B REGISTER DFSDM2_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017158 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017158 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x4001715C B REGISTER DFSDM3_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x4001715C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x4001715C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017160 B REGISTER DFSDM0_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017160 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017160 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017164 B REGISTER DFSDM1_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017164 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017164 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017168 B REGISTER DFSDM2_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017168 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017168 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x4001716C B REGISTER DFSDM3_EXMAX (ro): DFSDM Extremes detector maximum register
-0x4001716C C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x4001716C C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017170 B REGISTER DFSDM0_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017170 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017170 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017174 B REGISTER DFSDM1_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017174 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017174 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017178 B REGISTER DFSDM2_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017178 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017178 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x4001717C B REGISTER DFSDM3_EXMIN (ro): DFSDM Extremes detector minimum register
-0x4001717C C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x4001717C C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017180 B REGISTER DFSDM0_CNVTIMR (ro): DFSDM conversion timer register
-0x40017180 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017184 B REGISTER DFSDM1_CNVTIMR (ro): DFSDM conversion timer register
-0x40017184 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017188 B REGISTER DFSDM2_CNVTIMR (ro): DFSDM conversion timer register
-0x40017188 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x4001718C B REGISTER DFSDM3_CNVTIMR (ro): DFSDM conversion timer register
-0x4001718C C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
+0x40017124 B REGISTER DFSDM_FLT0AWLTR (rw): analog watchdog low threshold register
+0x40017124 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017124 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017128 B REGISTER DFSDM_FLT0AWSR (ro): analog watchdog status register
+0x40017128 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017128 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001712C B REGISTER DFSDM_FLT0AWCFR (rw): analog watchdog clear flag register
+0x4001712C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001712C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017130 B REGISTER DFSDM_FLT0EXMAX (ro): Extremes detector maximum register
+0x40017130 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017130 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017134 B REGISTER DFSDM_FLT0EXMIN (ro): Extremes detector minimum register
+0x40017134 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017134 C FIELD 08w24 EXMIN: EXMIN
+0x40017138 B REGISTER DFSDM_FLT0CNVTIMR (ro): conversion timer register
+0x40017138 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017180 B REGISTER DFSDM_FLT1CR1 (rw): control register 1
+0x40017180 C FIELD 00w01 DFEN: DFSDM enable
+0x40017180 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017180 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017180 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017180 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017180 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017180 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017180 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017180 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017180 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017180 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017180 C FIELD 24w03 RCH: Regular channel selection
+0x40017180 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017180 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017184 B REGISTER DFSDM_FLT1CR2 (rw): control register 2
+0x40017184 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017184 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017184 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017184 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017184 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017184 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017184 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017184 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017184 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017188 B REGISTER DFSDM_FLT1ISR (ro): interrupt and status register
+0x40017188 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017188 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017188 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017188 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017188 C FIELD 04w01 AWDF: Analog watchdog
+0x40017188 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017188 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017188 C FIELD 16w08 CKABF: Clock absence flag
+0x40017188 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001718C B REGISTER DFSDM_FLT1ICR (rw): interrupt flag clear register
+0x4001718C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001718C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001718C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001718C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017190 B REGISTER DFSDM_FLT1CHGR (rw): injected channel group selection register
+0x40017190 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017194 B REGISTER DFSDM_FLT1FCR (rw): filter control register
+0x40017194 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017194 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017194 C FIELD 29w03 FORD: Sinc filter order
+0x40017198 B REGISTER DFSDM_FLT1JDATAR (ro): data register for injected group
+0x40017198 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017198 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001719C B REGISTER DFSDM_FLT1RDATAR (ro): data register for the regular channel
+0x4001719C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001719C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001719C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400171A0 B REGISTER DFSDM_FLT1AWHTR (rw): analog watchdog high threshold register
+0x400171A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400171A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400171A4 B REGISTER DFSDM_FLT1AWLTR (rw): analog watchdog low threshold register
+0x400171A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400171A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400171A8 B REGISTER DFSDM_FLT1AWSR (ro): analog watchdog status register
+0x400171A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400171A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400171AC B REGISTER DFSDM_FLT1AWCFR (rw): analog watchdog clear flag register
+0x400171AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400171AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400171B0 B REGISTER DFSDM_FLT1EXMAX (ro): Extremes detector maximum register
+0x400171B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400171B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400171B4 B REGISTER DFSDM_FLT1EXMIN (ro): Extremes detector minimum register
+0x400171B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400171B4 C FIELD 08w24 EXMIN: EXMIN
+0x400171B8 B REGISTER DFSDM_FLT1CNVTIMR (ro): conversion timer register
+0x400171B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017200 B REGISTER DFSDM_FLT2CR1 (rw): control register 1
+0x40017200 C FIELD 00w01 DFEN: DFSDM enable
+0x40017200 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017200 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017200 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017200 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017200 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017200 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017200 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017200 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017200 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017200 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017200 C FIELD 24w03 RCH: Regular channel selection
+0x40017200 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017200 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017204 B REGISTER DFSDM_FLT2CR2 (rw): control register 2
+0x40017204 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017204 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017204 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017204 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017204 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017204 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017204 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017204 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017204 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017208 B REGISTER DFSDM_FLT2ISR (ro): interrupt and status register
+0x40017208 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017208 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017208 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017208 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017208 C FIELD 04w01 AWDF: Analog watchdog
+0x40017208 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017208 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017208 C FIELD 16w08 CKABF: Clock absence flag
+0x40017208 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001720C B REGISTER DFSDM_FLT2ICR (rw): interrupt flag clear register
+0x4001720C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001720C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001720C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001720C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017210 B REGISTER DFSDM_FLT2JCHGR (rw): injected channel group selection register
+0x40017210 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017214 B REGISTER DFSDM_FLT2FCR (rw): filter control register
+0x40017214 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017214 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017214 C FIELD 29w03 FORD: Sinc filter order
+0x40017218 B REGISTER DFSDM_FLT2JDATAR (ro): data register for injected group
+0x40017218 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017218 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001721C B REGISTER DFSDM_FLT2RDATAR (ro): data register for the regular channel
+0x4001721C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001721C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001721C C FIELD 08w24 RDATA: Regular channel conversion data
+0x40017220 B REGISTER DFSDM_FLT2AWHTR (rw): analog watchdog high threshold register
+0x40017220 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x40017220 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x40017224 B REGISTER DFSDM_FLT2AWLTR (rw): analog watchdog low threshold register
+0x40017224 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x40017224 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x40017228 B REGISTER DFSDM_FLT2AWSR (ro): analog watchdog status register
+0x40017228 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x40017228 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x4001722C B REGISTER DFSDM_FLT2AWCFR (rw): analog watchdog clear flag register
+0x4001722C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x4001722C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x40017230 B REGISTER DFSDM_FLT2EXMAX (ro): Extremes detector maximum register
+0x40017230 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x40017230 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x40017234 B REGISTER DFSDM_FLT2EXMIN (ro): Extremes detector minimum register
+0x40017234 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x40017234 C FIELD 08w24 EXMIN: EXMIN
+0x40017238 B REGISTER DFSDM_FLT2CNVTIMR (ro): conversion timer register
+0x40017238 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
+0x40017280 B REGISTER DFSDM_FLT3CR1 (rw): control register 1
+0x40017280 C FIELD 00w01 DFEN: DFSDM enable
+0x40017280 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
+0x40017280 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
+0x40017280 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
+0x40017280 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
+0x40017280 C FIELD 08w03 JEXTSEL: Trigger signal selection for launching injected conversions
+0x40017280 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
+0x40017280 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
+0x40017280 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
+0x40017280 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
+0x40017280 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
+0x40017280 C FIELD 24w03 RCH: Regular channel selection
+0x40017280 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
+0x40017280 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
+0x40017284 B REGISTER DFSDM_FLT3CR2 (rw): control register 2
+0x40017284 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
+0x40017284 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
+0x40017284 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
+0x40017284 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
+0x40017284 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
+0x40017284 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
+0x40017284 C FIELD 06w01 CKABIE: Clock absence interrupt enable
+0x40017284 C FIELD 08w08 EXCH: Extremes detector channel selection
+0x40017284 C FIELD 16w08 AWDCH: Analog watchdog channel selection
+0x40017288 B REGISTER DFSDM_FLT3ISR (ro): interrupt and status register
+0x40017288 C FIELD 00w01 JEOCF: End of injected conversion flag
+0x40017288 C FIELD 01w01 REOCF: End of regular conversion flag
+0x40017288 C FIELD 02w01 JOVRF: Injected conversion overrun flag
+0x40017288 C FIELD 03w01 ROVRF: Regular conversion overrun flag
+0x40017288 C FIELD 04w01 AWDF: Analog watchdog
+0x40017288 C FIELD 13w01 JCIP: Injected conversion in progress status
+0x40017288 C FIELD 14w01 RCIP: Regular conversion in progress status
+0x40017288 C FIELD 16w08 CKABF: Clock absence flag
+0x40017288 C FIELD 24w08 SCDF: short-circuit detector flag
+0x4001728C B REGISTER DFSDM_FLT3ICR (rw): interrupt flag clear register
+0x4001728C C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
+0x4001728C C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
+0x4001728C C FIELD 16w08 CLRCKABF: Clear the clock absence flag
+0x4001728C C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
+0x40017290 B REGISTER DFSDM_FLT3JCHGR (rw): injected channel group selection register
+0x40017290 C FIELD 00w08 JCHG: Injected channel group selection
+0x40017294 B REGISTER DFSDM_FLT3FCR (rw): filter control register
+0x40017294 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
+0x40017294 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
+0x40017294 C FIELD 29w03 FORD: Sinc filter order
+0x40017298 B REGISTER DFSDM_FLT3JDATAR (ro): data register for injected group
+0x40017298 C FIELD 00w03 JDATACH: Injected channel most recently converted
+0x40017298 C FIELD 08w24 JDATA: Injected group conversion data
+0x4001729C B REGISTER DFSDM_FLT3RDATAR (ro): data register for the regular channel
+0x4001729C C FIELD 00w03 RDATACH: Regular channel most recently converted
+0x4001729C C FIELD 04w01 RPEND: Regular channel pending data
+0x4001729C C FIELD 08w24 RDATA: Regular channel conversion data
+0x400172A0 B REGISTER DFSDM_FLT3AWHTR (rw): analog watchdog high threshold register
+0x400172A0 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
+0x400172A0 C FIELD 08w24 AWHT: Analog watchdog high threshold
+0x400172A4 B REGISTER DFSDM_FLT3AWLTR (rw): analog watchdog low threshold register
+0x400172A4 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
+0x400172A4 C FIELD 08w24 AWLT: Analog watchdog low threshold
+0x400172A8 B REGISTER DFSDM_FLT3AWSR (ro): analog watchdog status register
+0x400172A8 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
+0x400172A8 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
+0x400172AC B REGISTER DFSDM_FLT3AWCFR (rw): analog watchdog clear flag register
+0x400172AC C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
+0x400172AC C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
+0x400172B0 B REGISTER DFSDM_FLT3EXMAX (ro): Extremes detector maximum register
+0x400172B0 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
+0x400172B0 C FIELD 08w24 EXMAX: Extremes detector maximum value
+0x400172B4 B REGISTER DFSDM_FLT3EXMIN (ro): Extremes detector minimum register
+0x400172B4 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
+0x400172B4 C FIELD 08w24 EXMIN: EXMIN
+0x400172B8 B REGISTER DFSDM_FLT3CNVTIMR (ro): conversion timer register
+0x400172B8 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
0x40017400 A PERIPHERAL HRTIM_Master
0x40017400 B REGISTER MCR (rw): Master Timer Control Register
0x40017400 C FIELD 00w03 CK_PSC: HRTIM Master Clock prescaler
@@ -21619,48 +21614,48 @@
0x58027054 B REGISTER M2FECR (rw): RAMECC monitor 2 failing error code register
0x58027054 C FIELD 00w32 FEC (ro): ECC failing code
0x5C001000 A PERIPHERAL DBGMCU
-0x5C001000 B REGISTER IDC (ro): Identity code
+0x5C001000 B REGISTER IDC (ro): DBGMCU Identity Code Register
0x5C001000 C FIELD 00w12 DEV_ID: Device ID
-0x5C001000 C FIELD 16w16 REV_ID: Revision ID
-0x5C001004 B REGISTER CR (rw): Configuration register
-0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow debug in D1 Sleep mode
-0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow debug in D1 Stop mode
-0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow debug in D1 Standby mode
-0x5C001004 C FIELD 20w01 TRACECLKEN: Trace clock enable enable
-0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable enable
-0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable enable
+0x5C001000 C FIELD 16w16 REV_ID: Revision
+0x5C001004 B REGISTER CR (rw): DBGMCU Configuration Register
+0x5C001004 C FIELD 00w01 DBGSLEEP_D1: Allow D1 domain debug in Sleep mode
+0x5C001004 C FIELD 01w01 DBGSTOP_D1: Allow D1 domain debug in Stop mode
+0x5C001004 C FIELD 02w01 DBGSTBY_D1: Allow D1 domain debug in Standby mode
+0x5C001004 C FIELD 20w01 TRACECLKEN: Trace port clock enable
+0x5C001004 C FIELD 21w01 D1DBGCKEN: D1 debug clock enable
+0x5C001004 C FIELD 22w01 D3DBGCKEN: D3 debug clock enable
0x5C001004 C FIELD 28w01 TRGOEN: External trigger output enable
-0x5C001034 B REGISTER APB3FZ1 (rw): APB3 peripheral freeze register
-0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug mode
-0x5C00103C B REGISTER APB1LFZ1 (rw): APB1L peripheral freeze register
-0x5C00103C C FIELD 00w01 TIM2: TIM2 stop in debug mode
-0x5C00103C C FIELD 01w01 TIM3: TIM3 stop in debug mode
-0x5C00103C C FIELD 02w01 TIM4: TIM4 stop in debug mode
-0x5C00103C C FIELD 03w01 TIM5: TIM5 stop in debug mode
-0x5C00103C C FIELD 04w01 TIM6: TIM6 stop in debug mode
-0x5C00103C C FIELD 05w01 TIM7: TIM7 stop in debug mode
-0x5C00103C C FIELD 06w01 TIM12: TIM12 stop in debug mode
-0x5C00103C C FIELD 07w01 TIM13: TIM13 stop in debug mode
-0x5C00103C C FIELD 08w01 TIM14: TIM14 stop in debug mode
-0x5C00103C C FIELD 09w01 LPTIM1: LPTIM1 stop in debug mode
-0x5C00103C C FIELD 21w01 I2C1: I2C1 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 22w01 I2C2: I2C2 SMBUS timeout stop in debug mode
-0x5C00103C C FIELD 23w01 I2C3: I2C3 SMBUS timeout stop in debug mode
-0x5C00104C B REGISTER APB2FZ1 (rw): APB2 peripheral freeze register
-0x5C00104C C FIELD 00w01 TIM1: TIM1 stop in debug mode
-0x5C00104C C FIELD 01w01 TIM8: TIM8 stop in debug mode
-0x5C00104C C FIELD 16w01 TIM15: TIM15 stop in debug mode
-0x5C00104C C FIELD 17w01 TIM16: TIM16 stop in debug mode
-0x5C00104C C FIELD 18w01 TIM17: TIM17 stop in debug mode
-0x5C00104C C FIELD 29w01 HRTIM: HRTIM stop in debug mode
-0x5C001054 B REGISTER APB4FZ1 (rw): APB4 peripheral freeze register
-0x5C001054 C FIELD 07w01 I2C4: I2C4 SMBUS timeout stop in debug mode
-0x5C001054 C FIELD 09w01 LPTIM2: LPTIM2 stop in debug mode
-0x5C001054 C FIELD 10w01 LPTIM3: LPTIM3 stop in debug mode
-0x5C001054 C FIELD 11w01 LPTIM4: LPTIM4 stop in debug mode
-0x5C001054 C FIELD 12w01 LPTIM5: LPTIM5 stop in debug mode
-0x5C001054 C FIELD 16w01 RTC: RTC stop in debug mode
-0x5C001054 C FIELD 18w01 IWDG1: Independent watchdog for D1 stop in debug mode
+0x5C001034 B REGISTER APB3FZ1 (rw): DBGMCU APB3 peripheral freeze register
+0x5C001034 C FIELD 06w01 WWDG1: WWDG1 stop in debug
+0x5C00103C B REGISTER APB1LFZ1 (rw): DBGMCU APB1L peripheral freeze register
+0x5C00103C C FIELD 00w01 DBG_TIM2: TIM2 stop in debug
+0x5C00103C C FIELD 01w01 DBG_TIM3: TIM3 stop in debug
+0x5C00103C C FIELD 02w01 DBG_TIM4: TIM4 stop in debug
+0x5C00103C C FIELD 03w01 DBG_TIM5: TIM5 stop in debug
+0x5C00103C C FIELD 04w01 DBG_TIM6: TIM6 stop in debug
+0x5C00103C C FIELD 05w01 DBG_TIM7: TIM7 stop in debug
+0x5C00103C C FIELD 06w01 DBG_TIM12: TIM12 stop in debug
+0x5C00103C C FIELD 07w01 DBG_TIM13: TIM13 stop in debug
+0x5C00103C C FIELD 08w01 DBG_TIM14: TIM14 stop in debug
+0x5C00103C C FIELD 09w01 DBG_LPTIM1: LPTIM1 stop in debug
+0x5C00103C C FIELD 21w01 DBG_I2C1: I2C1 SMBUS timeout stop in debug
+0x5C00103C C FIELD 22w01 DBG_I2C2: I2C2 SMBUS timeout stop in debug
+0x5C00103C C FIELD 23w01 DBG_I2C3: I2C3 SMBUS timeout stop in debug
+0x5C00104C B REGISTER APB2FZ1 (rw): DBGMCU APB2 peripheral freeze register
+0x5C00104C C FIELD 00w01 DBG_TIM1: TIM1 stop in debug
+0x5C00104C C FIELD 01w01 DBG_TIM8: TIM8 stop in debug
+0x5C00104C C FIELD 16w01 DBG_TIM15: TIM15 stop in debug
+0x5C00104C C FIELD 17w01 DBG_TIM16: TIM16 stop in debug
+0x5C00104C C FIELD 18w01 DBG_TIM17: TIM17 stop in debug
+0x5C00104C C FIELD 29w01 DBG_HRTIM: HRTIM stop in debug
+0x5C001054 B REGISTER APB4FZ1 (rw): DBGMCU APB4 peripheral freeze register
+0x5C001054 C FIELD 07w01 DBG_I2C4: I2C4 SMBUS timeout stop in debug
+0x5C001054 C FIELD 09w01 DBG_LPTIM2: LPTIM2 stop in debug
+0x5C001054 C FIELD 10w01 DBG_LPTIM3: LPTIM2 stop in debug
+0x5C001054 C FIELD 11w01 DBG_LPTIM4: LPTIM4 stop in debug
+0x5C001054 C FIELD 12w01 DBG_LPTIM5: LPTIM5 stop in debug
+0x5C001054 C FIELD 16w01 DBG_RTC: RTC stop in debug
+0x5C001054 C FIELD 18w01 DBG_WDGLSD1: Independent watchdog for D1 stop in debug
0xE000E008 A PERIPHERAL SCB_ACTRL
0xE000E008 B REGISTER ACTRL (rw): Auxiliary control register
0xE000E008 C FIELD 02w01 DISFOLD: DISFOLD
@@ -21971,7 +21966,7 @@
0xE000ED20 B REGISTER SHPR3 (rw): System handler priority registers
0xE000ED20 C FIELD 16w08 PRI_14: Priority of system handler 14
0xE000ED20 C FIELD 24w08 PRI_15: Priority of system handler 15
-0xE000ED24 B REGISTER SHCRS (rw): System handler control and state register
+0xE000ED24 B REGISTER SHCSR (rw): System handler control and state register
0xE000ED24 C FIELD 00w01 MEMFAULTACT: Memory management fault exception active bit
0xE000ED24 C FIELD 01w01 BUSFAULTACT: Bus fault exception active bit
0xE000ED24 C FIELD 03w01 USGFAULTACT: Usage fault exception active bit
@@ -22048,7 +22043,7 @@
0xE000ED90 C FIELD 00w01 SEPARATE: Separate flag
0xE000ED90 C FIELD 08w08 DREGION: Number of MPU data regions
0xE000ED90 C FIELD 16w08 IREGION: Number of MPU instruction regions
-0xE000ED94 B REGISTER MPU_CTRL (ro): MPU control register
+0xE000ED94 B REGISTER MPU_CTRL (rw): MPU control register
0xE000ED94 C FIELD 00w01 ENABLE: Enables the MPU
0xE000ED94 C FIELD 01w01 HFNMIENA: Enables the operation of MPU during hard fault
0xE000ED94 C FIELD 02w01 PRIVDEFENA: Enable priviliged software access to default memory map
Raw
stm32h7b3.mmap.diff
This file has been truncated, but you can view the full file.
--- ./mmaps_old/stm32h7b3.mmap 2021-06-06 20:39:56.530000000 -0500
+++ mmaps_new/stm32h7b3.mmap 2021-06-06 20:39:04.730000000 -0500
@@ -91,7 +91,7 @@
0x4000001C C FIELD 11w01 OC4PE: OC4PE
0x4000001C C FIELD 12w03 OC4M: OC4M
0x4000001C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000001C C FIELD 15w01 OC4CE: O24CE
+0x4000001C C FIELD 15w01 OC4CE: OC4CE
0x4000001C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000001C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000020 B REGISTER CCER (rw): capture/compare enable register
@@ -226,7 +226,7 @@
0x4000041C C FIELD 11w01 OC4PE: OC4PE
0x4000041C C FIELD 12w03 OC4M: OC4M
0x4000041C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000041C C FIELD 15w01 OC4CE: O24CE
+0x4000041C C FIELD 15w01 OC4CE: OC4CE
0x4000041C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000041C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000420 B REGISTER CCER (rw): capture/compare enable register
@@ -367,7 +367,7 @@
0x4000081C C FIELD 11w01 OC4PE: OC4PE
0x4000081C C FIELD 12w03 OC4M: OC4M
0x4000081C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000081C C FIELD 15w01 OC4CE: O24CE
+0x4000081C C FIELD 15w01 OC4CE: OC4CE
0x4000081C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000081C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000820 B REGISTER CCER (rw): capture/compare enable register
@@ -508,7 +508,7 @@
0x40000C1C C FIELD 11w01 OC4PE: OC4PE
0x40000C1C C FIELD 12w03 OC4M: OC4M
0x40000C1C C FIELD 12w04 IC4F: Input capture 4 filter
-0x40000C1C C FIELD 15w01 OC4CE: O24CE
+0x40000C1C C FIELD 15w01 OC4CE: OC4CE
0x40000C1C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x40000C1C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40000C20 B REGISTER CCER (rw): capture/compare enable register
@@ -691,7 +691,7 @@
0x4000181C C FIELD 11w01 OC4PE: OC4PE
0x4000181C C FIELD 12w03 OC4M: OC4M
0x4000181C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000181C C FIELD 15w01 O24CE: O24CE
+0x4000181C C FIELD 15w01 OC4CE: OC4CE
0x4000181C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000181C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40001820 B REGISTER CCER (rw): capture/compare enable register
@@ -832,7 +832,7 @@
0x40001C1C C FIELD 11w01 OC4PE: OC4PE
0x40001C1C C FIELD 12w03 OC4M: OC4M
0x40001C1C C FIELD 12w04 IC4F: Input capture 4 filter
-0x40001C1C C FIELD 15w01 O24CE: O24CE
+0x40001C1C C FIELD 15w01 OC4CE: OC4CE
0x40001C1C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x40001C1C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40001C20 B REGISTER CCER (rw): capture/compare enable register
@@ -973,7 +973,7 @@
0x4000201C C FIELD 11w01 OC4PE: OC4PE
0x4000201C C FIELD 12w03 OC4M: OC4M
0x4000201C C FIELD 12w04 IC4F: Input capture 4 filter
-0x4000201C C FIELD 15w01 O24CE: O24CE
+0x4000201C C FIELD 15w01 OC4CE: OC4CE
0x4000201C C FIELD 16w01 OC3M_3: Output Compare 1 mode - bit 3
0x4000201C C FIELD 24w01 OC4M_3: Output Compare 2 mode - bit 3
0x40002020 B REGISTER CCER (rw): capture/compare enable register
@@ -3156,10 +3156,7 @@
0x4000A0F8 B REGISTER TXEFA (rw): FDCAN Tx Event FIFO Acknowledge Register
0x4000A0F8 C FIELD 00w05 EFAI: Event FIFO Acknowledge Index
0x4000A100 B REGISTER TTTMC (rw): FDCAN TT Trigger Memory Configuration Register
-0x4000A100 B REGISTER TTTS (rw): FDCAN TT Trigger Select Register
-0x4000A100 C FIELD 00w02 SWTDEL: Stop watch trigger input selection
0x4000A100 C FIELD 02w14 TMSA: Trigger Memory Start Address
-0x4000A100 C FIELD 04w02 EVTSEL: Event trigger input selection
0x4000A100 C FIELD 16w07 TME: Trigger Memory Elements
0x4000A104 B REGISTER TTRMC (rw): FDCAN TT Reference Message Configuration Register
0x4000A104 C FIELD 00w29 RID: Reference Identifier.
@@ -3294,6 +3291,9 @@
0x4000A13C C FIELD 16w16 SWV: Stop Watch Value
0x4000A140 B REGISTER TTCSM (ro): FDCAN TT Cycle Sync Mark Register
0x4000A140 C FIELD 00w16 CSM: Cycle Sync Mark
+0x4000A300 B REGISTER TTTS (rw): FDCAN TT Trigger Select Register
+0x4000A300 C FIELD 00w02 SWTDEL: Stop watch trigger input selection
+0x4000A300 C FIELD 04w02 EVTSEL: Event trigger input selection
0x4000A400 A PERIPHERAL FDCAN2
0x4000A400 B REGISTER CREL (ro): FDCAN Core Release Register
0x4000A400 C FIELD 00w08 DAY: Timestamp Day
@@ -3757,33 +3757,464 @@
0x4000A700 C FIELD 00w02 SWTDEL: Stop watch trigger input selection
0x4000A700 C FIELD 04w02 EVTSEL: Event trigger input selection
0x4000A800 A PERIPHERAL CAN_CCU
-0x4000A800 B REGISTER CREL (rw): Clock Calibration Unit Core Release Register
-0x4000A800 C FIELD 00w08 DAY: Time Stamp Day
-0x4000A800 C FIELD 08w08 MON: Time Stamp Month
-0x4000A800 C FIELD 16w04 YEAR: Time Stamp Year
-0x4000A800 C FIELD 20w04 SUBSTEP: Sub-step of Core Release
-0x4000A800 C FIELD 24w04 STEP: Step of Core Release
-0x4000A800 C FIELD 28w04 REL: Core Release
-0x4000A804 B REGISTER CCFG (rw): Calibration Configuration Register
-0x4000A804 C FIELD 00w05 TQBT: Time Quanta per Bit Time
-0x4000A804 C FIELD 06w01 BCC: Bypass Clock Calibration
-0x4000A804 C FIELD 07w01 CFL: Calibration Field Length
-0x4000A804 C FIELD 08w08 OCPM: Oscillator Clock Periods Minimum
-0x4000A804 C FIELD 16w04 CDIV: Clock Divider
-0x4000A804 C FIELD 31w01 SWR: Software Reset
-0x4000A808 B REGISTER CSTAT (rw): Calibration Status Register
-0x4000A808 C FIELD 00w18 OCPC: Oscillator Clock Period Counter
-0x4000A808 C FIELD 18w11 TQC: Time Quanta Counter
-0x4000A808 C FIELD 30w02 CALS: Calibration State
-0x4000A80C B REGISTER CWD (rw): Calibration Watchdog Register
-0x4000A80C C FIELD 00w16 WDC: WDC
-0x4000A80C C FIELD 16w16 WDV: WDV
-0x4000A810 B REGISTER IR (rw): Clock Calibration Unit Interrupt Register
-0x4000A810 C FIELD 00w01 CWE: Calibration Watchdog Event
-0x4000A810 C FIELD 01w01 CSC: Calibration State Changed
-0x4000A814 B REGISTER IE (rw): Clock Calibration Unit Interrupt Enable Register
-0x4000A814 C FIELD 00w01 CWEE: Calibration Watchdog Event Enable
-0x4000A814 C FIELD 01w01 CSCE: Calibration State Changed Enable
+0x4000A800 B REGISTER FDCAN_CREL (ro): FDCAN Core Release Register
+0x4000A800 C FIELD 00w08 DAY: Timestamp Day
+0x4000A800 C FIELD 08w08 MON: Timestamp Month
+0x4000A800 C FIELD 16w04 YEAR: Timestamp Year
+0x4000A800 C FIELD 20w04 SUBSTEP: Sub-step of Core release
+0x4000A800 C FIELD 24w04 STEP: Step of Core release
+0x4000A800 C FIELD 28w04 REL: Core release
+0x4000A804 B REGISTER FDCAN_ENDN (ro): FDCAN Core Release Register
+0x4000A804 C FIELD 00w32 ETV: Endiannes Test Value
+0x4000A80C B REGISTER FDCAN_DBTP (ro): FDCAN Data Bit Timing and Prescaler Register
+0x4000A80C C FIELD 00w04 DSJW: Synchronization Jump Width
+0x4000A80C C FIELD 04w04 DTSEG2: Data time segment after sample point
+0x4000A80C C FIELD 08w05 DTSEG1: Data time segment after sample point
+0x4000A80C C FIELD 16w05 DBRP: Data BIt Rate Prescaler
+0x4000A80C C FIELD 23w01 TDC: Transceiver Delay Compensation
+0x4000A810 B REGISTER FDCAN_TEST (ro): FDCAN Test Register
+0x4000A810 C FIELD 04w01 LBCK: Loop Back mode
+0x4000A810 C FIELD 05w02 TX: Loop Back mode
+0x4000A810 C FIELD 07w01 RX: Control of Transmit Pin
+0x4000A814 B REGISTER FDCAN_RWD (ro): FDCAN RAM Watchdog Register
+0x4000A814 C FIELD 00w08 WDC: Watchdog configuration
+0x4000A814 C FIELD 08w08 WDV: Watchdog value
+0x4000A818 B REGISTER FDCAN_CCCR (rw): FDCAN CC Control Register
+0x4000A818 C FIELD 00w01 INIT: Initialization
+0x4000A818 C FIELD 01w01 CCE: Configuration Change Enable
+0x4000A818 C FIELD 02w01 ASM: ASM Restricted Operation Mode
+0x4000A818 C FIELD 03w01 CSA: Clock Stop Acknowledge
+0x4000A818 C FIELD 04w01 CSR: Clock Stop Request
+0x4000A818 C FIELD 05w01 MON: Bus Monitoring Mode
+0x4000A818 C FIELD 06w01 DAR: Disable Automatic Retransmission
+0x4000A818 C FIELD 07w01 TEST: Test Mode Enable
+0x4000A818 C FIELD 08w01 FDOE: FD Operation Enable
+0x4000A818 C FIELD 09w01 BSE: FDCAN Bit Rate Switching
+0x4000A818 C FIELD 12w01 PXHD: Protocol Exception Handling Disable
+0x4000A818 C FIELD 13w01 EFBI: Edge Filtering during Bus Integration
+0x4000A818 C FIELD 14w01 TXP: TXP
+0x4000A818 C FIELD 15w01 NISO: Non ISO Operation
+0x4000A81C B REGISTER FDCAN_NBTP (rw): FDCAN Nominal Bit Timing and Prescaler Register
+0x4000A81C C FIELD 00w07 TSEG2: Nominal Time segment after sample point
+0x4000A81C C FIELD 08w08 NTSEG1: Nominal Time segment before sample point
+0x4000A81C C FIELD 16w09 NBRP: Bit Rate Prescaler
+0x4000A81C C FIELD 25w07 NSJW: NSJW: Nominal (Re)Synchronization Jump Width
+0x4000A820 B REGISTER FDCAN_TSCC (rw): FDCAN Timestamp Counter Configuration Register
+0x4000A820 C FIELD 00w02 TSS: Timestamp Select
+0x4000A820 C FIELD 16w04 TCP: Timestamp Counter Prescaler
+0x4000A824 B REGISTER FDCAN_TSCV (rw): FDCAN Timestamp Counter Value Register
+0x4000A824 C FIELD 00w16 TSC: Timestamp Counter
+0x4000A828 B REGISTER FDCAN_TOCC (rw): FDCAN Timeout Counter Configuration Register
+0x4000A828 C FIELD 00w01 ETOC: Enable Timeout Counter
+0x4000A828 C FIELD 01w02 TOS: Timeout Select
+0x4000A828 C FIELD 16w16 TOP: Timeout Period
+0x4000A82C B REGISTER FDCAN_TOCV (rw): FDCAN Timeout Counter Value Register
+0x4000A82C C FIELD 00w16 TOC: Timeout Counter
+0x4000A840 B REGISTER FDCAN_ECR (rw): FDCAN Error Counter Register
+0x4000A840 C FIELD 00w08 TEC: Transmit Error Counter
+0x4000A840 C FIELD 08w07 TREC: Receive Error Counter
+0x4000A840 C FIELD 15w01 RP: Receive Error Passive
+0x4000A840 C FIELD 16w08 CEL: AN Error Logging
+0x4000A844 B REGISTER FDCAN_PSR (rw): FDCAN Protocol Status Register
+0x4000A844 C FIELD 00w03 LEC: Last Error Code
+0x4000A844 C FIELD 03w02 ACT: Activity
+0x4000A844 C FIELD 05w01 EP: Error Passive
+0x4000A844 C FIELD 06w01 EW: Warning Status
+0x4000A844 C FIELD 07w01 BO: Bus_Off Status
+0x4000A844 C FIELD 08w03 DLEC: Data Last Error Code
+0x4000A844 C FIELD 11w01 RESI: ESI flag of last received FDCAN Message
+0x4000A844 C FIELD 12w01 RBRS: BRS flag of last received FDCAN Message
+0x4000A844 C FIELD 13w01 REDL: Received FDCAN Message
+0x4000A844 C FIELD 14w01 PXE: Protocol Exception Event
+0x4000A844 C FIELD 16w07 TDCV: Transmitter Delay Compensation Value
+0x4000A848 B REGISTER FDCAN_TDCR (ro): FDCAN Transmitter Delay Compensation Register
+0x4000A848 C FIELD 00w07 TDCF: Transmitter Delay Compensation Filter Window Length
+0x4000A848 C FIELD 08w07 TDCO: Transmitter Delay Compensation Offset
+0x4000A850 B REGISTER FDCAN_IR (ro): FDCAN Interrupt Register
+0x4000A850 C FIELD 00w01 RF0N: Rx FIFO 0 New Message
+0x4000A850 C FIELD 01w01 RF0W: Rx FIFO 0 Full
+0x4000A850 C FIELD 02w01 RF0F: Rx FIFO 0 Full
+0x4000A850 C FIELD 03w01 RF0L: Rx FIFO 0 Message Lost
+0x4000A850 C FIELD 04w01 RF1N: Rx FIFO 1 New Message
+0x4000A850 C FIELD 05w01 RF1W: Rx FIFO 1 Watermark Reached
+0x4000A850 C FIELD 06w01 RF1F: Rx FIFO 1 Watermark Reached
+0x4000A850 C FIELD 07w01 RF1L: Rx FIFO 1 Message Lost
+0x4000A850 C FIELD 08w01 HPM: High Priority Message
+0x4000A850 C FIELD 09w01 TC: Transmission Completed
+0x4000A850 C FIELD 10w01 TCF: Transmission Cancellation Finished
+0x4000A850 C FIELD 11w01 TEF: Tx FIFO Empty
+0x4000A850 C FIELD 12w01 TEFN: Tx Event FIFO New Entry
+0x4000A850 C FIELD 13w01 TEFW: Tx Event FIFO Watermark Reached
+0x4000A850 C FIELD 14w01 TEFF: Tx Event FIFO Full
+0x4000A850 C FIELD 15w01 TEFL: Tx Event FIFO Element Lost
+0x4000A850 C FIELD 16w01 TSW: Timestamp Wraparound
+0x4000A850 C FIELD 17w01 MRAF: Message RAM Access Failure
+0x4000A850 C FIELD 18w01 TOO: Timeout Occurred
+0x4000A850 C FIELD 19w01 DRX: Message stored to Dedicated Rx Buffer
+0x4000A850 C FIELD 22w01 ELO: Error Logging Overflow
+0x4000A850 C FIELD 23w01 EP: Error Passive
+0x4000A850 C FIELD 24w01 EW: Warning Status
+0x4000A850 C FIELD 25w01 BO: Bus_Off Status
+0x4000A850 C FIELD 26w01 WDI: Watchdog Interrupt
+0x4000A850 C FIELD 27w01 PEA: Protocol Error in Arbitration Phase (Nominal Bit Time is used)
+0x4000A850 C FIELD 28w01 PED: Protocol Error in Data Phase (Data Bit Time is used)
+0x4000A850 C FIELD 29w01 ARA: Access to Reserved Address
+0x4000A854 B REGISTER FDCAN_IE (rw): FDCAN Interrupt Enable Register
+0x4000A854 C FIELD 00w01 RF0NE: Rx FIFO 0 New Message Enable
+0x4000A854 C FIELD 01w01 RF0WE: Rx FIFO 0 Full Enable
+0x4000A854 C FIELD 02w01 RF0FE: Rx FIFO 0 Full Enable
+0x4000A854 C FIELD 03w01 RF0LE: Rx FIFO 0 Message Lost Enable
+0x4000A854 C FIELD 04w01 RF1NE: Rx FIFO 1 New Message Enable
+0x4000A854 C FIELD 05w01 RF1WE: Rx FIFO 1 Watermark Reached Enable
+0x4000A854 C FIELD 06w01 RF1FE: Rx FIFO 1 Watermark Reached Enable
+0x4000A854 C FIELD 07w01 RF1LE: Rx FIFO 1 Message Lost Enable
+0x4000A854 C FIELD 08w01 HPME: High Priority Message Enable
+0x4000A854 C FIELD 09w01 TCE: Transmission Completed Enable
+0x4000A854 C FIELD 10w01 TCFE: Transmission Cancellation Finished Enable
+0x4000A854 C FIELD 11w01 TEFE: Tx FIFO Empty Enable
+0x4000A854 C FIELD 12w01 TEFNE: Tx Event FIFO New Entry Enable
+0x4000A854 C FIELD 13w01 TEFWE: Tx Event FIFO Watermark Reached Enable
+0x4000A854 C FIELD 14w01 TEFFE: Tx Event FIFO Full Enable
+0x4000A854 C FIELD 15w01 TEFLE: Tx Event FIFO Element Lost Enable
+0x4000A854 C FIELD 16w01 TSWE: Timestamp Wraparound Enable
+0x4000A854 C FIELD 17w01 MRAFE: Message RAM Access Failure Enable
+0x4000A854 C FIELD 18w01 TOOE: Timeout Occurred Enable
+0x4000A854 C FIELD 19w01 DRXE: Message stored to Dedicated Rx Buffer Enable
+0x4000A854 C FIELD 20w01 BECE: Bit Error Corrected Interrupt Enable
+0x4000A854 C FIELD 21w01 BEUE: Bit Error Uncorrected Interrupt Enable
+0x4000A854 C FIELD 22w01 ELOE: Error Logging Overflow Enable
+0x4000A854 C FIELD 23w01 EPE: Error Passive Enable
+0x4000A854 C FIELD 24w01 EWE: Warning Status Enable
+0x4000A854 C FIELD 25w01 BOE: Bus_Off Status Enable
+0x4000A854 C FIELD 26w01 WDIE: Watchdog Interrupt Enable
+0x4000A854 C FIELD 27w01 PEAE: Protocol Error in Arbitration Phase Enable
+0x4000A854 C FIELD 28w01 PEDE: Protocol Error in Data Phase Enable
+0x4000A854 C FIELD 29w01 ARAE: Access to Reserved Address Enable
+0x4000A858 B REGISTER FDCAN_ILS (ro): FDCAN Interrupt Line Select Register
+0x4000A858 C FIELD 00w01 RF0NL: Rx FIFO 0 New Message Interrupt Line
+0x4000A858 C FIELD 01w01 RF0WL: Rx FIFO 0 Watermark Reached Interrupt Line
+0x4000A858 C FIELD 02w01 RF0FL: Rx FIFO 0 Full Interrupt Line
+0x4000A858 C FIELD 03w01 RF0LL: Rx FIFO 0 Message Lost Interrupt Line
+0x4000A858 C FIELD 04w01 RF1NL: Rx FIFO 1 New Message Interrupt Line
+0x4000A858 C FIELD 05w01 RF1WL: Rx FIFO 1 Watermark Reached Interrupt Line
+0x4000A858 C FIELD 06w01 RF1FL: Rx FIFO 1 Full Interrupt Line
+0x4000A858 C FIELD 07w01 RF1LL: Rx FIFO 1 Message Lost Interrupt Line
+0x4000A858 C FIELD 08w01 HPML: High Priority Message Interrupt Line
+0x4000A858 C FIELD 09w01 TCL: Transmission Completed Interrupt Line
+0x4000A858 C FIELD 10w01 TCFL: Transmission Cancellation Finished Interrupt Line
+0x4000A858 C FIELD 11w01 TEFL: Tx FIFO Empty Interrupt Line
+0x4000A858 C FIELD 12w01 TEFNL: Tx Event FIFO New Entry Interrupt Line
+0x4000A858 C FIELD 13w01 TEFWL: Tx Event FIFO Watermark Reached Interrupt Line
+0x4000A858 C FIELD 14w01 TEFFL: Tx Event FIFO Full Interrupt Line
+0x4000A858 C FIELD 15w01 TEFLL: Tx Event FIFO Element Lost Interrupt Line
+0x4000A858 C FIELD 16w01 TSWL: Timestamp Wraparound Interrupt Line
+0x4000A858 C FIELD 17w01 MRAFL: Message RAM Access Failure Interrupt Line
+0x4000A858 C FIELD 18w01 TOOL: Timeout Occurred Interrupt Line
+0x4000A858 C FIELD 19w01 DRXL: Message stored to Dedicated Rx Buffer Interrupt Line
+0x4000A858 C FIELD 20w01 BECL: Bit Error Corrected Interrupt Line
+0x4000A858 C FIELD 21w01 BEUL: Bit Error Uncorrected Interrupt Line
+0x4000A858 C FIELD 22w01 ELOL: Error Logging Overflow Interrupt Line
+0x4000A858 C FIELD 23w01 EPL: Error Passive Interrupt Line
+0x4000A858 C FIELD 24w01 EWL: Warning Status Interrupt Line
+0x4000A858 C FIELD 25w01 BOL: Bus_Off Status
+0x4000A858 C FIELD 26w01 WDIL: Watchdog Interrupt Line
+0x4000A858 C FIELD 27w01 PEAL: Protocol Error in Arbitration Phase Line
+0x4000A858 C FIELD 28w01 PEDL: Protocol Error in Data Phase Line
+0x4000A858 C FIELD 29w01 ARAL: Access to Reserved Address Line
+0x4000A85C B REGISTER FDCAN_ILE (rw): FDCAN Interrupt Line Enable Register
+0x4000A85C C FIELD 00w01 EINT0: Enable Interrupt Line 0
+0x4000A85C C FIELD 01w01 EINT1: Enable Interrupt Line 1
+0x4000A880 B REGISTER FDCAN_GFC (rw): FDCAN Global Filter Configuration Register
+0x4000A880 C FIELD 00w01 RRFE: Reject Remote Frames Extended
+0x4000A880 C FIELD 01w01 RRFS: Reject Remote Frames Standard
+0x4000A880 C FIELD 02w02 ANFE: Accept Non-matching Frames Extended
+0x4000A880 C FIELD 04w02 ANFS: Accept Non-matching Frames Standard
+0x4000A884 B REGISTER FDCAN_SIDFC (rw): FDCAN Standard ID Filter Configuration Register
+0x4000A884 C FIELD 02w14 FLSSA: Filter List Standard Start Address
+0x4000A884 C FIELD 16w08 LSS: List Size Standard
+0x4000A888 B REGISTER FDCAN_XIDFC (rw): FDCAN Extended ID Filter Configuration Register
+0x4000A888 C FIELD 02w14 FLESA: Filter List Standard Start Address
+0x4000A888 C FIELD 16w08 LSE: List Size Extended
+0x4000A890 B REGISTER FDCAN_XIDAM (rw): FDCAN Extended ID and Mask Register
+0x4000A890 C FIELD 00w29 EIDM: Extended ID Mask
+0x4000A894 B REGISTER FDCAN_HPMS (ro): FDCAN High Priority Message Status Register
+0x4000A894 C FIELD 00w06 BIDX: Buffer Index
+0x4000A894 C FIELD 06w02 MSI: Message Storage Indicator
+0x4000A894 C FIELD 08w07 FIDX: Filter Index
+0x4000A894 C FIELD 15w01 FLST: Filter List
+0x4000A898 B REGISTER FDCAN_NDAT1 (ro): FDCAN New Data 1 Register
+0x4000A898 C FIELD 00w01 ND0: New data
+0x4000A898 C FIELD 01w01 ND1: New data
+0x4000A898 C FIELD 02w01 ND2: New data
+0x4000A898 C FIELD 03w01 ND3: New data
+0x4000A898 C FIELD 04w01 ND4: New data
+0x4000A898 C FIELD 05w01 ND5: New data
+0x4000A898 C FIELD 06w01 ND6: New data
+0x4000A898 C FIELD 07w01 ND7: New data
+0x4000A898 C FIELD 08w01 ND8: New data
+0x4000A898 C FIELD 09w01 ND9: New data
+0x4000A898 C FIELD 10w01 ND10: New data
+0x4000A898 C FIELD 11w01 ND11: New data
+0x4000A898 C FIELD 12w01 ND12: New data
+0x4000A898 C FIELD 13w01 ND13: New data
+0x4000A898 C FIELD 14w01 ND14: New data
+0x4000A898 C FIELD 15w01 ND15: New data
+0x4000A898 C FIELD 16w01 ND16: New data
+0x4000A898 C FIELD 17w01 ND17: New data
+0x4000A898 C FIELD 18w01 ND18: New data
+0x4000A898 C FIELD 19w01 ND19: New data
+0x4000A898 C FIELD 20w01 ND20: New data
+0x4000A898 C FIELD 21w01 ND21: New data
+0x4000A898 C FIELD 22w01 ND22: New data
+0x4000A898 C FIELD 23w01 ND23: New data
+0x4000A898 C FIELD 24w01 ND24: New data
+0x4000A898 C FIELD 25w01 ND25: New data
+0x4000A898 C FIELD 26w01 ND26: New data
+0x4000A898 C FIELD 27w01 ND27: New data
+0x4000A898 C FIELD 28w01 ND28: New data
+0x4000A898 C FIELD 29w01 ND29: New data
+0x4000A898 C FIELD 30w01 ND30: New data
+0x4000A898 C FIELD 31w01 ND31: New data
+0x4000A89C B REGISTER FDCAN_NDAT2 (ro): FDCAN New Data 2 Register
+0x4000A89C C FIELD 00w01 ND32: New data
+0x4000A89C C FIELD 01w01 ND33: New data
+0x4000A89C C FIELD 02w01 ND34: New data
+0x4000A89C C FIELD 03w01 ND35: New data
+0x4000A89C C FIELD 04w01 ND36: New data
+0x4000A89C C FIELD 05w01 ND37: New data
+0x4000A89C C FIELD 06w01 ND38: New data
+0x4000A89C C FIELD 07w01 ND39: New data
+0x4000A89C C FIELD 08w01 ND40: New data
+0x4000A89C C FIELD 09w01 ND41: New data
+0x4000A89C C FIELD 10w01 ND42: New data
+0x4000A89C C FIELD 11w01 ND43: New data
+0x4000A89C C FIELD 12w01 ND44: New data
+0x4000A89C C FIELD 13w01 ND45: New data
+0x4000A89C C FIELD 14w01 ND46: New data
+0x4000A89C C FIELD 15w01 ND47: New data
+0x4000A89C C FIELD 16w01 ND48: New data
+0x4000A89C C FIELD 17w01 ND49: New data
+0x4000A89C C FIELD 18w01 ND50: New data
+0x4000A89C C FIELD 19w01 ND51: New data
+0x4000A89C C FIELD 20w01 ND52: New data
+0x4000A89C C FIELD 21w01 ND53: New data
+0x4000A89C C FIELD 22w01 ND54: New data
+0x4000A89C C FIELD 23w01 ND55: New data
+0x4000A89C C FIELD 24w01 ND56: New data
+0x4000A89C C FIELD 25w01 ND57: New data
+0x4000A89C C FIELD 26w01 ND58: New data
+0x4000A89C C FIELD 27w01 ND59: New data
+0x4000A89C C FIELD 28w01 ND60: New data
+0x4000A89C C FIELD 29w01 ND61: New data
+0x4000A89C C FIELD 30w01 ND62: New data
+0x4000A89C C FIELD 31w01 ND63: New data
+0x4000A8A0 B REGISTER FDCAN_RXF0C (rw): FDCAN Rx FIFO 0 Configuration Register
+0x4000A8A0 C FIELD 02w14 F0SA: Rx FIFO 0 Start Address
+0x4000A8A0 C FIELD 16w08 F0S: Rx FIFO 0 Size
+0x4000A8A0 C FIELD 24w08 F0WM: FIFO 0 Watermark
+0x4000A8A4 B REGISTER FDCAN_RXF0S (rw): FDCAN Rx FIFO 0 Status Register
+0x4000A8A4 C FIELD 00w07 F0FL: Rx FIFO 0 Fill Level
+0x4000A8A4 C FIELD 08w06 F0G: Rx FIFO 0 Get Index
+0x4000A8A4 C FIELD 16w06 F0P: Rx FIFO 0 Put Index
+0x4000A8A4 C FIELD 24w01 F0F: Rx FIFO 0 Full
+0x4000A8A4 C FIELD 25w01 RF0L: Rx FIFO 0 Message Lost
+0x4000A8A8 B REGISTER FDCAN_RXF0A (rw): CAN Rx FIFO 0 Acknowledge Register
+0x4000A8A8 C FIELD 00w06 FA01: Rx FIFO 0 Acknowledge Index
+0x4000A8AC B REGISTER FDCAN_RXBC (rw): FDCAN Rx Buffer Configuration Register
+0x4000A8AC C FIELD 02w14 RBSA: Rx Buffer Start Address
+0x4000A8B0 B REGISTER FDCAN_RXF1C (rw): FDCAN Rx FIFO 1 Configuration Register
+0x4000A8B0 C FIELD 02w14 F1SA: Rx FIFO 1 Start Address
+0x4000A8B0 C FIELD 16w07 F1S: Rx FIFO 1 Size
+0x4000A8B0 C FIELD 24w07 F1WM: Rx FIFO 1 Watermark
+0x4000A8B4 B REGISTER FDCAN_RXF1S (rw): FDCAN Rx FIFO 1 Status Register
+0x4000A8B4 C FIELD 00w07 F1FL: Rx FIFO 1 Fill Level
+0x4000A8B4 C FIELD 08w07 F1GI: Rx FIFO 1 Get Index
+0x4000A8B4 C FIELD 16w07 F1PI: Rx FIFO 1 Put Index
+0x4000A8B4 C FIELD 24w01 F1F: Rx FIFO 1 Full
+0x4000A8B4 C FIELD 25w01 RF1L: Rx FIFO 1 Message Lost
+0x4000A8B4 C FIELD 30w02 DMS: Debug Message Status
+0x4000A8B8 B REGISTER FDCAN_RXF1A (rw): FDCAN Rx FIFO 1 Acknowledge Register
+0x4000A8B8 C FIELD 00w06 F1AI: Rx FIFO 1 Acknowledge Index
+0x4000A8BC B REGISTER FDCAN_RXESC (rw): FDCAN Rx Buffer Element Size Configuration Register
+0x4000A8BC C FIELD 00w03 F0DS: Rx FIFO 1 Data Field Size:
+0x4000A8BC C FIELD 04w03 F1DS: Rx FIFO 0 Data Field Size:
+0x4000A8BC C FIELD 08w03 RBDS: Rx Buffer Data Field Size:
+0x4000A8C0 B REGISTER FDCAN_TXBC (rw): FDCAN Tx Buffer Configuration Register
+0x4000A8C0 C FIELD 02w14 TBSA: Tx Buffers Start Address
+0x4000A8C0 C FIELD 16w06 NDTB: Number of Dedicated Transmit Buffers
+0x4000A8C0 C FIELD 24w06 TFQS: Transmit FIFO/Queue Size
+0x4000A8C0 C FIELD 30w01 TFQM: Tx FIFO/Queue Mode
+0x4000A8C4 B REGISTER FDCAN_TXFQS (ro): FDCAN Tx FIFO/Queue Status Register
+0x4000A8C4 C FIELD 00w06 TFFL: Tx FIFO Free Level
+0x4000A8C4 C FIELD 08w05 TFGI: TFGI
+0x4000A8C4 C FIELD 16w05 TFQPI: Tx FIFO/Queue Put Index
+0x4000A8C4 C FIELD 21w01 TFQF: Tx FIFO/Queue Full
+0x4000A8C8 B REGISTER FDCAN_TXESC (rw): FDCAN Tx Buffer Element Size Configuration Register
+0x4000A8C8 C FIELD 00w03 TBDS: Tx Buffer Data Field Size:
+0x4000A8CC B REGISTER FDCAN_TXBRP (ro): FDCAN Tx Buffer Request Pending Register
+0x4000A8CC C FIELD 00w32 TRP: Transmission Request Pending
+0x4000A8D0 B REGISTER FDCAN_TXBAR (rw): FDCAN Tx Buffer Add Request Register
+0x4000A8D0 C FIELD 00w32 AR: Add Request
+0x4000A8D4 B REGISTER FDCAN_TXBCR (rw): FDCAN Tx Buffer Cancellation Request Register
+0x4000A8D4 C FIELD 00w32 CR: Cancellation Request
+0x4000A8D8 B REGISTER FDCAN_TXBTO (rw): FDCAN Tx Buffer Transmission Occurred Register
+0x4000A8D8 C FIELD 00w32 TO: Transmission Occurred.
+0x4000A8DC B REGISTER FDCAN_TXBCF (ro): FDCAN Tx Buffer Cancellation Finished Register
+0x4000A8DC C FIELD 00w32 CF: Cancellation Finished
+0x4000A8E0 B REGISTER FDCAN_TXBTIE (rw): FDCAN Tx Buffer Transmission Interrupt Enable Register
+0x4000A8E0 C FIELD 00w32 TIE: Transmission Interrupt Enable
+0x4000A8E4 B REGISTER FDCAN_TXBCIE (rw): FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
+0x4000A8E4 C FIELD 00w32 CF: Cancellation Finished Interrupt Enable
+0x4000A8F0 B REGISTER FDCAN_TXEFC (rw): FDCAN Tx Event FIFO Configuration Register
+0x4000A8F0 C FIELD 02w14 EFSA: Event FIFO Start Address
+0x4000A8F0 C FIELD 16w06 EFS: Event FIFO Size
+0x4000A8F0 C FIELD 24w06 EFWM: Event FIFO Watermark
+0x4000A8F4 B REGISTER FDCAN_TXEFS (rw): FDCAN Tx Event FIFO Status Register
+0x4000A8F4 C FIELD 00w06 EFFL: Event FIFO Fill Level
+0x4000A8F4 C FIELD 08w05 EFGI: Event FIFO Get Index.
+0x4000A8F4 C FIELD 24w01 EFF: Event FIFO Full.
+0x4000A8F4 C FIELD 25w01 TEFL: Tx Event FIFO Element Lost.
+0x4000A8F8 B REGISTER FDCAN_TXEFA (rw): FDCAN Tx Event FIFO Acknowledge Register
+0x4000A8F8 C FIELD 00w05 EFAI: Event FIFO Acknowledge Index
+0x4000A900 B REGISTER FDCAN_TTTMC (rw): FDCAN TT Trigger Memory Configuration Register
+0x4000A900 C FIELD 02w14 TMSA: Trigger Memory Start Address
+0x4000A900 C FIELD 16w07 TME: Trigger Memory Elements
+0x4000A904 B REGISTER FDCAN_TTRMC (rw): FDCAN TT Reference Message Configuration Register
+0x4000A904 C FIELD 00w29 RID: Reference Identifier.
+0x4000A904 C FIELD 30w01 XTD: Extended Identifier
+0x4000A904 C FIELD 31w01 RMPS: Reference Message Payload Select
+0x4000A908 B REGISTER FDCAN_TTOCF (rw): FDCAN TT Operation Configuration Register
+0x4000A908 C FIELD 00w02 OM: Operation Mode
+0x4000A908 C FIELD 03w01 GEN: Gap Enable
+0x4000A908 C FIELD 04w01 TM: Time Master
+0x4000A908 C FIELD 05w03 LDSDL: LD of Synchronization Deviation Limit
+0x4000A908 C FIELD 08w07 IRTO: Initial Reference Trigger Offset
+0x4000A908 C FIELD 15w01 EECS: Enable External Clock Synchronization
+0x4000A908 C FIELD 16w08 AWL: Application Watchdog Limit
+0x4000A908 C FIELD 24w01 EGTF: Enable Global Time Filtering
+0x4000A908 C FIELD 25w01 ECC: Enable Clock Calibration
+0x4000A908 C FIELD 26w01 EVTP: Event Trigger Polarity
+0x4000A90C B REGISTER FDCAN_TTMLM (rw): FDCAN TT Matrix Limits Register
+0x4000A90C C FIELD 00w06 CCM: Cycle Count Max
+0x4000A90C C FIELD 06w02 CSS: Cycle Start Synchronization
+0x4000A90C C FIELD 08w04 TXEW: Tx Enable Window
+0x4000A90C C FIELD 16w12 ENTT: Expected Number of Tx Triggers
+0x4000A910 B REGISTER FDCAN_TURCF (rw): FDCAN TUR Configuration Register
+0x4000A910 C FIELD 00w16 NCL: Numerator Configuration Low.
+0x4000A910 C FIELD 16w14 DC: Denominator Configuration.
+0x4000A910 C FIELD 31w01 ELT: Enable Local Time
+0x4000A914 B REGISTER FDCAN_TTOCN (rw): FDCAN TT Operation Control Register
+0x4000A914 C FIELD 00w01 SGT: Set Global time
+0x4000A914 C FIELD 01w01 ECS: External Clock Synchronization
+0x4000A914 C FIELD 02w01 SWP: Stop Watch Polarity
+0x4000A914 C FIELD 03w02 SWS: Stop Watch Source.
+0x4000A914 C FIELD 05w01 RTIE: Register Time Mark Interrupt Pulse Enable
+0x4000A914 C FIELD 06w02 TMC: Register Time Mark Compare
+0x4000A914 C FIELD 08w01 TTIE: Trigger Time Mark Interrupt Pulse Enable
+0x4000A914 C FIELD 09w01 GCS: Gap Control Select
+0x4000A914 C FIELD 10w01 FGP: Finish Gap.
+0x4000A914 C FIELD 11w01 TMG: Time Mark Gap
+0x4000A914 C FIELD 12w01 NIG: Next is Gap
+0x4000A914 C FIELD 13w01 ESCN: External Synchronization Control
+0x4000A914 C FIELD 15w01 LCKC: TT Operation Control Register Locked
+0x4000A918 B REGISTER CAN_TTGTP (rw): FDCAN TT Global Time Preset Register
+0x4000A918 C FIELD 00w16 NCL: Time Preset
+0x4000A918 C FIELD 16w16 CTP: Cycle Time Target Phase
+0x4000A91C B REGISTER FDCAN_TTTMK (rw): FDCAN TT Time Mark Register
+0x4000A91C C FIELD 00w16 TM: Time Mark
+0x4000A91C C FIELD 16w07 TICC: Time Mark Cycle Code
+0x4000A91C C FIELD 31w01 LCKM: TT Time Mark Register Locked
+0x4000A920 B REGISTER FDCAN_TTIR (rw): FDCAN TT Interrupt Register
+0x4000A920 C FIELD 00w01 SBC: Start of Basic Cycle
+0x4000A920 C FIELD 01w01 SMC: Start of Matrix Cycle
+0x4000A920 C FIELD 02w01 CSM: Change of Synchronization Mode
+0x4000A920 C FIELD 03w01 SOG: Start of Gap
+0x4000A920 C FIELD 04w01 RTMI: Register Time Mark Interrupt.
+0x4000A920 C FIELD 05w01 TTMI: Trigger Time Mark Event Internal
+0x4000A920 C FIELD 06w01 SWE: Stop Watch Event
+0x4000A920 C FIELD 07w01 GTW: Global Time Wrap
+0x4000A920 C FIELD 08w01 GTD: Global Time Discontinuity
+0x4000A920 C FIELD 09w01 GTE: Global Time Error
+0x4000A920 C FIELD 10w01 TXU: Tx Count Underflow
+0x4000A920 C FIELD 11w01 TXO: Tx Count Overflow
+0x4000A920 C FIELD 12w01 SE1: Scheduling Error 1
+0x4000A920 C FIELD 13w01 SE2: Scheduling Error 2
+0x4000A920 C FIELD 14w01 ELC: Error Level Changed.
+0x4000A920 C FIELD 15w01 IWTG: Initialization Watch Trigger
+0x4000A920 C FIELD 16w01 WT: Watch Trigger
+0x4000A920 C FIELD 17w01 AW: Application Watchdog
+0x4000A920 C FIELD 18w01 CER: Configuration Error
+0x4000A924 B REGISTER FDCAN_TTIE (rw): FDCAN TT Interrupt Enable Register
+0x4000A924 C FIELD 00w01 SBCE: Start of Basic Cycle Interrupt Enable
+0x4000A924 C FIELD 01w01 SMCE: Start of Matrix Cycle Interrupt Enable
+0x4000A924 C FIELD 02w01 CSME: Change of Synchronization Mode Interrupt Enable
+0x4000A924 C FIELD 03w01 SOGE: Start of Gap Interrupt Enable
+0x4000A924 C FIELD 04w01 RTMIE: Register Time Mark Interrupt Enable
+0x4000A924 C FIELD 05w01 TTMIE: Trigger Time Mark Event Internal Interrupt Enable
+0x4000A924 C FIELD 06w01 SWEE: Stop Watch Event Interrupt Enable
+0x4000A924 C FIELD 07w01 GTWE: Global Time Wrap Interrupt Enable
+0x4000A924 C FIELD 08w01 GTDE: Global Time Discontinuity Interrupt Enable
+0x4000A924 C FIELD 09w01 GTEE: Global Time Error Interrupt Enable
+0x4000A924 C FIELD 10w01 TXUE: Tx Count Underflow Interrupt Enable
+0x4000A924 C FIELD 11w01 TXOE: Tx Count Overflow Interrupt Enable
+0x4000A924 C FIELD 12w01 SE1E: Scheduling Error 1 Interrupt Enable
+0x4000A924 C FIELD 13w01 SE2E: Scheduling Error 2 Interrupt Enable
+0x4000A924 C FIELD 14w01 ELCE: Change Error Level Interrupt Enable
+0x4000A924 C FIELD 15w01 IWTGE: Initialization Watch Trigger Interrupt Enable
+0x4000A924 C FIELD 16w01 WTE: Watch Trigger Interrupt Enable
+0x4000A924 C FIELD 17w01 AWE: Application Watchdog Interrupt Enable
+0x4000A924 C FIELD 18w01 CERE: Configuration Error Interrupt Enable
+0x4000A928 B REGISTER FDCAN_TTILS (rw): FDCAN TT Interrupt Line Select Register
+0x4000A928 C FIELD 00w01 SBCL: Start of Basic Cycle Interrupt Line
+0x4000A928 C FIELD 01w01 SMCL: Start of Matrix Cycle Interrupt Line
+0x4000A928 C FIELD 02w01 CSML: Change of Synchronization Mode Interrupt Line
+0x4000A928 C FIELD 03w01 SOGL: Start of Gap Interrupt Line
+0x4000A928 C FIELD 04w01 RTMIL: Register Time Mark Interrupt Line
+0x4000A928 C FIELD 05w01 TTMIL: Trigger Time Mark Event Internal Interrupt Line
+0x4000A928 C FIELD 06w01 SWEL: Stop Watch Event Interrupt Line
+0x4000A928 C FIELD 07w01 GTWL: Global Time Wrap Interrupt Line
+0x4000A928 C FIELD 08w01 GTDL: Global Time Discontinuity Interrupt Line
+0x4000A928 C FIELD 09w01 GTEL: Global Time Error Interrupt Line
+0x4000A928 C FIELD 10w01 TXUL: Tx Count Underflow Interrupt Line
+0x4000A928 C FIELD 11w01 TXOL: Tx Count Overflow Interrupt Line
+0x4000A928 C FIELD 12w01 SE1L: Scheduling Error 1 Interrupt Line
+0x4000A928 C FIELD 13w01 SE2L: Scheduling Error 2 Interrupt Line
+0x4000A928 C FIELD 14w01 ELCL: Change Error Level Interrupt Line
+0x4000A928 C FIELD 15w01 IWTGL: Initialization Watch Trigger Interrupt Line
+0x4000A928 C FIELD 16w01 WTL: Watch Trigger Interrupt Line
+0x4000A928 C FIELD 17w01 AWL: Application Watchdog Interrupt Line
+0x4000A928 C FIELD 18w01 CERL: Configuration Error Interrupt Line
+0x4000A92C B REGISTER FDCAN_TTOST (ro): FDCAN TT Operation Status Register
+0x4000A92C C FIELD 00w02 EL: Error Level
+0x4000A92C C FIELD 02w02 MS: Master State.
+0x4000A92C C FIELD 04w02 SYS: Synchronization State
+0x4000A92C C FIELD 06w01 GTP: Quality of Global Time Phase
+0x4000A92C C FIELD 07w01 QCS: Quality of Clock Speed
+0x4000A92C C FIELD 08w08 RTO: Reference Trigger Offset
+0x4000A92C C FIELD 22w01 WGTD: Wait for Global Time Discontinuity
+0x4000A92C C FIELD 23w01 GFI: Gap Finished Indicator.
+0x4000A92C C FIELD 24w03 TMP: Time Master Priority
+0x4000A92C C FIELD 27w01 GSI: Gap Started Indicator.
+0x4000A92C C FIELD 28w01 WFE: Wait for Event
+0x4000A92C C FIELD 29w01 AWE: Application Watchdog Event
+0x4000A92C C FIELD 30w01 WECS: Wait for External Clock Synchronization
+0x4000A92C C FIELD 31w01 SPL: Schedule Phase Lock
+0x4000A930 B REGISTER FDCAN_TURNA (ro): FDCAN TUR Numerator Actual Register
+0x4000A930 C FIELD 00w18 NAV: Numerator Actual Value
+0x4000A934 B REGISTER FDCAN_TTLGT (ro): FDCAN TT Local and Global Time Register
+0x4000A934 C FIELD 00w16 LT: Local Time
+0x4000A934 C FIELD 16w16 GT: Global Time
+0x4000A938 B REGISTER FDCAN_TTCTC (ro): FDCAN TT Cycle Time and Count Register
+0x4000A938 C FIELD 00w16 CT: Cycle Time
+0x4000A938 C FIELD 16w06 CC: Cycle Count
+0x4000A93C B REGISTER FDCAN_TTCPT (ro): FDCAN TT Capture Time Register
+0x4000A93C C FIELD 00w06 CT: Cycle Count Value
+0x4000A93C C FIELD 16w16 SWV: Stop Watch Value
+0x4000A940 B REGISTER FDCAN_TTCSM (ro): FDCAN TT Cycle Sync Mark Register
+0x4000A940 C FIELD 00w16 CSM: Cycle Sync Mark
+0x4000AB00 B REGISTER FDCAN_TTTS (rw): FDCAN TT Trigger Select Register
+0x4000AB00 C FIELD 00w02 SWTDEL: Stop watch trigger input selection
+0x4000AB00 C FIELD 04w02 EVTSEL: Event trigger input selection
0x40010000 A PERIPHERAL TIM1
0x40010000 B REGISTER CR1 (rw): control register 1
0x40010000 C FIELD 00w01 CEN: Counter enable
@@ -5376,499 +5807,6 @@
0x40015C48 C FIELD 20w03 DLYM3R: Delay line for second microphone of pair 3
0x40015C48 C FIELD 24w03 DLYM4L: Delay line for first microphone of pair 4
0x40015C48 C FIELD 28w03 DLYM4R: Delay line for second microphone of pair 4
-0x40017000 A PERIPHERAL DFSDM
-0x40017000 B REGISTER DFSDM_CHCFG0R1 (rw): DFSDM channel configuration 0 register 1
-0x40017000 C FIELD 00w02 SITP: Serial interface type for channel 0
-0x40017000 C FIELD 02w02 SPICKSEL: SPI clock select for channel 0
-0x40017000 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 0
-0x40017000 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 0
-0x40017000 C FIELD 07w01 CHEN: Channel 0 enable
-0x40017000 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017000 C FIELD 12w02 DATMPX: Input data multiplexer for channel 0
-0x40017000 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017000 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017000 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017000 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017004 B REGISTER DFSDM_CHCFG1R1 (rw): DFSDM channel configuration 1 register 1
-0x40017004 C FIELD 00w02 SITP: Serial interface type for channel 1
-0x40017004 C FIELD 02w02 SPICKSEL: SPI clock select for channel 1
-0x40017004 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 1
-0x40017004 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 1
-0x40017004 C FIELD 07w01 CHEN: Channel 1 enable
-0x40017004 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017004 C FIELD 12w02 DATMPX: Input data multiplexer for channel 1
-0x40017004 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017004 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017004 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017004 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017008 B REGISTER DFSDM_CHCFG2R1 (rw): DFSDM channel configuration 2 register 1
-0x40017008 C FIELD 00w02 SITP: Serial interface type for channel 2
-0x40017008 C FIELD 02w02 SPICKSEL: SPI clock select for channel 2
-0x40017008 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 2
-0x40017008 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 2
-0x40017008 C FIELD 07w01 CHEN: Channel 2 enable
-0x40017008 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017008 C FIELD 12w02 DATMPX: Input data multiplexer for channel 2
-0x40017008 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017008 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017008 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017008 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001700C B REGISTER DFSDM_CHCFG3R1 (rw): DFSDM channel configuration 3 register 1
-0x4001700C C FIELD 00w02 SITP: Serial interface type for channel 3
-0x4001700C C FIELD 02w02 SPICKSEL: SPI clock select for channel 3
-0x4001700C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 3
-0x4001700C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 3
-0x4001700C C FIELD 07w01 CHEN: Channel 3 enable
-0x4001700C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001700C C FIELD 12w02 DATMPX: Input data multiplexer for channel 3
-0x4001700C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001700C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001700C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001700C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017010 B REGISTER DFSDM_CHCFG4R1 (rw): DFSDM channel configuration 4 register 1
-0x40017010 C FIELD 00w02 SITP: Serial interface type for channel 4
-0x40017010 C FIELD 02w02 SPICKSEL: SPI clock select for channel 4
-0x40017010 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 4
-0x40017010 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 4
-0x40017010 C FIELD 07w01 CHEN: Channel 4 enable
-0x40017010 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017010 C FIELD 12w02 DATMPX: Input data multiplexer for channel 4
-0x40017010 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017010 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017010 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017010 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017014 B REGISTER DFSDM_CHCFG5R1 (rw): DFSDM channel configuration 5 register 1
-0x40017014 C FIELD 00w02 SITP: Serial interface type for channel 5
-0x40017014 C FIELD 02w02 SPICKSEL: SPI clock select for channel 5
-0x40017014 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 5
-0x40017014 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 5
-0x40017014 C FIELD 07w01 CHEN: Channel 5 enable
-0x40017014 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017014 C FIELD 12w02 DATMPX: Input data multiplexer for channel 5
-0x40017014 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017014 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017014 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017014 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017018 B REGISTER DFSDM_CHCFG6R1 (rw): DFSDM channel configuration 6 register 1
-0x40017018 C FIELD 00w02 SITP: Serial interface type for channel 6
-0x40017018 C FIELD 02w02 SPICKSEL: SPI clock select for channel 6
-0x40017018 C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 6
-0x40017018 C FIELD 06w01 CKABEN: Clock absence detector enable on channel 6
-0x40017018 C FIELD 07w01 CHEN: Channel 6 enable
-0x40017018 C FIELD 08w01 CHINSEL: Channel inputs selection
-0x40017018 C FIELD 12w02 DATMPX: Input data multiplexer for channel 6
-0x40017018 C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x40017018 C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x40017018 C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x40017018 C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x4001701C B REGISTER DFSDM_CHCFG7R1 (rw): DFSDM channel configuration 7 register 1
-0x4001701C C FIELD 00w02 SITP: Serial interface type for channel 7
-0x4001701C C FIELD 02w02 SPICKSEL: SPI clock select for channel 7
-0x4001701C C FIELD 05w01 SCDEN: Short-circuit detector enable on channel 7
-0x4001701C C FIELD 06w01 CKABEN: Clock absence detector enable on channel 7
-0x4001701C C FIELD 07w01 CHEN: Channel 7 enable
-0x4001701C C FIELD 08w01 CHINSEL: Channel inputs selection
-0x4001701C C FIELD 12w02 DATMPX: Input data multiplexer for channel 7
-0x4001701C C FIELD 14w02 DATPACK: Data packing mode in DFSDM_CHDATINyR register
-0x4001701C C FIELD 16w08 CKOUTDIV: Output serial clock divider
-0x4001701C C FIELD 30w01 CKOUTSRC: Output serial clock source selection
-0x4001701C C FIELD 31w01 DFSDMEN: Global enable for DFSDM interface
-0x40017020 B REGISTER DFSDM_CHCFG0R2 (rw): DFSDM channel configuration 0 register 2
-0x40017020 C FIELD 03w05 DTRBS: Data right bit-shift for channel 0
-0x40017020 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 0
-0x40017024 B REGISTER DFSDM_CHCFG1R2 (rw): DFSDM channel configuration 1 register 2
-0x40017024 C FIELD 03w05 DTRBS: Data right bit-shift for channel 1
-0x40017024 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 1
-0x40017028 B REGISTER DFSDM_CHCFG2R2 (rw): DFSDM channel configuration 2 register 2
-0x40017028 C FIELD 03w05 DTRBS: Data right bit-shift for channel 2
-0x40017028 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 2
-0x4001702C B REGISTER DFSDM_CHCFG3R2 (rw): DFSDM channel configuration 3 register 2
-0x4001702C C FIELD 03w05 DTRBS: Data right bit-shift for channel 3
-0x4001702C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 3
-0x40017030 B REGISTER DFSDM_CHCFG4R2 (rw): DFSDM channel configuration 4 register 2
-0x40017030 C FIELD 03w05 DTRBS: Data right bit-shift for channel 4
-0x40017030 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 4
-0x40017034 B REGISTER DFSDM_CHCFG5R2 (rw): DFSDM channel configuration 5 register 2
-0x40017034 C FIELD 03w05 DTRBS: Data right bit-shift for channel 5
-0x40017034 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 5
-0x40017038 B REGISTER DFSDM_CHCFG6R2 (rw): DFSDM channel configuration 6 register 2
-0x40017038 C FIELD 03w05 DTRBS: Data right bit-shift for channel 6
-0x40017038 C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 6
-0x4001703C B REGISTER DFSDM_CHCFG7R2 (rw): DFSDM channel configuration 7 register 2
-0x4001703C C FIELD 03w05 DTRBS: Data right bit-shift for channel 7
-0x4001703C C FIELD 08w24 OFFSET: 24-bit calibration offset for channel 7
-0x40017040 B REGISTER DFSDM_AWSCD0R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017040 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 0
-0x40017040 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 0
-0x40017040 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 0
-0x40017040 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 0
-0x40017044 B REGISTER DFSDM_AWSCD1R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017044 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 1
-0x40017044 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 1
-0x40017044 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 1
-0x40017044 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 1
-0x40017048 B REGISTER DFSDM_AWSCD2R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017048 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 2
-0x40017048 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 2
-0x40017048 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 2
-0x40017048 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 2
-0x4001704C B REGISTER DFSDM_AWSCD3R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001704C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 3
-0x4001704C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 3
-0x4001704C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 3
-0x4001704C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 3
-0x40017050 B REGISTER DFSDM_AWSCD4R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017050 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 4
-0x40017050 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 4
-0x40017050 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 4
-0x40017050 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 4
-0x40017054 B REGISTER DFSDM_AWSCD5R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017054 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 5
-0x40017054 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 5
-0x40017054 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 5
-0x40017054 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 5
-0x40017058 B REGISTER DFSDM_AWSCD6R (rw): DFSDM analog watchdog and short-circuit detector register
-0x40017058 C FIELD 00w08 SCDT: short-circuit detector threshold for channel 6
-0x40017058 C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 6
-0x40017058 C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 6
-0x40017058 C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 6
-0x4001705C B REGISTER DFSDM_AWSCD7R (rw): DFSDM analog watchdog and short-circuit detector register
-0x4001705C C FIELD 00w08 SCDT: short-circuit detector threshold for channel 7
-0x4001705C C FIELD 12w04 BKSCD: Break signal assignment for short-circuit detector on channel 7
-0x4001705C C FIELD 16w05 AWFOSR: Analog watchdog filter oversampling ratio (decimation rate) on channel 7
-0x4001705C C FIELD 22w02 AWFORD: Analog watchdog Sinc filter order on channel 7
-0x40017060 B REGISTER DFSDM_CHWDAT0R (ro): DFSDM channel watchdog filter data register
-0x40017060 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017064 B REGISTER DFSDM_CHWDAT1R (ro): DFSDM channel watchdog filter data register
-0x40017064 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017068 B REGISTER DFSDM_CHWDAT2R (ro): DFSDM channel watchdog filter data register
-0x40017068 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001706C B REGISTER DFSDM_CHWDAT3R (ro): DFSDM channel watchdog filter data register
-0x4001706C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017070 B REGISTER DFSDM_CHWDAT4R (ro): DFSDM channel watchdog filter data register
-0x40017070 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017074 B REGISTER DFSDM_CHWDAT5R (ro): DFSDM channel watchdog filter data register
-0x40017074 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017078 B REGISTER DFSDM_CHWDAT6R (ro): DFSDM channel watchdog filter data register
-0x40017078 C FIELD 00w16 WDATA: Input channel y watchdog data
-0x4001707C B REGISTER DFSDM_CHWDAT7R (ro): DFSDM channel watchdog filter data register
-0x4001707C C FIELD 00w16 WDATA: Input channel y watchdog data
-0x40017080 B REGISTER DFSDM_CHDATIN0R (rw): DFSDM channel data input register
-0x40017080 C FIELD 00w16 INDAT0: Input data for channel 0
-0x40017080 C FIELD 16w16 INDAT1: Input data for channel 1
-0x40017084 B REGISTER DFSDM_CHDATIN1R (rw): DFSDM channel data input register
-0x40017084 C FIELD 00w16 INDAT0: Input data for channel 1
-0x40017084 C FIELD 16w16 INDAT1: Input data for channel 2
-0x40017088 B REGISTER DFSDM_CHDATIN2R (rw): DFSDM channel data input register
-0x40017088 C FIELD 00w16 INDAT0: Input data for channel 2
-0x40017088 C FIELD 16w16 INDAT1: Input data for channel 3
-0x4001708C B REGISTER DFSDM_CHDATIN3R (rw): DFSDM channel data input register
-0x4001708C C FIELD 00w16 INDAT0: Input data for channel 3
-0x4001708C C FIELD 16w16 INDAT1: Input data for channel 4
-0x40017090 B REGISTER DFSDM_CHDATIN4R (rw): DFSDM channel data input register
-0x40017090 C FIELD 00w16 INDAT0: Input data for channel 4
-0x40017090 C FIELD 16w16 INDAT1: Input data for channel 5
-0x40017094 B REGISTER DFSDM_CHDATIN5R (rw): DFSDM channel data input register
-0x40017094 C FIELD 00w16 INDAT0: Input data for channel 5
-0x40017094 C FIELD 16w16 INDAT1: Input data for channel 6
-0x40017098 B REGISTER DFSDM_CHDATIN6R (rw): DFSDM channel data input register
-0x40017098 C FIELD 00w16 INDAT0: Input data for channel 6
-0x40017098 C FIELD 16w16 INDAT1: Input data for channel 7
-0x4001709C B REGISTER DFSDM_CHDATIN7R (rw): DFSDM channel data input register
-0x4001709C C FIELD 00w16 INDAT0: Input data for channel 7
-0x4001709C C FIELD 16w16 INDAT1: Input data for channel 8
-0x400170A0 B REGISTER DFSDM0_CR1 (rw): DFSDM control register 1
-0x400170A0 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A0 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A0 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A0 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A0 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A0 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A0 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A0 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A0 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A0 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A0 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A0 C FIELD 24w03 RCH: Regular channel selection
-0x400170A0 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A0 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A4 B REGISTER DFSDM1_CR1 (rw): DFSDM control register 1
-0x400170A4 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A4 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A4 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A4 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A4 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A4 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A4 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A4 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A4 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A4 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A4 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A4 C FIELD 24w03 RCH: Regular channel selection
-0x400170A4 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A4 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170A8 B REGISTER DFSDM2_CR1 (rw): DFSDM control register 1
-0x400170A8 C FIELD 00w01 DFEN: DFSDM enable
-0x400170A8 C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170A8 C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170A8 C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170A8 C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170A8 C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170A8 C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170A8 C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170A8 C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170A8 C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170A8 C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170A8 C FIELD 24w03 RCH: Regular channel selection
-0x400170A8 C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170A8 C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170AC B REGISTER DFSDM3_CR1 (rw): DFSDM control register 1
-0x400170AC C FIELD 00w01 DFEN: DFSDM enable
-0x400170AC C FIELD 01w01 JSWSTART: Start a conversion of the injected group of channels
-0x400170AC C FIELD 03w01 JSYNC: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
-0x400170AC C FIELD 04w01 JSCAN: Scanning conversion mode for injected conversions
-0x400170AC C FIELD 05w01 JDMAEN: DMA channel enabled to read data for the injected channel group
-0x400170AC C FIELD 08w05 JEXTSEL: Trigger signal selection for launching injected conversions
-0x400170AC C FIELD 13w02 JEXTEN: Trigger enable and trigger edge selection for injected conversions
-0x400170AC C FIELD 17w01 RSWSTART: Software start of a conversion on the regular channel
-0x400170AC C FIELD 18w01 RCONT: Continuous mode selection for regular conversions
-0x400170AC C FIELD 19w01 RSYNC: Launch regular conversion synchronously with DFSDM0
-0x400170AC C FIELD 21w01 RDMAEN: DMA channel enabled to read data for the regular conversion
-0x400170AC C FIELD 24w03 RCH: Regular channel selection
-0x400170AC C FIELD 29w01 FAST: Fast conversion mode selection for regular conversions
-0x400170AC C FIELD 30w01 AWFSEL: Analog watchdog fast mode select
-0x400170B0 B REGISTER DFSDM0_CR2 (rw): DFSDM control register 2
-0x400170B0 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B0 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B0 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B0 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B0 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B0 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B0 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B0 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B0 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B4 B REGISTER DFSDM1_CR2 (rw): DFSDM control register 2
-0x400170B4 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B4 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B4 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B4 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B4 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B4 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B4 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B4 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B4 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170B8 B REGISTER DFSDM2_CR2 (rw): DFSDM control register 2
-0x400170B8 C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170B8 C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170B8 C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170B8 C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170B8 C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170B8 C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170B8 C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170B8 C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170B8 C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170BC B REGISTER DFSDM3_CR2 (rw): DFSDM control register 2
-0x400170BC C FIELD 00w01 JEOCIE: Injected end of conversion interrupt enable
-0x400170BC C FIELD 01w01 REOCIE: Regular end of conversion interrupt enable
-0x400170BC C FIELD 02w01 JOVRIE: Injected data overrun interrupt enable
-0x400170BC C FIELD 03w01 ROVRIE: Regular data overrun interrupt enable
-0x400170BC C FIELD 04w01 AWDIE: Analog watchdog interrupt enable
-0x400170BC C FIELD 05w01 SCDIE: Short-circuit detector interrupt enable
-0x400170BC C FIELD 06w01 CKABIE: Clock absence interrupt enable
-0x400170BC C FIELD 08w08 EXCH: Extremes detector channel selection
-0x400170BC C FIELD 16w08 AWDCH: Analog watchdog channel selection
-0x400170C0 B REGISTER DFSDM0_ISR (ro): DFSDM interrupt and status register
-0x400170C0 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C0 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C0 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C0 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C0 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C0 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C0 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C0 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C0 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C4 B REGISTER DFSDM1_ISR (ro): DFSDM interrupt and status register
-0x400170C4 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C4 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C4 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C4 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C4 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C4 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C4 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C4 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C4 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170C8 B REGISTER DFSDM2_ISR (ro): DFSDM interrupt and status register
-0x400170C8 C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170C8 C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170C8 C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170C8 C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170C8 C FIELD 04w01 AWDF: Analog watchdog
-0x400170C8 C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170C8 C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170C8 C FIELD 16w08 CKABF: Clock absence flag
-0x400170C8 C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170CC B REGISTER DFSDM3_ISR (ro): DFSDM interrupt and status register
-0x400170CC C FIELD 00w01 JEOCF: End of injected conversion flag
-0x400170CC C FIELD 01w01 REOCF: End of regular conversion flag
-0x400170CC C FIELD 02w01 JOVRF: Injected conversion overrun flag
-0x400170CC C FIELD 03w01 ROVRF: Regular conversion overrun flag
-0x400170CC C FIELD 04w01 AWDF: Analog watchdog
-0x400170CC C FIELD 13w01 JCIP: Injected conversion in progress status
-0x400170CC C FIELD 14w01 RCIP: Regular conversion in progress status
-0x400170CC C FIELD 16w08 CKABF: Clock absence flag
-0x400170CC C FIELD 24w08 SCDF: short-circuit detector flag
-0x400170D0 B REGISTER DFSDM0_ICR (rw): DFSDM interrupt flag clear register
-0x400170D0 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D0 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D0 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D0 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D4 B REGISTER DFSDM1_ICR (rw): DFSDM interrupt flag clear register
-0x400170D4 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D4 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D4 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D4 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170D8 B REGISTER DFSDM2_ICR (rw): DFSDM interrupt flag clear register
-0x400170D8 C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170D8 C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170D8 C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170D8 C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170DC B REGISTER DFSDM3_ICR (rw): DFSDM interrupt flag clear register
-0x400170DC C FIELD 02w01 CLRJOVRF: Clear the injected conversion overrun flag
-0x400170DC C FIELD 03w01 CLRROVRF: Clear the regular conversion overrun flag
-0x400170DC C FIELD 16w08 CLRCKABF: Clear the clock absence flag
-0x400170DC C FIELD 24w08 CLRSCDF: Clear the short-circuit detector flag
-0x400170E0 B REGISTER DFSDM0_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E0 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E4 B REGISTER DFSDM1_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E4 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170E8 B REGISTER DFSDM2_JCHGR (rw): DFSDM injected channel group selection register
-0x400170E8 C FIELD 00w08 JCHG: Injected channel group selection
-0x400170EC B REGISTER DFSDM3_JCHGR (rw): DFSDM injected channel group selection register
-0x400170EC C FIELD 00w08 JCHG: Injected channel group selection
-0x400170F0 B REGISTER DFSDM0_FCR (rw): DFSDM filter control register
-0x400170F0 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F0 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F0 C FIELD 29w03 FORD: Sinc filter order
-0x400170F4 B REGISTER DFSDM1_FCR (rw): DFSDM filter control register
-0x400170F4 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F4 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F4 C FIELD 29w03 FORD: Sinc filter order
-0x400170F8 B REGISTER DFSDM2_FCR (rw): DFSDM filter control register
-0x400170F8 C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170F8 C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170F8 C FIELD 29w03 FORD: Sinc filter order
-0x400170FC B REGISTER DFSDM3_FCR (rw): DFSDM filter control register
-0x400170FC C FIELD 00w08 IOSR: Integrator oversampling ratio (averaging length)
-0x400170FC C FIELD 16w10 FOSR: Sinc filter oversampling ratio (decimation rate)
-0x400170FC C FIELD 29w03 FORD: Sinc filter order
-0x40017100 B REGISTER DFSDM0_JDATAR (ro): DFSDM data register for injected group
-0x40017100 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017100 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017104 B REGISTER DFSDM1_JDATAR (ro): DFSDM data register for injected group
-0x40017104 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017104 C FIELD 08w24 JDATA: Injected group conversion data
-0x40017108 B REGISTER DFSDM2_JDATAR (ro): DFSDM data register for injected group
-0x40017108 C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x40017108 C FIELD 08w24 JDATA: Injected group conversion data
-0x4001710C B REGISTER DFSDM3_JDATAR (ro): DFSDM data register for injected group
-0x4001710C C FIELD 00w03 JDATACH: Injected channel most recently converted
-0x4001710C C FIELD 08w24 JDATA: Injected group conversion data
-0x40017110 B REGISTER DFSDM0_RDATAR (ro): DFSDM data register for the regular channel
-0x40017110 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017110 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017110 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017114 B REGISTER DFSDM1_RDATAR (ro): DFSDM data register for the regular channel
-0x40017114 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017114 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017114 C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017118 B REGISTER DFSDM2_RDATAR (ro): DFSDM data register for the regular channel
-0x40017118 C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x40017118 C FIELD 04w01 RPEND: Regular channel pending data
-0x40017118 C FIELD 08w24 RDATA: Regular channel conversion data
-0x4001711C B REGISTER DFSDM3_RDATAR (ro): DFSDM data register for the regular channel
-0x4001711C C FIELD 00w03 RDATACH: Regular channel most recently converted
-0x4001711C C FIELD 04w01 RPEND: Regular channel pending data
-0x4001711C C FIELD 08w24 RDATA: Regular channel conversion data
-0x40017120 B REGISTER DFSDM0_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017120 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017120 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017124 B REGISTER DFSDM1_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017124 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017124 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017128 B REGISTER DFSDM2_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x40017128 C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x40017128 C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x4001712C B REGISTER DFSDM3_AWHTR (rw): DFSDM analog watchdog high threshold register
-0x4001712C C FIELD 00w04 BKAWH: Break signal assignment to analog watchdog high threshold event
-0x4001712C C FIELD 08w24 AWHT: Analog watchdog high threshold
-0x40017130 B REGISTER DFSDM0_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017130 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017130 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017134 B REGISTER DFSDM1_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017134 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017134 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017138 B REGISTER DFSDM2_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x40017138 C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x40017138 C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x4001713C B REGISTER DFSDM3_AWLTR (rw): DFSDM analog watchdog low threshold register
-0x4001713C C FIELD 00w04 BKAWL: Break signal assignment to analog watchdog low threshold event
-0x4001713C C FIELD 08w24 AWLT: Analog watchdog low threshold
-0x40017140 B REGISTER DFSDM0_AWSR (ro): DFSDM analog watchdog status register
-0x40017140 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017140 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017144 B REGISTER DFSDM1_AWSR (ro): DFSDM analog watchdog status register
-0x40017144 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017144 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017148 B REGISTER DFSDM2_AWSR (ro): DFSDM analog watchdog status register
-0x40017148 C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x40017148 C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x4001714C B REGISTER DFSDM3_AWSR (ro): DFSDM analog watchdog status register
-0x4001714C C FIELD 00w08 AWLTF: Analog watchdog low threshold flag
-0x4001714C C FIELD 08w08 AWHTF: Analog watchdog high threshold flag
-0x40017150 B REGISTER DFSDM0_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017150 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017150 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017154 B REGISTER DFSDM1_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017154 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017154 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017158 B REGISTER DFSDM2_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x40017158 C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x40017158 C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x4001715C B REGISTER DFSDM3_AWCFR (rw): DFSDM analog watchdog clear flag register
-0x4001715C C FIELD 00w08 CLRAWLTF: Clear the analog watchdog low threshold flag
-0x4001715C C FIELD 08w08 CLRAWHTF: Clear the analog watchdog high threshold flag
-0x40017160 B REGISTER DFSDM0_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017160 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017160 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017164 B REGISTER DFSDM1_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017164 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017164 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017168 B REGISTER DFSDM2_EXMAX (ro): DFSDM Extremes detector maximum register
-0x40017168 C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x40017168 C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x4001716C B REGISTER DFSDM3_EXMAX (ro): DFSDM Extremes detector maximum register
-0x4001716C C FIELD 00w03 EXMAXCH: Extremes detector maximum data channel
-0x4001716C C FIELD 08w24 EXMAX: Extremes detector maximum value
-0x40017170 B REGISTER DFSDM0_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017170 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017170 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017174 B REGISTER DFSDM1_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017174 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017174 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017178 B REGISTER DFSDM2_EXMIN (ro): DFSDM Extremes detector minimum register
-0x40017178 C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x40017178 C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x4001717C B REGISTER DFSDM3_EXMIN (ro): DFSDM Extremes detector minimum register
-0x4001717C C FIELD 00w03 EXMINCH: Extremes detector minimum data channel
-0x4001717C C FIELD 08w24 EXMIN: Extremes detector minimum value
-0x40017180 B REGISTER DFSDM0_CNVTIMR (ro): DFSDM conversion timer register
-0x40017180 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017184 B REGISTER DFSDM1_CNVTIMR (ro): DFSDM conversion timer register
-0x40017184 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x40017188 B REGISTER DFSDM2_CNVTIMR (ro): DFSDM conversion timer register
-0x40017188 C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
-0x4001718C B REGISTER DFSDM3_CNVTIMR (ro): DFSDM conversion timer register
-0x4001718C C FIELD 04w28 CNVCNT: 28-bit timer counting conversion time
0x40017400 A PERIPHERAL HRTIM_Master
0x40017400 B REGISTER MCR (rw): Master Timer Control Register
0x40017400 C FIELD 00w03 CK_PSC: HRTIM Master Clock prescaler
@@ -8243,6 +8181,807 @@
0x400177DC C FIELD 20w01 TIMxFLTR: HRTIM_FLTxR register update enable
0x400177F0 B REGISTER BDMADR (rw): Burst DMA Data register
0x400177F0 C FIELD 00w32 BDMADR: Burst DMA Data register
+0x40017800 A PERIPHERAL DFSDM1
+0x40017800 B REGISTER DFSDM_CH0CFGR1: DFSDM channel 0 configuration register
+0x40017800 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017800 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017800 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x40017800 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x40017800 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x40017800 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017800 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017800 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017800 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x40017800 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017800 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017804 B REGISTER DFSDM_CH0CFGR2: DFSDM channel 0 configuration register
+0x40017804 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x40017804 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x40017808 B REGISTER DFSDM_CH0AWSCDR: DFSDM channel 0 analog watchdog and short-circuit detector register
+0x40017808 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x40017808 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x40017808 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x40017808 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x4001780C B REGISTER DFSDM_CH0WDATR: DFSDM channel 0 watchdog filter data register
+0x4001780C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x40017810 B REGISTER DFSDM_CH0DATINR: DFSDM channel 0 data input register
+0x40017810 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x40017810 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x40017814 B REGISTER DFSDM_CH0DLYR: None
+0x40017814 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x40017820 B REGISTER DFSDM_CH1CFGR1: DFSDM channel 1 configuration register
+0x40017820 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017820 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017820 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x40017820 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x40017820 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x40017820 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017820 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017820 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017820 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x40017820 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017820 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017824 B REGISTER DFSDM_CH1CFGR2: DFSDM channel 1 configuration register
+0x40017824 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x40017824 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x40017828 B REGISTER DFSDM_CH1AWSCDR: DFSDM channel 1 analog watchdog and short-circuit detector register
+0x40017828 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x40017828 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x40017828 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x40017828 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x4001782C B REGISTER DFSDM_CH1WDATR: DFSDM channel 1 watchdog filter data register
+0x4001782C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x40017830 B REGISTER DFSDM_CH1DATINR: DFSDM channel 1 data input register
+0x40017830 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x40017830 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x40017834 B REGISTER DFSDM_CH1DLYR: None
+0x40017834 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x40017840 B REGISTER DFSDM_CH2CFGR1: DFSDM channel 2 configuration register
+0x40017840 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017840 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017840 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x40017840 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x40017840 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x40017840 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017840 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017840 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017840 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x40017840 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017840 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017844 B REGISTER DFSDM_CH2CFGR2: DFSDM channel 2 configuration register
+0x40017844 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x40017844 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x40017848 B REGISTER DFSDM_CH2AWSCDR: DFSDM channel 2 analog watchdog and short-circuit detector register
+0x40017848 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x40017848 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x40017848 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x40017848 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x4001784C B REGISTER DFSDM_CH2WDATR: DFSDM channel 2 watchdog filter data register
+0x4001784C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x40017850 B REGISTER DFSDM_CH2DATINR: DFSDM channel 2 data input register
+0x40017850 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x40017850 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x40017854 B REGISTER DFSDM_CH2DLYR: None
+0x40017854 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x40017860 B REGISTER DFSDM_CH3CFGR1: DFSDM channel 3 configuration register
+0x40017860 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017860 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017860 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x40017860 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x40017860 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x40017860 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017860 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017860 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017860 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x40017860 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017860 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017864 B REGISTER DFSDM_CH3CFGR2: DFSDM channel 3 configuration register
+0x40017864 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x40017864 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x40017868 B REGISTER DFSDM_CH3AWSCDR: DFSDM channel 3 analog watchdog and short-circuit detector register
+0x40017868 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x40017868 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x40017868 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x40017868 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x4001786C B REGISTER DFSDM_CH3WDATR: DFSDM channel 3 watchdog filter data register
+0x4001786C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x40017870 B REGISTER DFSDM_CH3DATINR: DFSDM channel 3 data input register
+0x40017870 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x40017870 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x40017874 B REGISTER DFSDM_CH3DLYR: None
+0x40017874 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x40017880 B REGISTER DFSDM_CH4CFGR1: DFSDM channel 4 configuration register
+0x40017880 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017880 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017880 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x40017880 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x40017880 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x40017880 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017880 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017880 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x40017880 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x40017880 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017880 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x40017884 B REGISTER DFSDM_CH4CFGR2: DFSDM channel 4 configuration register
+0x40017884 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x40017884 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x40017888 B REGISTER DFSDM_CH4AWSCDR: DFSDM channel 4 analog watchdog and short-circuit detector register
+0x40017888 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x40017888 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x40017888 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x40017888 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x4001788C B REGISTER DFSDM_CH4WDATR: DFSDM channel 4 watchdog filter data register
+0x4001788C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x40017890 B REGISTER DFSDM_CH4DATINR: DFSDM channel 4 data input register
+0x40017890 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x40017890 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x40017894 B REGISTER DFSDM_CH4DLYR: None
+0x40017894 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x400178A0 B REGISTER DFSDM_CH5CFGR1: DFSDM channel 5 configuration register
+0x400178A0 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178A0 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178A0 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x400178A0 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x400178A0 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x400178A0 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178A0 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178A0 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178A0 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x400178A0 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x400178A0 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x400178A4 B REGISTER DFSDM_CH5CFGR2: DFSDM channel 5 configuration register
+0x400178A4 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x400178A4 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x400178A8 B REGISTER DFSDM_CH5AWSCDR: DFSDM channel 5 analog watchdog and short-circuit detector register
+0x400178A8 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x400178A8 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x400178A8 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x400178A8 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178AC B REGISTER DFSDM_CH5WDATR: DFSDM channel 5 watchdog filter data register
+0x400178AC C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x400178B0 B REGISTER DFSDM_CH5DATINR: DFSDM channel 5 data input register
+0x400178B0 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x400178B0 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x400178B4 B REGISTER DFSDM_CH5DLYR: None
+0x400178B4 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x400178C0 B REGISTER DFSDM_CH6CFGR1: DFSDM channel 6 configuration register
+0x400178C0 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178C0 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178C0 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x400178C0 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x400178C0 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x400178C0 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178C0 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178C0 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178C0 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x400178C0 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x400178C0 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x400178C4 B REGISTER DFSDM_CH6CFGR2: DFSDM channel 6 configuration register
+0x400178C4 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x400178C4 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x400178C8 B REGISTER DFSDM_CH6AWSCDR: DFSDM channel 6 analog watchdog and short-circuit detector register
+0x400178C8 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x400178C8 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x400178C8 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x400178C8 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178CC B REGISTER DFSDM_CH6WDATR: DFSDM channel 6 watchdog filter data register
+0x400178CC C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x400178D0 B REGISTER DFSDM_CH6DATINR: DFSDM channel 6 data input register
+0x400178D0 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x400178D0 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x400178D4 B REGISTER DFSDM_CH6DLYR: None
+0x400178D4 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x400178E0 B REGISTER DFSDM_CH7CFGR1: DFSDM channel 7 configuration register
+0x400178E0 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178E0 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178E0 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x400178E0 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x400178E0 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x400178E0 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178E0 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178E0 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178E0 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x400178E0 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x400178E0 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x400178E4 B REGISTER DFSDM_CH7CFGR2: DFSDM channel 7 configuration register
+0x400178E4 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x400178E4 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x400178E8 B REGISTER DFSDM_CH7AWSCDR: DFSDM channel 7 analog watchdog and short-circuit detector register
+0x400178E8 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x400178E8 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x400178E8 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x400178E8 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x400178EC B REGISTER DFSDM_CH7WDATR: DFSDM channel 7 watchdog filter data register
+0x400178EC C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x400178F0 B REGISTER DFSDM_CH7DATINR: DFSDM channel 7 data input register
+0x400178F0 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x400178F0 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x400178F4 B REGISTER DFSDM_CH7DLYR: None
+0x400178F4 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x40017900 B REGISTER DFSDM_FLT0CR1: None
+0x40017900 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017900 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017900 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017900 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017900 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017900 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017900 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017900 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017900 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017900 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017900 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017900 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017900 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017900 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017904 B REGISTER DFSDM_FLT0CR2: None
+0x40017904 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017904 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017904 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017904 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017904 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017904 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017904 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017904 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017904 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017908 B REGISTER DFSDM_FLT0ISR: None
+0x40017908 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017908 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017908 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017908 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017908 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017908 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017908 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017908 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017908 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x4001790C B REGISTER DFSDM_FLT0ICR: None
+0x4001790C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x4001790C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x4001790C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x4001790C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017910 B REGISTER DFSDM_FLT0JCHGR: None
+0x40017910 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017914 B REGISTER DFSDM_FLT0FCR: None
+0x40017914 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017914 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017914 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017918 B REGISTER DFSDM_FLT0JDATAR: None
+0x40017918 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017918 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x4001791C B REGISTER DFSDM_FLT0RDATAR: None
+0x4001791C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x4001791C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x4001791C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017920 B REGISTER DFSDM_FLT0AWHTR: None
+0x40017920 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017920 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017924 B REGISTER DFSDM_FLT0AWLTR: None
+0x40017924 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017924 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017928 B REGISTER DFSDM_FLT0AWSR: None
+0x40017928 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017928 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x4001792C B REGISTER DFSDM_FLT0AWCFR: None
+0x4001792C C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x4001792C C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017930 B REGISTER DFSDM_FLT0EXMAX: None
+0x40017930 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017930 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017934 B REGISTER DFSDM_FLT0EXMIN: None
+0x40017934 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017934 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017938 B REGISTER DFSDM_FLT0CNVTIMR: None
+0x40017938 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017980 B REGISTER DFSDM_FLT1CR1: None
+0x40017980 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017980 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017980 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017980 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017980 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017980 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017980 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017980 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017980 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017980 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017980 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017980 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017980 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017980 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017984 B REGISTER DFSDM_FLT1CR2: None
+0x40017984 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017984 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017984 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017984 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017984 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017984 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017984 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017984 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017984 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017988 B REGISTER DFSDM_FLT1ISR: None
+0x40017988 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017988 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017988 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017988 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017988 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017988 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017988 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017988 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017988 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x4001798C B REGISTER DFSDM_FLT1ICR: None
+0x4001798C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x4001798C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x4001798C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x4001798C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017990 B REGISTER DFSDM_FLT1JCHGR: None
+0x40017990 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017994 B REGISTER DFSDM_FLT1FCR: None
+0x40017994 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017994 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017994 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017998 B REGISTER DFSDM_FLT1JDATAR: None
+0x40017998 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017998 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x4001799C B REGISTER DFSDM_FLT1RDATAR: None
+0x4001799C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x4001799C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x4001799C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x400179A0 B REGISTER DFSDM_FLT1AWHTR: None
+0x400179A0 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x400179A0 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x400179A4 B REGISTER DFSDM_FLT1AWLTR: None
+0x400179A4 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x400179A4 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x400179A8 B REGISTER DFSDM_FLT1AWSR: None
+0x400179A8 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x400179A8 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x400179AC B REGISTER DFSDM_FLT1AWCFR: None
+0x400179AC C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x400179AC C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x400179B0 B REGISTER DFSDM_FLT1EXMAX: None
+0x400179B0 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x400179B0 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x400179B4 B REGISTER DFSDM_FLT1EXMIN: None
+0x400179B4 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x400179B4 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x400179B8 B REGISTER DFSDM_FLT1CNVTIMR: None
+0x400179B8 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017A00 B REGISTER DFSDM_FLT2CR1: None
+0x40017A00 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017A00 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017A00 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A00 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017A00 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A00 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017A00 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A00 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017A00 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017A00 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A00 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A00 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017A00 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017A00 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017A04 B REGISTER DFSDM_FLT2CR2: None
+0x40017A04 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017A04 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017A04 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017A04 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017A04 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017A04 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017A04 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017A04 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017A04 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017A08 B REGISTER DFSDM_FLT2ISR: None
+0x40017A08 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017A08 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017A08 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017A08 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017A08 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017A08 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017A08 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017A08 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017A08 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017A0C B REGISTER DFSDM_FLT2ICR: None
+0x40017A0C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x40017A0C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x40017A0C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017A0C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017A10 B REGISTER DFSDM_FLT2JCHGR: None
+0x40017A10 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017A14 B REGISTER DFSDM_FLT2FCR: None
+0x40017A14 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017A14 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017A14 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A18 B REGISTER DFSDM_FLT2JDATAR: None
+0x40017A18 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017A18 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x40017A1C B REGISTER DFSDM_FLT2RDATAR: None
+0x40017A1C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x40017A1C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x40017A1C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017A20 B REGISTER DFSDM_FLT2AWHTR: None
+0x40017A20 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017A20 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017A24 B REGISTER DFSDM_FLT2AWLTR: None
+0x40017A24 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017A24 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017A28 B REGISTER DFSDM_FLT2AWSR: None
+0x40017A28 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017A28 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017A2C B REGISTER DFSDM_FLT2AWCFR: None
+0x40017A2C C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017A2C C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017A30 B REGISTER DFSDM_FLT2EXMAX: None
+0x40017A30 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017A30 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017A34 B REGISTER DFSDM_FLT2EXMIN: None
+0x40017A34 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017A34 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017A38 B REGISTER DFSDM_FLT2CNVTIMR: None
+0x40017A38 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017A80 B REGISTER DFSDM_FLT3CR1: None
+0x40017A80 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017A80 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017A80 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A80 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017A80 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A80 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017A80 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A80 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017A80 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017A80 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A80 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A80 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017A80 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017A80 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017A84 B REGISTER DFSDM_FLT3CR2: None
+0x40017A84 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017A84 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017A84 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017A84 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017A84 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017A84 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017A84 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017A84 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017A84 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017A88 B REGISTER DFSDM_FLT3ISR: None
+0x40017A88 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017A88 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017A88 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017A88 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017A88 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017A88 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017A88 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017A88 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017A88 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017A8C B REGISTER DFSDM_FLT3ICR: None
+0x40017A8C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x40017A8C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x40017A8C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017A8C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017A90 B REGISTER DFSDM_FLT3JCHGR: None
+0x40017A90 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017A94 B REGISTER DFSDM_FLT3FCR: None
+0x40017A94 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017A94 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017A94 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017A98 B REGISTER DFSDM_FLT3JDATAR: None
+0x40017A98 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017A98 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x40017A9C B REGISTER DFSDM_FLT3RDATAR: None
+0x40017A9C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x40017A9C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x40017A9C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017AA0 B REGISTER DFSDM_FLT3AWHTR: None
+0x40017AA0 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017AA0 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017AA4 B REGISTER DFSDM_FLT3AWLTR: None
+0x40017AA4 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017AA4 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017AA8 B REGISTER DFSDM_FLT3AWSR: None
+0x40017AA8 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017AA8 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017AAC B REGISTER DFSDM_FLT3AWCFR: None
+0x40017AAC C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017AAC C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017AB0 B REGISTER DFSDM_FLT3EXMAX: None
+0x40017AB0 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017AB0 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017AB4 B REGISTER DFSDM_FLT3EXMIN: None
+0x40017AB4 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017AB4 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017AB8 B REGISTER DFSDM_FLT3CNVTIMR: None
+0x40017AB8 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017B00 B REGISTER DFSDM_FLT4CR1: None
+0x40017B00 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017B00 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017B00 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B00 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017B00 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B00 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017B00 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B00 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017B00 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017B00 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B00 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B00 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017B00 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017B00 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017B04 B REGISTER DFSDM_FLT4CR2: None
+0x40017B04 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017B04 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017B04 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017B04 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017B04 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017B04 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017B04 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017B04 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017B04 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017B08 B REGISTER DFSDM_FLT4ISR: None
+0x40017B08 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017B08 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017B08 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017B08 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017B08 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017B08 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017B08 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017B08 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017B08 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017B0C B REGISTER DFSDM_FLT4ICR: None
+0x40017B0C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x40017B0C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x40017B0C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017B0C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017B10 B REGISTER DFSDM_FLT4JCHGR: None
+0x40017B10 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017B14 B REGISTER DFSDM_FLT4FCR: None
+0x40017B14 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017B14 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017B14 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B18 B REGISTER DFSDM_FLT4JDATAR: None
+0x40017B18 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017B18 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x40017B1C B REGISTER DFSDM_FLT4RDATAR: None
+0x40017B1C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x40017B1C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x40017B1C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017B20 B REGISTER DFSDM_FLT4AWHTR: None
+0x40017B20 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017B20 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017B24 B REGISTER DFSDM_FLT4AWLTR: None
+0x40017B24 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017B24 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017B28 B REGISTER DFSDM_FLT4AWSR: None
+0x40017B28 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017B28 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017B2C B REGISTER DFSDM_FLT4AWCFR: None
+0x40017B2C C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017B2C C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017B30 B REGISTER DFSDM_FLT4EXMAX: None
+0x40017B30 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017B30 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017B34 B REGISTER DFSDM_FLT4EXMIN: None
+0x40017B34 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017B34 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017B38 B REGISTER DFSDM_FLT4CNVTIMR: None
+0x40017B38 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017B80 B REGISTER DFSDM_FLT5CR1: None
+0x40017B80 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017B80 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017B80 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B80 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017B80 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B80 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017B80 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B80 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017B80 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017B80 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B80 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B80 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017B80 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017B80 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017B84 B REGISTER DFSDM_FLT5CR2: None
+0x40017B84 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017B84 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017B84 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017B84 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017B84 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017B84 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017B84 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017B84 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017B84 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017B88 B REGISTER DFSDM_FLT5ISR: None
+0x40017B88 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017B88 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017B88 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017B88 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017B88 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017B88 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017B88 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017B88 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017B88 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017B8C B REGISTER DFSDM_FLT5ICR: None
+0x40017B8C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x40017B8C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x40017B8C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017B8C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017B90 B REGISTER DFSDM_FLT5JCHGR: None
+0x40017B90 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017B94 B REGISTER DFSDM_FLT5FCR: None
+0x40017B94 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017B94 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017B94 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017B98 B REGISTER DFSDM_FLT5JDATAR: None
+0x40017B98 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017B98 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x40017B9C B REGISTER DFSDM_FLT5RDATAR: None
+0x40017B9C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x40017B9C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x40017B9C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017BA0 B REGISTER DFSDM_FLT5AWHTR: None
+0x40017BA0 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017BA0 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017BA4 B REGISTER DFSDM_FLT5AWLTR: None
+0x40017BA4 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017BA4 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017BA8 B REGISTER DFSDM_FLT5AWSR: None
+0x40017BA8 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017BA8 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017BAC B REGISTER DFSDM_FLT5AWCFR: None
+0x40017BAC C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017BAC C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017BB0 B REGISTER DFSDM_FLT5EXMAX: None
+0x40017BB0 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017BB0 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017BB4 B REGISTER DFSDM_FLT5EXMIN: None
+0x40017BB4 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017BB4 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017BB8 B REGISTER DFSDM_FLT5CNVTIMR: None
+0x40017BB8 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017C00 B REGISTER DFSDM_FLT6CR1: None
+0x40017C00 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017C00 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017C00 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C00 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017C00 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C00 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017C00 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C00 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017C00 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017C00 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C00 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C00 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017C00 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017C00 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017C04 B REGISTER DFSDM_FLT6CR2: None
+0x40017C04 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017C04 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017C04 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017C04 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017C04 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017C04 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017C04 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017C04 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017C04 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017C08 B REGISTER DFSDM_FLT6ISR: None
+0x40017C08 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017C08 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017C08 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017C08 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017C08 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017C08 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017C08 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017C08 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017C08 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017C0C B REGISTER DFSDM_FLT6ICR: None
+0x40017C0C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x40017C0C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x40017C0C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017C0C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017C10 B REGISTER DFSDM_FLT6JCHGR: None
+0x40017C10 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017C14 B REGISTER DFSDM_FLT6FCR: None
+0x40017C14 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017C14 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017C14 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C18 B REGISTER DFSDM_FLT6JDATAR: None
+0x40017C18 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017C18 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x40017C1C B REGISTER DFSDM_FLT6RDATAR: None
+0x40017C1C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x40017C1C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x40017C1C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017C20 B REGISTER DFSDM_FLT6AWHTR: None
+0x40017C20 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017C20 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017C24 B REGISTER DFSDM_FLT6AWLTR: None
+0x40017C24 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017C24 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017C28 B REGISTER DFSDM_FLT6AWSR: None
+0x40017C28 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017C28 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017C2C B REGISTER DFSDM_FLT6AWCFR: None
+0x40017C2C C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017C2C C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017C30 B REGISTER DFSDM_FLT6EXMAX: None
+0x40017C30 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017C30 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017C34 B REGISTER DFSDM_FLT6EXMIN: None
+0x40017C34 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017C34 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017C38 B REGISTER DFSDM_FLT6CNVTIMR: None
+0x40017C38 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x40017C80 B REGISTER DFSDM_FLT7CR1: None
+0x40017C80 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x40017C80 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x40017C80 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C80 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x40017C80 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C80 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x40017C80 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C80 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x40017C80 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x40017C80 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C80 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C80 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x40017C80 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x40017C80 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x40017C84 B REGISTER DFSDM_FLT7CR2: None
+0x40017C84 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x40017C84 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x40017C84 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x40017C84 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x40017C84 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x40017C84 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017C84 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x40017C84 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x40017C84 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x40017C88 B REGISTER DFSDM_FLT7ISR: None
+0x40017C88 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x40017C88 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x40017C88 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x40017C88 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x40017C88 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x40017C88 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x40017C88 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x40017C88 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017C88 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x40017C8C B REGISTER DFSDM_FLT7ICR: None
+0x40017C8C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x40017C8C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x40017C8C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017C8C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x40017C90 B REGISTER DFSDM_FLT7JCHGR: None
+0x40017C90 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x40017C94 B REGISTER DFSDM_FLT7FCR: None
+0x40017C94 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x40017C94 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x40017C94 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x40017C98 B REGISTER DFSDM_FLT7JDATAR: None
+0x40017C98 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x40017C98 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x40017C9C B REGISTER DFSDM_FLT7RDATAR: None
+0x40017C9C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x40017C9C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x40017C9C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x40017CA0 B REGISTER DFSDM_FLT7AWHTR: None
+0x40017CA0 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x40017CA0 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x40017CA4 B REGISTER DFSDM_FLT7AWLTR: None
+0x40017CA4 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x40017CA4 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x40017CA8 B REGISTER DFSDM_FLT7AWSR: None
+0x40017CA8 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017CA8 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x40017CAC B REGISTER DFSDM_FLT7AWCFR: None
+0x40017CAC C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017CAC C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x40017CB0 B REGISTER DFSDM_FLT7EXMAX: None
+0x40017CB0 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x40017CB0 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x40017CB4 B REGISTER DFSDM_FLT7EXMIN: None
+0x40017CB4 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x40017CB4 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x40017CB8 B REGISTER DFSDM_FLT7CNVTIMR: None
+0x40017CB8 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
0x40018000 A PERIPHERAL UART9
0x40018000 B REGISTER CR1 (rw): Control register 1
0x40018000 C FIELD 00w01 UE: USART enable
@@ -9974,555 +10713,24 @@
0x4002230C B REGISTER CDR (ro): ADC common regular data register for dual and triple modes
0x4002230C C FIELD 00w16 RDATA_MST: Regular data of the master ADC
0x4002230C C FIELD 16w16 RDATA_SLV: Regular data of the slave ADC
-0x40028000 A PERIPHERAL Ethernet_MAC
-0x40028000 B REGISTER MACCR (rw): Operating mode configuration register
-0x40028000 C FIELD 00w01 RE: Receiver Enable
-0x40028000 C FIELD 01w01 TE: TE
-0x40028000 C FIELD 02w02 PRELEN: PRELEN
-0x40028000 C FIELD 04w01 DC: DC
-0x40028000 C FIELD 05w02 BL: BL
-0x40028000 C FIELD 08w01 DR: DR
-0x40028000 C FIELD 09w01 DCRS: DCRS
-0x40028000 C FIELD 10w01 DO: DO
-0x40028000 C FIELD 11w01 ECRSFD: ECRSFD
-0x40028000 C FIELD 12w01 LM: LM
-0x40028000 C FIELD 13w01 DM: DM
-0x40028000 C FIELD 14w01 FES: FES
-0x40028000 C FIELD 16w01 JE: JE
-0x40028000 C FIELD 17w01 JD: JD
-0x40028000 C FIELD 19w01 WD: WD
-0x40028000 C FIELD 20w01 ACS: ACS
-0x40028000 C FIELD 21w01 CST: CST
-0x40028000 C FIELD 22w01 S2KP: S2KP
-0x40028000 C FIELD 23w01 GPSLCE: GPSLCE
-0x40028000 C FIELD 24w03 IPG: IPG
-0x40028000 C FIELD 27w01 IPC: IPC
-0x40028000 C FIELD 28w03 SARC: SARC
-0x40028000 C FIELD 31w01 ARPEN: ARPEN
-0x40028004 B REGISTER MACECR (rw): Extended operating mode configuration register
-0x40028004 C FIELD 00w14 GPSL: GPSL
-0x40028004 C FIELD 16w01 DCRCC: DCRCC
-0x40028004 C FIELD 17w01 SPEN: SPEN
-0x40028004 C FIELD 18w01 USP: USP
-0x40028004 C FIELD 24w01 EIPGEN: EIPGEN
-0x40028004 C FIELD 25w05 EIPG: EIPG
-0x40028008 B REGISTER MACPFR (rw): Packet filtering control register
-0x40028008 C FIELD 00w01 PR: PR
-0x40028008 C FIELD 01w01 HUC: HUC
-0x40028008 C FIELD 02w01 HMC: HMC
-0x40028008 C FIELD 03w01 DAIF: DAIF
-0x40028008 C FIELD 04w01 PM: PM
-0x40028008 C FIELD 05w01 DBF: DBF
-0x40028008 C FIELD 06w02 PCF: PCF
-0x40028008 C FIELD 08w01 SAIF: SAIF
-0x40028008 C FIELD 09w01 SAF: SAF
-0x40028008 C FIELD 10w01 HPF: HPF
-0x40028008 C FIELD 16w01 VTFE: VTFE
-0x40028008 C FIELD 20w01 IPFE: IPFE
-0x40028008 C FIELD 21w01 DNTU: DNTU
-0x40028008 C FIELD 31w01 RA: RA
-0x4002800C B REGISTER MACWTR (rw): Watchdog timeout register
-0x4002800C C FIELD 00w04 WTO: WTO
-0x4002800C C FIELD 08w01 PWE: PWE
-0x40028010 B REGISTER MACHT0R (rw): Hash Table 0 register
-0x40028010 C FIELD 00w32 HT31T0: HT31T0
-0x40028014 B REGISTER MACHT1R (rw): Hash Table 1 register
-0x40028014 C FIELD 00w32 HT63T32: HT63T32
-0x40028050 B REGISTER MACVTR (rw): VLAN tag register
-0x40028050 C FIELD 00w16 VL: VL
-0x40028050 C FIELD 16w01 ETV: ETV
-0x40028050 C FIELD 17w01 VTIM: VTIM
-0x40028050 C FIELD 18w01 ESVL: ESVL
-0x40028050 C FIELD 19w01 ERSVLM: ERSVLM
-0x40028050 C FIELD 20w01 DOVLTC: DOVLTC
-0x40028050 C FIELD 21w02 EVLS: EVLS
-0x40028050 C FIELD 24w01 EVLRXS: EVLRXS
-0x40028050 C FIELD 25w01 VTHM: VTHM
-0x40028050 C FIELD 26w01 EDVLP: EDVLP
-0x40028050 C FIELD 27w01 ERIVLT: ERIVLT
-0x40028050 C FIELD 28w02 EIVLS: EIVLS
-0x40028050 C FIELD 31w01 EIVLRXS: EIVLRXS
-0x40028058 B REGISTER MACVHTR (rw): VLAN Hash table register
-0x40028058 C FIELD 00w16 VLHT: VLHT
-0x40028060 B REGISTER MACVIR (rw): VLAN inclusion register
-0x40028060 C FIELD 00w16 VLT: VLT
-0x40028060 C FIELD 16w02 VLC: VLC
-0x40028060 C FIELD 18w01 VLP: VLP
-0x40028060 C FIELD 19w01 CSVL: CSVL
-0x40028060 C FIELD 20w01 VLTI: VLTI
-0x40028064 B REGISTER MACIVIR (rw): Inner VLAN inclusion register
-0x40028064 C FIELD 00w16 VLT: VLT
-0x40028064 C FIELD 16w02 VLC: VLC
-0x40028064 C FIELD 18w01 VLP: VLP
-0x40028064 C FIELD 19w01 CSVL: CSVL
-0x40028064 C FIELD 20w01 VLTI: VLTI
-0x40028070 B REGISTER MACQTxFCR (rw): Tx Queue flow control register
-0x40028070 C FIELD 00w01 FCB_BPA: FCB_BPA
-0x40028070 C FIELD 01w01 TFE: TFE
-0x40028070 C FIELD 04w03 PLT: PLT
-0x40028070 C FIELD 07w01 DZPQ: DZPQ
-0x40028070 C FIELD 16w16 PT: PT
-0x40028090 B REGISTER MACRxFCR (rw): Rx flow control register
-0x40028090 C FIELD 00w01 RFE: RFE
-0x40028090 C FIELD 01w01 UP: UP
-0x400280B0 B REGISTER MACISR (ro): Interrupt status register
-0x400280B0 C FIELD 03w01 PHYIS: PHYIS
-0x400280B0 C FIELD 04w01 PMTIS: PMTIS
-0x400280B0 C FIELD 05w01 LPIIS: LPIIS
-0x400280B0 C FIELD 08w01 MMCIS: MMCIS
-0x400280B0 C FIELD 09w01 MMCRXIS: MMCRXIS
-0x400280B0 C FIELD 10w01 MMCTXIS: MMCTXIS
-0x400280B0 C FIELD 12w01 TSIS: TSIS
-0x400280B0 C FIELD 13w01 TXSTSIS: TXSTSIS
-0x400280B0 C FIELD 14w01 RXSTSIS: RXSTSIS
-0x400280B4 B REGISTER MACIER (rw): Interrupt enable register
-0x400280B4 C FIELD 03w01 PHYIE: PHYIE
-0x400280B4 C FIELD 04w01 PMTIE: PMTIE
-0x400280B4 C FIELD 05w01 LPIIE: LPIIE
-0x400280B4 C FIELD 12w01 TSIE: TSIE
-0x400280B4 C FIELD 13w01 TXSTSIE: TXSTSIE
-0x400280B4 C FIELD 14w01 RXSTSIE: RXSTSIE
-0x400280B8 B REGISTER MACRxTxSR (ro): Rx Tx status register
-0x400280B8 C FIELD 00w01 TJT: TJT
-0x400280B8 C FIELD 01w01 NCARR: NCARR
-0x400280B8 C FIELD 02w01 LCARR: LCARR
-0x400280B8 C FIELD 03w01 EXDEF: EXDEF
-0x400280B8 C FIELD 04w01 LCOL: LCOL
-0x400280B8 C FIELD 05w01 EXCOL: LCOL
-0x400280B8 C FIELD 08w01 RWT: RWT
-0x400280C0 B REGISTER MACPCSR: PMT control status register
-0x400280C0 C FIELD 00w01 PWRDWN (rw): PWRDWN
-0x400280C0 C FIELD 01w01 MGKPKTEN (rw): MGKPKTEN
-0x400280C0 C FIELD 02w01 RWKPKTEN (rw): RWKPKTEN
-0x400280C0 C FIELD 05w01 MGKPRCVD (ro): MGKPRCVD
-0x400280C0 C FIELD 06w01 RWKPRCVD (ro): RWKPRCVD
-0x400280C0 C FIELD 09w01 GLBLUCAST (rw): GLBLUCAST
-0x400280C0 C FIELD 10w01 RWKPFE (rw): RWKPFE
-0x400280C0 C FIELD 24w05 RWKPTR (rw): RWKPTR
-0x400280C0 C FIELD 31w01 RWKFILTRST (rw): RWKFILTRST
-0x400280C4 B REGISTER MACRWKPFR (rw): Remove wakeup packet filter register
-0x400280C4 C FIELD 00w32 WKUPFRMFTR: WKUPFRMFTR
-0x400280D0 B REGISTER MACLCSR: LPI control status register
-0x400280D0 C FIELD 00w01 TLPIEN (ro): TLPIEN
-0x400280D0 C FIELD 01w01 TLPIEX (ro): TLPIEX
-0x400280D0 C FIELD 02w01 RLPIEN (ro): RLPIEN
-0x400280D0 C FIELD 03w01 RLPIEX (ro): RLPIEX
-0x400280D0 C FIELD 08w01 TLPIST (ro): TLPIST
-0x400280D0 C FIELD 09w01 RLPIST (ro): RLPIST
-0x400280D0 C FIELD 16w01 LPIEN (rw): LPIEN
-0x400280D0 C FIELD 17w01 PLS (rw): PLS
-0x400280D0 C FIELD 18w01 PLSEN (rw): PLSEN
-0x400280D0 C FIELD 19w01 LPITXA (rw): LPITXA
-0x400280D0 C FIELD 20w01 LPITE (rw): LPITE
-0x400280D0 C FIELD 21w01 LPITCSE (rw): LPITCSE
-0x400280D4 B REGISTER MACLTCR (rw): LPI timers control register
-0x400280D4 C FIELD 00w16 TWT: TWT
-0x400280D4 C FIELD 16w10 LST: LST
-0x400280D8 B REGISTER MACLETR (rw): LPI entry timer register
-0x400280D8 C FIELD 00w17 LPIET: LPIET
-0x400280DC B REGISTER MAC1USTCR (rw): 1-microsecond-tick counter register
-0x400280DC C FIELD 00w12 TIC_1US_CNTR: TIC_1US_CNTR
-0x40028110 B REGISTER MACVR (ro): Version register
-0x40028110 C FIELD 00w08 SNPSVER: SNPSVER
-0x40028110 C FIELD 08w08 USERVER: USERVER
-0x40028114 B REGISTER MACDR (ro): Debug register
-0x40028114 C FIELD 00w01 RPESTS: RPESTS
-0x40028114 C FIELD 01w02 RFCFCSTS: RFCFCSTS
-0x40028114 C FIELD 16w01 TPESTS: TPESTS
-0x40028114 C FIELD 17w02 TFCSTS: TFCSTS
-0x40028120 B REGISTER MACHWF1R (ro): HW feature 1 register
-0x40028120 C FIELD 00w05 RXFIFOSIZE: RXFIFOSIZE
-0x40028120 C FIELD 06w05 TXFIFOSIZE: TXFIFOSIZE
-0x40028120 C FIELD 11w01 OSTEN: OSTEN
-0x40028120 C FIELD 12w01 PTOEN: PTOEN
-0x40028120 C FIELD 13w01 ADVTHWORD: ADVTHWORD
-0x40028120 C FIELD 16w01 DCBEN: DCBEN
-0x40028120 C FIELD 17w01 SPHEN: SPHEN
-0x40028120 C FIELD 18w01 TSOEN: TSOEN
-0x40028120 C FIELD 19w01 DBGMEMA: DBGMEMA
-0x40028120 C FIELD 20w01 AVSEL: AVSEL
-0x40028120 C FIELD 24w02 HASHTBLSZ: HASHTBLSZ
-0x40028120 C FIELD 27w04 L3L4FNUM: L3L4FNUM
-0x40028124 B REGISTER MACHWF2R (ro): HW feature 2 register
-0x40028124 C FIELD 00w04 RXQCNT: RXQCNT
-0x40028124 C FIELD 06w04 TXQCNT: TXQCNT
-0x40028124 C FIELD 12w04 RXCHCNT: RXCHCNT
-0x40028124 C FIELD 18w04 TXCHCNT: TXCHCNT
-0x40028124 C FIELD 24w03 PPSOUTNUM: PPSOUTNUM
-0x40028124 C FIELD 28w03 AUXSNAPNUM: AUXSNAPNUM
-0x40028200 B REGISTER MACMDIOAR (rw): MDIO address register
-0x40028200 C FIELD 00w01 MB: MB
-0x40028200 C FIELD 01w01 C45E: C45E
-0x40028200 C FIELD 02w02 GOC: GOC
-0x40028200 C FIELD 04w01 SKAP: SKAP
-0x40028200 C FIELD 08w04 CR: CR
-0x40028200 C FIELD 12w03 NTC: NTC
-0x40028200 C FIELD 16w05 RDA: RDA
-0x40028200 C FIELD 21w05 PA: PA
-0x40028200 C FIELD 26w01 BTB: BTB
-0x40028200 C FIELD 27w01 PSE: PSE
-0x40028204 B REGISTER MACMDIODR (rw): MDIO data register
-0x40028204 C FIELD 00w16 MD: MD
-0x40028204 C FIELD 16w16 RA: RA
-0x40028300 B REGISTER MACA0HR: Address 0 high register
-0x40028300 C FIELD 00w16 ADDRHI (rw): ADDRHI
-0x40028300 C FIELD 31w01 AE (ro): AE
-0x40028304 B REGISTER MACA0LR (rw): Address 0 low register
-0x40028304 C FIELD 00w32 ADDRLO: ADDRLO
-0x40028308 B REGISTER MACA1HR (rw): Address 1 high register
-0x40028308 C FIELD 00w16 ADDRHI: ADDRHI
-0x40028308 C FIELD 24w06 MBC: MBC
-0x40028308 C FIELD 30w01 SA: SA
-0x40028308 C FIELD 31w01 AE: AE
-0x4002830C B REGISTER MACA1LR (rw): Address 1 low register
-0x4002830C C FIELD 00w32 ADDRLO: ADDRLO
-0x40028310 B REGISTER MACA2HR (rw): Address 2 high register
-0x40028310 C FIELD 00w16 ADDRHI: ADDRHI
-0x40028310 C FIELD 24w06 MBC: MBC
-0x40028310 C FIELD 30w01 SA: SA
-0x40028310 C FIELD 31w01 AE: AE
-0x40028314 B REGISTER MACA2LR (rw): Address 2 low register
-0x40028314 C FIELD 00w32 ADDRLO: ADDRLO
-0x40028318 B REGISTER MACA3HR (rw): Address 3 high register
-0x40028318 C FIELD 00w16 ADDRHI: ADDRHI
-0x40028318 C FIELD 24w06 MBC: MBC
-0x40028318 C FIELD 30w01 SA: SA
-0x40028318 C FIELD 31w01 AE: AE
-0x4002831C B REGISTER MACA3LR (rw): Address 3 low register
-0x4002831C C FIELD 00w32 ADDRLO: ADDRLO
-0x40028700 B REGISTER MMC_CONTROL (rw): MMC control register
-0x40028700 C FIELD 00w01 CNTRST: CNTRST
-0x40028700 C FIELD 01w01 CNTSTOPRO: CNTSTOPRO
-0x40028700 C FIELD 02w01 RSTONRD: RSTONRD
-0x40028700 C FIELD 03w01 CNTFREEZ: CNTFREEZ
-0x40028700 C FIELD 04w01 CNTPRST: CNTPRST
-0x40028700 C FIELD 05w01 CNTPRSTLVL: CNTPRSTLVL
-0x40028700 C FIELD 08w01 UCDBC: UCDBC
-0x40028704 B REGISTER MMC_RX_INTERRUPT (ro): MMC Rx interrupt register
-0x40028704 C FIELD 05w01 RXCRCERPIS: RXCRCERPIS
-0x40028704 C FIELD 06w01 RXALGNERPIS: RXALGNERPIS
-0x40028704 C FIELD 17w01 RXUCGPIS: RXUCGPIS
-0x40028704 C FIELD 26w01 RXLPIUSCIS: RXLPIUSCIS
-0x40028704 C FIELD 27w01 RXLPITRCIS: RXLPITRCIS
-0x40028708 B REGISTER MMC_TX_INTERRUPT (ro): MMC Tx interrupt register
-0x40028708 C FIELD 14w01 TXSCOLGPIS: TXSCOLGPIS
-0x40028708 C FIELD 15w01 TXMCOLGPIS: TXMCOLGPIS
-0x40028708 C FIELD 21w01 TXGPKTIS: TXGPKTIS
-0x40028708 C FIELD 26w01 TXLPIUSCIS: TXLPIUSCIS
-0x40028708 C FIELD 27w01 TXLPITRCIS: TXLPITRCIS
-0x4002870C B REGISTER MMC_RX_INTERRUPT_MASK: MMC Rx interrupt mask register
-0x4002870C C FIELD 05w01 RXCRCERPIM (rw): RXCRCERPIM
-0x4002870C C FIELD 06w01 RXALGNERPIM (rw): RXALGNERPIM
-0x4002870C C FIELD 17w01 RXUCGPIM (rw): RXUCGPIM
-0x4002870C C FIELD 26w01 RXLPIUSCIM (rw): RXLPIUSCIM
-0x4002870C C FIELD 27w01 RXLPITRCIM (ro): RXLPITRCIM
-0x40028710 B REGISTER MMC_TX_INTERRUPT_MASK: MMC Tx interrupt mask register
-0x40028710 C FIELD 14w01 TXSCOLGPIM (rw): TXSCOLGPIM
-0x40028710 C FIELD 15w01 TXMCOLGPIM (rw): TXMCOLGPIM
-0x40028710 C FIELD 21w01 TXGPKTIM (rw): TXGPKTIM
-0x40028710 C FIELD 26w01 TXLPIUSCIM (rw): TXLPIUSCIM
-0x40028710 C FIELD 27w01 TXLPITRCIM (ro): TXLPITRCIM
-0x4002874C B REGISTER TX_SINGLE_COLLISION_GOOD_PACKETS (ro): Tx single collision good packets register
-0x4002874C C FIELD 00w32 TXSNGLCOLG: TXSNGLCOLG
-0x40028750 B REGISTER TX_MULTIPLE_COLLISION_GOOD_PACKETS (ro): Tx multiple collision good packets register
-0x40028750 C FIELD 00w32 TXMULTCOLG: TXMULTCOLG
-0x40028768 B REGISTER TX_PACKET_COUNT_GOOD (ro): Tx packet count good register
-0x40028768 C FIELD 00w32 TXPKTG: TXPKTG
-0x40028794 B REGISTER RX_CRC_ERROR_PACKETS (ro): Rx CRC error packets register
-0x40028794 C FIELD 00w32 RXCRCERR: RXCRCERR
-0x40028798 B REGISTER RX_ALIGNMENT_ERROR_PACKETS (ro): Rx alignment error packets register
-0x40028798 C FIELD 00w32 RXALGNERR: RXALGNERR
-0x400287C4 B REGISTER RX_UNICAST_PACKETS_GOOD (ro): Rx unicast packets good register
-0x400287C4 C FIELD 00w32 RXUCASTG: RXUCASTG
-0x400287EC B REGISTER TX_LPI_USEC_CNTR (ro): Tx LPI microsecond timer register
-0x400287EC C FIELD 00w32 TXLPIUSC: TXLPIUSC
-0x400287F0 B REGISTER TX_LPI_TRAN_CNTR (ro): Tx LPI transition counter register
-0x400287F0 C FIELD 00w32 TXLPITRC: TXLPITRC
-0x400287F4 B REGISTER RX_LPI_USEC_CNTR (ro): Rx LPI microsecond counter register
-0x400287F4 C FIELD 00w32 RXLPIUSC: RXLPIUSC
-0x400287F8 B REGISTER RX_LPI_TRAN_CNTR (ro): Rx LPI transition counter register
-0x400287F8 C FIELD 00w32 RXLPITRC: RXLPITRC
-0x40028900 B REGISTER MACL3L4C0R (rw): L3 and L4 control 0 register
-0x40028900 C FIELD 00w01 L3PEN0: L3PEN0
-0x40028900 C FIELD 02w01 L3SAM0: L3SAM0
-0x40028900 C FIELD 03w01 L3SAIM0: L3SAIM0
-0x40028900 C FIELD 04w01 L3DAM0: L3DAM0
-0x40028900 C FIELD 05w01 L3DAIM0: L3DAIM0
-0x40028900 C FIELD 06w05 L3HSBM0: L3HSBM0
-0x40028900 C FIELD 11w05 L3HDBM0: L3HDBM0
-0x40028900 C FIELD 16w01 L4PEN0: L4PEN0
-0x40028900 C FIELD 18w01 L4SPM0: L4SPM0
-0x40028900 C FIELD 19w01 L4SPIM0: L4SPIM0
-0x40028900 C FIELD 20w01 L4DPM0: L4DPM0
-0x40028900 C FIELD 21w01 L4DPIM0: L4DPIM0
-0x40028904 B REGISTER MACL4A0R (rw): Layer4 address filter 0 register
-0x40028904 C FIELD 00w16 L4SP0: L4SP0
-0x40028904 C FIELD 16w16 L4DP0: L4DP0
-0x40028910 B REGISTER MACL3A00R (rw): MACL3A00R
-0x40028910 C FIELD 00w32 L3A00: L3A00
-0x40028914 B REGISTER MACL3A10R (rw): Layer3 address 1 filter 0 register
-0x40028914 C FIELD 00w32 L3A10: L3A10
-0x40028918 B REGISTER MACL3A20 (rw): Layer3 Address 2 filter 0 register
-0x40028918 C FIELD 00w32 L3A20: L3A20
-0x4002891C B REGISTER MACL3A30 (rw): Layer3 Address 3 filter 0 register
-0x4002891C C FIELD 00w32 L3A30: L3A30
-0x40028930 B REGISTER MACL3L4C1R (rw): L3 and L4 control 1 register
-0x40028930 C FIELD 00w01 L3PEN1: L3PEN1
-0x40028930 C FIELD 02w01 L3SAM1: L3SAM1
-0x40028930 C FIELD 03w01 L3SAIM1: L3SAIM1
-0x40028930 C FIELD 04w01 L3DAM1: L3DAM1
-0x40028930 C FIELD 05w01 L3DAIM1: L3DAIM1
-0x40028930 C FIELD 06w05 L3HSBM1: L3HSBM1
-0x40028930 C FIELD 11w05 L3HDBM1: L3HDBM1
-0x40028930 C FIELD 16w01 L4PEN1: L4PEN1
-0x40028930 C FIELD 18w01 L4SPM1: L4SPM1
-0x40028930 C FIELD 19w01 L4SPIM1: L4SPIM1
-0x40028930 C FIELD 20w01 L4DPM1: L4DPM1
-0x40028930 C FIELD 21w01 L4DPIM1: L4DPIM1
-0x40028934 B REGISTER MACL4A1R (rw): Layer 4 address filter 1 register
-0x40028934 C FIELD 00w16 L4SP1: L4SP1
-0x40028934 C FIELD 16w16 L4DP1: L4DP1
-0x40028940 B REGISTER MACL3A01R (rw): Layer3 address 0 filter 1 Register
-0x40028940 C FIELD 00w32 L3A01: L3A01
-0x40028944 B REGISTER MACL3A11R (rw): Layer3 address 1 filter 1 register
-0x40028944 C FIELD 00w32 L3A11: L3A11
-0x40028948 B REGISTER MACL3A21R (rw): Layer3 address 2 filter 1 Register
-0x40028948 C FIELD 00w32 L3A21: L3A21
-0x4002894C B REGISTER MACL3A31R (rw): Layer3 address 3 filter 1 register
-0x4002894C C FIELD 00w32 L3A31: L3A31
-0x40028AE0 B REGISTER MACARPAR (rw): ARP address register
-0x40028AE0 C FIELD 00w32 ARPPA: ARPPA
-0x40028B00 B REGISTER MACTSCR: Timestamp control Register
-0x40028B00 C FIELD 00w01 TSENA (rw): TSENA
-0x40028B00 C FIELD 01w01 TSCFUPDT (rw): TSCFUPDT
-0x40028B00 C FIELD 02w01 TSINIT (rw): TSINIT
-0x40028B00 C FIELD 03w01 TSUPDT (rw): TSUPDT
-0x40028B00 C FIELD 05w01 TSADDREG (rw): TSADDREG
-0x40028B00 C FIELD 08w01 TSENALL (rw): TSENALL
-0x40028B00 C FIELD 09w01 TSCTRLSSR (rw): TSCTRLSSR
-0x40028B00 C FIELD 10w01 TSVER2ENA (rw): TSVER2ENA
-0x40028B00 C FIELD 11w01 TSIPENA (rw): TSIPENA
-0x40028B00 C FIELD 12w01 TSIPV6ENA (rw): TSIPV6ENA
-0x40028B00 C FIELD 13w01 TSIPV4ENA (rw): TSIPV4ENA
-0x40028B00 C FIELD 14w01 TSEVNTENA (rw): TSEVNTENA
-0x40028B00 C FIELD 15w01 TSMSTRENA (rw): TSMSTRENA
-0x40028B00 C FIELD 16w02 SNAPTYPSEL (rw): SNAPTYPSEL
-0x40028B00 C FIELD 18w01 TSENMACADDR (rw): TSENMACADDR
-0x40028B00 C FIELD 19w01 CSC (ro): CSC
-0x40028B00 C FIELD 24w01 TXTSSTSM (rw): TXTSSTSM
-0x40028B04 B REGISTER MACSSIR (rw): Sub-second increment register
-0x40028B04 C FIELD 08w08 SNSINC: SNSINC
-0x40028B04 C FIELD 16w08 SSINC: SSINC
-0x40028B08 B REGISTER MACSTSR (ro): System time seconds register
-0x40028B08 C FIELD 00w32 TSS: TSS
-0x40028B0C B REGISTER MACSTNR (ro): System time nanoseconds register
-0x40028B0C C FIELD 00w31 TSSS: TSSS
-0x40028B10 B REGISTER MACSTSUR (rw): System time seconds update register
-0x40028B10 C FIELD 00w32 TSS: TSS
-0x40028B14 B REGISTER MACSTNUR (rw): System time nanoseconds update register
-0x40028B14 C FIELD 00w31 TSSS: TSSS
-0x40028B14 C FIELD 31w01 ADDSUB: ADDSUB
-0x40028B18 B REGISTER MACTSAR (rw): Timestamp addend register
-0x40028B18 C FIELD 00w32 TSAR: TSAR
-0x40028B20 B REGISTER MACTSSR (ro): Timestamp status register
-0x40028B20 C FIELD 00w01 TSSOVF: TSSOVF
-0x40028B20 C FIELD 01w01 TSTARGT0: TSTARGT0
-0x40028B20 C FIELD 02w01 AUXTSTRIG: AUXTSTRIG
-0x40028B20 C FIELD 03w01 TSTRGTERR0: TSTRGTERR0
-0x40028B20 C FIELD 15w01 TXTSSIS: TXTSSIS
-0x40028B20 C FIELD 16w04 ATSSTN: ATSSTN
-0x40028B20 C FIELD 24w01 ATSSTM: ATSSTM
-0x40028B20 C FIELD 25w05 ATSNS: ATSNS
-0x40028B30 B REGISTER MACTxTSSNR (ro): Tx timestamp status nanoseconds register
-0x40028B30 C FIELD 00w31 TXTSSLO: TXTSSLO
-0x40028B30 C FIELD 31w01 TXTSSMIS: TXTSSMIS
-0x40028B34 B REGISTER MACTxTSSSR (ro): Tx timestamp status seconds register
-0x40028B34 C FIELD 00w32 TXTSSHI: TXTSSHI
-0x40028B40 B REGISTER MACACR (rw): Auxiliary control register
-0x40028B40 C FIELD 00w01 ATSFC: ATSFC
-0x40028B40 C FIELD 04w01 ATSEN0: ATSEN0
-0x40028B40 C FIELD 05w01 ATSEN1: ATSEN1
-0x40028B40 C FIELD 06w01 ATSEN2: ATSEN2
-0x40028B40 C FIELD 07w01 ATSEN3: ATSEN3
-0x40028B48 B REGISTER MACATSNR (ro): Auxiliary timestamp nanoseconds register
-0x40028B48 C FIELD 00w31 AUXTSLO: AUXTSLO
-0x40028B4C B REGISTER MACATSSR (ro): Auxiliary timestamp seconds register
-0x40028B4C C FIELD 00w32 AUXTSHI: AUXTSHI
-0x40028B50 B REGISTER MACTSIACR (rw): Timestamp Ingress asymmetric correction register
-0x40028B50 C FIELD 00w32 OSTIAC: OSTIAC
-0x40028B54 B REGISTER MACTSEACR (rw): Timestamp Egress asymmetric correction register
-0x40028B54 C FIELD 00w32 OSTEAC: OSTEAC
-0x40028B58 B REGISTER MACTSICNR (rw): Timestamp Ingress correction nanosecond register
-0x40028B58 C FIELD 00w32 TSIC: TSIC
-0x40028B5C B REGISTER MACTSECNR (rw): Timestamp Egress correction nanosecond register
-0x40028B5C C FIELD 00w32 TSEC: TSEC
-0x40028B70 B REGISTER MACPPSCR (rw): PPS control register
-0x40028B70 C FIELD 00w04 PPSCTRL: PPSCTRL
-0x40028B70 C FIELD 04w01 PPSEN0: PPSEN0
-0x40028B70 C FIELD 05w02 TRGTMODSEL0: TRGTMODSEL0
-0x40028B80 B REGISTER MACPPSTTSR (rw): PPS target time seconds register
-0x40028B80 C FIELD 00w31 TSTRH0: TSTRH0
-0x40028B84 B REGISTER MACPPSTTNR (rw): PPS target time nanoseconds register
-0x40028B84 C FIELD 00w31 TTSL0: TTSL0
-0x40028B84 C FIELD 31w01 TRGTBUSY0: TRGTBUSY0
-0x40028B88 B REGISTER MACPPSIR (rw): PPS interval register
-0x40028B88 C FIELD 00w32 PPSINT0: PPSINT0
-0x40028B8C B REGISTER MACPPSWR (rw): PPS width register
-0x40028B8C C FIELD 00w32 PPSWIDTH0: PPSWIDTH0
-0x40028BC0 B REGISTER MACPOCR (rw): PTP Offload control register
-0x40028BC0 C FIELD 00w01 PTOEN: PTOEN
-0x40028BC0 C FIELD 01w01 ASYNCEN: ASYNCEN
-0x40028BC0 C FIELD 02w01 APDREQEN: APDREQEN
-0x40028BC0 C FIELD 04w01 ASYNCTRIG: ASYNCTRIG
-0x40028BC0 C FIELD 05w01 APDREQTRIG: APDREQTRIG
-0x40028BC0 C FIELD 06w01 DRRDIS: DRRDIS
-0x40028BC0 C FIELD 08w08 DN: DN
-0x40028BC4 B REGISTER MACSPI0R (rw): PTP Source Port Identity 0 Register
-0x40028BC4 C FIELD 00w32 SPI0: SPI0
-0x40028BC8 B REGISTER MACSPI1R (rw): PTP Source port identity 1 register
-0x40028BC8 C FIELD 00w32 SPI1: SPI1
-0x40028BCC B REGISTER MACSPI2R (rw): PTP Source port identity 2 register
-0x40028BCC C FIELD 00w16 SPI2: SPI2
-0x40028BD0 B REGISTER MACLMIR (rw): Log message interval register
-0x40028BD0 C FIELD 00w08 LSI: LSI
-0x40028BD0 C FIELD 08w03 DRSYNCR: DRSYNCR
-0x40028BD0 C FIELD 24w08 LMPDRI: LMPDRI
-0x40028C00 B REGISTER MTLOMR (rw): Operating mode Register
-0x40028C00 C FIELD 01w01 DTXSTS: DTXSTS
-0x40028C00 C FIELD 08w01 CNTPRST: CNTPRST
-0x40028C00 C FIELD 09w01 CNTCLR: CNTCLR
-0x40028C20 B REGISTER MTLISR (ro): Interrupt status Register
-0x40028C20 C FIELD 00w01 Q0IS: Queue interrupt status
-0x40028D00 B REGISTER MTLTxQOMR: Tx queue operating mode Register
-0x40028D00 C FIELD 00w01 FTQ (rw): Flush Transmit Queue
-0x40028D00 C FIELD 01w01 TSF (rw): Transmit Store and Forward
-0x40028D00 C FIELD 02w02 TXQEN (ro): Transmit Queue Enable
-0x40028D00 C FIELD 04w03 TTC (rw): Transmit Threshold Control
-0x40028D00 C FIELD 16w09 TQS (rw): Transmit Queue Size
-0x40028D04 B REGISTER MTLTxQUR (ro): Tx queue underflow register
-0x40028D04 C FIELD 00w11 UFFRMCNT: Underflow Packet Counter
-0x40028D04 C FIELD 11w01 UFCNTOVF: UFCNTOVF
-0x40028D08 B REGISTER MTLTxQDR (ro): Tx queue debug Register
-0x40028D08 C FIELD 00w01 TXQPAUSED: TXQPAUSED
-0x40028D08 C FIELD 01w02 TRCSTS: TRCSTS
-0x40028D08 C FIELD 03w01 TWCSTS: TWCSTS
-0x40028D08 C FIELD 04w01 TXQSTS: TXQSTS
-0x40028D08 C FIELD 05w01 TXSTSFSTS: TXSTSFSTS
-0x40028D08 C FIELD 16w03 PTXQ: PTXQ
-0x40028D08 C FIELD 20w03 STXSTSF: STXSTSF
-0x40028D2C B REGISTER MTLQICSR (rw): Queue interrupt control status Register
-0x40028D2C C FIELD 00w01 TXUNFIS: TXUNFIS
-0x40028D2C C FIELD 08w01 TXUIE: TXUIE
-0x40028D2C C FIELD 16w01 RXOVFIS: RXOVFIS
-0x40028D2C C FIELD 24w01 RXOIE: RXOIE
-0x40028D30 B REGISTER MTLRxQOMR: Rx queue operating mode register
-0x40028D30 C FIELD 00w02 RTC (rw): RTC
-0x40028D30 C FIELD 03w01 FUP (rw): FUP
-0x40028D30 C FIELD 04w01 FEP (rw): FEP
-0x40028D30 C FIELD 05w01 RSF (rw): RSF
-0x40028D30 C FIELD 06w01 DIS_TCP_EF (rw): DIS_TCP_EF
-0x40028D30 C FIELD 07w01 EHFC (rw): EHFC
-0x40028D30 C FIELD 08w03 RFA (rw): RFA
-0x40028D30 C FIELD 14w03 RFD (rw): RFD
-0x40028D30 C FIELD 20w03 RQS (ro): RQS
-0x40028D34 B REGISTER MTLRxQMPOCR (ro): Rx queue missed packet and overflow counter register
-0x40028D34 C FIELD 00w11 OVFPKTCNT: OVFPKTCNT
-0x40028D34 C FIELD 11w01 OVFCNTOVF: OVFCNTOVF
-0x40028D34 C FIELD 16w11 MISPKTCNT: MISPKTCNT
-0x40028D34 C FIELD 27w01 MISCNTOVF: MISCNTOVF
-0x40028D38 B REGISTER MTLRxQDR (ro): Rx queue debug register
-0x40028D38 C FIELD 00w01 RWCSTS: RWCSTS
-0x40028D38 C FIELD 01w02 RRCSTS: RRCSTS
-0x40028D38 C FIELD 04w02 RXQSTS: RXQSTS
-0x40028D38 C FIELD 16w14 PRXQ: PRXQ
-0x40029000 B REGISTER DMAMR: DMA mode register
-0x40029000 C FIELD 00w01 SWR (rw): Software Reset
-0x40029000 C FIELD 01w01 DA (ro): DMA Tx or Rx Arbitration Scheme
-0x40029000 C FIELD 11w01 TXPR (ro): Transmit priority
-0x40029000 C FIELD 12w03 PR (ro): Priority ratio
-0x40029000 C FIELD 16w01 INTM (rw): Interrupt Mode
-0x40029004 B REGISTER DMASBMR: System bus mode register
-0x40029004 C FIELD 00w01 FB (rw): Fixed Burst Length
-0x40029004 C FIELD 12w01 AAL (rw): Address-Aligned Beats
-0x40029004 C FIELD 14w01 MB (ro): Mixed Burst
-0x40029004 C FIELD 15w01 RB (ro): Rebuild INCRx Burst
-0x40029008 B REGISTER DMAISR (ro): Interrupt status register
-0x40029008 C FIELD 00w01 DC0IS: DMA Channel Interrupt Status
-0x40029008 C FIELD 16w01 MTLIS: MTL Interrupt Status
-0x40029008 C FIELD 17w01 MACIS: MAC Interrupt Status
-0x4002900C B REGISTER DMADSR (ro): Debug status register
-0x4002900C C FIELD 00w01 AXWHSTS: AHB Master Write Channel
-0x4002900C C FIELD 08w04 RPS0: DMA Channel Receive Process State
-0x4002900C C FIELD 12w04 TPS0: DMA Channel Transmit Process State
-0x40029100 B REGISTER DMACCR (rw): Channel control register
-0x40029100 C FIELD 00w14 MSS: Maximum Segment Size
-0x40029100 C FIELD 16w01 PBLX8: 8xPBL mode
-0x40029100 C FIELD 18w03 DSL: Descriptor Skip Length
-0x40029104 B REGISTER DMACTxCR (rw): Channel transmit control register
-0x40029104 C FIELD 00w01 ST: Start or Stop Transmission Command
-0x40029104 C FIELD 04w01 OSF: Operate on Second Packet
-0x40029104 C FIELD 12w01 TSE: TCP Segmentation Enabled
-0x40029104 C FIELD 16w06 TXPBL: Transmit Programmable Burst Length
-0x40029108 B REGISTER DMACRxCR (rw): Channel receive control register
-0x40029108 C FIELD 00w01 SR: Start or Stop Receive Command
-0x40029108 C FIELD 01w14 RBSZ: Receive Buffer size
-0x40029108 C FIELD 16w06 RXPBL: RXPBL
-0x40029108 C FIELD 31w01 RPF: DMA Rx Channel Packet Flush
-0x40029114 B REGISTER DMACTxDLAR (rw): Channel Tx descriptor list address register
-0x40029114 C FIELD 02w30 TDESLA: Start of Transmit List
-0x4002911C B REGISTER DMACRxDLAR (rw): Channel Rx descriptor list address register
-0x4002911C C FIELD 02w30 RDESLA: Start of Receive List
-0x40029120 B REGISTER DMACTxDTPR (rw): Channel Tx descriptor tail pointer register
-0x40029120 C FIELD 02w30 TDT: Transmit Descriptor Tail Pointer
-0x40029128 B REGISTER DMACRxDTPR (rw): Channel Rx descriptor tail pointer register
-0x40029128 C FIELD 02w30 RDT: Receive Descriptor Tail Pointer
-0x4002912C B REGISTER DMACTxRLR (rw): Channel Tx descriptor ring length register
-0x4002912C C FIELD 00w10 TDRL: Transmit Descriptor Ring Length
-0x40029130 B REGISTER DMACRxRLR (rw): Channel Rx descriptor ring length register
-0x40029130 C FIELD 00w10 RDRL: Receive Descriptor Ring Length
-0x40029134 B REGISTER DMACIER (rw): Channel interrupt enable register
-0x40029134 C FIELD 00w01 TIE: Transmit Interrupt Enable
-0x40029134 C FIELD 01w01 TXSE: Transmit Stopped Enable
-0x40029134 C FIELD 02w01 TBUE: Transmit Buffer Unavailable Enable
-0x40029134 C FIELD 06w01 RIE: Receive Interrupt Enable
-0x40029134 C FIELD 07w01 RBUE: Receive Buffer Unavailable Enable
-0x40029134 C FIELD 08w01 RSE: Receive Stopped Enable
-0x40029134 C FIELD 09w01 RWTE: Receive Watchdog Timeout Enable
-0x40029134 C FIELD 10w01 ETIE: Early Transmit Interrupt Enable
-0x40029134 C FIELD 11w01 ERIE: Early Receive Interrupt Enable
-0x40029134 C FIELD 12w01 FBEE: Fatal Bus Error Enable
-0x40029134 C FIELD 13w01 CDEE: Context Descriptor Error Enable
-0x40029134 C FIELD 14w01 AIE: Abnormal Interrupt Summary Enable
-0x40029134 C FIELD 15w01 NIE: Normal Interrupt Summary Enable
-0x40029138 B REGISTER DMACRxIWTR (rw): Channel Rx interrupt watchdog timer register
-0x40029138 C FIELD 00w08 RWT: Receive Interrupt Watchdog Timer Count
-0x40029144 B REGISTER DMACCATxDR (ro): Channel current application transmit descriptor register
-0x40029144 C FIELD 00w32 CURTDESAPTR: Application Transmit Descriptor Address Pointer
-0x4002914C B REGISTER DMACCARxDR (ro): Channel current application receive descriptor register
-0x4002914C C FIELD 00w32 CURRDESAPTR: Application Receive Descriptor Address Pointer
-0x40029154 B REGISTER DMACCATxBR (ro): Channel current application transmit buffer register
-0x40029154 C FIELD 00w32 CURTBUFAPTR: Application Transmit Buffer Address Pointer
-0x4002915C B REGISTER DMACCARxBR (ro): Channel current application receive buffer register
-0x4002915C C FIELD 00w32 CURRBUFAPTR: Application Receive Buffer Address Pointer
-0x40029160 B REGISTER DMACSR: Channel status register
-0x40029160 C FIELD 00w01 TI (rw): Transmit Interrupt
-0x40029160 C FIELD 01w01 TPS (rw): Transmit Process Stopped
-0x40029160 C FIELD 02w01 TBU (rw): Transmit Buffer Unavailable
-0x40029160 C FIELD 06w01 RI (rw): Receive Interrupt
-0x40029160 C FIELD 07w01 RBU (rw): Receive Buffer Unavailable
-0x40029160 C FIELD 08w01 RPS (rw): Receive Process Stopped
-0x40029160 C FIELD 09w01 RWT (rw): Receive Watchdog Timeout
-0x40029160 C FIELD 10w01 ET (rw): Early Transmit Interrupt
-0x40029160 C FIELD 11w01 ER (rw): Early Receive Interrupt
-0x40029160 C FIELD 12w01 FBE (rw): Fatal Bus Error
-0x40029160 C FIELD 13w01 CDE (rw): Context Descriptor Error
-0x40029160 C FIELD 14w01 AIS (rw): Abnormal Interrupt Summary
-0x40029160 C FIELD 15w01 NIS (rw): Normal Interrupt Summary
-0x40029160 C FIELD 16w03 TEB (ro): Tx DMA Error Bits
-0x40029160 C FIELD 19w03 REB (ro): Rx DMA Error Bits
-0x4002916C B REGISTER DMACMFCR (ro): Channel missed frame count register
-0x4002916C C FIELD 00w11 MFC: Dropped Packet Counters
-0x4002916C C FIELD 15w01 MFCO: Overflow status of the MFC Counter
+0x40023000 A PERIPHERAL CRC
+0x40023000 B REGISTER DR (rw): Data register
+0x40023000 B REGISTER DR16 (rw): Data register - half-word sized
+0x40023000 B REGISTER DR8 (rw): Data register - byte sized
+0x40023000 C FIELD 00w08 DR8: Data register bits
+0x40023000 C FIELD 00w16 DR16: Data register bits
+0x40023000 C FIELD 00w32 DR: Data Register
+0x40023004 B REGISTER IDR (rw): Independent Data register
+0x40023004 C FIELD 00w32 IDR: Independent Data register
+0x40023008 B REGISTER CR: Control register
+0x40023008 C FIELD 00w01 RESET (wo): RESET bit
+0x40023008 C FIELD 03w02 POLYSIZE (rw): Polynomial size
+0x40023008 C FIELD 05w02 REV_IN (rw): Reverse input data
+0x40023008 C FIELD 07w01 REV_OUT (rw): Reverse output data
+0x40023010 B REGISTER INIT (rw): Initial CRC value
+0x40023010 C FIELD 00w32 INIT: Programmable initial CRC value
+0x40023014 B REGISTER POL (rw): CRC polynomial
+0x40023014 C FIELD 00w32 POL: Programmable polynomial
0x40040000 A PERIPHERAL OTG1_HS_GLOBAL
0x40040000 B REGISTER GOTGCTL: OTG_HS control and status register
0x40040000 C FIELD 00w01 SRQSCS (ro): Session request success
@@ -12034,1517 +12242,6 @@
0x40040E00 C FIELD 00w01 STPPCLK: Stop PHY clock
0x40040E00 C FIELD 01w01 GATEHCLK: Gate HCLK
0x40040E00 C FIELD 04w01 PHYSUSP: PHY suspended
-0x40080000 A PERIPHERAL OTG2_HS_GLOBAL
-0x40080000 B REGISTER GOTGCTL: OTG_HS control and status register
-0x40080000 C FIELD 00w01 SRQSCS (ro): Session request success
-0x40080000 C FIELD 01w01 SRQ (rw): Session request
-0x40080000 C FIELD 08w01 HNGSCS (ro): Host negotiation success
-0x40080000 C FIELD 09w01 HNPRQ (rw): HNP request
-0x40080000 C FIELD 10w01 HSHNPEN (rw): Host set HNP enable
-0x40080000 C FIELD 11w01 DHNPEN (rw): Device HNP enabled
-0x40080000 C FIELD 12w01 EHEN (rw): Embedded host enable
-0x40080000 C FIELD 16w01 CIDSTS (ro): Connector ID status
-0x40080000 C FIELD 17w01 DBCT (ro): Long/short debounce time
-0x40080000 C FIELD 18w01 ASVLD (ro): A-session valid
-0x40080000 C FIELD 19w01 BSVLD (ro): B-session valid
-0x40080004 B REGISTER GOTGINT (rw): OTG_HS interrupt register
-0x40080004 C FIELD 02w01 SEDET: Session end detected
-0x40080004 C FIELD 08w01 SRSSCHG: Session request success status change
-0x40080004 C FIELD 09w01 HNSSCHG: Host negotiation success status change
-0x40080004 C FIELD 17w01 HNGDET: Host negotiation detected
-0x40080004 C FIELD 18w01 ADTOCHG: A-device timeout change
-0x40080004 C FIELD 19w01 DBCDNE: Debounce done
-0x40080004 C FIELD 20w01 IDCHNG: ID input pin changed
-0x40080008 B REGISTER GAHBCFG (rw): OTG_HS AHB configuration register
-0x40080008 C FIELD 00w01 GINT: Global interrupt mask
-0x40080008 C FIELD 01w04 HBSTLEN: Burst length/type
-0x40080008 C FIELD 05w01 DMAEN: DMA enable
-0x40080008 C FIELD 07w01 TXFELVL: TxFIFO empty level
-0x40080008 C FIELD 08w01 PTXFELVL: Periodic TxFIFO empty level
-0x4008000C B REGISTER GUSBCFG: OTG_HS USB configuration register
-0x4008000C C FIELD 00w03 TOCAL (rw): FS timeout calibration
-0x4008000C C FIELD 06w01 PHYSEL (wo): USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
-0x4008000C C FIELD 08w01 SRPCAP (rw): SRP-capable
-0x4008000C C FIELD 09w01 HNPCAP (rw): HNP-capable
-0x4008000C C FIELD 10w04 TRDT (rw): USB turnaround time
-0x4008000C C FIELD 15w01 PHYLPCS (rw): PHY Low-power clock select
-0x4008000C C FIELD 17w01 ULPIFSLS (rw): ULPI FS/LS select
-0x4008000C C FIELD 18w01 ULPIAR (rw): ULPI Auto-resume
-0x4008000C C FIELD 19w01 ULPICSM (rw): ULPI Clock SuspendM
-0x4008000C C FIELD 20w01 ULPIEVBUSD (rw): ULPI External VBUS Drive
-0x4008000C C FIELD 21w01 ULPIEVBUSI (rw): ULPI external VBUS indicator
-0x4008000C C FIELD 22w01 TSDPS (rw): TermSel DLine pulsing selection
-0x4008000C C FIELD 23w01 PCCI (rw): Indicator complement
-0x4008000C C FIELD 24w01 PTCI (rw): Indicator pass through
-0x4008000C C FIELD 25w01 ULPIIPD (rw): ULPI interface protect disable
-0x4008000C C FIELD 29w01 FHMOD (rw): Forced host mode
-0x4008000C C FIELD 30w01 FDMOD (rw): Forced peripheral mode
-0x40080010 B REGISTER GRSTCTL: OTG_HS reset register
-0x40080010 C FIELD 00w01 CSRST (rw): Core soft reset
-0x40080010 C FIELD 01w01 HSRST (rw): HCLK soft reset
-0x40080010 C FIELD 02w01 FCRST (rw): Host frame counter reset
-0x40080010 C FIELD 04w01 RXFFLSH (rw): RxFIFO flush
-0x40080010 C FIELD 05w01 TXFFLSH (rw): TxFIFO flush
-0x40080010 C FIELD 06w05 TXFNUM (rw): TxFIFO number
-0x40080010 C FIELD 30w01 DMAREQ (ro): DMA request signal enabled for USB OTG HS
-0x40080010 C FIELD 31w01 AHBIDL (ro): AHB master idle
-0x40080014 B REGISTER GINTSTS: OTG_HS core interrupt register
-0x40080014 C FIELD 00w01 CMOD (ro): Current mode of operation
-0x40080014 C FIELD 01w01 MMIS (rw): Mode mismatch interrupt
-0x40080014 C FIELD 02w01 OTGINT (ro): OTG interrupt
-0x40080014 C FIELD 03w01 SOF (rw): Start of frame
-0x40080014 C FIELD 04w01 RXFLVL (ro): RxFIFO nonempty
-0x40080014 C FIELD 05w01 NPTXFE (ro): Nonperiodic TxFIFO empty
-0x40080014 C FIELD 06w01 GINAKEFF (ro): Global IN nonperiodic NAK effective
-0x40080014 C FIELD 07w01 BOUTNAKEFF (ro): Global OUT NAK effective
-0x40080014 C FIELD 10w01 ESUSP (rw): Early suspend
-0x40080014 C FIELD 11w01 USBSUSP (rw): USB suspend
-0x40080014 C FIELD 12w01 USBRST (rw): USB reset
-0x40080014 C FIELD 13w01 ENUMDNE (rw): Enumeration done
-0x40080014 C FIELD 14w01 ISOODRP (rw): Isochronous OUT packet dropped interrupt
-0x40080014 C FIELD 15w01 EOPF (rw): End of periodic frame interrupt
-0x40080014 C FIELD 18w01 IEPINT (ro): IN endpoint interrupt
-0x40080014 C FIELD 19w01 OEPINT (ro): OUT endpoint interrupt
-0x40080014 C FIELD 20w01 IISOIXFR (rw): Incomplete isochronous IN transfer
-0x40080014 C FIELD 21w01 PXFR_INCOMPISOOUT (rw): Incomplete periodic transfer
-0x40080014 C FIELD 22w01 DATAFSUSP (rw): Data fetch suspended
-0x40080014 C FIELD 24w01 HPRTINT (ro): Host port interrupt
-0x40080014 C FIELD 25w01 HCINT (ro): Host channels interrupt
-0x40080014 C FIELD 26w01 PTXFE (ro): Periodic TxFIFO empty
-0x40080014 C FIELD 28w01 CIDSCHG (rw): Connector ID status change
-0x40080014 C FIELD 29w01 DISCINT (rw): Disconnect detected interrupt
-0x40080014 C FIELD 30w01 SRQINT (rw): Session request/new session detected interrupt
-0x40080014 C FIELD 31w01 WKUINT (rw): Resume/remote wakeup detected interrupt
-0x40080018 B REGISTER GINTMSK: OTG_HS interrupt mask register
-0x40080018 C FIELD 01w01 MMISM (rw): Mode mismatch interrupt mask
-0x40080018 C FIELD 02w01 OTGINT (rw): OTG interrupt mask
-0x40080018 C FIELD 03w01 SOFM (rw): Start of frame mask
-0x40080018 C FIELD 04w01 RXFLVLM (rw): Receive FIFO nonempty mask
-0x40080018 C FIELD 05w01 NPTXFEM (rw): Nonperiodic TxFIFO empty mask
-0x40080018 C FIELD 06w01 GINAKEFFM (rw): Global nonperiodic IN NAK effective mask
-0x40080018 C FIELD 07w01 GONAKEFFM (rw): Global OUT NAK effective mask
-0x40080018 C FIELD 10w01 ESUSPM (rw): Early suspend mask
-0x40080018 C FIELD 11w01 USBSUSPM (rw): USB suspend mask
-0x40080018 C FIELD 12w01 USBRST (rw): USB reset mask
-0x40080018 C FIELD 13w01 ENUMDNEM (rw): Enumeration done mask
-0x40080018 C FIELD 14w01 ISOODRPM (rw): Isochronous OUT packet dropped interrupt mask
-0x40080018 C FIELD 15w01 EOPFM (rw): End of periodic frame interrupt mask
-0x40080018 C FIELD 18w01 IEPINT (rw): IN endpoints interrupt mask
-0x40080018 C FIELD 19w01 OEPINT (rw): OUT endpoints interrupt mask
-0x40080018 C FIELD 20w01 IISOIXFRM (rw): Incomplete isochronous IN transfer mask
-0x40080018 C FIELD 21w01 PXFRM_IISOOXFRM (rw): Incomplete periodic transfer mask
-0x40080018 C FIELD 22w01 FSUSPM (rw): Data fetch suspended mask
-0x40080018 C FIELD 23w01 RSTDE (rw): Reset detected interrupt mask
-0x40080018 C FIELD 24w01 PRTIM (ro): Host port interrupt mask
-0x40080018 C FIELD 25w01 HCIM (rw): Host channels interrupt mask
-0x40080018 C FIELD 26w01 PTXFEM (rw): Periodic TxFIFO empty mask
-0x40080018 C FIELD 27w01 LPMINTM (rw): LPM interrupt mask
-0x40080018 C FIELD 28w01 CIDSCHGM (rw): Connector ID status change mask
-0x40080018 C FIELD 29w01 DISCINT (rw): Disconnect detected interrupt mask
-0x40080018 C FIELD 30w01 SRQIM (rw): Session request/new session detected interrupt mask
-0x40080018 C FIELD 31w01 WUIM (rw): Resume/remote wakeup detected interrupt mask
-0x4008001C B REGISTER GRXSTSR_Device (ro): OTG_HS Receive status debug read register (peripheral mode mode)
-0x4008001C B REGISTER GRXSTSR_Host (ro): OTG_HS Receive status debug read register (host mode)
-0x4008001C C FIELD 00w04 CHNUM: Channel number
-0x4008001C C FIELD 00w04 EPNUM: Endpoint number
-0x4008001C C FIELD 04w11 BCNT: Byte count
-0x4008001C C FIELD 04w11 BCNT: Byte count
-0x4008001C C FIELD 15w02 DPID: Data PID
-0x4008001C C FIELD 15w02 DPID: Data PID
-0x4008001C C FIELD 17w04 PKTSTS: Packet status
-0x4008001C C FIELD 17w04 PKTSTS: Packet status
-0x4008001C C FIELD 21w04 FRMNUM: Frame number
-0x40080020 B REGISTER GRXSTSP_Device (ro): OTG_HS status read and pop register (peripheral mode)
-0x40080020 B REGISTER GRXSTSP_Host (ro): OTG_HS status read and pop register (host mode)
-0x40080020 C FIELD 00w04 CHNUM: Channel number
-0x40080020 C FIELD 00w04 EPNUM: Endpoint number
-0x40080020 C FIELD 04w11 BCNT: Byte count
-0x40080020 C FIELD 04w11 BCNT: Byte count
-0x40080020 C FIELD 15w02 DPID: Data PID
-0x40080020 C FIELD 15w02 DPID: Data PID
-0x40080020 C FIELD 17w04 PKTSTS: Packet status
-0x40080020 C FIELD 17w04 PKTSTS: Packet status
-0x40080020 C FIELD 21w04 FRMNUM: Frame number
-0x40080024 B REGISTER GRXFSIZ (rw): OTG_HS Receive FIFO size register
-0x40080024 C FIELD 00w16 RXFD: RxFIFO depth
-0x40080028 B REGISTER DIEPTXF0_Device (rw): Endpoint 0 transmit FIFO size (peripheral mode)
-0x40080028 B REGISTER HNPTXFSIZ_Host (rw): OTG_HS nonperiodic transmit FIFO size register (host mode)
-0x40080028 C FIELD 00w16 NPTXFSA: Nonperiodic transmit RAM start address
-0x40080028 C FIELD 00w16 TX0FSA: Endpoint 0 transmit RAM start address
-0x40080028 C FIELD 16w16 NPTXFD: Nonperiodic TxFIFO depth
-0x40080028 C FIELD 16w16 TX0FD: Endpoint 0 TxFIFO depth
-0x4008002C B REGISTER GNPTXSTS (ro): OTG_HS nonperiodic transmit FIFO/queue status register
-0x4008002C C FIELD 00w16 NPTXFSAV: Nonperiodic TxFIFO space available
-0x4008002C C FIELD 16w08 NPTQXSAV: Nonperiodic transmit request queue space available
-0x4008002C C FIELD 24w07 NPTXQTOP: Top of the nonperiodic transmit request queue
-0x40080038 B REGISTER GCCFG (rw): OTG_HS general core configuration register
-0x40080038 C FIELD 00w01 DCDET: Data contact detection (DCD) status
-0x40080038 C FIELD 01w01 PDET: Primary detection (PD) status
-0x40080038 C FIELD 02w01 SDET: Secondary detection (SD) status
-0x40080038 C FIELD 03w01 PS2DET: DM pull-up detection status
-0x40080038 C FIELD 16w01 PWRDWN: Power down
-0x40080038 C FIELD 17w01 BCDEN: Battery charging detector (BCD) enable
-0x40080038 C FIELD 18w01 DCDEN: Data contact detection (DCD) mode enable
-0x40080038 C FIELD 19w01 PDEN: Primary detection (PD) mode enable
-0x40080038 C FIELD 20w01 SDEN: Secondary detection (SD) mode enable
-0x40080038 C FIELD 21w01 VBDEN: USB VBUS detection enable
-0x4008003C B REGISTER CID (rw): OTG_HS core ID register
-0x4008003C C FIELD 00w32 PRODUCT_ID: Product ID field
-0x40080054 B REGISTER GLPMCFG: OTG core LPM configuration register
-0x40080054 C FIELD 00w01 LPMEN (rw): LPM support enable
-0x40080054 C FIELD 01w01 LPMACK (rw): LPM token acknowledge enable
-0x40080054 C FIELD 02w04 BESL (ro): Best effort service latency
-0x40080054 C FIELD 06w01 REMWAKE (ro): bRemoteWake value
-0x40080054 C FIELD 07w01 L1SSEN (rw): L1 Shallow Sleep enable
-0x40080054 C FIELD 08w04 BESLTHRS (rw): BESL threshold
-0x40080054 C FIELD 12w01 L1DSEN (rw): L1 deep sleep enable
-0x40080054 C FIELD 13w02 LPMRST (ro): LPM response
-0x40080054 C FIELD 15w01 SLPSTS (ro): Port sleep status
-0x40080054 C FIELD 16w01 L1RSMOK (ro): Sleep State Resume OK
-0x40080054 C FIELD 17w04 LPMCHIDX (rw): LPM Channel Index
-0x40080054 C FIELD 21w03 LPMRCNT (rw): LPM retry count
-0x40080054 C FIELD 24w01 SNDLPM (rw): Send LPM transaction
-0x40080054 C FIELD 25w03 LPMRCNTSTS (ro): LPM retry count status
-0x40080054 C FIELD 28w01 ENBESL (rw): Enable best effort service latency
-0x40080100 B REGISTER HPTXFSIZ (rw): OTG_HS Host periodic transmit FIFO size register
-0x40080100 C FIELD 00w16 PTXSA: Host periodic TxFIFO start address
-0x40080100 C FIELD 16w16 PTXFD: Host periodic TxFIFO depth
-0x40080104 B REGISTER DIEPTXF1 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x40080104 C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x40080104 C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x40080108 B REGISTER DIEPTXF2 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x40080108 C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x40080108 C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x4008011C B REGISTER DIEPTXF3 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x4008011C C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x4008011C C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x40080120 B REGISTER DIEPTXF4 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x40080120 C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x40080120 C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x40080124 B REGISTER DIEPTXF5 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x40080124 C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x40080124 C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x40080128 B REGISTER DIEPTXF6 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x40080128 C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x40080128 C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x4008012C B REGISTER DIEPTXF7 (rw): OTG_HS device IN endpoint transmit FIFO size register
-0x4008012C C FIELD 00w16 INEPTXSA: IN endpoint FIFOx transmit RAM start address
-0x4008012C C FIELD 16w16 INEPTXFD: IN endpoint TxFIFO depth
-0x40080400 A PERIPHERAL OTG2_HS_HOST
-0x40080400 B REGISTER HCFG: OTG_HS host configuration register
-0x40080400 C FIELD 00w02 FSLSPCS (rw): FS/LS PHY clock select
-0x40080400 C FIELD 02w01 FSLSS (ro): FS- and LS-only support
-0x40080404 B REGISTER HFIR (rw): OTG_HS Host frame interval register
-0x40080404 C FIELD 00w16 FRIVL: Frame interval
-0x40080408 B REGISTER HFNUM (ro): OTG_HS host frame number/frame time remaining register
-0x40080408 C FIELD 00w16 FRNUM: Frame number
-0x40080408 C FIELD 16w16 FTREM: Frame time remaining
-0x40080410 B REGISTER HPTXSTS: OTG_HS_Host periodic transmit FIFO/queue status register
-0x40080410 C FIELD 00w16 PTXFSAVL (rw): Periodic transmit data FIFO space available
-0x40080410 C FIELD 16w08 PTXQSAV (ro): Periodic transmit request queue space available
-0x40080410 C FIELD 24w08 PTXQTOP (ro): Top of the periodic transmit request queue
-0x40080414 B REGISTER HAINT (ro): OTG_HS Host all channels interrupt register
-0x40080414 C FIELD 00w16 HAINT: Channel interrupts
-0x40080418 B REGISTER HAINTMSK (rw): OTG_HS host all channels interrupt mask register
-0x40080418 C FIELD 00w16 HAINTM: Channel interrupt mask
-0x40080440 B REGISTER HPRT: OTG_HS host port control and status register
-0x40080440 C FIELD 00w01 PCSTS (ro): Port connect status
-0x40080440 C FIELD 01w01 PCDET (rw): Port connect detected
-0x40080440 C FIELD 02w01 PENA (rw): Port enable
-0x40080440 C FIELD 03w01 PENCHNG (rw): Port enable/disable change
-0x40080440 C FIELD 04w01 POCA (ro): Port overcurrent active
-0x40080440 C FIELD 05w01 POCCHNG (rw): Port overcurrent change
-0x40080440 C FIELD 06w01 PRES (rw): Port resume
-0x40080440 C FIELD 07w01 PSUSP (rw): Port suspend
-0x40080440 C FIELD 08w01 PRST (rw): Port reset
-0x40080440 C FIELD 10w02 PLSTS (ro): Port line status
-0x40080440 C FIELD 12w01 PPWR (rw): Port power
-0x40080440 C FIELD 13w04 PTCTL (rw): Port test control
-0x40080440 C FIELD 17w02 PSPD (ro): Port speed
-0x40080500 B REGISTER HCCHAR0 (rw): OTG_HS host channel-0 characteristics register
-0x40080500 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080500 C FIELD 11w04 EPNUM: Endpoint number
-0x40080500 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080500 C FIELD 17w01 LSDEV: Low-speed device
-0x40080500 C FIELD 18w02 EPTYP: Endpoint type
-0x40080500 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080500 C FIELD 22w07 DAD: Device address
-0x40080500 C FIELD 29w01 ODDFRM: Odd frame
-0x40080500 C FIELD 30w01 CHDIS: Channel disable
-0x40080500 C FIELD 31w01 CHENA: Channel enable
-0x40080504 B REGISTER HCSPLT0 (rw): OTG_HS host channel-0 split control register
-0x40080504 C FIELD 00w07 PRTADDR: Port address
-0x40080504 C FIELD 07w07 HUBADDR: Hub address
-0x40080504 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080504 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080504 C FIELD 31w01 SPLITEN: Split enable
-0x40080508 B REGISTER HCINT0 (rw): OTG_HS host channel-11 interrupt register
-0x40080508 C FIELD 00w01 XFRC: Transfer completed
-0x40080508 C FIELD 01w01 CHH: Channel halted
-0x40080508 C FIELD 02w01 AHBERR: AHB error
-0x40080508 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080508 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080508 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080508 C FIELD 06w01 NYET: Response received interrupt
-0x40080508 C FIELD 07w01 TXERR: Transaction error
-0x40080508 C FIELD 08w01 BBERR: Babble error
-0x40080508 C FIELD 09w01 FRMOR: Frame overrun
-0x40080508 C FIELD 10w01 DTERR: Data toggle error
-0x4008050C B REGISTER HCINTMSK0 (rw): OTG_HS host channel-11 interrupt mask register
-0x4008050C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008050C C FIELD 01w01 CHHM: Channel halted mask
-0x4008050C C FIELD 02w01 AHBERR: AHB error
-0x4008050C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008050C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008050C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008050C C FIELD 06w01 NYET: response received interrupt mask
-0x4008050C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008050C C FIELD 08w01 BBERRM: Babble error mask
-0x4008050C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008050C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080510 B REGISTER HCTSIZ0 (rw): OTG_HS host channel-11 transfer size register
-0x40080510 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080510 C FIELD 19w10 PKTCNT: Packet count
-0x40080510 C FIELD 29w02 DPID: Data PID
-0x40080514 B REGISTER HCDMA0 (rw): OTG_HS host channel-0 DMA address register
-0x40080514 C FIELD 00w32 DMAADDR: DMA address
-0x40080520 B REGISTER HCCHAR1 (rw): OTG_HS host channel-1 characteristics register
-0x40080520 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080520 C FIELD 11w04 EPNUM: Endpoint number
-0x40080520 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080520 C FIELD 17w01 LSDEV: Low-speed device
-0x40080520 C FIELD 18w02 EPTYP: Endpoint type
-0x40080520 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080520 C FIELD 22w07 DAD: Device address
-0x40080520 C FIELD 29w01 ODDFRM: Odd frame
-0x40080520 C FIELD 30w01 CHDIS: Channel disable
-0x40080520 C FIELD 31w01 CHENA: Channel enable
-0x40080524 B REGISTER HCSPLT1 (rw): OTG_HS host channel-1 split control register
-0x40080524 C FIELD 00w07 PRTADDR: Port address
-0x40080524 C FIELD 07w07 HUBADDR: Hub address
-0x40080524 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080524 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080524 C FIELD 31w01 SPLITEN: Split enable
-0x40080528 B REGISTER HCINT1 (rw): OTG_HS host channel-1 interrupt register
-0x40080528 C FIELD 00w01 XFRC: Transfer completed
-0x40080528 C FIELD 01w01 CHH: Channel halted
-0x40080528 C FIELD 02w01 AHBERR: AHB error
-0x40080528 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080528 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080528 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080528 C FIELD 06w01 NYET: Response received interrupt
-0x40080528 C FIELD 07w01 TXERR: Transaction error
-0x40080528 C FIELD 08w01 BBERR: Babble error
-0x40080528 C FIELD 09w01 FRMOR: Frame overrun
-0x40080528 C FIELD 10w01 DTERR: Data toggle error
-0x4008052C B REGISTER HCINTMSK1 (rw): OTG_HS host channel-1 interrupt mask register
-0x4008052C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008052C C FIELD 01w01 CHHM: Channel halted mask
-0x4008052C C FIELD 02w01 AHBERR: AHB error
-0x4008052C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008052C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008052C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008052C C FIELD 06w01 NYET: response received interrupt mask
-0x4008052C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008052C C FIELD 08w01 BBERRM: Babble error mask
-0x4008052C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008052C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080530 B REGISTER HCTSIZ1 (rw): OTG_HS host channel-1 transfer size register
-0x40080530 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080530 C FIELD 19w10 PKTCNT: Packet count
-0x40080530 C FIELD 29w02 DPID: Data PID
-0x40080534 B REGISTER HCDMA1 (rw): OTG_HS host channel-1 DMA address register
-0x40080534 C FIELD 00w32 DMAADDR: DMA address
-0x40080540 B REGISTER HCCHAR2 (rw): OTG_HS host channel-2 characteristics register
-0x40080540 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080540 C FIELD 11w04 EPNUM: Endpoint number
-0x40080540 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080540 C FIELD 17w01 LSDEV: Low-speed device
-0x40080540 C FIELD 18w02 EPTYP: Endpoint type
-0x40080540 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080540 C FIELD 22w07 DAD: Device address
-0x40080540 C FIELD 29w01 ODDFRM: Odd frame
-0x40080540 C FIELD 30w01 CHDIS: Channel disable
-0x40080540 C FIELD 31w01 CHENA: Channel enable
-0x40080544 B REGISTER HCSPLT2 (rw): OTG_HS host channel-2 split control register
-0x40080544 C FIELD 00w07 PRTADDR: Port address
-0x40080544 C FIELD 07w07 HUBADDR: Hub address
-0x40080544 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080544 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080544 C FIELD 31w01 SPLITEN: Split enable
-0x40080548 B REGISTER HCINT2 (rw): OTG_HS host channel-2 interrupt register
-0x40080548 C FIELD 00w01 XFRC: Transfer completed
-0x40080548 C FIELD 01w01 CHH: Channel halted
-0x40080548 C FIELD 02w01 AHBERR: AHB error
-0x40080548 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080548 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080548 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080548 C FIELD 06w01 NYET: Response received interrupt
-0x40080548 C FIELD 07w01 TXERR: Transaction error
-0x40080548 C FIELD 08w01 BBERR: Babble error
-0x40080548 C FIELD 09w01 FRMOR: Frame overrun
-0x40080548 C FIELD 10w01 DTERR: Data toggle error
-0x4008054C B REGISTER HCINTMSK2 (rw): OTG_HS host channel-2 interrupt mask register
-0x4008054C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008054C C FIELD 01w01 CHHM: Channel halted mask
-0x4008054C C FIELD 02w01 AHBERR: AHB error
-0x4008054C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008054C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008054C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008054C C FIELD 06w01 NYET: response received interrupt mask
-0x4008054C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008054C C FIELD 08w01 BBERRM: Babble error mask
-0x4008054C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008054C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080550 B REGISTER HCTSIZ2 (rw): OTG_HS host channel-2 transfer size register
-0x40080550 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080550 C FIELD 19w10 PKTCNT: Packet count
-0x40080550 C FIELD 29w02 DPID: Data PID
-0x40080554 B REGISTER HCDMA2 (rw): OTG_HS host channel-2 DMA address register
-0x40080554 C FIELD 00w32 DMAADDR: DMA address
-0x40080560 B REGISTER HCCHAR3 (rw): OTG_HS host channel-3 characteristics register
-0x40080560 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080560 C FIELD 11w04 EPNUM: Endpoint number
-0x40080560 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080560 C FIELD 17w01 LSDEV: Low-speed device
-0x40080560 C FIELD 18w02 EPTYP: Endpoint type
-0x40080560 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080560 C FIELD 22w07 DAD: Device address
-0x40080560 C FIELD 29w01 ODDFRM: Odd frame
-0x40080560 C FIELD 30w01 CHDIS: Channel disable
-0x40080560 C FIELD 31w01 CHENA: Channel enable
-0x40080564 B REGISTER HCSPLT3 (rw): OTG_HS host channel-3 split control register
-0x40080564 C FIELD 00w07 PRTADDR: Port address
-0x40080564 C FIELD 07w07 HUBADDR: Hub address
-0x40080564 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080564 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080564 C FIELD 31w01 SPLITEN: Split enable
-0x40080568 B REGISTER HCINT3 (rw): OTG_HS host channel-3 interrupt register
-0x40080568 C FIELD 00w01 XFRC: Transfer completed
-0x40080568 C FIELD 01w01 CHH: Channel halted
-0x40080568 C FIELD 02w01 AHBERR: AHB error
-0x40080568 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080568 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080568 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080568 C FIELD 06w01 NYET: Response received interrupt
-0x40080568 C FIELD 07w01 TXERR: Transaction error
-0x40080568 C FIELD 08w01 BBERR: Babble error
-0x40080568 C FIELD 09w01 FRMOR: Frame overrun
-0x40080568 C FIELD 10w01 DTERR: Data toggle error
-0x4008056C B REGISTER HCINTMSK3 (rw): OTG_HS host channel-3 interrupt mask register
-0x4008056C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008056C C FIELD 01w01 CHHM: Channel halted mask
-0x4008056C C FIELD 02w01 AHBERR: AHB error
-0x4008056C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008056C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008056C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008056C C FIELD 06w01 NYET: response received interrupt mask
-0x4008056C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008056C C FIELD 08w01 BBERRM: Babble error mask
-0x4008056C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008056C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080570 B REGISTER HCTSIZ3 (rw): OTG_HS host channel-3 transfer size register
-0x40080570 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080570 C FIELD 19w10 PKTCNT: Packet count
-0x40080570 C FIELD 29w02 DPID: Data PID
-0x40080574 B REGISTER HCDMA3 (rw): OTG_HS host channel-3 DMA address register
-0x40080574 C FIELD 00w32 DMAADDR: DMA address
-0x40080580 B REGISTER HCCHAR4 (rw): OTG_HS host channel-4 characteristics register
-0x40080580 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080580 C FIELD 11w04 EPNUM: Endpoint number
-0x40080580 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080580 C FIELD 17w01 LSDEV: Low-speed device
-0x40080580 C FIELD 18w02 EPTYP: Endpoint type
-0x40080580 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080580 C FIELD 22w07 DAD: Device address
-0x40080580 C FIELD 29w01 ODDFRM: Odd frame
-0x40080580 C FIELD 30w01 CHDIS: Channel disable
-0x40080580 C FIELD 31w01 CHENA: Channel enable
-0x40080584 B REGISTER HCSPLT4 (rw): OTG_HS host channel-4 split control register
-0x40080584 C FIELD 00w07 PRTADDR: Port address
-0x40080584 C FIELD 07w07 HUBADDR: Hub address
-0x40080584 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080584 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080584 C FIELD 31w01 SPLITEN: Split enable
-0x40080588 B REGISTER HCINT4 (rw): OTG_HS host channel-4 interrupt register
-0x40080588 C FIELD 00w01 XFRC: Transfer completed
-0x40080588 C FIELD 01w01 CHH: Channel halted
-0x40080588 C FIELD 02w01 AHBERR: AHB error
-0x40080588 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080588 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080588 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080588 C FIELD 06w01 NYET: Response received interrupt
-0x40080588 C FIELD 07w01 TXERR: Transaction error
-0x40080588 C FIELD 08w01 BBERR: Babble error
-0x40080588 C FIELD 09w01 FRMOR: Frame overrun
-0x40080588 C FIELD 10w01 DTERR: Data toggle error
-0x4008058C B REGISTER HCINTMSK4 (rw): OTG_HS host channel-4 interrupt mask register
-0x4008058C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008058C C FIELD 01w01 CHHM: Channel halted mask
-0x4008058C C FIELD 02w01 AHBERR: AHB error
-0x4008058C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008058C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008058C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008058C C FIELD 06w01 NYET: response received interrupt mask
-0x4008058C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008058C C FIELD 08w01 BBERRM: Babble error mask
-0x4008058C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008058C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080590 B REGISTER HCTSIZ4 (rw): OTG_HS host channel-4 transfer size register
-0x40080590 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080590 C FIELD 19w10 PKTCNT: Packet count
-0x40080590 C FIELD 29w02 DPID: Data PID
-0x40080594 B REGISTER HCDMA4 (rw): OTG_HS host channel-4 DMA address register
-0x40080594 C FIELD 00w32 DMAADDR: DMA address
-0x400805A0 B REGISTER HCCHAR5 (rw): OTG_HS host channel-5 characteristics register
-0x400805A0 C FIELD 00w11 MPSIZ: Maximum packet size
-0x400805A0 C FIELD 11w04 EPNUM: Endpoint number
-0x400805A0 C FIELD 15w01 EPDIR: Endpoint direction
-0x400805A0 C FIELD 17w01 LSDEV: Low-speed device
-0x400805A0 C FIELD 18w02 EPTYP: Endpoint type
-0x400805A0 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x400805A0 C FIELD 22w07 DAD: Device address
-0x400805A0 C FIELD 29w01 ODDFRM: Odd frame
-0x400805A0 C FIELD 30w01 CHDIS: Channel disable
-0x400805A0 C FIELD 31w01 CHENA: Channel enable
-0x400805A4 B REGISTER HCSPLT5 (rw): OTG_HS host channel-5 split control register
-0x400805A4 C FIELD 00w07 PRTADDR: Port address
-0x400805A4 C FIELD 07w07 HUBADDR: Hub address
-0x400805A4 C FIELD 14w02 XACTPOS: XACTPOS
-0x400805A4 C FIELD 16w01 COMPLSPLT: Do complete split
-0x400805A4 C FIELD 31w01 SPLITEN: Split enable
-0x400805A8 B REGISTER HCINT5 (rw): OTG_HS host channel-5 interrupt register
-0x400805A8 C FIELD 00w01 XFRC: Transfer completed
-0x400805A8 C FIELD 01w01 CHH: Channel halted
-0x400805A8 C FIELD 02w01 AHBERR: AHB error
-0x400805A8 C FIELD 03w01 STALL: STALL response received interrupt
-0x400805A8 C FIELD 04w01 NAK: NAK response received interrupt
-0x400805A8 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x400805A8 C FIELD 06w01 NYET: Response received interrupt
-0x400805A8 C FIELD 07w01 TXERR: Transaction error
-0x400805A8 C FIELD 08w01 BBERR: Babble error
-0x400805A8 C FIELD 09w01 FRMOR: Frame overrun
-0x400805A8 C FIELD 10w01 DTERR: Data toggle error
-0x400805AC B REGISTER HCINTMSK5 (rw): OTG_HS host channel-5 interrupt mask register
-0x400805AC C FIELD 00w01 XFRCM: Transfer completed mask
-0x400805AC C FIELD 01w01 CHHM: Channel halted mask
-0x400805AC C FIELD 02w01 AHBERR: AHB error
-0x400805AC C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x400805AC C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x400805AC C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x400805AC C FIELD 06w01 NYET: response received interrupt mask
-0x400805AC C FIELD 07w01 TXERRM: Transaction error mask
-0x400805AC C FIELD 08w01 BBERRM: Babble error mask
-0x400805AC C FIELD 09w01 FRMORM: Frame overrun mask
-0x400805AC C FIELD 10w01 DTERRM: Data toggle error mask
-0x400805B0 B REGISTER HCTSIZ5 (rw): OTG_HS host channel-5 transfer size register
-0x400805B0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400805B0 C FIELD 19w10 PKTCNT: Packet count
-0x400805B0 C FIELD 29w02 DPID: Data PID
-0x400805B4 B REGISTER HCDMA5 (rw): OTG_HS host channel-5 DMA address register
-0x400805B4 C FIELD 00w32 DMAADDR: DMA address
-0x400805C0 B REGISTER HCCHAR6 (rw): OTG_HS host channel-6 characteristics register
-0x400805C0 C FIELD 00w11 MPSIZ: Maximum packet size
-0x400805C0 C FIELD 11w04 EPNUM: Endpoint number
-0x400805C0 C FIELD 15w01 EPDIR: Endpoint direction
-0x400805C0 C FIELD 17w01 LSDEV: Low-speed device
-0x400805C0 C FIELD 18w02 EPTYP: Endpoint type
-0x400805C0 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x400805C0 C FIELD 22w07 DAD: Device address
-0x400805C0 C FIELD 29w01 ODDFRM: Odd frame
-0x400805C0 C FIELD 30w01 CHDIS: Channel disable
-0x400805C0 C FIELD 31w01 CHENA: Channel enable
-0x400805C4 B REGISTER HCSPLT6 (rw): OTG_HS host channel-6 split control register
-0x400805C4 C FIELD 00w07 PRTADDR: Port address
-0x400805C4 C FIELD 07w07 HUBADDR: Hub address
-0x400805C4 C FIELD 14w02 XACTPOS: XACTPOS
-0x400805C4 C FIELD 16w01 COMPLSPLT: Do complete split
-0x400805C4 C FIELD 31w01 SPLITEN: Split enable
-0x400805C8 B REGISTER HCINT6 (rw): OTG_HS host channel-6 interrupt register
-0x400805C8 C FIELD 00w01 XFRC: Transfer completed
-0x400805C8 C FIELD 01w01 CHH: Channel halted
-0x400805C8 C FIELD 02w01 AHBERR: AHB error
-0x400805C8 C FIELD 03w01 STALL: STALL response received interrupt
-0x400805C8 C FIELD 04w01 NAK: NAK response received interrupt
-0x400805C8 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x400805C8 C FIELD 06w01 NYET: Response received interrupt
-0x400805C8 C FIELD 07w01 TXERR: Transaction error
-0x400805C8 C FIELD 08w01 BBERR: Babble error
-0x400805C8 C FIELD 09w01 FRMOR: Frame overrun
-0x400805C8 C FIELD 10w01 DTERR: Data toggle error
-0x400805CC B REGISTER HCINTMSK6 (rw): OTG_HS host channel-6 interrupt mask register
-0x400805CC C FIELD 00w01 XFRCM: Transfer completed mask
-0x400805CC C FIELD 01w01 CHHM: Channel halted mask
-0x400805CC C FIELD 02w01 AHBERR: AHB error
-0x400805CC C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x400805CC C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x400805CC C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x400805CC C FIELD 06w01 NYET: response received interrupt mask
-0x400805CC C FIELD 07w01 TXERRM: Transaction error mask
-0x400805CC C FIELD 08w01 BBERRM: Babble error mask
-0x400805CC C FIELD 09w01 FRMORM: Frame overrun mask
-0x400805CC C FIELD 10w01 DTERRM: Data toggle error mask
-0x400805D0 B REGISTER HCTSIZ6 (rw): OTG_HS host channel-6 transfer size register
-0x400805D0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400805D0 C FIELD 19w10 PKTCNT: Packet count
-0x400805D0 C FIELD 29w02 DPID: Data PID
-0x400805D4 B REGISTER HCDMA6 (rw): OTG_HS host channel-6 DMA address register
-0x400805D4 C FIELD 00w32 DMAADDR: DMA address
-0x400805E0 B REGISTER HCCHAR7 (rw): OTG_HS host channel-7 characteristics register
-0x400805E0 C FIELD 00w11 MPSIZ: Maximum packet size
-0x400805E0 C FIELD 11w04 EPNUM: Endpoint number
-0x400805E0 C FIELD 15w01 EPDIR: Endpoint direction
-0x400805E0 C FIELD 17w01 LSDEV: Low-speed device
-0x400805E0 C FIELD 18w02 EPTYP: Endpoint type
-0x400805E0 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x400805E0 C FIELD 22w07 DAD: Device address
-0x400805E0 C FIELD 29w01 ODDFRM: Odd frame
-0x400805E0 C FIELD 30w01 CHDIS: Channel disable
-0x400805E0 C FIELD 31w01 CHENA: Channel enable
-0x400805E4 B REGISTER HCSPLT7 (rw): OTG_HS host channel-7 split control register
-0x400805E4 C FIELD 00w07 PRTADDR: Port address
-0x400805E4 C FIELD 07w07 HUBADDR: Hub address
-0x400805E4 C FIELD 14w02 XACTPOS: XACTPOS
-0x400805E4 C FIELD 16w01 COMPLSPLT: Do complete split
-0x400805E4 C FIELD 31w01 SPLITEN: Split enable
-0x400805E8 B REGISTER HCINT7 (rw): OTG_HS host channel-7 interrupt register
-0x400805E8 C FIELD 00w01 XFRC: Transfer completed
-0x400805E8 C FIELD 01w01 CHH: Channel halted
-0x400805E8 C FIELD 02w01 AHBERR: AHB error
-0x400805E8 C FIELD 03w01 STALL: STALL response received interrupt
-0x400805E8 C FIELD 04w01 NAK: NAK response received interrupt
-0x400805E8 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x400805E8 C FIELD 06w01 NYET: Response received interrupt
-0x400805E8 C FIELD 07w01 TXERR: Transaction error
-0x400805E8 C FIELD 08w01 BBERR: Babble error
-0x400805E8 C FIELD 09w01 FRMOR: Frame overrun
-0x400805E8 C FIELD 10w01 DTERR: Data toggle error
-0x400805EC B REGISTER HCINTMSK7 (rw): OTG_HS host channel-7 interrupt mask register
-0x400805EC C FIELD 00w01 XFRCM: Transfer completed mask
-0x400805EC C FIELD 01w01 CHHM: Channel halted mask
-0x400805EC C FIELD 02w01 AHBERR: AHB error
-0x400805EC C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x400805EC C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x400805EC C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x400805EC C FIELD 06w01 NYET: response received interrupt mask
-0x400805EC C FIELD 07w01 TXERRM: Transaction error mask
-0x400805EC C FIELD 08w01 BBERRM: Babble error mask
-0x400805EC C FIELD 09w01 FRMORM: Frame overrun mask
-0x400805EC C FIELD 10w01 DTERRM: Data toggle error mask
-0x400805F0 B REGISTER HCTSIZ7 (rw): OTG_HS host channel-7 transfer size register
-0x400805F0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400805F0 C FIELD 19w10 PKTCNT: Packet count
-0x400805F0 C FIELD 29w02 DPID: Data PID
-0x400805F4 B REGISTER HCDMA7 (rw): OTG_HS host channel-7 DMA address register
-0x400805F4 C FIELD 00w32 DMAADDR: DMA address
-0x40080600 B REGISTER HCCHAR8 (rw): OTG_HS host channel-8 characteristics register
-0x40080600 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080600 C FIELD 11w04 EPNUM: Endpoint number
-0x40080600 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080600 C FIELD 17w01 LSDEV: Low-speed device
-0x40080600 C FIELD 18w02 EPTYP: Endpoint type
-0x40080600 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080600 C FIELD 22w07 DAD: Device address
-0x40080600 C FIELD 29w01 ODDFRM: Odd frame
-0x40080600 C FIELD 30w01 CHDIS: Channel disable
-0x40080600 C FIELD 31w01 CHENA: Channel enable
-0x40080604 B REGISTER HCSPLT8 (rw): OTG_HS host channel-8 split control register
-0x40080604 C FIELD 00w07 PRTADDR: Port address
-0x40080604 C FIELD 07w07 HUBADDR: Hub address
-0x40080604 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080604 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080604 C FIELD 31w01 SPLITEN: Split enable
-0x40080608 B REGISTER HCINT8 (rw): OTG_HS host channel-8 interrupt register
-0x40080608 C FIELD 00w01 XFRC: Transfer completed
-0x40080608 C FIELD 01w01 CHH: Channel halted
-0x40080608 C FIELD 02w01 AHBERR: AHB error
-0x40080608 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080608 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080608 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080608 C FIELD 06w01 NYET: Response received interrupt
-0x40080608 C FIELD 07w01 TXERR: Transaction error
-0x40080608 C FIELD 08w01 BBERR: Babble error
-0x40080608 C FIELD 09w01 FRMOR: Frame overrun
-0x40080608 C FIELD 10w01 DTERR: Data toggle error
-0x4008060C B REGISTER HCINTMSK8 (rw): OTG_HS host channel-8 interrupt mask register
-0x4008060C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008060C C FIELD 01w01 CHHM: Channel halted mask
-0x4008060C C FIELD 02w01 AHBERR: AHB error
-0x4008060C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008060C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008060C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008060C C FIELD 06w01 NYET: response received interrupt mask
-0x4008060C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008060C C FIELD 08w01 BBERRM: Babble error mask
-0x4008060C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008060C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080610 B REGISTER HCTSIZ8 (rw): OTG_HS host channel-8 transfer size register
-0x40080610 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080610 C FIELD 19w10 PKTCNT: Packet count
-0x40080610 C FIELD 29w02 DPID: Data PID
-0x40080614 B REGISTER HCDMA8 (rw): OTG_HS host channel-8 DMA address register
-0x40080614 C FIELD 00w32 DMAADDR: DMA address
-0x40080620 B REGISTER HCCHAR9 (rw): OTG_HS host channel-9 characteristics register
-0x40080620 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080620 C FIELD 11w04 EPNUM: Endpoint number
-0x40080620 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080620 C FIELD 17w01 LSDEV: Low-speed device
-0x40080620 C FIELD 18w02 EPTYP: Endpoint type
-0x40080620 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080620 C FIELD 22w07 DAD: Device address
-0x40080620 C FIELD 29w01 ODDFRM: Odd frame
-0x40080620 C FIELD 30w01 CHDIS: Channel disable
-0x40080620 C FIELD 31w01 CHENA: Channel enable
-0x40080624 B REGISTER HCSPLT9 (rw): OTG_HS host channel-9 split control register
-0x40080624 C FIELD 00w07 PRTADDR: Port address
-0x40080624 C FIELD 07w07 HUBADDR: Hub address
-0x40080624 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080624 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080624 C FIELD 31w01 SPLITEN: Split enable
-0x40080628 B REGISTER HCINT9 (rw): OTG_HS host channel-9 interrupt register
-0x40080628 C FIELD 00w01 XFRC: Transfer completed
-0x40080628 C FIELD 01w01 CHH: Channel halted
-0x40080628 C FIELD 02w01 AHBERR: AHB error
-0x40080628 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080628 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080628 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080628 C FIELD 06w01 NYET: Response received interrupt
-0x40080628 C FIELD 07w01 TXERR: Transaction error
-0x40080628 C FIELD 08w01 BBERR: Babble error
-0x40080628 C FIELD 09w01 FRMOR: Frame overrun
-0x40080628 C FIELD 10w01 DTERR: Data toggle error
-0x4008062C B REGISTER HCINTMSK9 (rw): OTG_HS host channel-9 interrupt mask register
-0x4008062C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008062C C FIELD 01w01 CHHM: Channel halted mask
-0x4008062C C FIELD 02w01 AHBERR: AHB error
-0x4008062C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008062C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008062C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008062C C FIELD 06w01 NYET: response received interrupt mask
-0x4008062C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008062C C FIELD 08w01 BBERRM: Babble error mask
-0x4008062C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008062C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080630 B REGISTER HCTSIZ9 (rw): OTG_HS host channel-9 transfer size register
-0x40080630 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080630 C FIELD 19w10 PKTCNT: Packet count
-0x40080630 C FIELD 29w02 DPID: Data PID
-0x40080634 B REGISTER HCDMA9 (rw): OTG_HS host channel-9 DMA address register
-0x40080634 C FIELD 00w32 DMAADDR: DMA address
-0x40080640 B REGISTER HCCHAR10 (rw): OTG_HS host channel-10 characteristics register
-0x40080640 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080640 C FIELD 11w04 EPNUM: Endpoint number
-0x40080640 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080640 C FIELD 17w01 LSDEV: Low-speed device
-0x40080640 C FIELD 18w02 EPTYP: Endpoint type
-0x40080640 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080640 C FIELD 22w07 DAD: Device address
-0x40080640 C FIELD 29w01 ODDFRM: Odd frame
-0x40080640 C FIELD 30w01 CHDIS: Channel disable
-0x40080640 C FIELD 31w01 CHENA: Channel enable
-0x40080644 B REGISTER HCSPLT10 (rw): OTG_HS host channel-10 split control register
-0x40080644 C FIELD 00w07 PRTADDR: Port address
-0x40080644 C FIELD 07w07 HUBADDR: Hub address
-0x40080644 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080644 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080644 C FIELD 31w01 SPLITEN: Split enable
-0x40080648 B REGISTER HCINT10 (rw): OTG_HS host channel-10 interrupt register
-0x40080648 C FIELD 00w01 XFRC: Transfer completed
-0x40080648 C FIELD 01w01 CHH: Channel halted
-0x40080648 C FIELD 02w01 AHBERR: AHB error
-0x40080648 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080648 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080648 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080648 C FIELD 06w01 NYET: Response received interrupt
-0x40080648 C FIELD 07w01 TXERR: Transaction error
-0x40080648 C FIELD 08w01 BBERR: Babble error
-0x40080648 C FIELD 09w01 FRMOR: Frame overrun
-0x40080648 C FIELD 10w01 DTERR: Data toggle error
-0x4008064C B REGISTER HCINTMSK10 (rw): OTG_HS host channel-10 interrupt mask register
-0x4008064C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008064C C FIELD 01w01 CHHM: Channel halted mask
-0x4008064C C FIELD 02w01 AHBERR: AHB error
-0x4008064C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008064C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008064C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008064C C FIELD 06w01 NYET: response received interrupt mask
-0x4008064C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008064C C FIELD 08w01 BBERRM: Babble error mask
-0x4008064C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008064C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080650 B REGISTER HCTSIZ10 (rw): OTG_HS host channel-10 transfer size register
-0x40080650 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080650 C FIELD 19w10 PKTCNT: Packet count
-0x40080650 C FIELD 29w02 DPID: Data PID
-0x40080654 B REGISTER HCDMA10 (rw): OTG_HS host channel-10 DMA address register
-0x40080654 C FIELD 00w32 DMAADDR: DMA address
-0x40080660 B REGISTER HCCHAR11 (rw): OTG_HS host channel-11 characteristics register
-0x40080660 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080660 C FIELD 11w04 EPNUM: Endpoint number
-0x40080660 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080660 C FIELD 17w01 LSDEV: Low-speed device
-0x40080660 C FIELD 18w02 EPTYP: Endpoint type
-0x40080660 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080660 C FIELD 22w07 DAD: Device address
-0x40080660 C FIELD 29w01 ODDFRM: Odd frame
-0x40080660 C FIELD 30w01 CHDIS: Channel disable
-0x40080660 C FIELD 31w01 CHENA: Channel enable
-0x40080664 B REGISTER HCSPLT11 (rw): OTG_HS host channel-11 split control register
-0x40080664 C FIELD 00w07 PRTADDR: Port address
-0x40080664 C FIELD 07w07 HUBADDR: Hub address
-0x40080664 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080664 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080664 C FIELD 31w01 SPLITEN: Split enable
-0x40080668 B REGISTER HCINT11 (rw): OTG_HS host channel-11 interrupt register
-0x40080668 C FIELD 00w01 XFRC: Transfer completed
-0x40080668 C FIELD 01w01 CHH: Channel halted
-0x40080668 C FIELD 02w01 AHBERR: AHB error
-0x40080668 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080668 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080668 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080668 C FIELD 06w01 NYET: Response received interrupt
-0x40080668 C FIELD 07w01 TXERR: Transaction error
-0x40080668 C FIELD 08w01 BBERR: Babble error
-0x40080668 C FIELD 09w01 FRMOR: Frame overrun
-0x40080668 C FIELD 10w01 DTERR: Data toggle error
-0x4008066C B REGISTER HCINTMSK11 (rw): OTG_HS host channel-11 interrupt mask register
-0x4008066C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008066C C FIELD 01w01 CHHM: Channel halted mask
-0x4008066C C FIELD 02w01 AHBERR: AHB error
-0x4008066C C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x4008066C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008066C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008066C C FIELD 06w01 NYET: response received interrupt mask
-0x4008066C C FIELD 07w01 TXERRM: Transaction error mask
-0x4008066C C FIELD 08w01 BBERRM: Babble error mask
-0x4008066C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008066C C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080670 B REGISTER HCTSIZ11 (rw): OTG_HS host channel-11 transfer size register
-0x40080670 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080670 C FIELD 19w10 PKTCNT: Packet count
-0x40080670 C FIELD 29w02 DPID: Data PID
-0x40080674 B REGISTER HCDMA11 (rw): OTG_HS host channel-11 DMA address register
-0x40080674 C FIELD 00w32 DMAADDR: DMA address
-0x40080678 B REGISTER HCCHAR12 (rw): OTG_HS host channel-12 characteristics register
-0x40080678 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080678 C FIELD 11w04 EPNUM: Endpoint number
-0x40080678 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080678 C FIELD 17w01 LSDEV: Low-speed device
-0x40080678 C FIELD 18w02 EPTYP: Endpoint type
-0x40080678 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080678 C FIELD 22w07 DAD: Device address
-0x40080678 C FIELD 29w01 ODDFRM: Odd frame
-0x40080678 C FIELD 30w01 CHDIS: Channel disable
-0x40080678 C FIELD 31w01 CHENA: Channel enable
-0x4008067C B REGISTER HCSPLT12 (rw): OTG_HS host channel-12 split control register
-0x4008067C C FIELD 00w07 PRTADDR: Port address
-0x4008067C C FIELD 07w07 HUBADDR: Hub address
-0x4008067C C FIELD 14w02 XACTPOS: XACTPOS
-0x4008067C C FIELD 16w01 COMPLSPLT: Do complete split
-0x4008067C C FIELD 31w01 SPLITEN: Split enable
-0x40080680 B REGISTER HCINT12 (rw): OTG_HS host channel-12 interrupt register
-0x40080680 C FIELD 00w01 XFRC: Transfer completed
-0x40080680 C FIELD 01w01 CHH: Channel halted
-0x40080680 C FIELD 02w01 AHBERR: AHB error
-0x40080680 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080680 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080680 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080680 C FIELD 06w01 NYET: Response received interrupt
-0x40080680 C FIELD 07w01 TXERR: Transaction error
-0x40080680 C FIELD 08w01 BBERR: Babble error
-0x40080680 C FIELD 09w01 FRMOR: Frame overrun
-0x40080680 C FIELD 10w01 DTERR: Data toggle error
-0x40080684 B REGISTER HCINTMSK12 (rw): OTG_HS host channel-12 interrupt mask register
-0x40080684 C FIELD 00w01 XFRCM: Transfer completed mask
-0x40080684 C FIELD 01w01 CHHM: Channel halted mask
-0x40080684 C FIELD 02w01 AHBERR: AHB error
-0x40080684 C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x40080684 C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x40080684 C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x40080684 C FIELD 06w01 NYET: Response received interrupt
-0x40080684 C FIELD 07w01 TXERRM: Transaction error
-0x40080684 C FIELD 08w01 BBERRM: Babble error
-0x40080684 C FIELD 09w01 FRMORM: Frame overrun mask
-0x40080684 C FIELD 10w01 DTERRM: Data toggle error mask
-0x40080688 B REGISTER HCTSIZ12 (rw): OTG_HS host channel-12 transfer size register
-0x40080688 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080688 C FIELD 19w10 PKTCNT: Packet count
-0x40080688 C FIELD 29w02 DPID: Data PID
-0x4008068C B REGISTER HCDMA12 (rw): OTG_HS host channel-12 DMA address register
-0x4008068C C FIELD 00w32 DMAADDR: DMA address
-0x40080690 B REGISTER HCCHAR13 (rw): OTG_HS host channel-13 characteristics register
-0x40080690 C FIELD 00w11 MPSIZ: Maximum packet size
-0x40080690 C FIELD 11w04 EPNUM: Endpoint number
-0x40080690 C FIELD 15w01 EPDIR: Endpoint direction
-0x40080690 C FIELD 17w01 LSDEV: Low-speed device
-0x40080690 C FIELD 18w02 EPTYP: Endpoint type
-0x40080690 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x40080690 C FIELD 22w07 DAD: Device address
-0x40080690 C FIELD 29w01 ODDFRM: Odd frame
-0x40080690 C FIELD 30w01 CHDIS: Channel disable
-0x40080690 C FIELD 31w01 CHENA: Channel enable
-0x40080694 B REGISTER HCSPLT13 (rw): OTG_HS host channel-13 split control register
-0x40080694 C FIELD 00w07 PRTADDR: Port address
-0x40080694 C FIELD 07w07 HUBADDR: Hub address
-0x40080694 C FIELD 14w02 XACTPOS: XACTPOS
-0x40080694 C FIELD 16w01 COMPLSPLT: Do complete split
-0x40080694 C FIELD 31w01 SPLITEN: Split enable
-0x40080698 B REGISTER HCINT13 (rw): OTG_HS host channel-13 interrupt register
-0x40080698 C FIELD 00w01 XFRC: Transfer completed
-0x40080698 C FIELD 01w01 CHH: Channel halted
-0x40080698 C FIELD 02w01 AHBERR: AHB error
-0x40080698 C FIELD 03w01 STALL: STALL response received interrupt
-0x40080698 C FIELD 04w01 NAK: NAK response received interrupt
-0x40080698 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x40080698 C FIELD 06w01 NYET: Response received interrupt
-0x40080698 C FIELD 07w01 TXERR: Transaction error
-0x40080698 C FIELD 08w01 BBERR: Babble error
-0x40080698 C FIELD 09w01 FRMOR: Frame overrun
-0x40080698 C FIELD 10w01 DTERR: Data toggle error
-0x4008069C B REGISTER HCINTMSK13 (rw): OTG_HS host channel-13 interrupt mask register
-0x4008069C C FIELD 00w01 XFRCM: Transfer completed mask
-0x4008069C C FIELD 01w01 CHHM: Channel halted mask
-0x4008069C C FIELD 02w01 AHBERR: AHB error
-0x4008069C C FIELD 03w01 STALLM: STALLM response received interrupt mask
-0x4008069C C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x4008069C C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x4008069C C FIELD 06w01 NYET: Response received interrupt
-0x4008069C C FIELD 07w01 TXERRM: Transaction error
-0x4008069C C FIELD 08w01 BBERRM: Babble error
-0x4008069C C FIELD 09w01 FRMORM: Frame overrun mask
-0x4008069C C FIELD 10w01 DTERRM: Data toggle error mask
-0x400806A0 B REGISTER HCTSIZ13 (rw): OTG_HS host channel-13 transfer size register
-0x400806A0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400806A0 C FIELD 19w10 PKTCNT: Packet count
-0x400806A0 C FIELD 29w02 DPID: Data PID
-0x400806A4 B REGISTER HCDMA13 (rw): OTG_HS host channel-13 DMA address register
-0x400806A4 C FIELD 00w32 DMAADDR: DMA address
-0x400806A8 B REGISTER HCCHAR14 (rw): OTG_HS host channel-14 characteristics register
-0x400806A8 C FIELD 00w11 MPSIZ: Maximum packet size
-0x400806A8 C FIELD 11w04 EPNUM: Endpoint number
-0x400806A8 C FIELD 15w01 EPDIR: Endpoint direction
-0x400806A8 C FIELD 17w01 LSDEV: Low-speed device
-0x400806A8 C FIELD 18w02 EPTYP: Endpoint type
-0x400806A8 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x400806A8 C FIELD 22w07 DAD: Device address
-0x400806A8 C FIELD 29w01 ODDFRM: Odd frame
-0x400806A8 C FIELD 30w01 CHDIS: Channel disable
-0x400806A8 C FIELD 31w01 CHENA: Channel enable
-0x400806AC B REGISTER HCSPLT14 (rw): OTG_HS host channel-14 split control register
-0x400806AC C FIELD 00w07 PRTADDR: Port address
-0x400806AC C FIELD 07w07 HUBADDR: Hub address
-0x400806AC C FIELD 14w02 XACTPOS: XACTPOS
-0x400806AC C FIELD 16w01 COMPLSPLT: Do complete split
-0x400806AC C FIELD 31w01 SPLITEN: Split enable
-0x400806B0 B REGISTER HCINT14 (rw): OTG_HS host channel-14 interrupt register
-0x400806B0 C FIELD 00w01 XFRC: Transfer completed
-0x400806B0 C FIELD 01w01 CHH: Channel halted
-0x400806B0 C FIELD 02w01 AHBERR: AHB error
-0x400806B0 C FIELD 03w01 STALL: STALL response received interrupt
-0x400806B0 C FIELD 04w01 NAK: NAK response received interrupt
-0x400806B0 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x400806B0 C FIELD 06w01 NYET: Response received interrupt
-0x400806B0 C FIELD 07w01 TXERR: Transaction error
-0x400806B0 C FIELD 08w01 BBERR: Babble error
-0x400806B0 C FIELD 09w01 FRMOR: Frame overrun
-0x400806B0 C FIELD 10w01 DTERR: Data toggle error
-0x400806B4 B REGISTER HCINTMSK14 (rw): OTG_HS host channel-14 interrupt mask register
-0x400806B4 C FIELD 00w01 XFRCM: Transfer completed mask
-0x400806B4 C FIELD 01w01 CHHM: Channel halted mask
-0x400806B4 C FIELD 02w01 AHBERR: AHB error
-0x400806B4 C FIELD 03w01 STALLM: STALL response received interrupt mask
-0x400806B4 C FIELD 04w01 NAKM: NAKM response received interrupt mask
-0x400806B4 C FIELD 05w01 ACKM: ACKM response received/transmitted interrupt mask
-0x400806B4 C FIELD 06w01 NYET: Response received interrupt
-0x400806B4 C FIELD 07w01 TXERRM: Transaction error
-0x400806B4 C FIELD 08w01 BBERRM: Babble error
-0x400806B4 C FIELD 09w01 FRMORM: Frame overrun mask
-0x400806B4 C FIELD 10w01 DTERRM: Data toggle error mask
-0x400806B8 B REGISTER HCTSIZ14 (rw): OTG_HS host channel-14 transfer size register
-0x400806B8 C FIELD 00w19 XFRSIZ: Transfer size
-0x400806B8 C FIELD 19w10 PKTCNT: Packet count
-0x400806B8 C FIELD 29w02 DPID: Data PID
-0x400806BC B REGISTER HCDMA14 (rw): OTG_HS host channel-14 DMA address register
-0x400806BC C FIELD 00w32 DMAADDR: DMA address
-0x400806C0 B REGISTER HCCHAR15 (rw): OTG_HS host channel-15 characteristics register
-0x400806C0 C FIELD 00w11 MPSIZ: Maximum packet size
-0x400806C0 C FIELD 11w04 EPNUM: Endpoint number
-0x400806C0 C FIELD 15w01 EPDIR: Endpoint direction
-0x400806C0 C FIELD 17w01 LSDEV: Low-speed device
-0x400806C0 C FIELD 18w02 EPTYP: Endpoint type
-0x400806C0 C FIELD 20w02 MC: Multi Count (MC) / Error Count (EC)
-0x400806C0 C FIELD 22w07 DAD: Device address
-0x400806C0 C FIELD 29w01 ODDFRM: Odd frame
-0x400806C0 C FIELD 30w01 CHDIS: Channel disable
-0x400806C0 C FIELD 31w01 CHENA: Channel enable
-0x400806C4 B REGISTER HCSPLT15 (rw): OTG_HS host channel-15 split control register
-0x400806C4 C FIELD 00w07 PRTADDR: Port address
-0x400806C4 C FIELD 07w07 HUBADDR: Hub address
-0x400806C4 C FIELD 14w02 XACTPOS: XACTPOS
-0x400806C4 C FIELD 16w01 COMPLSPLT: Do complete split
-0x400806C4 C FIELD 31w01 SPLITEN: Split enable
-0x400806C8 B REGISTER HCINT15 (rw): OTG_HS host channel-15 interrupt register
-0x400806C8 C FIELD 00w01 XFRC: Transfer completed
-0x400806C8 C FIELD 01w01 CHH: Channel halted
-0x400806C8 C FIELD 02w01 AHBERR: AHB error
-0x400806C8 C FIELD 03w01 STALL: STALL response received interrupt
-0x400806C8 C FIELD 04w01 NAK: NAK response received interrupt
-0x400806C8 C FIELD 05w01 ACK: ACK response received/transmitted interrupt
-0x400806C8 C FIELD 06w01 NYET: Response received interrupt
-0x400806C8 C FIELD 07w01 TXERR: Transaction error
-0x400806C8 C FIELD 08w01 BBERR: Babble error
-0x400806C8 C FIELD 09w01 FRMOR: Frame overrun
-0x400806C8 C FIELD 10w01 DTERR: Data toggle error
-0x400806CC B REGISTER HCINTMSK15 (rw): OTG_HS host channel-15 interrupt mask register
-0x400806CC C FIELD 00w01 XFRCM: Transfer completed mask
-0x400806CC C FIELD 01w01 CHHM: Channel halted mask
-0x400806CC C FIELD 02w01 AHBERR: AHB error
-0x400806CC C FIELD 03w01 STALL: STALL response received interrupt mask
-0x400806CC C FIELD 04w01 NAKM: NAK response received interrupt mask
-0x400806CC C FIELD 05w01 ACKM: ACK response received/transmitted interrupt mask
-0x400806CC C FIELD 06w01 NYET: Response received interrupt
-0x400806CC C FIELD 07w01 TXERRM: Transaction error
-0x400806CC C FIELD 08w01 BBERRM: Babble error
-0x400806CC C FIELD 09w01 FRMORM: Frame overrun mask
-0x400806CC C FIELD 10w01 DTERRM: Data toggle error mask
-0x400806D0 B REGISTER HCTSIZ15 (rw): OTG_HS host channel-15 transfer size register
-0x400806D0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400806D0 C FIELD 19w10 PKTCNT: Packet count
-0x400806D0 C FIELD 29w02 DPID: Data PID
-0x400806D4 B REGISTER HCDMA15 (rw): OTG_HS host channel-15 DMA address register
-0x400806D4 C FIELD 00w32 DMAADDR: DMA address
-0x40080800 A PERIPHERAL OTG2_HS_DEVICE
-0x40080800 B REGISTER DCFG (rw): OTG_HS device configuration register
-0x40080800 C FIELD 00w02 DSPD: Device speed
-0x40080800 C FIELD 02w01 NZLSOHSK: Nonzero-length status OUT handshake
-0x40080800 C FIELD 04w07 DAD: Device address
-0x40080800 C FIELD 11w02 PFIVL: Periodic (micro)frame interval
-0x40080800 C FIELD 24w02 PERSCHIVL: Periodic scheduling interval
-0x40080804 B REGISTER DCTL: OTG_HS device control register
-0x40080804 C FIELD 00w01 RWUSIG (rw): Remote wakeup signaling
-0x40080804 C FIELD 01w01 SDIS (rw): Soft disconnect
-0x40080804 C FIELD 02w01 GINSTS (ro): Global IN NAK status
-0x40080804 C FIELD 03w01 GONSTS (ro): Global OUT NAK status
-0x40080804 C FIELD 04w03 TCTL (rw): Test control
-0x40080804 C FIELD 07w01 SGINAK (wo): Set global IN NAK
-0x40080804 C FIELD 08w01 CGINAK (wo): Clear global IN NAK
-0x40080804 C FIELD 09w01 SGONAK (wo): Set global OUT NAK
-0x40080804 C FIELD 10w01 CGONAK (wo): Clear global OUT NAK
-0x40080804 C FIELD 11w01 POPRGDNE (rw): Power-on programming done
-0x40080808 B REGISTER DSTS (ro): OTG_HS device status register
-0x40080808 C FIELD 00w01 SUSPSTS: Suspend status
-0x40080808 C FIELD 01w02 ENUMSPD: Enumerated speed
-0x40080808 C FIELD 03w01 EERR: Erratic error
-0x40080808 C FIELD 08w14 FNSOF: Frame number of the received SOF
-0x40080810 B REGISTER DIEPMSK (rw): OTG_HS device IN endpoint common interrupt mask register
-0x40080810 C FIELD 00w01 XFRCM: Transfer completed interrupt mask
-0x40080810 C FIELD 01w01 EPDM: Endpoint disabled interrupt mask
-0x40080810 C FIELD 03w01 TOM: Timeout condition mask (nonisochronous endpoints)
-0x40080810 C FIELD 04w01 ITTXFEMSK: IN token received when TxFIFO empty mask
-0x40080810 C FIELD 05w01 INEPNMM: IN token received with EP mismatch mask
-0x40080810 C FIELD 06w01 INEPNEM: IN endpoint NAK effective mask
-0x40080810 C FIELD 08w01 TXFURM: FIFO underrun mask
-0x40080810 C FIELD 09w01 BIM: BNA interrupt mask
-0x40080814 B REGISTER DOEPMSK (rw): OTG_HS device OUT endpoint common interrupt mask register
-0x40080814 C FIELD 00w01 XFRCM: Transfer completed interrupt mask
-0x40080814 C FIELD 01w01 EPDM: Endpoint disabled interrupt mask
-0x40080814 C FIELD 03w01 STUPM: SETUP phase done mask
-0x40080814 C FIELD 04w01 OTEPDM: OUT token received when endpoint disabled mask
-0x40080814 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received mask
-0x40080814 C FIELD 08w01 OPEM: OUT packet error mask
-0x40080814 C FIELD 09w01 BOIM: BNA interrupt mask
-0x40080818 B REGISTER DAINT (ro): OTG_HS device all endpoints interrupt register
-0x40080818 C FIELD 00w16 IEPINT: IN endpoint interrupt bits
-0x40080818 C FIELD 16w16 OEPINT: OUT endpoint interrupt bits
-0x4008081C B REGISTER DAINTMSK (rw): OTG_HS all endpoints interrupt mask register
-0x4008081C C FIELD 00w16 IEPM: IN EP interrupt mask bits
-0x4008081C C FIELD 16w16 OEPM: OUT EP interrupt mask bits
-0x40080828 B REGISTER DVBUSDIS (rw): OTG_HS device VBUS discharge time register
-0x40080828 C FIELD 00w16 VBUSDT: Device VBUS discharge time
-0x4008082C B REGISTER DVBUSPULSE (rw): OTG_HS device VBUS pulsing time register
-0x4008082C C FIELD 00w12 DVBUSP: Device VBUS pulsing time
-0x40080830 B REGISTER DTHRCTL (rw): OTG_HS Device threshold control register
-0x40080830 C FIELD 00w01 NONISOTHREN: Nonisochronous IN endpoints threshold enable
-0x40080830 C FIELD 01w01 ISOTHREN: ISO IN endpoint threshold enable
-0x40080830 C FIELD 02w09 TXTHRLEN: Transmit threshold length
-0x40080830 C FIELD 16w01 RXTHREN: Receive threshold enable
-0x40080830 C FIELD 17w09 RXTHRLEN: Receive threshold length
-0x40080830 C FIELD 27w01 ARPEN: Arbiter parking enable
-0x40080834 B REGISTER DIEPEMPMSK (rw): OTG_HS device IN endpoint FIFO empty interrupt mask register
-0x40080834 C FIELD 00w16 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits
-0x40080838 B REGISTER DEACHINT (rw): OTG_HS device each endpoint interrupt register
-0x40080838 C FIELD 01w01 IEP1INT: IN endpoint 1interrupt bit
-0x40080838 C FIELD 17w01 OEP1INT: OUT endpoint 1 interrupt bit
-0x4008083C B REGISTER DEACHINTMSK (rw): OTG_HS device each endpoint interrupt register mask
-0x4008083C C FIELD 01w01 IEP1INTM: IN Endpoint 1 interrupt mask bit
-0x4008083C C FIELD 17w01 OEP1INTM: OUT Endpoint 1 interrupt mask bit
-0x40080900 B REGISTER DIEPCTL0: OTG device endpoint-0 control register
-0x40080900 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080900 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080900 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x40080900 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080900 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080900 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080900 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x40080900 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080900 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080900 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x40080900 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080900 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080900 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080908 B REGISTER DIEPINT0: OTG device endpoint-0 interrupt register
-0x40080908 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x40080908 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x40080908 C FIELD 03w01 TOC (rw): Timeout condition
-0x40080908 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x40080908 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x40080908 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x40080908 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x40080908 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x40080908 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x40080908 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x40080908 C FIELD 13w01 NAK (rw): NAK interrupt
-0x40080910 B REGISTER DIEPTSIZ0 (rw): OTG_HS device IN endpoint 0 transfer size register
-0x40080910 C FIELD 00w07 XFRSIZ: Transfer size
-0x40080910 C FIELD 19w02 PKTCNT: Packet count
-0x40080914 B REGISTER DIEPDMA1 (rw): OTG_HS device endpoint-1 DMA address register
-0x40080914 C FIELD 00w32 DMAADDR: DMA address
-0x40080918 B REGISTER DTXFSTS0 (ro): OTG_HS device IN endpoint transmit FIFO status register
-0x40080918 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x40080920 B REGISTER DIEPCTL1: OTG device endpoint-1 control register
-0x40080920 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080920 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080920 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x40080920 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080920 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080920 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080920 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x40080920 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080920 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080920 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x40080920 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080920 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080920 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080928 B REGISTER DIEPINT1: OTG device endpoint-1 interrupt register
-0x40080928 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x40080928 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x40080928 C FIELD 03w01 TOC (rw): Timeout condition
-0x40080928 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x40080928 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x40080928 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x40080928 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x40080928 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x40080928 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x40080928 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x40080928 C FIELD 13w01 NAK (rw): NAK interrupt
-0x40080930 B REGISTER DIEPTSIZ1 (rw): OTG_HS device endpoint transfer size register
-0x40080930 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080930 C FIELD 19w10 PKTCNT: Packet count
-0x40080930 C FIELD 29w02 MCNT: Multi count
-0x40080934 B REGISTER DIEPDMA2 (rw): OTG_HS device endpoint-2 DMA address register
-0x40080934 C FIELD 00w32 DMAADDR: DMA address
-0x40080938 B REGISTER DTXFSTS1 (ro): OTG_HS device IN endpoint transmit FIFO status register
-0x40080938 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x40080940 B REGISTER DIEPCTL2: OTG device endpoint-2 control register
-0x40080940 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080940 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080940 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x40080940 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080940 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080940 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080940 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x40080940 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080940 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080940 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x40080940 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080940 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080940 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080948 B REGISTER DIEPINT2: OTG device endpoint-2 interrupt register
-0x40080948 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x40080948 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x40080948 C FIELD 03w01 TOC (rw): Timeout condition
-0x40080948 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x40080948 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x40080948 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x40080948 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x40080948 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x40080948 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x40080948 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x40080948 C FIELD 13w01 NAK (rw): NAK interrupt
-0x40080950 B REGISTER DIEPTSIZ2 (rw): OTG_HS device endpoint transfer size register
-0x40080950 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080950 C FIELD 19w10 PKTCNT: Packet count
-0x40080950 C FIELD 29w02 MCNT: Multi count
-0x40080954 B REGISTER DIEPDMA3 (rw): OTG_HS device endpoint-3 DMA address register
-0x40080954 C FIELD 00w32 DMAADDR: DMA address
-0x40080958 B REGISTER DTXFSTS2 (ro): OTG_HS device IN endpoint transmit FIFO status register
-0x40080958 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x40080960 B REGISTER DIEPCTL3: OTG device endpoint-3 control register
-0x40080960 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080960 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080960 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x40080960 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080960 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080960 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080960 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x40080960 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080960 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080960 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x40080960 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080960 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080960 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080968 B REGISTER DIEPINT3: OTG device endpoint-3 interrupt register
-0x40080968 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x40080968 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x40080968 C FIELD 03w01 TOC (rw): Timeout condition
-0x40080968 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x40080968 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x40080968 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x40080968 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x40080968 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x40080968 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x40080968 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x40080968 C FIELD 13w01 NAK (rw): NAK interrupt
-0x40080970 B REGISTER DIEPTSIZ3 (rw): OTG_HS device endpoint transfer size register
-0x40080970 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080970 C FIELD 19w10 PKTCNT: Packet count
-0x40080970 C FIELD 29w02 MCNT: Multi count
-0x40080974 B REGISTER DIEPDMA4 (rw): OTG_HS device endpoint-4 DMA address register
-0x40080974 C FIELD 00w32 DMAADDR: DMA address
-0x40080978 B REGISTER DTXFSTS3 (ro): OTG_HS device IN endpoint transmit FIFO status register
-0x40080978 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x40080980 B REGISTER DIEPCTL4: OTG device endpoint-4 control register
-0x40080980 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080980 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080980 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x40080980 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080980 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080980 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080980 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x40080980 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080980 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080980 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x40080980 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080980 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080980 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080988 B REGISTER DIEPINT4: OTG device endpoint-4 interrupt register
-0x40080988 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x40080988 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x40080988 C FIELD 03w01 TOC (rw): Timeout condition
-0x40080988 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x40080988 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x40080988 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x40080988 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x40080988 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x40080988 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x40080988 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x40080988 C FIELD 13w01 NAK (rw): NAK interrupt
-0x40080990 B REGISTER DIEPTSIZ4 (rw): OTG_HS device endpoint transfer size register
-0x40080990 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080990 C FIELD 19w10 PKTCNT: Packet count
-0x40080990 C FIELD 29w02 MCNT: Multi count
-0x40080994 B REGISTER DIEPDMA5 (rw): OTG_HS device endpoint-5 DMA address register
-0x40080994 C FIELD 00w32 DMAADDR: DMA address
-0x40080998 B REGISTER DTXFSTS4 (ro): OTG_HS device IN endpoint transmit FIFO status register
-0x40080998 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x400809A0 B REGISTER DIEPCTL5: OTG device endpoint-5 control register
-0x400809A0 B REGISTER DIEPTSIZ6 (rw): OTG_HS device endpoint transfer size register
-0x400809A0 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x400809A0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400809A0 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x400809A0 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x400809A0 C FIELD 17w01 NAKSTS (ro): NAK status
-0x400809A0 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x400809A0 C FIELD 19w10 PKTCNT: Packet count
-0x400809A0 C FIELD 21w01 Stall (rw): STALL handshake
-0x400809A0 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x400809A0 C FIELD 26w01 CNAK (wo): Clear NAK
-0x400809A0 C FIELD 27w01 SNAK (wo): Set NAK
-0x400809A0 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x400809A0 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x400809A0 C FIELD 29w02 MCNT: Multi count
-0x400809A0 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x400809A0 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x400809A4 B REGISTER DTXFSTS6 (rw): OTG_HS device IN endpoint transmit FIFO status register
-0x400809A4 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x400809A8 B REGISTER DIEPINT5: OTG device endpoint-5 interrupt register
-0x400809A8 B REGISTER DIEPTSIZ7 (rw): OTG_HS device endpoint transfer size register
-0x400809A8 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x400809A8 C FIELD 00w19 XFRSIZ: Transfer size
-0x400809A8 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x400809A8 C FIELD 03w01 TOC (rw): Timeout condition
-0x400809A8 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x400809A8 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x400809A8 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x400809A8 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x400809A8 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x400809A8 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x400809A8 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x400809A8 C FIELD 13w01 NAK (rw): NAK interrupt
-0x400809A8 C FIELD 19w10 PKTCNT: Packet count
-0x400809A8 C FIELD 29w02 MCNT: Multi count
-0x400809AC B REGISTER DTXFSTS7 (rw): OTG_HS device IN endpoint transmit FIFO status register
-0x400809AC C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x400809B0 B REGISTER DIEPTSIZ5 (rw): OTG_HS device endpoint transfer size register
-0x400809B0 C FIELD 00w19 XFRSIZ: Transfer size
-0x400809B0 C FIELD 19w10 PKTCNT: Packet count
-0x400809B0 C FIELD 29w02 MCNT: Multi count
-0x400809B8 B REGISTER DTXFSTS5 (ro): OTG_HS device IN endpoint transmit FIFO status register
-0x400809B8 C FIELD 00w16 INEPTFSAV: IN endpoint TxFIFO space avail
-0x400809C0 B REGISTER DIEPCTL6: OTG device endpoint-6 control register
-0x400809C0 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x400809C0 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x400809C0 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x400809C0 C FIELD 17w01 NAKSTS (ro): NAK status
-0x400809C0 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x400809C0 C FIELD 21w01 Stall (rw): STALL handshake
-0x400809C0 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x400809C0 C FIELD 26w01 CNAK (wo): Clear NAK
-0x400809C0 C FIELD 27w01 SNAK (wo): Set NAK
-0x400809C0 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x400809C0 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x400809C0 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x400809C0 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x400809C8 B REGISTER DIEPINT6: OTG device endpoint-6 interrupt register
-0x400809C8 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x400809C8 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x400809C8 C FIELD 03w01 TOC (rw): Timeout condition
-0x400809C8 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x400809C8 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x400809C8 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x400809C8 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x400809C8 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x400809C8 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x400809C8 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x400809C8 C FIELD 13w01 NAK (rw): NAK interrupt
-0x400809E0 B REGISTER DIEPCTL7: OTG device endpoint-7 control register
-0x400809E0 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x400809E0 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x400809E0 C FIELD 16w01 EONUM_DPID (ro): Even/odd frame
-0x400809E0 C FIELD 17w01 NAKSTS (ro): NAK status
-0x400809E0 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x400809E0 C FIELD 21w01 Stall (rw): STALL handshake
-0x400809E0 C FIELD 22w04 TXFNUM (rw): TxFIFO number
-0x400809E0 C FIELD 26w01 CNAK (wo): Clear NAK
-0x400809E0 C FIELD 27w01 SNAK (wo): Set NAK
-0x400809E0 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID
-0x400809E0 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x400809E0 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x400809E0 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x400809E8 B REGISTER DIEPINT7: OTG device endpoint-7 interrupt register
-0x400809E8 C FIELD 00w01 XFRC (rw): Transfer completed interrupt
-0x400809E8 C FIELD 01w01 EPDISD (rw): Endpoint disabled interrupt
-0x400809E8 C FIELD 03w01 TOC (rw): Timeout condition
-0x400809E8 C FIELD 04w01 ITTXFE (rw): IN token received when TxFIFO is empty
-0x400809E8 C FIELD 06w01 INEPNE (rw): IN endpoint NAK effective
-0x400809E8 C FIELD 07w01 TXFE (ro): Transmit FIFO empty
-0x400809E8 C FIELD 08w01 TXFIFOUDRN (rw): Transmit Fifo Underrun
-0x400809E8 C FIELD 09w01 BNA (rw): Buffer not available interrupt
-0x400809E8 C FIELD 11w01 PKTDRPSTS (rw): Packet dropped status
-0x400809E8 C FIELD 12w01 BERR (rw): Babble error interrupt
-0x400809E8 C FIELD 13w01 NAK (rw): NAK interrupt
-0x40080B00 B REGISTER DOEPCTL0: OTG_HS device control OUT endpoint 0 control register
-0x40080B00 C FIELD 00w02 MPSIZ (ro): Maximum packet size
-0x40080B00 C FIELD 15w01 USBAEP (ro): USB active endpoint
-0x40080B00 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080B00 C FIELD 18w02 EPTYP (ro): Endpoint type
-0x40080B00 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080B00 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080B00 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080B00 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080B00 C FIELD 30w01 EPDIS (ro): Endpoint disable
-0x40080B00 C FIELD 31w01 EPENA (wo): Endpoint enable
-0x40080B08 B REGISTER DOEPINT0 (rw): OTG_HS device endpoint-0 interrupt register
-0x40080B08 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080B08 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080B08 C FIELD 03w01 STUP: SETUP phase done
-0x40080B08 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080B08 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080B08 C FIELD 14w01 NYET: NYET interrupt
-0x40080B10 B REGISTER DOEPTSIZ0 (rw): OTG_HS device endpoint-0 transfer size register
-0x40080B10 C FIELD 00w07 XFRSIZ: Transfer size
-0x40080B10 C FIELD 19w01 PKTCNT: Packet count
-0x40080B10 C FIELD 29w02 STUPCNT: SETUP packet count
-0x40080B20 B REGISTER DOEPCTL1: OTG device endpoint-1 control register
-0x40080B20 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080B20 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080B20 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080B20 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080B20 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080B20 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080B20 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080B20 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080B20 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080B20 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080B20 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080B20 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080B20 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080B28 B REGISTER DOEPINT1 (rw): OTG_HS device endpoint-1 interrupt register
-0x40080B28 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080B28 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080B28 C FIELD 03w01 STUP: SETUP phase done
-0x40080B28 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080B28 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080B28 C FIELD 14w01 NYET: NYET interrupt
-0x40080B30 B REGISTER DOEPTSIZ1 (rw): OTG_HS device endpoint-1 transfer size register
-0x40080B30 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080B30 C FIELD 19w10 PKTCNT: Packet count
-0x40080B30 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080B40 B REGISTER DOEPCTL2: OTG device endpoint-2 control register
-0x40080B40 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080B40 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080B40 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080B40 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080B40 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080B40 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080B40 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080B40 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080B40 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080B40 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080B40 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080B40 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080B40 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080B48 B REGISTER DOEPINT2 (rw): OTG_HS device endpoint-2 interrupt register
-0x40080B48 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080B48 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080B48 C FIELD 03w01 STUP: SETUP phase done
-0x40080B48 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080B48 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080B48 C FIELD 14w01 NYET: NYET interrupt
-0x40080B50 B REGISTER DOEPTSIZ2 (rw): OTG_HS device endpoint-2 transfer size register
-0x40080B50 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080B50 C FIELD 19w10 PKTCNT: Packet count
-0x40080B50 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080B60 B REGISTER DOEPCTL3: OTG device endpoint-3 control register
-0x40080B60 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080B60 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080B60 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080B60 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080B60 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080B60 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080B60 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080B60 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080B60 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080B60 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080B60 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080B60 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080B60 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080B68 B REGISTER DOEPINT3 (rw): OTG_HS device endpoint-3 interrupt register
-0x40080B68 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080B68 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080B68 C FIELD 03w01 STUP: SETUP phase done
-0x40080B68 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080B68 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080B68 C FIELD 14w01 NYET: NYET interrupt
-0x40080B70 B REGISTER DOEPTSIZ3 (rw): OTG_HS device endpoint-3 transfer size register
-0x40080B70 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080B70 C FIELD 19w10 PKTCNT: Packet count
-0x40080B70 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080B80 B REGISTER DOEPCTL4: OTG device endpoint-4 control register
-0x40080B80 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080B80 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080B80 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080B80 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080B80 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080B80 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080B80 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080B80 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080B80 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080B80 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080B80 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080B80 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080B80 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080B88 B REGISTER DOEPINT4 (rw): OTG_HS device endpoint-4 interrupt register
-0x40080B88 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080B88 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080B88 C FIELD 03w01 STUP: SETUP phase done
-0x40080B88 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080B88 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080B88 C FIELD 14w01 NYET: NYET interrupt
-0x40080B90 B REGISTER DOEPTSIZ4 (rw): OTG_HS device endpoint-4 transfer size register
-0x40080B90 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080B90 C FIELD 19w10 PKTCNT: Packet count
-0x40080B90 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080BA0 B REGISTER DOEPCTL5: OTG device endpoint-5 control register
-0x40080BA0 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080BA0 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080BA0 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080BA0 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080BA0 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080BA0 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080BA0 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080BA0 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080BA0 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080BA0 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080BA0 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080BA0 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080BA0 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080BA8 B REGISTER DOEPINT5 (rw): OTG_HS device endpoint-5 interrupt register
-0x40080BA8 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080BA8 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080BA8 C FIELD 03w01 STUP: SETUP phase done
-0x40080BA8 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080BA8 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080BA8 C FIELD 14w01 NYET: NYET interrupt
-0x40080BB0 B REGISTER DOEPTSIZ5 (rw): OTG_HS device endpoint-5 transfer size register
-0x40080BB0 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080BB0 C FIELD 19w10 PKTCNT: Packet count
-0x40080BB0 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080BC0 B REGISTER DOEPCTL6: OTG device endpoint-6 control register
-0x40080BC0 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080BC0 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080BC0 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080BC0 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080BC0 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080BC0 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080BC0 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080BC0 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080BC0 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080BC0 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080BC0 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080BC0 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080BC0 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080BC8 B REGISTER DOEPINT6 (rw): OTG_HS device endpoint-6 interrupt register
-0x40080BC8 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080BC8 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080BC8 C FIELD 03w01 STUP: SETUP phase done
-0x40080BC8 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080BC8 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080BC8 C FIELD 14w01 NYET: NYET interrupt
-0x40080BD0 B REGISTER DOEPTSIZ6 (rw): OTG_HS device endpoint-6 transfer size register
-0x40080BD0 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080BD0 C FIELD 19w10 PKTCNT: Packet count
-0x40080BD0 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080BE0 B REGISTER DOEPCTL7: OTG device endpoint-7 control register
-0x40080BE0 C FIELD 00w11 MPSIZ (rw): Maximum packet size
-0x40080BE0 C FIELD 15w01 USBAEP (rw): USB active endpoint
-0x40080BE0 C FIELD 16w01 EONUM_DPID (ro): Even odd frame/Endpoint data PID
-0x40080BE0 C FIELD 17w01 NAKSTS (ro): NAK status
-0x40080BE0 C FIELD 18w02 EPTYP (rw): Endpoint type
-0x40080BE0 C FIELD 20w01 SNPM (rw): Snoop mode
-0x40080BE0 C FIELD 21w01 Stall (rw): STALL handshake
-0x40080BE0 C FIELD 26w01 CNAK (wo): Clear NAK
-0x40080BE0 C FIELD 27w01 SNAK (wo): Set NAK
-0x40080BE0 C FIELD 28w01 SD0PID_SEVNFRM (wo): Set DATA0 PID/Set even frame
-0x40080BE0 C FIELD 29w01 SODDFRM (wo): Set odd frame
-0x40080BE0 C FIELD 30w01 EPDIS (rw): Endpoint disable
-0x40080BE0 C FIELD 31w01 EPENA (rw): Endpoint enable
-0x40080BE8 B REGISTER DOEPINT7 (rw): OTG_HS device endpoint-7 interrupt register
-0x40080BE8 C FIELD 00w01 XFRC: Transfer completed interrupt
-0x40080BE8 C FIELD 01w01 EPDISD: Endpoint disabled interrupt
-0x40080BE8 C FIELD 03w01 STUP: SETUP phase done
-0x40080BE8 C FIELD 04w01 OTEPDIS: OUT token received when endpoint disabled
-0x40080BE8 C FIELD 06w01 B2BSTUP: Back-to-back SETUP packets received
-0x40080BE8 C FIELD 14w01 NYET: NYET interrupt
-0x40080BF0 B REGISTER DOEPTSIZ7 (rw): OTG_HS device endpoint-7 transfer size register
-0x40080BF0 C FIELD 00w19 XFRSIZ: Transfer size
-0x40080BF0 C FIELD 19w10 PKTCNT: Packet count
-0x40080BF0 C FIELD 29w02 RXDPID_STUPCNT: Received data PID/SETUP packet count
-0x40080E00 A PERIPHERAL OTG2_HS_PWRCLK
-0x40080E00 B REGISTER PCGCR (rw): Power and clock gating control register
-0x40080E00 C FIELD 00w01 STPPCLK: Stop PHY clock
-0x40080E00 C FIELD 01w01 GATEHCLK: Gate HCLK
-0x40080E00 C FIELD 04w01 PHYSUSP: PHY suspended
0x48020000 A PERIPHERAL DCMI
0x48020000 B REGISTER CR (rw): control register 1
0x48020000 C FIELD 00w01 CAPTURE: Capture enable
@@ -13611,6 +12308,400 @@
0x48020028 C FIELD 08w08 Byte1: Data byte 1
0x48020028 C FIELD 16w08 Byte2: Data byte 2
0x48020028 C FIELD 24w08 Byte3: Data byte 3
+0x48020800 A PERIPHERAL HSEM
+0x48020800 B REGISTER R0 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020800 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020800 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020800 C FIELD 31w01 LOCK: Lock indication
+0x48020804 B REGISTER R1 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020804 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020804 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020804 C FIELD 31w01 LOCK: Lock indication
+0x48020808 B REGISTER R2 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020808 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020808 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020808 C FIELD 31w01 LOCK: Lock indication
+0x4802080C B REGISTER R3 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802080C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802080C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802080C C FIELD 31w01 LOCK: Lock indication
+0x48020810 B REGISTER R4 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020810 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020810 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020810 C FIELD 31w01 LOCK: Lock indication
+0x48020814 B REGISTER R5 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020814 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020814 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020814 C FIELD 31w01 LOCK: Lock indication
+0x48020818 B REGISTER R6 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020818 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020818 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020818 C FIELD 31w01 LOCK: Lock indication
+0x4802081C B REGISTER R7 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802081C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802081C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802081C C FIELD 31w01 LOCK: Lock indication
+0x48020820 B REGISTER R8 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020820 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020820 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020820 C FIELD 31w01 LOCK: Lock indication
+0x48020824 B REGISTER R9 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020824 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020824 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020824 C FIELD 31w01 LOCK: Lock indication
+0x48020828 B REGISTER R10 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020828 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020828 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020828 C FIELD 31w01 LOCK: Lock indication
+0x4802082C B REGISTER R11 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802082C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802082C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802082C C FIELD 31w01 LOCK: Lock indication
+0x48020830 B REGISTER R12 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020830 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020830 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020830 C FIELD 31w01 LOCK: Lock indication
+0x48020834 B REGISTER R13 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020834 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020834 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020834 C FIELD 31w01 LOCK: Lock indication
+0x48020838 B REGISTER R14 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020838 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020838 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020838 C FIELD 31w01 LOCK: Lock indication
+0x4802083C B REGISTER R15 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802083C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802083C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802083C C FIELD 31w01 LOCK: Lock indication
+0x48020840 B REGISTER R16 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020840 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020840 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020840 C FIELD 31w01 LOCK: Lock indication
+0x48020844 B REGISTER R17 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020844 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020844 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020844 C FIELD 31w01 LOCK: Lock indication
+0x48020848 B REGISTER R18 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020848 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020848 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020848 C FIELD 31w01 LOCK: Lock indication
+0x4802084C B REGISTER R19 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802084C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802084C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802084C C FIELD 31w01 LOCK: Lock indication
+0x48020850 B REGISTER R20 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020850 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020850 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020850 C FIELD 31w01 LOCK: Lock indication
+0x48020854 B REGISTER R21 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020854 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020854 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020854 C FIELD 31w01 LOCK: Lock indication
+0x48020858 B REGISTER R22 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020858 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020858 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020858 C FIELD 31w01 LOCK: Lock indication
+0x4802085C B REGISTER R23 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802085C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802085C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802085C C FIELD 31w01 LOCK: Lock indication
+0x48020860 B REGISTER R24 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020860 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020860 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020860 C FIELD 31w01 LOCK: Lock indication
+0x48020864 B REGISTER R25 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020864 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020864 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020864 C FIELD 31w01 LOCK: Lock indication
+0x48020868 B REGISTER R26 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020868 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020868 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020868 C FIELD 31w01 LOCK: Lock indication
+0x4802086C B REGISTER R27 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802086C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802086C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802086C C FIELD 31w01 LOCK: Lock indication
+0x48020870 B REGISTER R28 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020870 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020870 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020870 C FIELD 31w01 LOCK: Lock indication
+0x48020874 B REGISTER R29 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020874 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020874 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020874 C FIELD 31w01 LOCK: Lock indication
+0x48020878 B REGISTER R30 (rw): HSEM register HSEM_R0 HSEM_R31
+0x48020878 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020878 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020878 C FIELD 31w01 LOCK: Lock indication
+0x4802087C B REGISTER R31 (rw): HSEM register HSEM_R0 HSEM_R31
+0x4802087C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802087C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802087C C FIELD 31w01 LOCK: Lock indication
+0x48020880 B REGISTER RLR0 (ro): HSEM Read lock register
+0x48020880 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020880 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020880 C FIELD 31w01 LOCK: Lock indication
+0x48020884 B REGISTER RLR1 (ro): HSEM Read lock register
+0x48020884 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020884 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020884 C FIELD 31w01 LOCK: Lock indication
+0x48020888 B REGISTER RLR2 (ro): HSEM Read lock register
+0x48020888 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020888 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020888 C FIELD 31w01 LOCK: Lock indication
+0x4802088C B REGISTER RLR3 (ro): HSEM Read lock register
+0x4802088C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802088C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802088C C FIELD 31w01 LOCK: Lock indication
+0x48020890 B REGISTER RLR4 (ro): HSEM Read lock register
+0x48020890 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020890 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020890 C FIELD 31w01 LOCK: Lock indication
+0x48020894 B REGISTER RLR5 (ro): HSEM Read lock register
+0x48020894 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020894 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020894 C FIELD 31w01 LOCK: Lock indication
+0x48020898 B REGISTER RLR6 (ro): HSEM Read lock register
+0x48020898 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x48020898 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x48020898 C FIELD 31w01 LOCK: Lock indication
+0x4802089C B REGISTER RLR7 (ro): HSEM Read lock register
+0x4802089C C FIELD 00w08 PROCID: Semaphore ProcessID
+0x4802089C C FIELD 08w08 MASTERID: Semaphore MasterID
+0x4802089C C FIELD 31w01 LOCK: Lock indication
+0x480208A0 B REGISTER RLR8 (ro): HSEM Read lock register
+0x480208A0 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208A0 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208A0 C FIELD 31w01 LOCK: Lock indication
+0x480208A4 B REGISTER RLR9 (ro): HSEM Read lock register
+0x480208A4 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208A4 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208A4 C FIELD 31w01 LOCK: Lock indication
+0x480208A8 B REGISTER RLR10 (ro): HSEM Read lock register
+0x480208A8 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208A8 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208A8 C FIELD 31w01 LOCK: Lock indication
+0x480208AC B REGISTER RLR11 (ro): HSEM Read lock register
+0x480208AC C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208AC C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208AC C FIELD 31w01 LOCK: Lock indication
+0x480208B0 B REGISTER RLR12 (ro): HSEM Read lock register
+0x480208B0 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208B0 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208B0 C FIELD 31w01 LOCK: Lock indication
+0x480208B4 B REGISTER RLR13 (ro): HSEM Read lock register
+0x480208B4 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208B4 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208B4 C FIELD 31w01 LOCK: Lock indication
+0x480208B8 B REGISTER RLR14 (ro): HSEM Read lock register
+0x480208B8 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208B8 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208B8 C FIELD 31w01 LOCK: Lock indication
+0x480208BC B REGISTER RLR15 (ro): HSEM Read lock register
+0x480208BC C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208BC C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208BC C FIELD 31w01 LOCK: Lock indication
+0x480208C0 B REGISTER RLR16 (ro): HSEM Read lock register
+0x480208C0 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208C0 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208C0 C FIELD 31w01 LOCK: Lock indication
+0x480208C4 B REGISTER RLR17 (ro): HSEM Read lock register
+0x480208C4 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208C4 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208C4 C FIELD 31w01 LOCK: Lock indication
+0x480208C8 B REGISTER RLR18 (ro): HSEM Read lock register
+0x480208C8 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208C8 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208C8 C FIELD 31w01 LOCK: Lock indication
+0x480208CC B REGISTER RLR19 (ro): HSEM Read lock register
+0x480208CC C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208CC C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208CC C FIELD 31w01 LOCK: Lock indication
+0x480208D0 B REGISTER RLR20 (ro): HSEM Read lock register
+0x480208D0 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208D0 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208D0 C FIELD 31w01 LOCK: Lock indication
+0x480208D4 B REGISTER RLR21 (ro): HSEM Read lock register
+0x480208D4 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208D4 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208D4 C FIELD 31w01 LOCK: Lock indication
+0x480208D8 B REGISTER RLR22 (ro): HSEM Read lock register
+0x480208D8 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208D8 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208D8 C FIELD 31w01 LOCK: Lock indication
+0x480208DC B REGISTER RLR23 (ro): HSEM Read lock register
+0x480208DC C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208DC C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208DC C FIELD 31w01 LOCK: Lock indication
+0x480208E0 B REGISTER RLR24 (ro): HSEM Read lock register
+0x480208E0 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208E0 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208E0 C FIELD 31w01 LOCK: Lock indication
+0x480208E4 B REGISTER RLR25 (ro): HSEM Read lock register
+0x480208E4 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208E4 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208E4 C FIELD 31w01 LOCK: Lock indication
+0x480208E8 B REGISTER RLR26 (ro): HSEM Read lock register
+0x480208E8 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208E8 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208E8 C FIELD 31w01 LOCK: Lock indication
+0x480208EC B REGISTER RLR27 (ro): HSEM Read lock register
+0x480208EC C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208EC C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208EC C FIELD 31w01 LOCK: Lock indication
+0x480208F0 B REGISTER RLR28 (ro): HSEM Read lock register
+0x480208F0 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208F0 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208F0 C FIELD 31w01 LOCK: Lock indication
+0x480208F4 B REGISTER RLR29 (ro): HSEM Read lock register
+0x480208F4 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208F4 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208F4 C FIELD 31w01 LOCK: Lock indication
+0x480208F8 B REGISTER RLR30 (ro): HSEM Read lock register
+0x480208F8 C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208F8 C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208F8 C FIELD 31w01 LOCK: Lock indication
+0x480208FC B REGISTER RLR31 (ro): HSEM Read lock register
+0x480208FC C FIELD 00w08 PROCID: Semaphore ProcessID
+0x480208FC C FIELD 08w08 MASTERID: Semaphore MasterID
+0x480208FC C FIELD 31w01 LOCK: Lock indication
+0x48020900 B REGISTER IER (rw): HSEM Interrupt enable register
+0x48020900 C FIELD 00w01 ISEM0: Interrupt semaphore n enable bit
+0x48020900 C FIELD 01w01 ISEM1: Interrupt semaphore n enable bit
+0x48020900 C FIELD 02w01 ISEM2: Interrupt semaphore n enable bit
+0x48020900 C FIELD 03w01 ISEM3: Interrupt semaphore n enable bit
+0x48020900 C FIELD 04w01 ISEM4: Interrupt semaphore n enable bit
+0x48020900 C FIELD 05w01 ISEM5: Interrupt semaphore n enable bit
+0x48020900 C FIELD 06w01 ISEM6: Interrupt semaphore n enable bit
+0x48020900 C FIELD 07w01 ISEM7: Interrupt semaphore n enable bit
+0x48020900 C FIELD 08w01 ISEM8: Interrupt semaphore n enable bit
+0x48020900 C FIELD 09w01 ISEM9: Interrupt semaphore n enable bit
+0x48020900 C FIELD 10w01 ISEM10: Interrupt semaphore n enable bit
+0x48020900 C FIELD 11w01 ISEM11: Interrupt semaphore n enable bit
+0x48020900 C FIELD 12w01 ISEM12: Interrupt semaphore n enable bit
+0x48020900 C FIELD 13w01 ISEM13: Interrupt semaphore n enable bit
+0x48020900 C FIELD 14w01 ISEM14: Interrupt semaphore n enable bit
+0x48020900 C FIELD 15w01 ISEM15: Interrupt semaphore n enable bit
+0x48020900 C FIELD 16w01 ISEM16: Interrupt semaphore n enable bit
+0x48020900 C FIELD 17w01 ISEM17: Interrupt semaphore n enable bit
+0x48020900 C FIELD 18w01 ISEM18: Interrupt semaphore n enable bit
+0x48020900 C FIELD 19w01 ISEM19: Interrupt semaphore n enable bit
+0x48020900 C FIELD 20w01 ISEM20: Interrupt semaphore n enable bit
+0x48020900 C FIELD 21w01 ISEM21: Interrupt semaphore n enable bit
+0x48020900 C FIELD 22w01 ISEM22: Interrupt semaphore n enable bit
+0x48020900 C FIELD 23w01 ISEM23: Interrupt semaphore n enable bit
+0x48020900 C FIELD 24w01 ISEM24: Interrupt semaphore n enable bit
+0x48020900 C FIELD 25w01 ISEM25: Interrupt semaphore n enable bit
+0x48020900 C FIELD 26w01 ISEM26: Interrupt semaphore n enable bit
+0x48020900 C FIELD 27w01 ISEM27: Interrupt semaphore n enable bit
+0x48020900 C FIELD 28w01 ISEM28: Interrupt semaphore n enable bit
+0x48020900 C FIELD 29w01 ISEM29: Interrupt semaphore n enable bit
+0x48020900 C FIELD 30w01 ISEM30: Interrupt semaphore n enable bit
+0x48020900 C FIELD 31w01 ISEM31: Interrupt(N) semaphore n enable bit.
+0x48020904 B REGISTER ICR (ro): HSEM Interrupt clear register
+0x48020904 C FIELD 00w01 ISEM0: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 01w01 ISEM1: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 02w01 ISEM2: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 03w01 ISEM3: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 04w01 ISEM4: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 05w01 ISEM5: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 06w01 ISEM6: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 07w01 ISEM7: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 08w01 ISEM8: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 09w01 ISEM9: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 10w01 ISEM10: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 11w01 ISEM11: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 12w01 ISEM12: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 13w01 ISEM13: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 14w01 ISEM14: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 15w01 ISEM15: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 16w01 ISEM16: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 17w01 ISEM17: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 18w01 ISEM18: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 19w01 ISEM19: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 20w01 ISEM20: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 21w01 ISEM21: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 22w01 ISEM22: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 23w01 ISEM23: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 24w01 ISEM24: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 25w01 ISEM25: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 26w01 ISEM26: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 27w01 ISEM27: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 28w01 ISEM28: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 29w01 ISEM29: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 30w01 ISEM30: Interrupt(N) semaphore n clear bit
+0x48020904 C FIELD 31w01 ISEM31: Interrupt(N) semaphore n clear bit
+0x48020908 B REGISTER ISR (ro): HSEM Interrupt status register
+0x48020908 C FIELD 00w01 ISEM0: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 01w01 ISEM1: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 02w01 ISEM2: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 03w01 ISEM3: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 04w01 ISEM4: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 05w01 ISEM5: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 06w01 ISEM6: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 07w01 ISEM7: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 08w01 ISEM8: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 09w01 ISEM9: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 10w01 ISEM10: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 11w01 ISEM11: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 12w01 ISEM12: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 13w01 ISEM13: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 14w01 ISEM14: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 15w01 ISEM15: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 16w01 ISEM16: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 17w01 ISEM17: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 18w01 ISEM18: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 19w01 ISEM19: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 20w01 ISEM20: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 21w01 ISEM21: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 22w01 ISEM22: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 23w01 ISEM23: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 24w01 ISEM24: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 25w01 ISEM25: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 26w01 ISEM26: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 27w01 ISEM27: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 28w01 ISEM28: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 29w01 ISEM29: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 30w01 ISEM30: Interrupt(N) semaphore n status bit before enable (mask)
+0x48020908 C FIELD 31w01 ISEM31: Interrupt(N) semaphore n status bit before enable (mask)
+0x4802090C B REGISTER MISR (ro): HSEM Masked interrupt status register
+0x4802090C C FIELD 00w01 ISEM0: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 01w01 ISEM1: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 02w01 ISEM2: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 03w01 ISEM3: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 04w01 ISEM4: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 05w01 ISEM5: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 06w01 ISEM6: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 07w01 ISEM7: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 08w01 ISEM8: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 09w01 ISEM9: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 10w01 ISEM10: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 11w01 ISEM11: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 12w01 ISEM12: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 13w01 ISEM13: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 14w01 ISEM14: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 15w01 ISEM15: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 16w01 ISEM16: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 17w01 ISEM17: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 18w01 ISEM18: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 19w01 ISEM19: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 20w01 ISEM20: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 21w01 ISEM21: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 22w01 ISEM22: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 23w01 ISEM23: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 24w01 ISEM24: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 25w01 ISEM25: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 26w01 ISEM26: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 27w01 ISEM27: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 28w01 ISEM28: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 29w01 ISEM29: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 30w01 ISEM30: masked interrupt(N) semaphore n status bit after enable (mask)
+0x4802090C C FIELD 31w01 ISEM31: masked interrupt(N) semaphore n status bit after enable (mask)
+0x48020940 B REGISTER CR (rw): HSEM Clear register
+0x48020940 C FIELD 08w08 MASTERID: MasterID of semaphores to be cleared
+0x48020940 C FIELD 16w16 KEY: Semaphore clear Key
+0x48020944 B REGISTER KEYR (rw): HSEM Interrupt clear register
+0x48020944 C FIELD 16w16 KEY: Semaphore Clear Key
0x48021000 A PERIPHERAL CRYP
0x48021000 B REGISTER CR: control register
0x48021000 C FIELD 02w01 ALGODIR (rw): Algorithm direction
@@ -14097,6 +13188,7 @@
0x48022C04 C FIELD 29w01 CTCIF8: Channel x transfer complete clear This bit is set and cleared by software.
0x48022C04 C FIELD 30w01 CHTIF8: Channel x half transfer clear This bit is set and cleared by software.
0x48022C04 C FIELD 31w01 CTEIF8: Channel x transfer error clear This bit is set and cleared by software.
+0x48022C08 B CLUSTER CH0: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C08 B REGISTER CR0 (rw): DMA channel x configuration register
0x48022C08 C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C08 C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14120,6 +13212,7 @@
0x48022C14 C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C18 B REGISTER M1AR0 (rw): This register must not be written when the channel is enabled
0x48022C18 C FIELD 00w32 MA: Memory address
+0x48022C1C B CLUSTER CH1: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C1C B REGISTER CR1 (rw): DMA channel x configuration register
0x48022C1C C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C1C C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14143,6 +13236,7 @@
0x48022C28 C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C2C B REGISTER M1AR1 (rw): This register must not be written when the channel is enabled
0x48022C2C C FIELD 00w32 MA: Memory address
+0x48022C30 B CLUSTER CH2: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C30 B REGISTER CR2 (rw): DMA channel x configuration register
0x48022C30 C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C30 C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14166,6 +13260,7 @@
0x48022C3C C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C40 B REGISTER M1AR2 (rw): This register must not be written when the channel is enabled
0x48022C40 C FIELD 00w32 MA: Memory address
+0x48022C44 B CLUSTER CH3: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C44 B REGISTER CR3 (rw): DMA channel x configuration register
0x48022C44 C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C44 C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14189,6 +13284,7 @@
0x48022C50 C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C54 B REGISTER M1AR3 (rw): This register must not be written when the channel is enabled
0x48022C54 C FIELD 00w32 MA: Memory address
+0x48022C58 B CLUSTER CH4: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C58 B REGISTER CR4 (rw): DMA channel x configuration register
0x48022C58 C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C58 C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14212,6 +13308,7 @@
0x48022C64 C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C68 B REGISTER M1AR4 (rw): This register must not be written when the channel is enabled
0x48022C68 C FIELD 00w32 MA: Memory address
+0x48022C6C B CLUSTER CH5: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C6C B REGISTER CR5 (rw): DMA channel x configuration register
0x48022C6C C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C6C C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14235,6 +13332,7 @@
0x48022C78 C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C7C B REGISTER M1AR5 (rw): This register must not be written when the channel is enabled
0x48022C7C C FIELD 00w32 MA: Memory address
+0x48022C80 B CLUSTER CH6: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C80 B REGISTER CR6 (rw): DMA channel x configuration register
0x48022C80 C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C80 C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -14258,6 +13356,7 @@
0x48022C8C C FIELD 00w32 MA: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
0x48022C90 B REGISTER M1AR6 (rw): This register must not be written when the channel is enabled
0x48022C90 C FIELD 00w32 MA: Memory address
+0x48022C94 B CLUSTER CH7: Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?
0x48022C94 B REGISTER CR7 (rw): DMA channel x configuration register
0x48022C94 C FIELD 00w01 EN: Channel enable This bit is set and cleared by software.
0x48022C94 C FIELD 01w01 TCIE: Transfer complete interrupt enable This bit is set and cleared by software.
@@ -18601,6 +17700,807 @@
0x5800480C C FIELD 02w01 WVU: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic window = 1
0x58004810 B REGISTER WINR (rw): Window register
0x58004810 C FIELD 00w12 WIN: Watchdog counter window value These bits are write access protected see Section23.3.6. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset.
+0x58006C00 A PERIPHERAL DFSDM2
+0x58006C00 B REGISTER DFSDM_CH0CFGR1: DFSDM channel 0 configuration register
+0x58006C00 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C00 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C00 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006C00 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006C00 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006C00 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C00 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C00 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C00 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006C00 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C00 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C04 B REGISTER DFSDM_CH0CFGR2: DFSDM channel 0 configuration register
+0x58006C04 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006C04 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006C08 B REGISTER DFSDM_CH0AWSCDR: DFSDM channel 0 analog watchdog and short-circuit detector register
+0x58006C08 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006C08 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006C08 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006C08 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C0C B REGISTER DFSDM_CH0WDATR: DFSDM channel 0 watchdog filter data register
+0x58006C0C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006C10 B REGISTER DFSDM_CH0DATINR: DFSDM channel 0 data input register
+0x58006C10 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006C10 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006C14 B REGISTER DFSDM_CH0DLYR: None
+0x58006C14 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006C20 B REGISTER DFSDM_CH1CFGR1: DFSDM channel 1 configuration register
+0x58006C20 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C20 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C20 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006C20 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006C20 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006C20 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C20 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C20 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C20 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006C20 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C20 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C24 B REGISTER DFSDM_CH1CFGR2: DFSDM channel 1 configuration register
+0x58006C24 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006C24 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006C28 B REGISTER DFSDM_CH1AWSCDR: DFSDM channel 1 analog watchdog and short-circuit detector register
+0x58006C28 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006C28 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006C28 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006C28 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C2C B REGISTER DFSDM_CH1WDATR: DFSDM channel 1 watchdog filter data register
+0x58006C2C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006C30 B REGISTER DFSDM_CH1DATINR: DFSDM channel 1 data input register
+0x58006C30 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006C30 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006C34 B REGISTER DFSDM_CH1DLYR: None
+0x58006C34 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006C40 B REGISTER DFSDM_CH2CFGR1: DFSDM channel 2 configuration register
+0x58006C40 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C40 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C40 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006C40 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006C40 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006C40 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C40 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C40 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C40 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006C40 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C40 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C44 B REGISTER DFSDM_CH2CFGR2: DFSDM channel 2 configuration register
+0x58006C44 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006C44 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006C48 B REGISTER DFSDM_CH2AWSCDR: DFSDM channel 2 analog watchdog and short-circuit detector register
+0x58006C48 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006C48 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006C48 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006C48 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C4C B REGISTER DFSDM_CH2WDATR: DFSDM channel 2 watchdog filter data register
+0x58006C4C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006C50 B REGISTER DFSDM_CH2DATINR: DFSDM channel 2 data input register
+0x58006C50 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006C50 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006C54 B REGISTER DFSDM_CH2DLYR: None
+0x58006C54 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006C60 B REGISTER DFSDM_CH3CFGR1: DFSDM channel 3 configuration register
+0x58006C60 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C60 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C60 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006C60 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006C60 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006C60 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C60 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C60 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C60 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006C60 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C60 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C64 B REGISTER DFSDM_CH3CFGR2: DFSDM channel 3 configuration register
+0x58006C64 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006C64 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006C68 B REGISTER DFSDM_CH3AWSCDR: DFSDM channel 3 analog watchdog and short-circuit detector register
+0x58006C68 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006C68 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006C68 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006C68 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C6C B REGISTER DFSDM_CH3WDATR: DFSDM channel 3 watchdog filter data register
+0x58006C6C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006C70 B REGISTER DFSDM_CH3DATINR: DFSDM channel 3 data input register
+0x58006C70 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006C70 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006C74 B REGISTER DFSDM_CH3DLYR: None
+0x58006C74 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006C80 B REGISTER DFSDM_CH4CFGR1: DFSDM channel 4 configuration register
+0x58006C80 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C80 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C80 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006C80 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006C80 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006C80 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C80 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C80 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C80 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006C80 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C80 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006C84 B REGISTER DFSDM_CH4CFGR2: DFSDM channel 4 configuration register
+0x58006C84 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006C84 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006C88 B REGISTER DFSDM_CH4AWSCDR: DFSDM channel 4 analog watchdog and short-circuit detector register
+0x58006C88 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006C88 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006C88 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006C88 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006C8C B REGISTER DFSDM_CH4WDATR: DFSDM channel 4 watchdog filter data register
+0x58006C8C C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006C90 B REGISTER DFSDM_CH4DATINR: DFSDM channel 4 data input register
+0x58006C90 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006C90 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006C94 B REGISTER DFSDM_CH4DLYR: None
+0x58006C94 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006CA0 B REGISTER DFSDM_CH5CFGR1: DFSDM channel 5 configuration register
+0x58006CA0 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CA0 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CA0 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006CA0 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006CA0 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006CA0 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CA0 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CA0 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CA0 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006CA0 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006CA0 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006CA4 B REGISTER DFSDM_CH5CFGR2: DFSDM channel 5 configuration register
+0x58006CA4 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006CA4 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006CA8 B REGISTER DFSDM_CH5AWSCDR: DFSDM channel 5 analog watchdog and short-circuit detector register
+0x58006CA8 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006CA8 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006CA8 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006CA8 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CAC B REGISTER DFSDM_CH5WDATR: DFSDM channel 5 watchdog filter data register
+0x58006CAC C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006CB0 B REGISTER DFSDM_CH5DATINR: DFSDM channel 5 data input register
+0x58006CB0 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006CB0 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006CB4 B REGISTER DFSDM_CH5DLYR: None
+0x58006CB4 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006CC0 B REGISTER DFSDM_CH6CFGR1: DFSDM channel 6 configuration register
+0x58006CC0 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CC0 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CC0 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006CC0 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006CC0 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006CC0 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CC0 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CC0 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CC0 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006CC0 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006CC0 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006CC4 B REGISTER DFSDM_CH6CFGR2: DFSDM channel 6 configuration register
+0x58006CC4 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006CC4 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006CC8 B REGISTER DFSDM_CH6AWSCDR: DFSDM channel 6 analog watchdog and short-circuit detector register
+0x58006CC8 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006CC8 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006CC8 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006CC8 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CCC B REGISTER DFSDM_CH6WDATR: DFSDM channel 6 watchdog filter data register
+0x58006CCC C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006CD0 B REGISTER DFSDM_CH6DATINR: DFSDM channel 6 data input register
+0x58006CD0 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006CD0 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006CD4 B REGISTER DFSDM_CH6DLYR: None
+0x58006CD4 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006CE0 B REGISTER DFSDM_CH7CFGR1: DFSDM channel 7 configuration register
+0x58006CE0 C FIELD 00w02 SITP (rw): Serial interface type for channel y This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CE0 C FIELD 02w02 SPICKSEL (rw): SPI clock select for channel y 2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge). 3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CE0 C FIELD 05w01 SCDEN (rw): Short-circuit detector enable on channel y
+0x58006CE0 C FIELD 06w01 CKABEN (rw): Clock absence detector enable on channel y
+0x58006CE0 C FIELD 07w01 CHEN (rw): Channel y enable If channel y is enabled, then serial data receiving is started according to the given channel setting.
+0x58006CE0 C FIELD 08w01 CHINSEL (rw): Channel inputs selection This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CE0 C FIELD 12w02 DATMPX (rw): Input data multiplexer for channel y 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CE0 C FIELD 14w02 DATPACK (rw): Data packing mode in DFSDM_CHyDATINR register. first sample in INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y) To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next sample). 2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples: first sample INDAT0[15:0] (assigned to channel y) second sample INDAT1[15:0] (assigned to channel y+1) To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel y and second sample must be read by another digital filter from channel y+1. Dual mode is available only on even channel numbers (y = 0, 2, 4, 6), for odd channel numbers (y = 1, 3, 5, 7) DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even channel. 3: Reserved This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CE0 C FIELD 16w08 CKOUTDIV (rw): Output serial clock divider  256 (Divider = CKOUTDIV+1). CKOUTDIV also defines the threshold for a clock absence detection. This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is performed one DFSDM clock cycle after DFSDMEN=0). Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
+0x58006CE0 C FIELD 30w01 CKOUTSRC (rw): Output serial clock source selection This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register). Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006CE0 C FIELD 31w01 DFSDMEN (rw): Global enable for DFSDM interface If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1). Data cleared by setting DFSDMEN=0: all registers DFSDM_FLTxISR are set to reset state (x = 0..7) all registers DFSDM_FLTxAWSR are set to reset state (x = 0..7) Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
+0x58006CE4 B REGISTER DFSDM_CH7CFGR2: DFSDM channel 7 configuration register
+0x58006CE4 C FIELD 03w05 DTRBS (rw): Data right bit-shift for channel y will be performed to have final results. Bit-shift is performed before offset correction. The data shift is rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid 24-bit signed format of result data). This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
+0x58006CE4 C FIELD 08w24 OFFSET (rw): 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software.
+0x58006CE8 B REGISTER DFSDM_CH7AWSCDR: DFSDM channel 7 analog watchdog and short-circuit detector register
+0x58006CE8 C FIELD 00w08 SCDT (rw): short-circuit detector threshold for channel y These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given channel.
+0x58006CE8 C FIELD 12w04 BKSCD (rw): Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
+0x58006CE8 C FIELD 16w05 AWFOSR (rw): Analog watchdog filter oversampling ratio (decimation rate) on channel y also the decimation ratio of the analog data rate. This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register). Note: If AWFOSR = 0 then the filter has no effect (filter bypass). 0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
+0x58006CE8 C FIELD 22w02 AWFORD (rw): Analog watchdog Sinc filter order on channel y 2: Sinc2 filter type 3: Sinc3 filter type Sincx filter type transfer function: FastSinc filter type transfer function: This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
+0x58006CEC B REGISTER DFSDM_CH7WDATR: DFSDM channel 7 watchdog filter data register
+0x58006CEC C FIELD 00w16 WDATA (ro): Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
+0x58006CF0 B REGISTER DFSDM_CH7DATINR: DFSDM channel 7 data input register
+0x58006CF0 C FIELD 00w16 INDAT0 (rw): Input data for channel y Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) Channel y data sample is stored into INDAT0[15:0]. If DATPACK[1:0]=1 (interleaved mode) First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: Channel y data sample is stored into INDAT0[15:0]. For odd y channels: INDAT0[15:0] is write protected. See for more details. INDAT0[15:0] is in the16-bit signed format.
+0x58006CF0 C FIELD 16w16 INDAT1 (rw): Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample). If DATPACK[1:0]=1 (interleaved mode) Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y data samples. If DATPACK[1:0]=2 (dual mode). For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of channel (y+1). For odd y channels: INDAT1[15:0] is write protected. See for more details. INDAT0[15:1] is in the16-bit signed format.
+0x58006CF4 B REGISTER DFSDM_CH7DLYR: None
+0x58006CF4 C FIELD 00w06 PLSSKP (rw): Pulses to skip for input data skipping function immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped. Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero. 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
+0x58006D00 B REGISTER DFSDM_FLT0CR1: None
+0x58006D00 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x58006D00 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x58006D00 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D00 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x58006D00 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D00 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x58006D00 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D00 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x58006D00 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x58006D00 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D00 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D00 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x58006D00 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x58006D00 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x58006D04 B REGISTER DFSDM_FLT0CR2: None
+0x58006D04 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x58006D04 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x58006D04 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x58006D04 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x58006D04 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x58006D04 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006D04 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006D04 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x58006D04 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x58006D08 B REGISTER DFSDM_FLT0ISR: None
+0x58006D08 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x58006D08 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x58006D08 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x58006D08 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x58006D08 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x58006D08 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x58006D08 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x58006D08 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006D08 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006D0C B REGISTER DFSDM_FLT0ICR: None
+0x58006D0C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x58006D0C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x58006D0C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006D0C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006D10 B REGISTER DFSDM_FLT0JCHGR: None
+0x58006D10 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x58006D14 B REGISTER DFSDM_FLT0FCR: None
+0x58006D14 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x58006D14 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x58006D14 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D18 B REGISTER DFSDM_FLT0JDATAR: None
+0x58006D18 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x58006D18 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x58006D1C B REGISTER DFSDM_FLT0RDATAR: None
+0x58006D1C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x58006D1C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x58006D1C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x58006D20 B REGISTER DFSDM_FLT0AWHTR: None
+0x58006D20 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x58006D20 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x58006D24 B REGISTER DFSDM_FLT0AWLTR: None
+0x58006D24 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x58006D24 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x58006D28 B REGISTER DFSDM_FLT0AWSR: None
+0x58006D28 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006D28 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006D2C B REGISTER DFSDM_FLT0AWCFR: None
+0x58006D2C C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006D2C C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006D30 B REGISTER DFSDM_FLT0EXMAX: None
+0x58006D30 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x58006D30 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x58006D34 B REGISTER DFSDM_FLT0EXMIN: None
+0x58006D34 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x58006D34 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x58006D38 B REGISTER DFSDM_FLT0CNVTIMR: None
+0x58006D38 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x58006D80 B REGISTER DFSDM_FLT1CR1: None
+0x58006D80 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x58006D80 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x58006D80 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D80 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x58006D80 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D80 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x58006D80 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D80 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x58006D80 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x58006D80 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D80 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D80 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x58006D80 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x58006D80 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x58006D84 B REGISTER DFSDM_FLT1CR2: None
+0x58006D84 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x58006D84 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x58006D84 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x58006D84 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x58006D84 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x58006D84 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006D84 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006D84 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x58006D84 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x58006D88 B REGISTER DFSDM_FLT1ISR: None
+0x58006D88 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x58006D88 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x58006D88 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x58006D88 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x58006D88 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x58006D88 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x58006D88 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x58006D88 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006D88 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006D8C B REGISTER DFSDM_FLT1ICR: None
+0x58006D8C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x58006D8C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x58006D8C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006D8C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006D90 B REGISTER DFSDM_FLT1JCHGR: None
+0x58006D90 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x58006D94 B REGISTER DFSDM_FLT1FCR: None
+0x58006D94 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x58006D94 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x58006D94 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x58006D98 B REGISTER DFSDM_FLT1JDATAR: None
+0x58006D98 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x58006D98 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x58006D9C B REGISTER DFSDM_FLT1RDATAR: None
+0x58006D9C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x58006D9C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x58006D9C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x58006DA0 B REGISTER DFSDM_FLT1AWHTR: None
+0x58006DA0 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x58006DA0 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x58006DA4 B REGISTER DFSDM_FLT1AWLTR: None
+0x58006DA4 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x58006DA4 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x58006DA8 B REGISTER DFSDM_FLT1AWSR: None
+0x58006DA8 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006DA8 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006DAC B REGISTER DFSDM_FLT1AWCFR: None
+0x58006DAC C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006DAC C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006DB0 B REGISTER DFSDM_FLT1EXMAX: None
+0x58006DB0 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x58006DB0 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x58006DB4 B REGISTER DFSDM_FLT1EXMIN: None
+0x58006DB4 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x58006DB4 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x58006DB8 B REGISTER DFSDM_FLT1CNVTIMR: None
+0x58006DB8 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x58006E00 B REGISTER DFSDM_FLT2CR1: None
+0x58006E00 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x58006E00 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x58006E00 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E00 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x58006E00 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E00 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x58006E00 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E00 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x58006E00 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x58006E00 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E00 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E00 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x58006E00 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x58006E00 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x58006E04 B REGISTER DFSDM_FLT2CR2: None
+0x58006E04 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x58006E04 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x58006E04 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x58006E04 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x58006E04 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x58006E04 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006E04 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006E04 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x58006E04 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x58006E08 B REGISTER DFSDM_FLT2ISR: None
+0x58006E08 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x58006E08 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x58006E08 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x58006E08 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x58006E08 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x58006E08 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x58006E08 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x58006E08 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006E08 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006E0C B REGISTER DFSDM_FLT2ICR: None
+0x58006E0C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x58006E0C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x58006E0C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006E0C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006E10 B REGISTER DFSDM_FLT2JCHGR: None
+0x58006E10 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x58006E14 B REGISTER DFSDM_FLT2FCR: None
+0x58006E14 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x58006E14 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x58006E14 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E18 B REGISTER DFSDM_FLT2JDATAR: None
+0x58006E18 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x58006E18 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x58006E1C B REGISTER DFSDM_FLT2RDATAR: None
+0x58006E1C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x58006E1C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x58006E1C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x58006E20 B REGISTER DFSDM_FLT2AWHTR: None
+0x58006E20 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x58006E20 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x58006E24 B REGISTER DFSDM_FLT2AWLTR: None
+0x58006E24 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x58006E24 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x58006E28 B REGISTER DFSDM_FLT2AWSR: None
+0x58006E28 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006E28 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006E2C B REGISTER DFSDM_FLT2AWCFR: None
+0x58006E2C C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006E2C C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006E30 B REGISTER DFSDM_FLT2EXMAX: None
+0x58006E30 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x58006E30 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x58006E34 B REGISTER DFSDM_FLT2EXMIN: None
+0x58006E34 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x58006E34 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x58006E38 B REGISTER DFSDM_FLT2CNVTIMR: None
+0x58006E38 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also this interruption time.
+0x58006E80 B REGISTER DFSDM_FLT3CR1: None
+0x58006E80 C FIELD 00w01 DFEN (rw): DFSDM_FLTx enable Data which are cleared by setting DFEN=0: register DFSDM_FLTxISR is set to the reset state register DFSDM_FLTxAWSR is set to the reset state
+0x58006E80 C FIELD 01w01 JSWSTART (rw): Start a conversion of the injected group of channels This bit is always read as '0’.
+0x58006E80 C FIELD 03w01 JSYNC (rw): Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E80 C FIELD 04w01 JSCAN (rw): Scanning conversion mode for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
+0x58006E80 C FIELD 05w01 JDMAEN (rw): DMA channel enabled to read data for the injected channel group This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E80 C FIELD 08w05 JEXTSEL (rw): Trigger signal selection for launching injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter), asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle). DFSDM_FLTx 0x00 dfsdm_jtrg0 0x01 dfsdm_jtrg1 ... 0x1E dfsdm_jtrg30 0x1F dfsdm_jtrg31 Refer to . 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
+0x58006E80 C FIELD 13w02 JEXTEN (rw): Trigger enable and trigger edge selection for injected conversions This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E80 C FIELD 17w01 RSWSTART (rw): Software start of a conversion on the regular channel This bit is always read as '0’.
+0x58006E80 C FIELD 18w01 RCONT (rw): Continuous mode selection for regular conversions Writing '0’ to this bit while a continuous regular conversion is already in progress stops the continuous mode immediately.
+0x58006E80 C FIELD 19w01 RSYNC (rw): Launch regular conversion synchronously with DFSDM_FLT0 This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E80 C FIELD 21w01 RDMAEN (rw): DMA channel enabled to read data for the regular conversion This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E80 C FIELD 24w03 RCH (rw): Regular channel selection ... 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It also affects regular conversions which are pending (due to ongoing injected conversion).
+0x58006E80 C FIELD 29w01 FAST (rw): Fast conversion mode selection for regular conversions When converting a regular conversion in continuous mode, having enabled the fast mode causes each conversion (except the first) to execute faster than in standard mode. This bit has no effect on conversions which are not continuous. This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): t = IOSR / fCKIN (... but CNVCNT=0) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input.
+0x58006E80 C FIELD 30w01 AWFSEL (rw): Analog watchdog fast mode select
+0x58006E84 B REGISTER DFSDM_FLT3CR2: None
+0x58006E84 C FIELD 00w01 JEOCIE (rw): Injected end of conversion interrupt enable Please see the explanation of JEOCF in DFSDM_FLTxISR.
+0x58006E84 C FIELD 01w01 REOCIE (rw): Regular end of conversion interrupt enable Please see the explanation of REOCF in DFSDM_FLTxISR.
+0x58006E84 C FIELD 02w01 JOVRIE (rw): Injected data overrun interrupt enable Please see the explanation of JOVRF in DFSDM_FLTxISR.
+0x58006E84 C FIELD 03w01 ROVRIE (rw): Regular data overrun interrupt enable Please see the explanation of ROVRF in DFSDM_FLTxISR.
+0x58006E84 C FIELD 04w01 AWDIE (rw): Analog watchdog interrupt enable Please see the explanation of AWDF in DFSDM_FLTxISR.
+0x58006E84 C FIELD 05w01 SCDIE (rw): Short-circuit detector interrupt enable Please see the explanation of SCDF[7:0] in DFSDM_FLTxISR. Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006E84 C FIELD 06w01 CKABIE (rw): Clock absence interrupt enable Please see the explanation of CKABF[7:0] in DFSDM_FLTxISR. Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
+0x58006E84 C FIELD 08w08 EXCH (rw): Extremes detector channel selection These bits select the input channels to be taken by the Extremes detector. EXCH[y] = 0: Extremes detector does not accept data from channel y EXCH[y] = 1: Extremes detector accepts data from channel y
+0x58006E84 C FIELD 16w08 AWDCH (rw): Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y
+0x58006E88 B REGISTER DFSDM_FLT3ISR: None
+0x58006E88 C FIELD 00w01 JEOCF (ro): End of injected conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.
+0x58006E88 C FIELD 01w01 REOCF (ro): End of regular conversion flag This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
+0x58006E88 C FIELD 02w01 JOVRF (ro): Injected conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the DFSDM_FLTxICR register.
+0x58006E88 C FIELD 03w01 ROVRF (ro): Regular conversion overrun flag This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the DFSDM_FLTxICR register.
+0x58006E88 C FIELD 04w01 AWDF (ro): Analog watchdog This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[7:0] and AWLTF[7:0] in DFSDM_FLTxAWSR register (by writing '1’ into the clear bits in DFSDM_FLTxAWCFR register).
+0x58006E88 C FIELD 13w01 JCIP (ro): Injected conversion in progress status A request to start an injected conversion is ignored when JCIP=1.
+0x58006E88 C FIELD 14w01 RCIP (ro): Regular conversion in progress status A request to start a regular conversion is ignored when RCIP=1.
+0x58006E88 C FIELD 16w08 CKABF (ro): Clock absence flag CKABF[y]=0: Clock signal on channel y is present. CKABF[y]=1: Clock signal on channel y is not present. Given y bit is set by hardware when clock absence is detected on channel y. It is held at CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register. Note: CKABF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006E88 C FIELD 24w08 SCDF (ro): short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given channel is disabled). Note: SCDF[7:0] is present only in DFSDM_FLT0ISR register (filter x=0)
+0x58006E8C B REGISTER DFSDM_FLT3ICR: None
+0x58006E8C C FIELD 02w01 CLRJOVRF (rw): Clear the injected conversion overrun flag
+0x58006E8C C FIELD 03w01 CLRROVRF (rw): Clear the regular conversion overrun flag
+0x58006E8C C FIELD 16w08 CLRCKABF (rw): Clear the clock absence flag CLRCKABF[y]=0: Writing '0’ has no effect CLRCKABF[y]=1: Writing '1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006E8C C FIELD 24w08 CLRSCDF (rw): Clear the short-circuit detector flag CLRSCDF[y]=0: Writing '0’ has no effect CLRSCDF[y]=1: Writing '1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0)
+0x58006E90 B REGISTER DFSDM_FLT3JCHGR: None
+0x58006E90 C FIELD 00w08 JCHG (rw): Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first and the sequence ends at the highest selected channel. If JSCAN=0, then only one channel is converted from the selected channels, and the channel selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to the lowest selected channel. At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored.
+0x58006E94 B REGISTER DFSDM_FLT3FCR: None
+0x58006E94 C FIELD 00w08 IOSR (rw): Integrator oversampling ratio (averaging length) from Sinc filter will be summed into one output data sample from the integrator. The output data rate from the integrator will be decreased by this number (additional data decimation ratio). This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass). 0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
+0x58006E94 C FIELD 16w10 FOSR (rw): Sinc filter oversampling ratio (decimation rate) number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass). 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
+0x58006E94 C FIELD 29w03 FORD (rw): Sinc filter order 2: Sinc2 filter type 3: Sinc3 filter type 4: Sinc4 filter type 5: Sinc5 filter type 6-7: Reserved Sincx filter type transfer function: FastSinc filter type transfer function: This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
+0x58006E98 B REGISTER DFSDM_FLT3JDATAR: None
+0x58006E98 C FIELD 00w03 JDATACH (ro): Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the channel indicated by JDATACH[2:0].
+0x58006E98 C FIELD 08w24 JDATA (ro): Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
+0x58006E9C B REGISTER DFSDM_FLT3RDATAR: None
+0x58006E9C C FIELD 00w03 RDATACH (ro): Regular channel most recently converted When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the channel indicated by RDATACH[2:0].
+0x58006E9C C FIELD 04w01 RPEND (ro): Regular channel pending data Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
+0x58006E9C C FIELD 08w24 RDATA (ro): Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears the corresponding REOCF.
+0x58006EA0 B REGISTER DFSDM_FLT3AWHTR: None
+0x58006EA0 C FIELD 00w04 BKAWH (rw): Break signal assignment to analog watchdog high threshold event BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
+0x58006EA0 C FIELD 08w24 AWHT (rw): Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into comparison in this case.
+0x58006EA4 B REGISTER DFSDM_FLT3AWLTR: None
+0x58006EA4 C FIELD 00w04 BKAWL (rw): Break signal assignment to analog watchdog low threshold event BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
+0x58006EA4 C FIELD 08w24 AWLT (rw): Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into comparison in this case.
+0x58006EA8 B REGISTER DFSDM_FLT3AWSR: None
+0x58006EA8 C FIELD 00w08 AWLTF (ro): Analog watchdog low threshold flag AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006EA8 C FIELD 08w08 AWHTF (ro): Analog watchdog high threshold flag AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
+0x58006EAC B REGISTER DFSDM_FLT3AWCFR: None
+0x58006EAC C FIELD 00w08 CLRAWLTF (rw): Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing '0’ has no effect CLRAWLTF[y]=1: Writing '1’ to position y clears the corresponding AWLTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006EAC C FIELD 08w08 CLRAWHTF (rw): Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing '0’ has no effect CLRAWHTF[y]=1: Writing '1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register
+0x58006EB0 B REGISTER DFSDM_FLT3EXMAX: None
+0x58006EB0 C FIELD 00w03 EXMAXCH (ro): Extremes detector maximum data channel. These bits contains information about the channel on which the data is stored into EXMAX[23:0]. Bits are cleared by reading of this register.
+0x58006EB0 C FIELD 08w24 EXMAX (ro): Extremes detector maximum value These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx. EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
+0x58006EB4 B REGISTER DFSDM_FLT3EXMIN: None
+0x58006EB4 C FIELD 00w03 EXMINCH (ro): Extremes detector minimum data channel These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits are cleared by reading of this register.
+0x58006EB4 C FIELD 08w24 EXMIN (rw): Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
+0x58006EB8 B REGISTER DFSDM_FLT3CNVTIMR: None
+0x58006EB8 C FIELD 04w28 CNVCNT (ro): 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion time measurement stopped and CNVCNT[27:0] = 0. The counted time is: if FAST=0 (or first conversion in continuous mode if FAST=1): t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN ..... for Sincx filters t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN ..... for FastSinc filter if FAST=1 in continuous mode (except first conversion): t = [FOSR * IOSR] / fCKIN in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator): CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN) where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in case of parallel data input (from internal ADC or from CPU/DMA write) Note: When conversion is interrupted (e.g. by disable/enable selected channel) the
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