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October 22, 2019 05:12
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AppleIntelInfo.kext v2.9 Copyright © 2012-2017 Pike R. Alpha. All rights reserved. | |
Settings: | |
------------------------------------------ | |
logMSRs..................................: 1 | |
logIGPU..................................: 0 | |
logCStates...............................: 1 | |
logIPGStyle..............................: 1 | |
InitialTSC...............................: 0x16a3fb110da4 (777 MHz) | |
MWAIT C-States...........................: 135456 | |
Processor Brandstring....................: Intel(R) Xeon(R) CPU E5-1650 0 @ 3.20GHz | |
Processor Signature..................... : 0x206D7 | |
------------------------------------------ | |
- Family............................... : 6 | |
- Stepping............................. : 7 | |
- Model................................ : 0x2D (45) | |
Model Specific Registers (MSRs) | |
------------------------------------------ | |
MSR_IA32_PLATFORM_ID.............(0x17) : 0x0 | |
------------------------------------------ | |
- Processor Flags...................... : 0 | |
MSR_CORE_THREAD_COUNT............(0x35) : 0x6000C | |
------------------------------------------ | |
- Core Count........................... : 6 | |
- Thread Count......................... : 12 | |
MSR_PLATFORM_INFO................(0xCE) : 0xC0074012000 | |
------------------------------------------ | |
- Maximum Non-Turbo Ratio.............. : 0x20 (3200 MHz) | |
- Ratio Limit for Turbo Mode........... : 1 (programmable) | |
- TDP Limit for Turbo Mode............. : 1 (programmable) | |
- Low Power Mode Support............... : 0 (LMP not supported) | |
- Number of ConfigTDP Levels........... : 0 (only base TDP level available) | |
- Maximum Efficiency Ratio............. : 12 | |
MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x1E008403 | |
------------------------------------------ | |
- I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT) | |
- CFG Lock............................. : 1 (MSR locked until next reset) | |
- C3 State Auto Demotion............... : 1 (enabled) | |
- C1 State Auto Demotion............... : 1 (enabled) | |
- C3 State Undemotion.................. : 1 (enabled) | |
- C1 State Undemotion.................. : 1 (enabled) | |
- Package C-State Auto Demotion........ : 0 (disabled/unsupported) | |
- Package C-State Undemotion........... : 0 (disabled/unsupported) | |
MSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x10414 | |
------------------------------------------ | |
- LVL_2 Base Address................... : 0x414 | |
- C-state Range........................ : 1 (C6 is the max C-State to include) | |
IA32_MPERF.......................(0xE7) : 0xDC4A7C9376 | |
IA32_APERF.......................(0xE8) : 0xCF3AA80301 | |
MSR_FLEX_RATIO...................(0x194) : 0xE0000 | |
------------------------------------------ | |
MSR_IA32_PERF_STATUS.............(0x198) : 0x25CA00002000 | |
------------------------------------------ | |
- Current Performance State Value...... : 0x2000 (3200 MHz) | |
MSR_IA32_PERF_CONTROL............(0x199) : 0x2000 | |
------------------------------------------ | |
- Target performance State Value....... : 0x2000 (3200 MHz) | |
- Intel Dynamic Acceleration........... : 0 (IDA engaged) | |
IA32_CLOCK_MODULATION............(0x19A) : 0x0 | |
IA32_THERM_INTERRUPT.............(0x19B) : 0x0 | |
IA32_THERM_STATUS................(0x19C) : 0x88220000 | |
------------------------------------------ | |
- Thermal Status....................... : 0 | |
- Thermal Log.......................... : 0 | |
- PROCHOT # or FORCEPR# event.......... : 0 | |
- PROCHOT # or FORCEPR# log............ : 0 | |
- Critical Temperature Status.......... : 0 | |
- Critical Temperature log............. : 0 | |
- Thermal Threshold #1 Status.......... : 0 | |
- Thermal Threshold #1 log............. : 0 | |
- Thermal Threshold #2 Status.......... : 0 | |
- Thermal Threshold #2 log............. : 0 | |
- Power Limitation Status.............. : 0 | |
- Power Limitation log................. : 0 | |
- Current Limit Status................. : 0 | |
- Current Limit log.................... : 0 | |
- Cross Domain Limit Status............ : 0 | |
- Cross Domain Limit log............... : 0 | |
- Digital Readout...................... : 34 | |
- Resolution in Degrees Celsius........ : 1 | |
- Reading Valid........................ : 1 (valid) | |
MSR_THERM2_CTL...................(0x19D) : 0x0 | |
IA32_MISC_ENABLES................(0x1A0) : 0x850089 | |
------------------------------------------ | |
- Fast-Strings......................... : 1 (enabled) | |
- FOPCODE compatibility mode Enable.... : 0 | |
- Automatic Thermal Control Circuit.... : 1 (enabled) | |
- Split-lock Disable................... : 0 | |
- Performance Monitoring............... : 1 (available) | |
- Bus Lock On Cache Line Splits Disable : 0 | |
- Hardware prefetch Disable............ : 0 | |
- Processor Event Based Sampling....... : 0 (PEBS supported) | |
- GV1/2 legacy Enable.................. : 0 | |
- Enhanced Intel SpeedStep Technology.. : 1 (enabled) | |
- MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported) | |
- Adjacent sector prefetch Disable..... : 0 | |
- CFG Lock............................. : 0 (MSR not locked) | |
- xTPR Message Disable................. : 1 (disabled) | |
MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x5B0A00 | |
------------------------------------------ | |
- Turbo Attenuation Units.............. : 0 | |
- Temperature Target................... : 91 | |
- TCC Activation Offset................ : 0 | |
MSR_MISC_PWR_MGMT................(0x1AA) : 0x400000 | |
------------------------------------------ | |
- EIST Hardware Coordination........... : 0 (hardware coordination enabled) | |
- Energy/Performance Bias support...... : 1 | |
- Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software) | |
- Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores) | |
- SpeedShift Technology Enable......... : 0 (disabled) | |
- SpeedShift Interrupt Coordination.... : 0 (disabled) | |
- SpeedShift Energy Efficient Perf..... : 0 (disabled) | |
- SpeedShift Technology Setup for HWP.. : No (not setup for HWP) | |
MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2323232324252626 | |
------------------------------------------ | |
- Maximum Ratio Limit for C01.......... : 26 (3800 MHz) | |
- Maximum Ratio Limit for C02.......... : 26 (3800 MHz) | |
- Maximum Ratio Limit for C03.......... : 25 (3700 MHz) | |
- Maximum Ratio Limit for C04.......... : 24 (3600 MHz) | |
- Maximum Ratio Limit for C05.......... : 23 (3500 MHz) | |
- Maximum Ratio Limit for C06.......... : 23 (3500 MHz) | |
IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x0 | |
MSR_POWER_CTL....................(0x1FC) : 0x2504005B | |
------------------------------------------ | |
- Bi-Directional Processor Hot..........: 1 (enabled) | |
- C1E Enable............................: 1 (enabled) | |
MSR_RAPL_POWER_UNIT..............(0x606) : 0xA1003 | |
------------------------------------------ | |
- Power Units.......................... : 3 (1/8 Watt) | |
- Energy Status Units.................. : 16 (15.3 micro-Joules) | |
- Time Units .......................... : 10 (976.6 micro-Seconds) | |
MSR_PKG_POWER_LIMIT..............(0x610) : 0x8000851400148410 | |
------------------------------------------ | |
- Package Power Limit #1............... : 130 Watt | |
- Enable Power Limit #1................ : 1 (enabled) | |
- Package Clamping Limitation #1....... : 0 (disabled) | |
- Time Window for Power Limit #1....... : 10 (2560 milli-Seconds) | |
- Package Power Limit #2............... : 162 Watt | |
- Enable Power Limit #2................ : 1 (enabled) | |
- Package Clamping Limitation #2....... : 0 (disabled) | |
- Time Window for Power Limit #2....... : 0 (2 milli-Seconds) | |
- Lock................................. : 1 (MSR locked until next reset) | |
MSR_PKG_ENERGY_STATUS............(0x611) : 0x7E0C3F9F | |
------------------------------------------ | |
- Total Energy Consumed................ : 32268 Joules (Watt = Joules / seconds) | |
MSR_PP0_POWER_LIMIT..............(0x638) : 0x0 | |
MSR_PP0_ENERGY_STATUS............(0x639) : 0x2372D9A1 | |
------------------------------------------ | |
- Total Energy Consumed................ : 9074 Joules (Watt = Joules / seconds) | |
MSR_PP0_POWER_LIMIT..............(0x638) : 0x0 | |
MSR_PP0_ENERGY_STATUS............(0x639) : 0x2372D9A1 | |
------------------------------------------ | |
- Total Energy Consumed................ : 9074 Joules (Watt = Joules / seconds) | |
MSR_PKGC3_IRTL...................(0x60a) : 0x0 | |
MSR_PKGC6_IRTL...................(0x60b) : 0x0 | |
MSR_PKGC7_IRTL...................(0x60c) : 0x0 | |
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x0 | |
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0 | |
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x0 | |
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0 | |
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x0 | |
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x0 | |
IA32_TSC_DEADLINE................(0x6E0) : 0x16A3FF8B1A76 | |
CPU Ratio Info: | |
------------------------------------------ | |
Base Clock Frequency (BLCK)............. : 100 MHz | |
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz) | |
Maximum non-Turbo Ratio/Frequency........: 32 (3200 MHz) | |
Maximum Turbo Ratio/Frequency............: 38 (3800 MHz) | |
P-State ratio * 100 = Frequency in MHz | |
------------------------------------------ | |
CPU P-States [ (12) 32 ] | |
CPU P-States [ (12) 23 32 ] | |
CPU P-States [ (12) 23 25 32 ] | |
CPU P-States [ (12) 23 25 27 32 ] | |
CPU P-States [ (12) 22 23 25 27 32 ] | |
CPU P-States [ (12) 22 23 25 27 31 32 ] | |
CPU P-States [ (12) 21 22 23 25 27 31 32 ] | |
CPU P-States [ (12) 19 21 22 23 25 27 31 32 ] | |
CPU P-States [ (12) 19 21 22 23 24 25 27 31 32 ] | |
CPU P-States [ (12) 19 20 21 22 23 24 25 27 31 32 ] | |
CPU P-States [ (12) 19 20 21 22 23 24 25 26 27 31 32 ] | |
CPU P-States [ (12) 19 20 21 22 23 24 25 26 27 28 31 32 ] | |
CPU P-States [ 12 19 20 21 22 23 24 25 26 27 28 30 31 (32) ] | |
CPU P-States [ (12) 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ] | |
CPU P-States [ 12 16 19 20 21 22 23 24 25 26 27 28 29 30 31 (32) ] | |
CPU P-States [ (12) 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ] | |
CPU P-States [ (12) 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ] | |
CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ] | |
CPU P-States [ (12) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ] | |
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ] |
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