Skip to content

Instantly share code, notes, and snippets.

@maxfierke

maxfierke/0001-AxDroid-Dell-Axim-x51v-patches.patch

Created November 9, 2015 04:50
Show Gist options
  • Save maxfierke/c81ad26470688ea07daf to your computer and use it in GitHub Desktop.
Save maxfierke/c81ad26470688ea07daf to your computer and use it in GitHub Desktop.
Download ZIP
Collection of Dell Axim X50/X51(v) related linux patches
Raw
0001-AxDroid-Dell-Axim-x51v-patches.patch
From 6d9ae3523f12b1cf0e65ca493b8a2fb73fd31bf9 Mon Sep 17 00:00:00 2001
From: Ertan Deniz <ertan@ertan-desktop.local>
Date: Tue, 25 Aug 2009 20:04:07 +0300
Subject: [PATCH] AxDroid - Dell Axim x51v patches
---
Makefile | 6 +-
arch/arm/configs/aximx50_static_defconfig | 1638 ++++++++++++++++
arch/arm/mach-pxa/Kconfig | 2 +
arch/arm/mach-pxa/Makefile | 1 +
arch/arm/mach-pxa/Makefile.boot | 3 +
arch/arm/mach-pxa/aximx50/Kconfig | 17 +
arch/arm/mach-pxa/aximx50/Makefile | 4 +
arch/arm/mach-pxa/aximx50/aximx50.c | 303 +++
arch/arm/mach-pxa/aximx50/aximx50_bt.c | 187 ++
arch/arm/mach-pxa/aximx50/aximx50_buttons.c | 82 +
arch/arm/mach-pxa/aximx50/aximx50_lcd.c | 141 ++
arch/arm/mach-pxa/aximx50/aximx50_mmc.c | 94 +
arch/arm/mach-pxa/aximx50/aximx50_udc.c | 68 +
arch/arm/mach-pxa/include/mach/memory.h | 4 +
drivers/input/touchscreen/ads7846.c | 18 +-
include/asm-arm/arch-pxa/aximx50-gpio.h | 64 +
include/asm-arm/arch-pxa/pxa-regs.h | 2819 +++++++++++++++++++++++++++
sound/soc/pxa/Kconfig | 10 +
sound/soc/pxa/Makefile | 2 +
sound/soc/pxa/aximx50-soc.c | 333 ++++
20 files changed, 5788 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/configs/aximx50_static_defconfig
create mode 100644 arch/arm/mach-pxa/aximx50/Kconfig
create mode 100644 arch/arm/mach-pxa/aximx50/Makefile
create mode 100644 arch/arm/mach-pxa/aximx50/aximx50.c
create mode 100644 arch/arm/mach-pxa/aximx50/aximx50_bt.c
create mode 100644 arch/arm/mach-pxa/aximx50/aximx50_buttons.c
create mode 100644 arch/arm/mach-pxa/aximx50/aximx50_lcd.c
create mode 100644 arch/arm/mach-pxa/aximx50/aximx50_mmc.c
create mode 100644 arch/arm/mach-pxa/aximx50/aximx50_udc.c
create mode 100644 include/asm-arm/arch-pxa/aximx50-gpio.h
create mode 100644 include/asm-arm/arch-pxa/pxa-regs.h
create mode 100644 sound/soc/pxa/aximx50-soc.c
diff --git a/Makefile b/Makefile
index 1ab3ebf..c724812 100644
--- a/Makefile
+++ b/Makefile
@@ -189,9 +189,9 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
# Alternatively CROSS_COMPILE can be set in the environment.
# Default value for CROSS_COMPILE is not to prefix executables
# Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
-export KBUILD_BUILDHOST := $(SUBARCH)
-ARCH ?= $(SUBARCH)
-CROSS_COMPILE ?=
+export KBUILD_BUILDHOST := arm
+ARCH ?= arm
+CROSS_COMPILE ?= arm-none-eabi-
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)
diff --git a/arch/arm/configs/aximx50_static_defconfig b/arch/arm/configs/aximx50_static_defconfig
new file mode 100644
index 0000000..cc9d6ba
--- /dev/null
+++ b/arch/arm/configs/aximx50_static_defconfig
@@ -0,0 +1,1638 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29
+# Tue May 12 21:47:04 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ASHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_ARCH_PXA_IDP is not set
+CONFIG_MACH_X50=y
+CONFIG_DRAM_BASE=0xa8000000
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_VIPER is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_H5000 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA27x=y
+CONFIG_PXA_SSP=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="keepinitrd"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+# CONFIG_ATAGS_PROC is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_MIN_TICKS=10
+CONFIG_CPU_FREQ_SAMPLING_LATENCY_MULTIPLIER=1000
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+# CONFIG_CONSOLE_EARLYSUSPEND is not set
+CONFIG_FB_EARLYSUSPEND=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=y
+CONFIG_IRCOMM=y
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+
+#
+# FIR device drivers
+#
+# CONFIG_PXA_FICP is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+# CONFIG_BT_BNEP is not set
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIVHCI=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+# CONFIG_MTD_BLKDEVS is not set
+# CONFIG_MTD_BLOCK is not set
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_H1900 is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_SHARPSL is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+CONFIG_UID_STAT=y
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MOUSE_GPIO=y
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+CONFIG_INPUT_GPIO=y
+CONFIG_INPUT_KEYCHORD=y
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DCC_TTY=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+CONFIG_I2C_PXA_SLAVE=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_PCA963X is not set
+CONFIG_I2C_DEBUG_CORE=y
+CONFIG_I2C_DEBUG_ALGO=y
+CONFIG_I2C_DEBUG_BUS=y
+CONFIG_I2C_DEBUG_CHIP=y
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_W1=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_GPIO is not set
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=y
+# CONFIG_W1_SLAVE_BQ27000 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+CONFIG_APM_POWER=y
+CONFIG_BATTERY_DS2760=y
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
+CONFIG_FB_MBX=y
+# CONFIG_FB_MBX_DEBUG is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_LIB=y
+# CONFIG_SND_PXA2XX_AC97 is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_SOC=y
+CONFIG_SND_PXA2XX_SOC=y
+CONFIG_SND_PXA2XX_SOC_I2S=y
+CONFIG_SND_PXA2XX_SOC_X50=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8750=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+# CONFIG_HID_APPLE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+CONFIG_USB_GADGET_PXA27X=y
+CONFIG_USB_PXA27X=y
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+# CONFIG_USB_ETH_RNDIS is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# CONFIG_MMC_EMBEDDED_SDIO is not set
+# CONFIG_MMC_PARANOID_SD_INIT is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_MMC_BLOCK_PARANOID_RESUME=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+# CONFIG_LEDS_TRIGGER_SLEEP is not set
+CONFIG_SWITCH=y
+CONFIG_SWITCH_GPIO=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_INTF_ALARM=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+# CONFIG_RTC_DRV_PXA is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_MEILHAUS is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR=0
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE=0
+CONFIG_ANDROID_TIMED_OUTPUT=y
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 8eea730..b249944 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -74,6 +74,8 @@ config ARCH_PXA_IDP
bool "Accelent Xscale IDP"
select PXA25x
+source "arch/arm/mach-pxa/aximx50/Kconfig"
+
config PXA_SHARPSL
bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
select SHARP_SCOOP
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 7b28bb5..85715dd 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MACH_E800) += e800.o
obj-$(CONFIG_MACH_PALMTX) += palmtx.o
obj-$(CONFIG_MACH_PALMZ72) += palmz72.o
obj-$(CONFIG_ARCH_VIPER) += viper.o
+obj-$(CONFIG_MACH_X50) += aximx50/
ifeq ($(CONFIG_MACH_ZYLONITE),y)
obj-y += zylonite.o
diff --git a/arch/arm/mach-pxa/Makefile.boot b/arch/arm/mach-pxa/Makefile.boot
index 1ead671..53c2154 100644
--- a/arch/arm/mach-pxa/Makefile.boot
+++ b/arch/arm/mach-pxa/Makefile.boot
@@ -1,2 +1,5 @@
zreladdr-y := 0xa0008000
+ifeq ($(CONFIG_ARCH_PXA),y)
+ zreladdr-$(CONFIG_MACH_X50) := 0xa8008000
+endif
diff --git a/arch/arm/mach-pxa/aximx50/Kconfig b/arch/arm/mach-pxa/aximx50/Kconfig
new file mode 100644
index 0000000..29e4b7e
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/Kconfig
@@ -0,0 +1,17 @@
+menuconfig MACH_X50
+ bool "Dell Axim X50/X51(v)"
+ select PXA27x
+ select KEYBOARD_GPIO
+ help
+ Enable this if you plan to boot the kernel on the Dell Axim X50/X51(v)
+ series of PDAs. Currently there is only basic support for this
+ type of PDAs.
+
+config DRAM_BASE
+ hex '(S)DRAM Base Address'
+ depends on MACH_X50
+ default 0xa8000000
+ help
+ On the Dell Axim X50/X51(v), RAM starts at 0xa8000000. You should not
+ need to modify this value.
+
diff --git a/arch/arm/mach-pxa/aximx50/Makefile b/arch/arm/mach-pxa/aximx50/Makefile
new file mode 100644
index 0000000..2763745
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/Makefile
@@ -0,0 +1,4 @@
+#
+# Dell Axim x50/x51(v) PDA Makefile for the linux kernel.
+#
+obj-$(CONFIG_MACH_X50) += aximx50.o aximx50_lcd.o aximx50_buttons.o aximx50_udc.o aximx50_mmc.o aximx50_bt.o
diff --git a/arch/arm/mach-pxa/aximx50/aximx50.c b/arch/arm/mach-pxa/aximx50/aximx50.c
new file mode 100644
index 0000000..cea4b78
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/aximx50.c
@@ -0,0 +1,303 @@
+/*
+ * Hardware definitions for Dell Axim X50/51(v)
+ *
+ * Copyright (c) 2009 Ertan Deniz
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+
+#include <linux/mfd/htc-egpio.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <mach/pxa2xx_spi.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch-pxa/aximx50-gpio.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+//#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxafb.h>
+#include <mach/gpio.h>
+#include <mach/ssp.h>
+#include <mach/i2c.h>
+
+#include "../generic.h"
+
+/***********
+ * Buttons *
+ ***********/
+
+static struct platform_device aximx50_buttons = {
+ .name = "aximx50-buttons",
+ .id = -1,
+};
+
+static struct platform_device aximx50_lcd = {
+ .name = "aximx50-lcd",
+ .id = -1,
+};
+
+static struct platform_device aximx50_udc = {
+ .name = "aximx50-udc",
+ .id = -1,
+};
+
+static struct platform_device aximx50_bt = {
+ .name = "aximx50-bt",
+ .id = -1,
+};
+
+/****************
+ * Init Machine *
+ ****************/
+
+static unsigned long aximx50_pin_config[] __initdata = {
+
+ /* BTUART */
+ GPIO42_BTUART_RXD,
+ GPIO43_BTUART_TXD,
+ GPIO44_BTUART_CTS,
+ GPIO45_BTUART_RTS,
+
+ /* STUART */
+ GPIO46_STUART_RXD,
+ GPIO47_STUART_TXD,
+
+ /* MCI controller */
+/* GPIO32_MMC_CLK,
+ GPIO112_MMC_CMD,
+ GPIO92_MMC_DAT_0,
+ GPIO109_MMC_DAT_1,
+ GPIO110_MMC_DAT_2,
+ GPIO111_MMC_DAT_3,*/
+
+ /* LCD */
+ GPIO58_LCD_LDD_0,
+ GPIO59_LCD_LDD_1,
+ GPIO60_LCD_LDD_2,
+ GPIO61_LCD_LDD_3,
+ GPIO62_LCD_LDD_4,
+ GPIO63_LCD_LDD_5,
+ GPIO64_LCD_LDD_6,
+ GPIO65_LCD_LDD_7,
+ GPIO66_LCD_LDD_8,
+ GPIO67_LCD_LDD_9,
+ GPIO68_LCD_LDD_10,
+ GPIO69_LCD_LDD_11,
+ GPIO70_LCD_LDD_12,
+ GPIO71_LCD_LDD_13,
+ GPIO72_LCD_LDD_14,
+ GPIO73_LCD_LDD_15,
+ GPIO74_LCD_FCLK,
+ GPIO75_LCD_LCLK,
+ GPIO76_LCD_PCLK,
+ GPIO77_LCD_BIAS,
+
+ /* I2C */
+ GPIO117_I2C_SCL,
+ GPIO118_I2C_SDA,
+
+ /* SSP1 */
+ GPIO23_SSP1_SCLK,
+ GPIO24_GPIO, /* GPIO_NR_X50_TSC2046_CS - SFRM as chip select */
+ GPIO25_SSP1_TXD,
+ GPIO26_SSP1_RXD,
+
+ /* PC Card */
+ GPIO48_nPOE,
+ GPIO49_nPWE,
+ GPIO50_nPIOR,
+ GPIO51_nPIOW,
+ GPIO85_nPCE_1,
+ GPIO54_nPCE_2,
+ GPIO55_nPREG,
+ GPIO56_nPWAIT,
+ GPIO57_nIOIS16,
+
+ /* SDRAM and local bus */
+ GPIO15_nCS_1,
+ GPIO78_nCS_2,
+ GPIO79_nCS_3,
+ GPIO80_nCS_4,
+ GPIO33_nCS_5,
+ GPIO18_RDY,
+};
+
+/* ADS7846 is connected through SSP ... */
+static struct pxa2xx_spi_master pxa_ssp_master_info = {
+ .num_chipselect = 3, /* Matches the number of chips attached to NSSP */
+// .clock_enable = CKEN_SSP1,
+ .enable_dma = 1,
+};
+
+static void ads7846_cs(u32 command)
+{
+ gpio_set_value(GPIO_NR_X50_TSC2046_CS, !(command == PXA2XX_CS_ASSERT));
+}
+
+static int aximx50_ads7846_pendown_state(void)
+{
+ return !gpio_get_value(GPIO_NR_X50_PEN_IRQ_N);
+}
+
+static struct pxa2xx_spi_chip ads_hw = {
+// .tx_threshold = 12,
+// .rx_threshold = 12,
+// .dma_burst_size = 8,
+ .cs_control = ads7846_cs,
+};
+
+static const struct ads7846_platform_data aximx50_ts_info = {
+ .model = 7846,
+ .vref_delay_usecs = 100, /* internal, no capacitor */
+ .settle_delay_usecs = 150,
+ .x_min = 1,
+ .x_max = 480,
+ .y_min = 1,
+ .y_max = 640,
+ .pressure_min = 1,
+ .pressure_max = 512,
+ .debounce_max = 20,
+ .debounce_tol = 10,
+ .debounce_rep = 1,
+// .get_pendown_state = &aximx50_ads7846_pendown_state,
+ .gpio_pendown = GPIO_NR_X50_PEN_IRQ_N,
+};
+
+static struct spi_board_info __initdata aximx50_boardinfo[] = { {
+ .modalias = "ads7846",
+ .platform_data = &aximx50_ts_info,
+ .controller_data = &ads_hw,
+ .irq = X50_IRQ(PEN_IRQ_N),
+ .max_speed_hz = 100000 /* max sample rate at 3V */
+ * 26 /* command + data + overhead */,
+ .bus_num = 1,
+ .chip_select = 0,
+} };
+
+/******************************************************/
+/* EGPIOs */
+
+
+/*
+ * EGPIO (Xilinx CPLD)
+ *
+ * 7 32-bit aligned 8-bit registers: 3x output, 1x irq, 3x input
+ */
+static struct resource egpio_resources[] = {
+ [0] = {
+ .start = PXA_CS4_PHYS,
+ .end = PXA_CS4_PHYS + 0x20,
+ .flags = IORESOURCE_MEM,
+ },/*
+ [1] = {
+ .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+ .end = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+ .flags = IORESOURCE_IRQ,
+ },*/
+};
+
+static struct htc_egpio_chip egpio_chips[] = {
+ [0] = {
+ .reg_start = 0,
+ .gpio_base = X50_EGPIO_BASE,
+ .num_gpios = 24,
+ .direction = HTC_EGPIO_OUTPUT,
+ //.initial_values = 0x40, /* EGPIO_MAGICIAN_GSM_RESET */
+ },/*
+ [1] = {
+ .reg_start = 4,
+ .gpio_base = MAGICIAN_EGPIO(4, 0),
+ .num_gpios = 24,
+ .direction = HTC_EGPIO_INPUT,
+ },*/
+};
+
+static struct htc_egpio_platform_data egpio_info = {
+ .reg_width = 8,
+ .bus_width = 32,
+ /*.irq_base = IRQ_BOARD_START,
+ .num_irqs = 4,
+ .ack_register = 3,*/
+ .chip = egpio_chips,
+ .num_chips = ARRAY_SIZE(egpio_chips),
+};
+
+static struct platform_device aximx50_egpio = {
+ .name = "htc-egpio",
+ .id = -1,
+ .resource = egpio_resources,
+ .num_resources = ARRAY_SIZE(egpio_resources),
+ .dev = {
+ .platform_data = &egpio_info,
+ },
+};
+
+/******************************************************/
+
+static struct platform_device *devices[] __initdata = {
+ &aximx50_egpio,
+ &aximx50_buttons,
+ &aximx50_lcd,
+ &aximx50_udc,
+ &aximx50_bt,
+};
+
+static void __init aximx50_map_io(void)
+{
+ pxa_map_io();
+}
+
+static void __init aximx50_init_irq(void)
+{
+ pxa27x_init_irq();
+}
+
+static void __init aximx50_init( void )
+{
+ int err;
+ printk(KERN_NOTICE "Dell Axim x50/x51v initialization\n");
+
+ pxa2xx_mfp_config(ARRAY_AND_SIZE(aximx50_pin_config));
+
+ err = gpio_request(GPIO_NR_X50_TSC2046_CS, "ADS7846_CS");
+ if (err)
+ return;
+
+ gpio_direction_output(GPIO_NR_X50_TSC2046_CS, 1);
+
+ pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
+ spi_register_board_info(aximx50_boardinfo, ARRAY_SIZE(aximx50_boardinfo));
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+ pxa_set_i2c_info(NULL);
+}
+
+
+MACHINE_START(X50, "Dell Axim x50/x51v")
+ .phys_io = 0x40000000,
+ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
+ .boot_params = 0xa8000100,
+ .map_io = aximx50_map_io,
+ .init_irq = aximx50_init_irq,
+ .timer = &pxa_timer,
+ .init_machine = aximx50_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/aximx50/aximx50_bt.c b/arch/arm/mach-pxa/aximx50/aximx50_bt.c
new file mode 100644
index 0000000..e7152ca
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/aximx50_bt.c
@@ -0,0 +1,187 @@
+/*
+ * Bluetooth driver for Dell Axim x50/x51v
+ *
+ * Copyright (c) 2009 Ertan Deniz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/rfkill.h>
+
+#include <asm/arch-pxa/aximx50-gpio.h>
+
+static void aximx50_bt_on()
+{
+ printk("***** DELL AXIM BLUETOOTH ON ******\n");
+ gpio_set_value(EGPIO_X50_BT_RESET, 0);
+ gpio_set_value(EGPIO_X50_BT_PWR, 1);
+ gpio_set_value(GPIO_NR_X50_BT_PWR_EN, 1);
+ gpio_set_value(EGPIO_X50_BT_RESET, 1);
+ mdelay(20);
+ gpio_set_value(EGPIO_X50_BT_RESET, 0);
+
+ //gpio_set_value(EGPIO_X50_BT_RESET, 0);
+ mdelay(20);
+ //gpio_set_value(EGPIO_X50_BT_RESET, 1);
+}
+
+static void aximx50_bt_off()
+{
+ printk("***** DELL AXIM BLUETOOTH OFF ******\n");
+ gpio_set_value(EGPIO_X50_BT_RESET, 1);
+ mdelay(10);
+ gpio_set_value(EGPIO_X50_BT_PWR, 0);
+ gpio_set_value(GPIO_NR_X50_BT_PWR_EN, 0);
+ gpio_set_value(EGPIO_X50_BT_RESET, 0);
+}
+
+static int aximx50_bt_toggle_radio(enum rfkill_state state)
+{
+ static int on = 1;
+
+ if( on == 0 )
+ {
+ state = RFKILL_STATE_ON;
+ on = 1;
+ }
+ else
+ {
+ state = RFKILL_STATE_OFF;
+ on = 0;
+ }
+
+ pr_info("BT_RADIO going: %s, %d\n",
+ state == RFKILL_STATE_ON ? "on" : "off", state);
+
+ if (state == RFKILL_STATE_ON) {
+ pr_info("aximx50_BT: going ON\n");
+ aximx50_bt_on();
+ } else {
+ pr_info("aximx50_BT: going OFF\n");
+ aximx50_bt_off();
+ }
+ return 0;
+}
+
+static int aximx50_bt_probe(struct platform_device *dev)
+{
+ int rc;
+ struct rfkill *rfk;
+
+ printk( "***** DELL AXIM BLUETOOTH PROBE ******\n");
+
+ rc = gpio_request(EGPIO_X50_BT_RESET, "Bluetooth reset");
+ if (rc)
+ goto err_reset;
+ rc = gpio_direction_output(EGPIO_X50_BT_RESET, 0);
+
+ if (rc)
+ goto err_reset_dir;
+
+ rc = gpio_request(GPIO_NR_X50_BT_PWR_EN, "Bluetooth power1");
+ if (rc)
+ goto err_pwr1;
+ rc = gpio_direction_output(GPIO_NR_X50_BT_PWR_EN, 0);
+
+ if (rc)
+ goto err_pwr1_dir;
+
+ rc = gpio_request(EGPIO_X50_BT_PWR, "Bluetooth power");
+ if (rc)
+ goto err_pwr;
+ rc = gpio_direction_output(EGPIO_X50_BT_PWR, 0);
+
+ if (rc)
+ goto err_pwr_dir;
+
+ rfk = rfkill_allocate(&dev->dev, RFKILL_TYPE_BLUETOOTH);
+ if (!rfk) {
+ rc = -ENOMEM;
+ goto err_rfk_alloc;
+ }
+
+ rfk->name = "aximx50-bt";
+ rfk->toggle_radio = aximx50_bt_toggle_radio;
+/*
+#ifdef CONFIG_RFKILL_LEDS
+ rfk->led_trigger.name = "aximx50-bt";
+#endif
+*/
+ rc = rfkill_register(rfk);
+ if (rc)
+ goto err_rfkill;
+
+ platform_set_drvdata(dev, rfk);
+
+ return 0;
+
+err_rfkill:
+ if (rfk)
+ rfkill_free(rfk);
+ rfk = NULL;
+err_rfk_alloc:
+ aximx50_bt_off();
+err_pwr1_dir:
+ gpio_free(GPIO_NR_X50_BT_PWR_EN);
+err_pwr1:
+err_pwr_dir:
+ gpio_free(EGPIO_X50_BT_PWR);
+err_pwr:
+err_reset_dir:
+ gpio_free(EGPIO_X50_BT_RESET);
+err_reset:
+ return rc;
+}
+
+static int __devexit aximx50_bt_remove(struct platform_device *dev)
+{
+ struct rfkill *rfk = platform_get_drvdata(dev);
+
+ platform_set_drvdata(dev, NULL);
+
+ if (rfk)
+ rfkill_unregister(rfk);
+ rfk = NULL;
+
+ aximx50_bt_off();
+
+ gpio_free(GPIO_NR_X50_BT_PWR_EN);
+ gpio_free(EGPIO_X50_BT_PWR);
+ gpio_free(EGPIO_X50_BT_RESET);
+
+ return 0;
+}
+
+static struct platform_driver aximx50_bt_driver = {
+ .probe = aximx50_bt_probe,
+ .remove = __devexit_p(aximx50_bt_remove),
+
+ .driver = {
+ .name = "aximx50-bt",
+ .owner = THIS_MODULE,
+ },
+};
+
+
+static int __init aximx50_bt_init(void)
+{
+ return platform_driver_register(&aximx50_bt_driver);
+}
+
+static void __exit aximx50_bt_exit(void)
+{
+ platform_driver_unregister(&aximx50_bt_driver);
+}
+
+module_init(aximx50_bt_init);
+module_exit(aximx50_bt_exit);
+
+MODULE_AUTHOR ("Ertan Deniz");
+MODULE_DESCRIPTION ("Bluetooth driver for Dell Axim x50/x51v");
+MODULE_LICENSE ("GPL");
diff --git a/arch/arm/mach-pxa/aximx50/aximx50_buttons.c b/arch/arm/mach-pxa/aximx50/aximx50_buttons.c
new file mode 100644
index 0000000..c43e1ed
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/aximx50_buttons.c
@@ -0,0 +1,82 @@
+/*
+ * Buttons driver for Dell Axim x50/x51v
+ *
+ * Copyright (c) 2009 Ertan Deniz
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/mfp-pxa27x.h>
+
+/****************************************************************
+ * Keyboard
+ ****************************************************************/
+static unsigned long x50_keypad_pins[] __initdata = {
+ GPIO93_KP_DKIN_0,
+ GPIO100_KP_MKIN_0,
+ GPIO101_KP_MKIN_1,
+ GPIO97_KP_MKIN_3,
+ GPIO98_KP_MKIN_4,
+ GPIO90_KP_MKIN_5,
+ GPIO91_KP_MKIN_6,
+ GPIO103_KP_MKOUT_0,
+ GPIO105_KP_MKOUT_2,
+};
+
+static unsigned int x50_key_map[] = {
+ KEY(0, 0, KEY_WLAN),
+ KEY(0, 2, KEY_UP),
+
+ KEY(1, 0, KEY_RECORD),
+ KEY(1, 2, KEY_DOWN),
+
+ KEY(3, 0, 67), // calendar
+ KEY(3, 2, KEY_RIGHT),
+
+ KEY(4, 0, 68), // contacts
+ KEY(4, 2, KEY_LEFT),
+
+ KEY(5, 0, KEY_MENU), // mail
+ KEY(5, 2, KEY_ENTER),
+
+ KEY(6, 0, KEY_BACK), // home
+};
+
+static struct pxa27x_keypad_platform_data x50_kbd = {
+ .matrix_key_rows = 7,
+ .matrix_key_cols = 3,
+ .matrix_key_map = x50_key_map,
+ .matrix_key_map_size = ARRAY_SIZE(x50_key_map),
+
+ .direct_key_num = 1,
+ .direct_key_map = { KEY_POWER, 0, 0, 0, 0, 0, 0, 0 },
+};
+
+static int __init aximx50_buttons_init(void)
+{
+ printk("aximx50 buttons initialization\n");
+
+ pxa2xx_mfp_config(x50_keypad_pins, ARRAY_SIZE(x50_keypad_pins));
+ pxa_set_keypad_info(&x50_kbd);
+}
+
+static void __exit aximx50_buttons_exit(void)
+{
+ printk("aximx50 buttons exit\n");
+}
+
+module_init(aximx50_buttons_init);
+module_exit(aximx50_buttons_exit);
+
+MODULE_AUTHOR ("Ertan Deniz");
+MODULE_DESCRIPTION ("Buttons driver for Dell Axim x50/x51v");
+MODULE_LICENSE ("GPL");
diff --git a/arch/arm/mach-pxa/aximx50/aximx50_lcd.c b/arch/arm/mach-pxa/aximx50/aximx50_lcd.c
new file mode 100644
index 0000000..465e658
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/aximx50_lcd.c
@@ -0,0 +1,141 @@
+/*
+ * LCD driver for Dell Axim x50/x51v
+ *
+ * Copyright (c) 2009 Ertan Deniz
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/notifier.h>
+#include <linux/lcd.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/platform_device.h>
+
+#include <asm/gpio.h>
+
+#include <asm/mach-types.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+//#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/regs-lcd.h>
+#include <mach/pxafb.h>
+
+#include <asm/arch-pxa/aximx50-gpio.h>
+
+
+static void aximx50_lcd_power(int on, struct fb_var_screeninfo *si);
+
+/* Axim X50 VGA Version */
+static struct pxafb_mode_info aximx50_pxafb_modes_vga[] = {
+{
+ .pixclock = 96153,
+ .bpp = 16,
+ .xres = 480,
+ .yres = 640,
+ .hsync_len = 64,
+ .vsync_len = 5,
+ .left_margin = 17,
+ .upper_margin = 1,
+ .right_margin = 87,
+ .lower_margin = 4,
+ .sync = 0,
+},
+};
+
+static struct pxafb_mach_info aximx50_fb_info_vga = {
+ .modes = aximx50_pxafb_modes_vga,
+ .num_modes = ARRAY_SIZE(aximx50_pxafb_modes_vga),
+ //.lccr0 = 0x01b008f9,
+ .lccr0 = LCCR0_ENB | LCCR0_LDM | // 0x9
+ LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | LCCR0_Act | // 0xf
+ LCCR0_QDM | // 0x8
+ // 0x0
+ // 0x0
+ LCCR0_BM | LCCR0_OUM | LCCR0_RDSTM | // 0xb
+ LCCR0_CMDIM // 0x1
+ , // 0x0
+ .lccr3 = 0x04f00001,
+ .pxafb_lcd_power = aximx50_lcd_power,
+};
+
+static void aximx50_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+ printk("aximx50 LCD power o%s\n", on ? "n" : "ff");
+/*
+ if (on) {
+ printk(KERN_DEBUG "aximx50 power on\n");
+
+ pxa_gpio_mode(GPIO_NR_aximx50_LCD_POWER_1_MD);
+ pxa_gpio_mode(GPIO_NR_aximx50_LCD_POWER_2_MD);
+
+ gpio_set_value(GPIO_NR_aximx50_LCD_POWER_1, 1);
+ ndelay(1000);
+ gpio_set_value(GPIO_NR_aximx50_LCD_POWER_2, 1);
+ } else {
+ printk(KERN_DEBUG "aximx50 power off\n");
+ udelay(15);
+ gpio_set_value(GPIO_NR_aximx50_LCD_POWER_1, 0);
+ udelay(1);
+ gpio_set_value(GPIO_NR_aximx50_LCD_POWER_2, 0);
+ }*/
+}
+
+static int aximx50_lcd_probe(struct platform_device *dev)
+{
+ printk(KERN_NOTICE "DELL AXIMX50 VGA LCD driver\n");
+ set_pxa_fb_info(&aximx50_fb_info_vga);
+
+ return 0;
+}
+
+static int aximx50_lcd_remove(struct platform_device *dev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int aximx50_lcd_suspend(struct platform_device *dev, pm_message_t state)
+{
+ return 0;
+}
+
+static int aximx50_lcd_resume(struct platform_device *dev)
+{
+ return 0;
+}
+#endif
+
+static struct platform_driver aximx50_lcd_driver = {
+ .driver = {
+ .name = "aximx50-lcd",
+ },
+ .probe = aximx50_lcd_probe,
+ .remove = aximx50_lcd_remove,
+#ifdef CONFIG_PM
+ .suspend = aximx50_lcd_suspend,
+ .resume = aximx50_lcd_resume,
+#endif
+};
+
+static __init int aximx50_lcd_init(void)
+{
+ return platform_driver_register(&aximx50_lcd_driver);
+}
+
+static __exit void aximx50_lcd_exit(void)
+{
+ platform_driver_unregister(&aximx50_lcd_driver);
+}
+
+module_init(aximx50_lcd_init);
+module_exit(aximx50_lcd_exit);
+
+MODULE_AUTHOR("Ertan Deniz");
+MODULE_DESCRIPTION("LCD driver for Dell Axim x50/x51v");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/aximx50/aximx50_mmc.c b/arch/arm/mach-pxa/aximx50/aximx50_mmc.c
new file mode 100644
index 0000000..83adb8b
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/aximx50_mmc.c
@@ -0,0 +1,94 @@
+/*
+ * 2008-11-18 Ertan Deniz Based on p535_mmc.c
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+
+#include <mach/mmc.h>
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+#include <asm/gpio.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/pxa2xx-gpio.h>
+//#include <mach/mfp-pxa27x.h>
+#include <asm/arch-pxa/aximx50-gpio.h>
+
+static int aximx50_mci_init(struct device *dev, irqreturn_t (*aximx50_detect_int)(int, void *), void *data)
+{
+ int err;
+
+ pxa_gpio_mode(GPIO32_MMCCLK_MD);
+ pxa_gpio_mode(GPIO92_MMCDAT0_MD);
+ pxa_gpio_mode(GPIO109_MMCDAT1_MD);
+ pxa_gpio_mode(GPIO110_MMCDAT2_MD);
+ pxa_gpio_mode(GPIO111_MMCDAT3_MD);
+ pxa_gpio_mode(GPIO112_MMCCMD_MD);
+
+ set_irq_type(X50_IRQ(SD_DETECT_N), IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING);
+ err = request_irq(X50_IRQ(SD_DETECT_N), aximx50_detect_int, IRQF_SAMPLE_RANDOM, "SD/MMC CD", data);
+ if (err) {
+ printk(KERN_ERR "aximx50_mci_init: SD/MMC: can't request SD/MMC card detect IRQ\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static void aximx50_mci_set_power(struct device *dev, unsigned int vdd)
+{/*
+ struct pxamci_platform_data* p_d = dev->platform_data;
+
+ if (( 1 << vdd) & p_d->ocr_mask)
+ {
+ gpio_set_value(GPIO_NR_aximx50_SD_POWER_N, 0);
+ }
+ else
+ {
+ gpio_set_value(GPIO_NR_aximx50_SD_POWER_N, 1);
+ }*/
+}
+
+static int aximx50_mci_get_ro(struct device *dev)
+{
+ return 0;
+/* return gpio_get_value(GPIO_NR_aximx50_SD_RO);*/
+}
+
+static void aximx50_mci_exit(struct device *dev, void *data)
+{
+// free_irq(X50_IRQ(SD_DETECT_N), data);
+}
+
+static struct pxamci_platform_data aximx50_mci_platform_data = {
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .init = aximx50_mci_init,
+ .setpower = aximx50_mci_set_power,
+ .get_ro = aximx50_mci_get_ro,
+ .exit = aximx50_mci_exit,
+};
+
+static int __init aximx50_mci_mod_init(void)
+{
+// if (!machine_is_aximx50()) return -ENODEV;
+
+ pxa_set_mci_info(&aximx50_mci_platform_data);
+ return 0;
+}
+
+static void __exit aximx50_mci_mod_exit(void)
+{
+}
+
+module_init(aximx50_mci_mod_init);
+module_exit(aximx50_mci_mod_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Ertan Deniz");
+MODULE_DESCRIPTION("MCI platform support for Dell Axim x50/x51(v)");
diff --git a/arch/arm/mach-pxa/aximx50/aximx50_udc.c b/arch/arm/mach-pxa/aximx50/aximx50_udc.c
new file mode 100644
index 0000000..fe1cab9
--- /dev/null
+++ b/arch/arm/mach-pxa/aximx50/aximx50_udc.c
@@ -0,0 +1,68 @@
+/*
+ * USB Gadget driver for Dell Axim x50/x51v
+ *
+ * Copyright (c) 2009 Ertan Deniz
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/udc.h>
+#include <asm/arch-pxa/aximx50-gpio.h>
+
+static struct pxa2xx_udc_mach_info x50_udc_info = {
+ .gpio_vbus_inverted = false,
+ .gpio_vbus = GPIO_NR_X50_USB_CABLE_DETECT,
+// .gpio_pullup =
+};
+
+static int x50_udc_probe(struct platform_device *pdev)
+{
+ printk("******Probing Axim x50 UDC*****\n");
+ pxa_set_udc_info(&x50_udc_info);
+
+ return 0;
+}
+
+static int x50_udc_remove(struct platform_device *pdev)
+{
+ printk("******Removing Axim x50 UDC*****\n");
+ return 0;
+}
+
+static struct platform_driver x50_udc_driver = {
+ .driver = {
+ .name = "aximx50-udc",
+ },
+ .probe = x50_udc_probe,
+ .remove = x50_udc_remove,
+};
+
+static int __init x50_udc_init(void)
+{
+ //pxa_gpio_mode(GPIO_NR_X50_USB_CABLE_DETECT);
+ printk("******Dell AXIM x50 USB UDC initialization*****\n");
+
+ return platform_driver_register(&x50_udc_driver);
+}
+
+static void __exit x50_udc_exit(void)
+{
+ return;
+}
+
+module_init(x50_udc_init);
+module_exit(x50_udc_exit);
+
+MODULE_AUTHOR("Ertan Deniz");
+MODULE_DESCRIPTION("USB Gadget driver for Dell Axim x50/x51v");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index f626730..3690313 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -15,7 +15,11 @@
/*
* Physical DRAM offset.
*/
+#ifdef CONFIG_DRAM_BASE
+#define PHYS_OFFSET (CONFIG_DRAM_BASE)
+#else
#define PHYS_OFFSET UL(0xa0000000)
+#endif
/*
* The nodes are matched with the physical SDRAM banks as follows:
diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c
index 7c27c8b..4cc4313 100644
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -593,8 +593,16 @@ static void ads7846_rx(void *ads)
dev_dbg(&ts->spi->dev, "DOWN\n");
#endif
}
- input_report_abs(input, ABS_X, x);
+
+ int xtmp, ytmp;
+ xtmp = x;
+ ytmp = y;
+
+ y = (((xtmp-176)*173)/1000);
+ x = 480-(((ytmp-256)*136)/1000);
+
input_report_abs(input, ABS_Y, y);
+ input_report_abs(input, ABS_X, x);
input_report_abs(input, ABS_PRESSURE, Rt);
input_sync(input);
@@ -956,12 +964,12 @@ static int __devinit ads7846_probe(struct spi_device *spi)
input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
input_set_abs_params(input_dev, ABS_X,
- pdata->x_min ? : 0,
- pdata->x_max ? : MAX_12BIT,
+ pdata->x_min,
+ pdata->x_max,
0, 0);
input_set_abs_params(input_dev, ABS_Y,
- pdata->y_min ? : 0,
- pdata->y_max ? : MAX_12BIT,
+ pdata->y_min,
+ pdata->y_max,
0, 0);
input_set_abs_params(input_dev, ABS_PRESSURE,
pdata->pressure_min, pdata->pressure_max, 0, 0);
diff --git a/include/asm-arm/arch-pxa/aximx50-gpio.h b/include/asm-arm/arch-pxa/aximx50-gpio.h
new file mode 100644
index 0000000..18a3a52
--- /dev/null
+++ b/include/asm-arm/arch-pxa/aximx50-gpio.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-arm/arch-pxa/aximx50-gpio.h
+ * History:
+ *
+ * 2007-01-25 Pierre Gaufillet Creation
+ *
+ */
+
+#ifndef _X50_GPIO_H_
+#define _X50_GPIO_H_
+
+#include <mach/pxa2xx-regs.h>
+
+#define GET_X50_GPIO(gpio) \
+ (GPLR(GPIO_NR_X50_ ## gpio) & GPIO_bit(GPIO_NR_X50_ ## gpio))
+
+#define SET_X50_GPIO(gpio, setp) \
+do { \
+if (setp) \
+ GPSR(GPIO_NR_X50_ ## gpio) = GPIO_bit(GPIO_NR_X50_ ## gpio); \
+else \
+ GPCR(GPIO_NR_X50_ ## gpio) = GPIO_bit(GPIO_NR_X50_ ## gpio); \
+} while (0)
+
+#define SET_X50_GPIO_N(gpio, setp) \
+do { \
+if (setp) \
+ GPCR(GPIO_NR_X50_ ## gpio ## _N) = GPIO_bit(GPIO_NR_X50_ ## gpio ## _N); \
+else \
+ GPSR(GPIO_NR_X50_ ## gpio ## _N) = GPIO_bit(GPIO_NR_X50_ ## gpio ## _N); \
+} while (0)
+
+#define X50_IRQ(gpio) \
+ IRQ_GPIO(GPIO_NR_X50_ ## gpio)
+
+/*********************************************************************/
+
+#define GPIO_NR_X50_AC_IN_N 11 /* Input = 1 when externally powered */
+#define GPIO_NR_X50_BACKLIGHT_ON 17 /* Tied to PWM0 when Alt function == 2 */
+#define GPIO_NR_X50_PEN_IRQ_N 94 /* Input = 0 when stylus down */
+#define GPIO_NR_X50_USB_CABLE_DETECT 14 /* Input = 0 when USB is connected */
+#define GPIO_NR_X50_USB_PULLUP 2 /* Input = 0 when USB is connected */
+#define GPIO_NR_X50_TSC2046_CS 24 /* TSC2047 Touchscreen chip select */
+#define GPIO_NR_X50_BT_PWR_EN 22 /* 1 when bluetooth is enabled */
+
+/* experimental values ?? */
+#define GPIO_NR_X50_MUTE_L 83
+#define GPIO_NR_X50_MUTE_R 96
+
+/*#define GPIO_NR_X50_SD_POWER_N 10*/
+#define GPIO_NR_X50_SD_DETECT_N 12
+/*#define GPIO_NR_X50_SD_RO 79*/
+
+/* CPLD */
+
+#define X50_EGPIO_BASE 0x80 /* GPIO_BOARD_START */
+#define X50_EGPIO(reg,bit) \
+ (X50_EGPIO_BASE + 16*reg + bit)
+
+#define EGPIO_X50_BT_PWR X50_EGPIO(3,2)
+#define EGPIO_X50_BT_RESET X50_EGPIO(0,3)
+
+#endif /* _X50_GPIO_H */
+
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
new file mode 100644
index 0000000..d27a91c
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -0,0 +1,2819 @@
+/*
+ * linux/include/asm-arm/arch-pxa/pxa-regs.h
+ *
+ * Author: Nicolas Pitre
+ * Created: Jun 15, 2001
+ * Copyright: MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA_REGS_H
+#define __PXA_REGS_H
+
+
+/*
+ * PXA Chip selects
+ */
+
+#define PXA_CS0_PHYS 0x00000000
+#define PXA_CS1_PHYS 0x04000000
+#define PXA_CS2_PHYS 0x08000000
+#define PXA_CS3_PHYS 0x0C000000
+#define PXA_CS4_PHYS 0x10000000
+#define PXA_CS5_PHYS 0x14000000
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
+#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
+#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
+#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
+#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
+
+#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
+#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
+#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
+
+#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
+#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
+#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
+
+#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
+ (0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
+#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
+ (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
+ (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
+#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
+#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
+#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
+
+#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
+#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
+#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
+#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
+
+
+
+/*
+ * DMA Controller
+ */
+
+#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
+#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
+#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
+#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
+#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
+#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
+#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
+#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
+#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
+#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
+#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
+#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
+#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
+#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
+#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
+#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
+
+#define DCSR(x) __REG2(0x40000000, (x) << 2)
+
+#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
+#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
+#ifdef CONFIG_PXA27x
+#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
+#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
+#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
+#define DCSR_EORINTR (1 << 9) /* The end of Receive */
+#endif
+#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
+#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
+#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
+#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
+#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
+
+#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
+#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
+
+#define DRCMR(n) __REG2(0x40000100, (n)<<2)
+#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
+#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
+#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23 __REG(0x4000015c) /* Reserved */
+#define DRCMR24 __REG(0x40000160) /* Reserved */
+#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29 __REG(0x40000174) /* Reserved */
+#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34 __REG(0x40000188) /* Reserved */
+#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39 __REG(0x4000019C) /* Reserved */
+#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
+#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
+#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
+
+#define DRCMRRXSADR DRCMR2
+#define DRCMRTXSADR DRCMR3
+#define DRCMRRXBTRBR DRCMR4
+#define DRCMRTXBTTHR DRCMR5
+#define DRCMRRXFFRBR DRCMR6
+#define DRCMRTXFFTHR DRCMR7
+#define DRCMRRXMCDR DRCMR8
+#define DRCMRRXMODR DRCMR9
+#define DRCMRTXMODR DRCMR10
+#define DRCMRRXPCDR DRCMR11
+#define DRCMRTXPCDR DRCMR12
+#define DRCMRRXSSDR DRCMR13
+#define DRCMRTXSSDR DRCMR14
+#define DRCMRRXSS2DR DRCMR15
+#define DRCMRTXSS2DR DRCMR16
+#define DRCMRRXICDR DRCMR17
+#define DRCMRTXICDR DRCMR18
+#define DRCMRRXSTRBR DRCMR19
+#define DRCMRTXSTTHR DRCMR20
+#define DRCMRRXMMC DRCMR21
+#define DRCMRTXMMC DRCMR22
+#define DRCMRRXSS3DR DRCMR66
+#define DRCMRTXSS3DR DRCMR67
+#define DRCMRUDC(x) DRCMR((x) + 24)
+
+#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
+#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
+
+#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
+#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
+#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
+#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
+#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
+#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
+#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
+#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
+#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
+#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
+#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
+#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
+#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
+#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
+#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
+#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
+#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
+#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
+#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
+#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
+#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
+#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
+#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
+#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
+#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
+#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
+#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
+#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
+#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
+#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
+#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
+#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
+#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
+#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
+#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
+#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
+#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
+#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
+#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
+#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
+#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
+#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
+#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
+#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
+#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
+#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
+#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
+#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x) __REG2(0x40000200, (x) << 4)
+#define DSADR(x) __REG2(0x40000204, (x) << 4)
+#define DTADR(x) __REG2(0x40000208, (x) << 4)
+#define DCMD(x) __REG2(0x4000020c, (x) << 4)
+
+#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
+#define DDADR_STOP (1 << 0) /* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
+#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
+#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
+#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
+#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
+#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
+#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
+#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
+#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
+
+/* default combinations */
+#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
+
+
+/*
+ * UARTs
+ */
+
+/* Full Function UART (FFUART) */
+#define FFUART FFRBR
+#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
+#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
+#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
+#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
+#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
+#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
+#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
+#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
+#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
+#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
+#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
+#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Bluetooth UART (BTUART) */
+#define BTUART BTRBR
+#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
+#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
+#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
+#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
+#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
+#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
+#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
+#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
+#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
+#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
+#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
+#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Standard UART (STUART) */
+#define STUART STRBR
+#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
+#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
+#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
+#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
+#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
+#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
+#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
+#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
+#define STMSR __REG(0x40700018) /* Reserved */
+#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
+#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
+#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Hardware UART (HWUART) */
+#define HWUART HWRBR
+#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
+#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
+#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
+#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
+#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
+#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
+#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
+#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
+#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
+#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
+#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
+#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
+#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
+#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
+#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+#define IER_DMAE (1 << 7) /* DMA Requests Enable */
+#define IER_UUE (1 << 6) /* UART Unit Enable */
+#define IER_NRZE (1 << 5) /* NRZ coding Enable */
+#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
+#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
+#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
+#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
+#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
+#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
+#define IIR_TOD (1 << 3) /* Time Out Detected */
+#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
+#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
+#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
+
+#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
+#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
+#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
+#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
+#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1 (0)
+#define FCR_ITL_8 (FCR_ITL1)
+#define FCR_ITL_16 (FCR_ITL2)
+#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
+#define LCR_SB (1 << 6) /* Set Break */
+#define LCR_STKYP (1 << 5) /* Sticky Parity */
+#define LCR_EPS (1 << 4) /* Even Parity Select */
+#define LCR_PEN (1 << 3) /* Parity Enable */
+#define LCR_STB (1 << 2) /* Stop Bit */
+#define LCR_WLS1 (1 << 1) /* Word Length Select */
+#define LCR_WLS0 (1 << 0) /* Word Length Select */
+
+#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
+#define LSR_TEMT (1 << 6) /* Transmitter Empty */
+#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
+#define LSR_BI (1 << 4) /* Break Interrupt */
+#define LSR_FE (1 << 3) /* Framing Error */
+#define LSR_PE (1 << 2) /* Parity Error */
+#define LSR_OE (1 << 1) /* Overrun Error */
+#define LSR_DR (1 << 0) /* Data Ready */
+
+#define MCR_AFE (1 << 5) /* auto-flow control enable */
+#define MCR_LOOP (1 << 4) /* loopback mode */
+#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
+#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
+#define MCR_RTS (1 << 1) /* Request to Send */
+#define MCR_DTR (1 << 0) /* Data Terminal Ready */
+
+#define MSR_DCD (1 << 7) /* Data Carrier Detect */
+#define MSR_RI (1 << 6) /* Ring Indicator */
+#define MSR_DSR (1 << 5) /* Data Set Ready */
+#define MSR_CTS (1 << 4) /* Clear To Send */
+#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
+#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
+#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
+#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
+
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
+#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
+#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
+#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
+#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
+
+
+/*
+ * I2C registers
+ */
+
+#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
+#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
+#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
+#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
+#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
+
+#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
+#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
+#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
+
+#define ICR_START (1 << 0) /* start bit */
+#define ICR_STOP (1 << 1) /* stop bit */
+#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
+#define ICR_TB (1 << 3) /* transfer byte bit */
+#define ICR_MA (1 << 4) /* master abort */
+#define ICR_SCLE (1 << 5) /* master clock enable */
+#define ICR_IUE (1 << 6) /* unit enable */
+#define ICR_GCD (1 << 7) /* general call disable */
+#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
+#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
+#define ICR_BEIE (1 << 10) /* enable bus error ints */
+#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
+#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
+#define ICR_SADIE (1 << 13) /* slave address detected int enable */
+#define ICR_UR (1 << 14) /* unit reset */
+#define ICR_FM (1 << 15) /* fast mode */
+
+#define ISR_RWM (1 << 0) /* read/write mode */
+#define ISR_ACKNAK (1 << 1) /* ack/nak status */
+#define ISR_UB (1 << 2) /* unit busy */
+#define ISR_IBB (1 << 3) /* bus busy */
+#define ISR_SSD (1 << 4) /* slave stop detected */
+#define ISR_ALD (1 << 5) /* arbitration loss detected */
+#define ISR_ITE (1 << 6) /* tx buffer empty */
+#define ISR_IRF (1 << 7) /* rx buffer full */
+#define ISR_GCAD (1 << 8) /* general call address detected */
+#define ISR_SAD (1 << 9) /* slave address detected */
+#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
+
+
+/*
+ * Serial Audio Controller
+ */
+
+#define SACR0 __REG(0x40400000) /* Global Control Register */
+#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
+#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
+#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
+#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
+
+#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
+#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
+#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
+#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
+#define SACR0_ENB (1 << 0) /* Enable I2S Link */
+#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
+#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
+#define SACR1_DREC (1 << 3) /* Disable Recording Function */
+#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
+
+#define SASR0_I2SOFF (1 << 7) /* Controller Status */
+#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
+#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
+#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
+#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
+#define SASR0_BSY (1 << 2) /* I2S Busy */
+#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
+#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
+
+#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
+#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
+
+#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
+#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
+#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
+#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
+
+/*
+ * AC97 Controller registers
+ */
+
+#define POCR __REG(0x40500000) /* PCM Out Control Register */
+#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
+#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
+
+#define PICR __REG(0x40500004) /* PCM In Control Register */
+#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
+#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
+
+#define MCCR __REG(0x40500008) /* Mic In Control Register */
+#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
+#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
+
+#define GCR __REG(0x4050000C) /* Global Control Register */
+#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
+#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
+#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
+#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
+#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
+
+#define POSR __REG(0x40500010) /* PCM Out Status Register */
+#define POSR_FIFOE (1 << 4) /* FIFO error */
+#define POSR_FSR (1 << 2) /* FIFO Service Request */
+
+#define PISR __REG(0x40500014) /* PCM In Status Register */
+#define PISR_FIFOE (1 << 4) /* FIFO error */
+#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
+#define PISR_FSR (1 << 2) /* FIFO Service Request */
+
+#define MCSR __REG(0x40500018) /* Mic In Status Register */
+#define MCSR_FIFOE (1 << 4) /* FIFO error */
+#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
+#define MCSR_FSR (1 << 2) /* FIFO Service Request */
+
+#define GSR __REG(0x4050001C) /* Global Status Register */
+#define GSR_CDONE (1 << 19) /* Command Done */
+#define GSR_SDONE (1 << 18) /* Status Done */
+#define GSR_RDCS (1 << 15) /* Read Completion Status */
+#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
+#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
+#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
+#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
+#define GSR_PCR (1 << 8) /* Primary Codec Ready */
+#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
+#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
+#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
+#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
+#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
+#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
+#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
+
+#define CAR __REG(0x40500020) /* CODEC Access Register */
+#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
+
+#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
+#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
+
+#define MOCR __REG(0x40500100) /* Modem Out Control Register */
+#define MOCR_FEIE (1 << 3) /* FIFO Error */
+#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
+
+#define MICR __REG(0x40500108) /* Modem In Control Register */
+#define MICR_FEIE (1 << 3) /* FIFO Error */
+#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
+
+#define MOSR __REG(0x40500110) /* Modem Out Status Register */
+#define MOSR_FIFOE (1 << 4) /* FIFO error */
+#define MOSR_FSR (1 << 2) /* FIFO Service Request */
+
+#define MISR __REG(0x40500118) /* Modem In Status Register */
+#define MISR_FIFOE (1 << 4) /* FIFO error */
+#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
+#define MISR_FSR (1 << 2) /* FIFO Service Request */
+
+#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
+
+#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
+#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
+#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
+#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
+
+
+/*
+ * USB Device Controller
+ * PXA25x and PXA27x USB device controller registers are different.
+ */
+#if defined(CONFIG_PXA25x)
+
+#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
+#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
+#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
+
+#define UDCCR __REG(0x40600000) /* UDC Control Register */
+#define UDCCR_UDE (1 << 0) /* UDC enable */
+#define UDCCR_UDA (1 << 1) /* UDC active */
+#define UDCCR_RSM (1 << 2) /* Device resume */
+#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
+#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
+#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
+#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
+
+#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
+#define UDCCS0_IPR (1 << 1) /* IN packet ready */
+#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
+#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
+#define UDCCS0_SST (1 << 4) /* Sent stall */
+#define UDCCS0_FST (1 << 5) /* Force stall */
+#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
+#define UDCCS0_SA (1 << 7) /* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
+#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
+#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
+#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
+#define UDCCS_BI_SST (1 << 4) /* Sent stall */
+#define UDCCS_BI_FST (1 << 5) /* Force stall */
+#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
+#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
+#define UDCCS_BO_DME (1 << 3) /* DMA enable */
+#define UDCCS_BO_SST (1 << 4) /* Sent stall */
+#define UDCCS_BO_FST (1 << 5) /* Force stall */
+#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
+#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
+#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
+#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
+#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
+#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
+#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
+#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
+#define UDCCS_IO_DME (1 << 3) /* DMA enable */
+#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
+#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
+#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
+#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
+#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
+#define UDCCS_INT_SST (1 << 4) /* Sent stall */
+#define UDCCS_INT_FST (1 << 5) /* Force stall */
+#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
+
+#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
+#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
+#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
+#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
+#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
+#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
+#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
+#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
+#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
+#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
+#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
+#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
+#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
+#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
+#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
+#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
+#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
+#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
+#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
+#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
+#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
+#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
+#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
+#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
+
+#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
+#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
+#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
+#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
+#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
+#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
+#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
+#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
+
+#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
+#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
+#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
+#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
+#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
+#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
+#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
+#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
+
+#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
+#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
+#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
+#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
+#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
+#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
+#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
+#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
+
+#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
+#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
+#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
+#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
+#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
+#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
+#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
+#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
+
+#elif defined(CONFIG_PXA27x)
+
+#define UDCCR __REG(0x40600000) /* UDC Control Register */
+#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
+#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
+ Protocol Port Support */
+#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
+ Support */
+#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
+ Enable */
+#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
+#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
+#define UDCCR_ACN_S 11
+#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
+#define UDCCR_AIN_S 8
+#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
+ Setting Number */
+#define UDCCR_AAISN_S 5
+#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
+ Configuration */
+#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
+ Error */
+#define UDCCR_UDR (1 << 2) /* UDC Resume */
+#define UDCCR_UDA (1 << 1) /* UDC Active */
+#define UDCCR_UDE (1 << 0) /* UDC Enable */
+
+#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
+#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
+
+#define UDC_INT_FIFOERROR (0x2)
+#define UDC_INT_PACKETCMP (0x1)
+
+#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+/* Older defines, do not use. */
+#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
+#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
+#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
+#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
+#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
+/* New defines. */
+#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
+#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
+#define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
+#define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
+#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
+
+#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
+#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
+#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
+#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
+#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
+
+#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
+#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
+ Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
+ Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
+ Interrupt Enable */
+#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
+ Interrupt Enable */
+#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
+ Interrupt Enable */
+#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
+ Interrupt Enable */
+#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
+ Interrupt Enable */
+#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
+ Interrupt Enable */
+#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
+ Edge Interrupt Enable */
+#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
+ Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
+ Interrupt Enable */
+#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
+ Interrupt Enable */
+
+#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
+
+#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
+#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
+#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
+
+#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
+#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0_SA (1 << 7) /* Setup Active */
+#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
+#define UDCCSR0_FST (1 << 5) /* Force Stall */
+#define UDCCSR0_SST (1 << 4) /* Sent Stall */
+#define UDCCSR0_DME (1 << 3) /* DMA Enable */
+#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
+#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
+#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
+
+#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+
+#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
+#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
+#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
+#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST (1 << 5) /* Force STALL */
+#define UDCCSR_SST (1 << 4) /* Sent STALL */
+#define UDCCSR_DME (1 << 3) /* DMA Enable */
+#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
+#define UDCCSR_PC (1 << 1) /* Packet Complete */
+#define UDCCSR_FS (1 << 0) /* FIFO needs service */
+
+#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
+#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
+#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
+#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
+#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
+#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
+#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
+#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
+#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
+#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
+#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
+#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
+#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
+#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
+#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
+#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
+#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
+#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
+#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
+#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
+#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
+#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
+#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
+#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
+#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
+
+#define UDCDN(x) __REG2(0x40600300, (x)<<2)
+#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
+#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
+#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
+#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
+#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
+#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
+#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
+#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
+#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
+#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
+#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
+#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
+#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
+#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
+#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
+#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
+#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
+#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
+#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
+#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
+#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
+#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
+#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
+#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
+#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
+#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
+
+#define UDCCN(x) __REG2(0x40600400, (x)<<2)
+#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
+#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
+#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
+#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
+#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
+#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
+#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
+#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
+#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
+#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
+#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
+#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
+#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
+#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
+#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
+#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
+#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
+#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
+#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
+#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
+#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
+#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
+#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
+
+#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
+#define UDCCONR_CN_S (25)
+#define UDCCONR_IN (0x07 << 22) /* Interface Number */
+#define UDCCONR_IN_S (22)
+#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
+#define UDCCONR_AISN_S (19)
+#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
+#define UDCCONR_EN_S (15)
+#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
+#define UDCCONR_ET_S (13)
+#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
+#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
+#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
+#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
+#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
+#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
+#define UDCCONR_MPS_S (2)
+#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
+#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
+
+
+#define UDC_INT_FIFOERROR (0x2)
+#define UDC_INT_PACKETCMP (0x1)
+
+#define UDC_FNR_MASK (0x7ff)
+
+#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK (0x3ff)
+#endif
+
+/*
+ * Fast Infrared Communication Port
+ */
+
+#define FICP __REG(0x40800000) /* Start of FICP area */
+#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
+#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
+#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
+#define ICDR __REG(0x4080000c) /* ICP Data Register */
+#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
+#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
+
+#define ICCR0_AME (1 << 7) /* Adress match enable */
+#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
+#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
+#define ICCR0_RXE (1 << 4) /* Receive enable */
+#define ICCR0_TXE (1 << 3) /* Transmit enable */
+#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
+#define ICCR0_LBM (1 << 1) /* Loopback mode */
+#define ICCR0_ITR (1 << 0) /* IrDA transmission */
+
+#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
+#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
+#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
+#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
+#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
+#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
+
+#ifdef CONFIG_PXA27x
+#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
+#endif
+#define ICSR0_FRE (1 << 5) /* Framing error */
+#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
+#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
+#define ICSR0_RAB (1 << 2) /* Receiver abort */
+#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
+#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
+
+#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
+#define ICSR1_CRE (1 << 5) /* CRC error */
+#define ICSR1_EOF (1 << 4) /* End of frame */
+#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
+#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
+#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
+#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
+
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR __REG(0x40900000) /* RTC Count Register */
+#define RTAR __REG(0x40900004) /* RTC Alarm Register */
+#define RTSR __REG(0x40900008) /* RTC Status Register */
+#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
+#define RDCR __REG(0x40900010) /* RTC Day Counter Register */
+#define RYCR __REG(0x40900014) /* RTC Year Counter Register */
+#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
+
+#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
+#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
+#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
+#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
+#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
+#define RTSR_AL (1 << 0) /* RTC alarm detected */
+
+
+/*
+ * OS Timer & Match Registers
+ */
+
+#define OSMR0 __REG(0x40A00000) /* */
+#define OSMR1 __REG(0x40A00004) /* */
+#define OSMR2 __REG(0x40A00008) /* */
+#define OSMR3 __REG(0x40A0000C) /* */
+#define OSMR4 __REG(0x40A00080) /* */
+#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
+#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
+#define OMCR4 __REG(0x40A000C0) /* */
+#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
+#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
+#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
+
+#define OSSR_M3 (1 << 3) /* Match status channel 3 */
+#define OSSR_M2 (1 << 2) /* Match status channel 2 */
+#define OSSR_M1 (1 << 1) /* Match status channel 1 */
+#define OSSR_M0 (1 << 0) /* Match status channel 0 */
+
+#define OWER_WME (1 << 0) /* Watchdog Match Enable */
+
+#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
+#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
+#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
+#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
+
+
+/*
+ * Pulse Width Modulator
+ */
+
+#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
+#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
+
+#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
+#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
+
+#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
+#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
+
+#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
+#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
+
+
+/*
+ * Interrupt Controller
+ */
+
+#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
+#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
+#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
+#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
+#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
+#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
+
+
+/*
+ * General Purpose I/O
+ */
+
+#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
+
+#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
+
+#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
+
+#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+
+#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+
+#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
+#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
+
+#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+/* More handy macros. The argument is a literal GPIO number. */
+
+#define GPIO_bit(x) (1 << ((x) & 0x1f))
+
+#ifdef CONFIG_PXA27x
+
+/* Interrupt Controller */
+
+#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
+#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
+#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
+
+#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
+#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
+#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
+#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
+#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
+#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
+#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
+#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
+ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
+#else
+
+#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#endif
+
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST 1 /* reset */
+#define GPIO6_MMCCLK 6 /* MMC Clock */
+#define GPIO7_48MHz 7 /* 48 MHz clock output */
+#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
+#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
+#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
+#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
+#define GPIO12_32KHz 12 /* 32 kHz out */
+#define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */
+#define GPIO13_MBGNT 13 /* memory controller grant */
+#define GPIO14_MBREQ 14 /* alternate bus master request */
+#define GPIO15_nCS_1 15 /* chip select 1 */
+#define GPIO16_PWM0 16 /* PWM0 output */
+#define GPIO17_PWM1 17 /* PWM1 output */
+#define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */
+#define GPIO18_RDY 18 /* Ext. Bus Ready */
+#define GPIO19_DREQ1 19 /* External DMA Request */
+#define GPIO20_DREQ0 20 /* External DMA Request */
+#define GPIO23_SCLK 23 /* SSP clock */
+#define GPIO24_SFRM 24 /* SSP Frame */
+#define GPIO25_STXD 25 /* SSP transmit */
+#define GPIO26_SRXD 26 /* SSP receive */
+#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
+#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
+#define GPIO31_SYNC 31 /* AC97/I2S sync */
+#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
+#define GPIO32_SYSCLK 32 /* I2S System Clock */
+#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */
+#define GPIO33_nCS_5 33 /* chip select 5 */
+#define GPIO34_FFRXD 34 /* FFUART receive */
+#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
+#define GPIO35_FFCTS 35 /* FFUART Clear to send */
+#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
+#define GPIO37_FFDSR 37 /* FFUART data set ready */
+#define GPIO38_FFRI 38 /* FFUART Ring Indicator */
+#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
+#define GPIO39_FFTXD 39 /* FFUART transmit data */
+#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
+#define GPIO41_FFRTS 41 /* FFUART request to send */
+#define GPIO42_BTRXD 42 /* BTUART receive data */
+#define GPIO42_HWRXD 42 /* HWUART receive data */
+#define GPIO43_BTTXD 43 /* BTUART transmit data */
+#define GPIO43_HWTXD 43 /* HWUART transmit data */
+#define GPIO44_BTCTS 44 /* BTUART clear to send */
+#define GPIO44_HWCTS 44 /* HWUART clear to send */
+#define GPIO45_BTRTS 45 /* BTUART request to send */
+#define GPIO45_HWRTS 45 /* HWUART request to send */
+#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
+#define GPIO46_ICPRXD 46 /* ICP receive data */
+#define GPIO46_STRXD 46 /* STD_UART receive data */
+#define GPIO47_ICPTXD 47 /* ICP transmit data */
+#define GPIO47_STTXD 47 /* STD_UART transmit data */
+#define GPIO48_nPOE 48 /* Output Enable for Card Space */
+#define GPIO49_nPWE 49 /* Write Enable for Card Space */
+#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
+#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */
+#define GPIO51_nPIOW 51 /* I/O Write for Card Space */
+#define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */
+#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
+#define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */
+#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
+#define GPIO53_MMCCLK 53 /* MMC Clock */
+#define GPIO53_CIF_MCLK 53 /* Camera Master Clock */
+#define GPIO54_MMCCLK 54 /* MMC Clock */
+#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
+#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */
+#define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */
+#define GPIO55_nPREG 55 /* Card Address bit 26 */
+#define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */
+#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
+#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0 58 /* LCD data pin 0 */
+#define GPIO59_LDD_1 59 /* LCD data pin 1 */
+#define GPIO60_LDD_2 60 /* LCD data pin 2 */
+#define GPIO61_LDD_3 61 /* LCD data pin 3 */
+#define GPIO62_LDD_4 62 /* LCD data pin 4 */
+#define GPIO63_LDD_5 63 /* LCD data pin 5 */
+#define GPIO64_LDD_6 64 /* LCD data pin 6 */
+#define GPIO65_LDD_7 65 /* LCD data pin 7 */
+#define GPIO66_LDD_8 66 /* LCD data pin 8 */
+#define GPIO66_MBREQ 66 /* alternate bus master req */
+#define GPIO67_LDD_9 67 /* LCD data pin 9 */
+#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
+#define GPIO68_LDD_10 68 /* LCD data pin 10 */
+#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
+#define GPIO69_LDD_11 69 /* LCD data pin 11 */
+#define GPIO69_MMCCLK 69 /* MMC_CLK */
+#define GPIO70_LDD_12 70 /* LCD data pin 12 */
+#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13 71 /* LCD data pin 13 */
+#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14 72 /* LCD data pin 14 */
+#define GPIO72_32kHz 72 /* 32 kHz clock */
+#define GPIO73_LDD_15 73 /* LCD data pin 15 */
+#define GPIO73_MBGNT 73 /* Memory controller grant */
+#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
+#define GPIO75_LCD_LCLK 75 /* LCD line clock */
+#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
+#define GPIO78_nCS_2 78 /* chip select 2 */
+#define GPIO79_nCS_3 79 /* chip select 3 */
+#define GPIO80_nCS_4 80 /* chip select 4 */
+#define GPIO81_NSCLK 81 /* NSSP clock */
+#define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */
+#define GPIO82_NSFRM 82 /* NSSP Frame */
+#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */
+#define GPIO83_NSTXD 83 /* NSSP transmit */
+#define GPIO84_NSRXD 84 /* NSSP receive */
+#define GPIO84_CIF_FV 84 /* Camera frame start signal */
+#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
+#define GPIO85_CIF_LV 85 /* Camera line start signal */
+#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
+#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
+#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
+#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
+#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
+#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */
+#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */
+#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
+#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
+#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN 0x000
+#define GPIO_OUT 0x080
+#define GPIO_ALT_FN_1_IN 0x100
+#define GPIO_ALT_FN_1_OUT 0x180
+#define GPIO_ALT_FN_2_IN 0x200
+#define GPIO_ALT_FN_2_OUT 0x280
+#define GPIO_ALT_FN_3_IN 0x300
+#define GPIO_ALT_FN_3_OUT 0x380
+#define GPIO_MD_MASK_NR 0x07f
+#define GPIO_MD_MASK_DIR 0x080
+#define GPIO_MD_MASK_FN 0x300
+#define GPIO_DFLT_LOW 0x400
+#define GPIO_DFLT_HIGH 0x800
+#define GPIO_ACTIVE_LOW 0x1000
+#define GPIO_MD_MASK_SET 0x2000
+#define GPIO_MD_HIGH 0x2000
+
+#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN)
+#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN)
+#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
+#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
+#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
+#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT)
+#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
+#define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT)
+#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT)
+#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
+#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
+#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
+#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
+#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
+#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
+#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN)
+#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
+#define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN)
+#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN)
+#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT | GPIO_DFLT_HIGH)
+#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT)
+#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT | GPIO_DFLT_HIGH)
+#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT)
+#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN)
+#define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN)
+#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT)
+#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN)
+#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN)
+#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
+#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
+#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
+#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
+#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN)
+#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
+#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
+#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT | GPIO_DFLT_HIGH)
+#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
+#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
+#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
+#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
+#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
+#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
+#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN)
+#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT)
+#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT)
+#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT)
+#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT)
+#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT)
+#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT)
+#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
+#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN)
+#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN)
+
+/*
+ * Power Manager
+ */
+
+#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
+#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
+#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
+#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
+#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
+#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
+
+#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
+#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
+#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
+#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
+#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
+#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
+#define PCMD(x) __REG2(0x40F00080, (x)<<2)
+#define PCMD0 __REG(0x40F00080 + 0 * 4)
+#define PCMD1 __REG(0x40F00080 + 1 * 4)
+#define PCMD2 __REG(0x40F00080 + 2 * 4)
+#define PCMD3 __REG(0x40F00080 + 3 * 4)
+#define PCMD4 __REG(0x40F00080 + 4 * 4)
+#define PCMD5 __REG(0x40F00080 + 5 * 4)
+#define PCMD6 __REG(0x40F00080 + 6 * 4)
+#define PCMD7 __REG(0x40F00080 + 7 * 4)
+#define PCMD8 __REG(0x40F00080 + 8 * 4)
+#define PCMD9 __REG(0x40F00080 + 9 * 4)
+#define PCMD10 __REG(0x40F00080 + 10 * 4)
+#define PCMD11 __REG(0x40F00080 + 11 * 4)
+#define PCMD12 __REG(0x40F00080 + 12 * 4)
+#define PCMD13 __REG(0x40F00080 + 13 * 4)
+#define PCMD14 __REG(0x40F00080 + 14 * 4)
+#define PCMD15 __REG(0x40F00080 + 15 * 4)
+#define PCMD16 __REG(0x40F00080 + 16 * 4)
+#define PCMD17 __REG(0x40F00080 + 17 * 4)
+#define PCMD18 __REG(0x40F00080 + 18 * 4)
+#define PCMD19 __REG(0x40F00080 + 19 * 4)
+#define PCMD20 __REG(0x40F00080 + 20 * 4)
+#define PCMD21 __REG(0x40F00080 + 21 * 4)
+#define PCMD22 __REG(0x40F00080 + 22 * 4)
+#define PCMD23 __REG(0x40F00080 + 23 * 4)
+#define PCMD24 __REG(0x40F00080 + 24 * 4)
+#define PCMD25 __REG(0x40F00080 + 25 * 4)
+#define PCMD26 __REG(0x40F00080 + 26 * 4)
+#define PCMD27 __REG(0x40F00080 + 27 * 4)
+#define PCMD28 __REG(0x40F00080 + 28 * 4)
+#define PCMD29 __REG(0x40F00080 + 29 * 4)
+#define PCMD30 __REG(0x40F00080 + 30 * 4)
+#define PCMD31 __REG(0x40F00080 + 31 * 4)
+
+#define PCMD_MBC (1<<12)
+#define PCMD_DCE (1<<11)
+#define PCMD_LC (1<<10)
+/* FIXME: PCMD_SQC need be checked. */
+#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
+ bit 9 should be 0 all day. */
+#define PVCR_VCSA (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PCFR_PI2C_EN (0x1 << 6)
+
+#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
+#define PSSR_RDH (1 << 5) /* Read Disable Hold */
+#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
+#define PSSR_STS (1 << 3) /* Standby Mode Status */
+#define PSSR_VFS (1 << 2) /* VDD Fault Status */
+#define PSSR_BFS (1 << 1) /* Battery Fault Status */
+#define PSSR_SSS (1 << 0) /* Software Sleep Status */
+
+#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+
+#define PCFR_RO (1 << 15) /* RDH Override */
+#define PCFR_PO (1 << 14) /* PH Override */
+#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
+#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
+#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
+#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
+#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
+#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
+#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
+#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
+#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
+#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR (1 << 3) /* GPIO Reset */
+#define RCSR_SMR (1 << 2) /* Sleep Mode */
+#define RCSR_WDR (1 << 1) /* Watchdog Reset */
+#define RCSR_HWR (1 << 0) /* Hardware Reset */
+
+#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
+#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
+#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
+#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
+#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
+#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
+#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
+#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
+#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
+#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
+#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
+#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
+#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
+#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
+#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
+#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
+#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
+#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
+#define PWER_WEP1 0x40000000 /* RTC alarm wake-up enable */
+
+
+/*
+ * SSP Serial Port Registers
+ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
+ * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ */
+
+ /* Common PXA2xx bits first */
+#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
+#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
+#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
+#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
+#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
+#define SSCR0_National (0x2 << 4) /* National Microwire */
+#define SSCR0_ECS (1 << 6) /* External clock select */
+#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
+#if defined(CONFIG_PXA25x) && !defined(CONFIG_PXA26x)
+#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA26x)
+#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#define SSCR0_EDSS (1 << 20) /* Extended data size select */
+#define SSCR0_NCS (1 << 21) /* Network clock select */
+#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
+#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
+#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
+#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
+#define SSCR0_ADC (1 << 30) /* Audio clock select */
+#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
+#endif
+
+#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
+#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
+#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
+#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+
+#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
+#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
+#define SSSR_BSY (1 << 4) /* SSP Busy */
+#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
+#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
+#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
+
+#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
+#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
+#define SSCR0_NCS (1 << 21) /* Network Clock Select */
+#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
+
+/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
+#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
+#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
+#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
+#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
+#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
+#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
+#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
+#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
+#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
+#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
+#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
+#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
+#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
+#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
+#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
+#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
+#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
+
+#define SSSR_BCE (1 << 23) /* Bit Count Error */
+#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
+#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
+#define SSSR_EOC (1 << 20) /* End Of Chain */
+#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
+#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
+
+#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
+#define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */
+#define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */
+#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
+#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
+#define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */
+
+#define SSACD_ACDS(x) (x) /* Audio Clock Divider Select */
+#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass (SSCR0_ADC must be set) */
+#define SSACD_ACPS(x) ((x) << 4) /* Audio Clock PLL Select */
+
+#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
+#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
+#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
+#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
+#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
+
+/* Support existing PXA25x drivers */
+#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
+#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
+#define SSSR SSSR_P1 /* SSP Status Register */
+#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
+#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+
+/* PXA27x ports */
+#if defined (CONFIG_PXA27x)
+#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
+#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
+#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
+#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
+#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
+#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
+#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
+#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
+#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
+#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
+#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
+#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
+#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
+#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
+#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
+#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
+#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
+#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
+#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
+#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
+#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
+#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
+#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
+#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
+#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
+#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
+#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
+#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
+#else /* PXA255 (only port 2) and PXA26x ports*/
+#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
+#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
+#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
+#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
+#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
+#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
+#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
+#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
+#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
+#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
+#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
+#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
+#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
+#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
+#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
+#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
+#endif
+
+#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
+#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
+#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
+#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
+#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
+#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
+#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
+#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
+#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
+#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
+#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
+
+/*
+ * MultiMediaCard (MMC) controller
+ */
+
+#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
+#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
+#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
+#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
+#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
+#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
+#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
+#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
+#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
+#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
+#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
+#define MMC_CMD __REG(0x41100030) /* Index of current command */
+#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
+#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
+#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
+#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
+#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
+
+#define MMC_STRPCL_STRT_CLK (1 << 1) /* Start the MMC clock */
+#define MMC_STRPCL_STOP_CLK (1 << 0) /* Stop the MMC clock */
+
+#define MMC_STAT_SDIO_SUSPEND_ACK (1 << 16) /* SDIO data transfer has been
+ suspended by SDIO card */
+#define MMC_STAT_SDIO_INT (1 << 15) /* SDIO Interrupt occured */
+#define MMC_STAT_RD_STALLED (1 << 14) /* Read transfer stalled */
+#define MMC_STAT_END_CMD_RES (1 << 13) /* Command and response
+ sequence has completed */
+#define MMC_STAT_PRG_DONE (1 << 12) /* Card has finished programming
+ and is not busy */
+#define MMC_STAT_DATA_TRAN_DONE (1 << 11) /* Data transmission to card
+ has been completed */
+#define MMC_STAT_SPI_WR_ERR (1 << 10) /* Write data rejected by card
+ due to a Write Error */
+#define MMC_STAT_FLASH_ERR (1 << 9) /* Flash programming error
+ occurred */
+#define MMC_STAT_CLK_EN (1 << 8) /* MMC/SDIO clock is on */
+#define MMC_STAT_RES_CRC_ERR (1 << 5) /* Response CRC error */
+#define MMC_STAT_DAT_ERR_TOKEN (1 << 4) /* SPI data error token recv*/
+#define MMC_STAT_CRC_RD_ERR (1 << 3) /* CRC error on receive */
+#define MMC_STAT_CRC_WR_ERR (1 << 2) /* Write data rejected due to
+ CRC error */
+#define MMC_STAT_TIME_OUT_RES (1 << 1) /* Card response timed out */
+#define MMC_STAT_TIME_OUT_READ (1 << 0) /* Card read data timed out*/
+#define MMC_STAT_ALL (0x1ffff)
+
+#define MMC_CLKRT_FREQ (7 << 0) /* Clock Frequency: */
+#define MMC_CLKRT_FREQ_19_5MHZ (0 << 0) /* 19.5 MHz */
+#define MMC_CLKRT_FREQ_9_75MHZ (1 << 0) /* 9.75 MHz */
+#define MMC_CLKRT_FREQ_4_88MHZ (2 << 0) /* 4.88 MHz */
+#define MMC_CLKRT_FREQ_2_44MHZ (3 << 0) /* 2.44 MHz */
+#define MMC_CLKRT_FREQ_1_22MHZ (4 << 0) /* 1.22 MHz */
+#define MMC_CLKRT_FREQ_609KHZ (5 << 0) /* 609 KHz */
+#define MMC_CLKRT_FREQ_304KHZ (6 << 0) /* 304 KHz */
+
+#define MMC_SPI_CS_ADDRESS (1 << 3) /* Enable CS1 or CS0 */
+#define MMC_SPI_CS_EN (1 << 2) /* Enable SPI Chip Select */
+#define MMC_SPI_CRC_EN (1 << 1) /* Enable CRC generation and
+ verification */
+#define MMC_SPI_MODE (1 << 0) /* Enable SPI mode */
+
+#define MMC_CMDAT_SDIO_RESUME (1 << 13) /* SDIO CMD52, resume a
+ suspended data transfer */
+#define MMC_CMDAT_SDIO_SUSPEND (1 << 12) /* SDIO CMD52, suspend current
+ data transfer */
+#define MMC_CMDAT_SDIO_INT_EN (1 << 11) /* Enable check for SDIO
+ interrupt from card */
+#define MMC_CMDAT_STOP_TRAN (1 << 10) /* Stop data transmission */
+#define MMC_CMDAT_SD_4DAT (1 << 8) /* Enable 4-bit data transfer*/
+
+
+#define MMC_CMDAT_DMA_EN (1 << 7) /* Enable DMA access to FIFO */
+#define MMC_CMDAT_INIT (1 << 6) /* Precede command sequence
+ with 80 clocks, for
+ initialisation */
+#define MMC_CMDAT_BUSY (1 << 5) /* Specifies whether a busy
+ signal possible after the
+ current command */
+#define MMC_CMDAT_STRM_BLK (1 << 4) /* Data transfer is in
+ stream mode */
+#define MMC_CMDAT_WR (1 << 3) /* Data transfer is a write
+ operation */
+#define MMC_CMDAT_RD (0 << 3) /* Data transfer is a read
+ operation */
+#define MMC_CMDAT_DATA_EN (1 << 2) /* Current command includes
+ a data transfer */
+#define MMC_CMDAT_RES_TYPE (3 << 0) /* Command reponse format */
+#define MMC_CMDAT_RES_NORESP (0 << 0) /* No response */
+#define MMC_CMDAT_RES_RESP (1 << 0) /* Response with CRC */
+#define MMC_CMDAT_RES_R2 (2 << 0) /* CID/CSD response */
+#define MMC_CMDAT_RES_R3 (3 << 0) /* R3 response */
+
+#define MMC_RESTO_MASK (0x0000007f)
+#define MMC_RDTO_MASK (0x0000ffff)
+#define MMC_BLKLEN_MASK (0x00000fff)
+#define MMC_BLKLEN_MASK (0x00000fff)
+#define MMC_NOB_MASK (0x0000ffff)
+#define MMC_PRTBUF_PRT_FULL (1 << 0) /* Buffer is partially full */
+
+#define MMC_I_SDIO_SUSPEND_ACK (1 << 12) /* SDIO data transfer has been
+ suspended by SDIO card */
+#define MMC_I_SDIO_INT (1 << 11) /* An SDIO interrupt occured*/
+#define MMC_I_RD_STALLED (1 << 10) /* Card has stalled read */
+#define MMC_I_RES_ERR (1 << 9) /* Error occured on the resp */
+#define MMC_I_DAT_ERR (1 << 8) /* Data error occurred during
+ data transmission */
+#define MMC_I_TINT (1 << 7) /* Transmit Interrupt */
+#define MMC_I_TXFIFO_WR_REQ (1 << 6) /* Tx FIFO Write Request */
+#define MMC_I_TXFIFO_RD_REQ (1 << 5) /* Rx FIFO Read Request */
+#define MMC_I_CLK_IS_OFF (1 << 4) /* Clock is Off */
+#define MMC_I_STOP_CMD (1 << 3) /* MMC is ready for the stop
+ transmission command */
+#define MMC_I_END_CMD_RES (1 << 2) /* End Command Response */
+#define MMC_I_PRG_DONE (1 << 1) /* Programming Done */
+#define MMC_I_DATA_TRAN_DONE (1 << 0) /* Data Transfer Done */
+
+#if 0
+#error This conflicts with <linux/mmc/mmc.h>. Consider using PXA-specific prefixes.
+#define MMC_CMD_MASK (0x0000003f)
+#define MMC_ARGH_MASK (0x0000ffff)
+#define MMC_ARGL_MASK (0x0000ffff)
+#endif
+
+#define MMC_RDWAIT_START (1 << 1) /* Restart the read data tran*/
+#define MMC_RDWAIT_EN (1 << 0) /* RD_WAIT enable */
+
+
+/*
+ * Core Clock
+ */
+
+#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
+#define CKEN __REG(0x41300004) /* Clock Enable Register */
+#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
+#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
+
+#define CCCR_N_MASK 0x0780 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
+#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
+#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
+#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
+#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
+#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
+#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
+#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
+#define CKEN10_ASSP (1 << 10) /* ASSP (SSP3) Clock Enable */
+#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
+#define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
+#define CKEN9_NSSP (1 << 9) /* NSSP (SSP2) Clock Enable */
+#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
+#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
+#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
+#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
+#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
+#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
+#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
+#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
+#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
+#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
+#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
+
+#define OSCC_TOUT_EN (1 << 2) /* 32.768kHz Output enable */
+#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
+
+
+/*
+ * LCD
+ */
+
+#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
+#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
+#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
+#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
+#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
+#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
+#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
+#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
+#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
+#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
+#define TMEDCR __REG(0x44000044) /* TMED Control Register */
+
+#define LCCR3_1BPP (0 << 24)
+#define LCCR3_2BPP (1 << 24)
+#define LCCR3_4BPP (2 << 24)
+#define LCCR3_8BPP (3 << 24)
+#define LCCR3_16BPP (4 << 24)
+#define LCCR3_18BPP (6 << 24)
+#define LCCR3_19BPP (8 << 24)
+#define LCCR3_24BPP (9 << 24)
+#define LCCR3_25BPP (10<< 24)
+
+#ifdef CONFIG_PXA27x
+#define LCCR3_18BPP (6 << 24)
+#define LCCR3_19BPP (8 << 24)
+#define LCCR3_24BPP (9 << 24)
+#define LCCR3_25BPP (10<< 24)
+#endif
+
+#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
+#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
+#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
+#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
+
+#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
+#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
+#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
+#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
+#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
+ /* Select */
+#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
+#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
+
+#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
+#define LCCR0_SFM (1 << 4) /* Start of frame mask */
+#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
+#define LCCR0_EFM (1 << 6) /* End of Frame mask */
+#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
+#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
+#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
+#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
+ /* display mode) */
+#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
+ /* display */
+#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
+ /* display */
+#define LCCR0_DIS (1 << 10) /* LCD Disable */
+#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
+#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
+#define LCCR0_PDD_S 12
+#define LCCR0_BM (1 << 20) /* Branch mask */
+#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
+#define LCCR0_LCDT (1 << 22) /* LCD panel type */
+#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
+#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
+#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
+#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
+
+#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
+ (((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
+#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
+ /* pulse Width [1..64 Tpix] */ \
+ (((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
+ /* count - 1 [Tpix] */
+#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
+ /* [1..256 Tpix] */ \
+ (((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
+ /* Wait count - 1 [Tpix] */
+#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
+ /* [1..256 Tpix] */ \
+ (((Tpix) - 1) << FShft (LCCR1_BLW))
+
+
+#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
+#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
+ (((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
+ /* Width - 1 [Tln] (L_FCLK) */
+#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
+ /* Width [1..64 Tln] */ \
+ (((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
+ /* count [Tln] */
+#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
+ /* [0..255 Tln] */ \
+ ((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
+ /* Wait count [Tln] */
+#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
+ /* [0..255 Tln] */ \
+ ((Tln) << FShft (LCCR2_BFW))
+
+#if 0
+#define LCCR3_PCD (0xff) /* Pixel clock divisor */
+#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
+#define LCCR3_ACB_S 8
+#endif
+
+#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
+#define LCCR3_API_S 16
+#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
+#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
+#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
+#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
+#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
+
+#define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
+ /* active display mode) */
+#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
+#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
+
+#if 0
+#define LCCR3_BPP (7 << 24) /* bits per pixel */
+#define LCCR3_BPP_S 24
+#endif
+#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
+
+
+#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
+ (((Div) << FShft (LCCR3_PCD)))
+
+
+#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
+ (((Bpp) << FShft (LCCR3_BPP)))
+
+#define LCCR3_ACB Fld (8, 8) /* AC Bias */
+#define LCCR3_Acb(Acb) /* BAC Bias */ \
+ (((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
+ /* pulse active High */
+#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
+
+#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
+ /* active High */
+#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
+ /* active Low */
+
+#define LCSR_LDD (1 << 0) /* LCD Disable Done */
+#define LCSR_SOF (1 << 1) /* Start of frame */
+#define LCSR_BER (1 << 2) /* Bus error */
+#define LCSR_ABC (1 << 3) /* AC Bias count */
+#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
+#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
+#define LCSR_OU (1 << 6) /* output FIFO underrun */
+#define LCSR_QD (1 << 7) /* quick disable */
+#define LCSR_EOF (1 << 8) /* end of frame */
+#define LCSR_BS (1 << 9) /* branch status */
+#define LCSR_SINT (1 << 10) /* subsequent interrupt */
+
+#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
+
+#define LCSR_LDD (1 << 0) /* LCD Disable Done */
+#define LCSR_SOF (1 << 1) /* Start of frame */
+#define LCSR_BER (1 << 2) /* Bus error */
+#define LCSR_ABC (1 << 3) /* AC Bias count */
+#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
+#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
+#define LCSR_OU (1 << 6) /* output FIFO underrun */
+#define LCSR_QD (1 << 7) /* quick disable */
+#define LCSR_EOF (1 << 8) /* end of frame */
+#define LCSR_BS (1 << 9) /* branch status */
+#define LCSR_SINT (1 << 10) /* subsequent interrupt */
+
+#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
+
+#ifdef CONFIG_PXA27x
+/* Overlay1 & Overlay2 & Hardware Cursor */
+#define LCSR1_SOF1 (1 << 0)
+#define LCSR1_SOF2 (1 << 1)
+#define LCSR1_SOF3 (1 << 2)
+#define LCSR1_SOF4 (1 << 3)
+#define LCSR1_SOF5 (1 << 4)
+#define LCSR1_SOF6 (1 << 5)
+
+#define LCSR1_EOF1 (1 << 8)
+#define LCSR1_EOF2 (1 << 9)
+#define LCSR1_EOF3 (1 << 10)
+#define LCSR1_EOF4 (1 << 11)
+#define LCSR1_EOF5 (1 << 12)
+#define LCSR1_EOF6 (1 << 13)
+
+#define LCSR1_BS1 (1 << 16)
+#define LCSR1_BS2 (1 << 17)
+#define LCSR1_BS3 (1 << 18)
+#define LCSR1_BS4 (1 << 19)
+#define LCSR1_BS5 (1 << 20)
+#define LCSR1_BS6 (1 << 21)
+
+#define LCSR1_IU2 (1 << 25)
+#define LCSR1_IU3 (1 << 26)
+#define LCSR1_IU4 (1 << 27)
+#define LCSR1_IU5 (1 << 28)
+#define LCSR1_IU6 (1 << 29)
+
+#define LDCMD_SOFINT (1 << 22)
+#define LDCMD_EOFINT (1 << 21)
+
+#define LCCR4_13M_PCD_EN (1<<25) /* 13M PCD enable */
+#define LCCR4_PCDDIV (1<<31) /* PCD selection */
+
+#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
+
+#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
+#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
+#define CCR_CEN (1<<31) /* Enable bit for Cursor */
+
+/* LCD registers */
+#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
+#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
+#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
+#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
+#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
+#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
+#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
+#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
+#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
+#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
+#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
+#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
+#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
+#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
+#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
+
+#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
+#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
+#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
+#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
+#define CCR __REG(0x44000090) /* Cursor Control Register */
+
+#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
+#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
+#endif
+
+/* Overlay1 & Overlay2 & Hardware Cursor */
+#define LCSR1_SOF1 (1 << 0)
+#define LCSR1_SOF2 (1 << 1)
+#define LCSR1_SOF3 (1 << 2)
+#define LCSR1_SOF4 (1 << 3)
+#define LCSR1_SOF5 (1 << 4)
+#define LCSR1_SOF6 (1 << 5)
+
+#define LCSR1_EOF1 (1 << 8)
+#define LCSR1_EOF2 (1 << 9)
+#define LCSR1_EOF3 (1 << 10)
+#define LCSR1_EOF4 (1 << 11)
+#define LCSR1_EOF5 (1 << 12)
+#define LCSR1_EOF6 (1 << 13)
+
+#define LCSR1_BS1 (1 << 16)
+#define LCSR1_BS2 (1 << 17)
+#define LCSR1_BS3 (1 << 18)
+#define LCSR1_BS4 (1 << 19)
+#define LCSR1_BS5 (1 << 20)
+#define LCSR1_BS6 (1 << 21)
+
+#define LCSR1_IU2 (1 << 25)
+#define LCSR1_IU3 (1 << 26)
+#define LCSR1_IU4 (1 << 27)
+#define LCSR1_IU5 (1 << 28)
+#define LCSR1_IU6 (1 << 29)
+
+#define LDCMD_SOFINT (1 << 22)
+#define LDCMD_EOFINT (1 << 21)
+
+
+#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
+
+#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
+#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
+#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
+#define CCR_CEN (1<<31) /* Enable bit for Cursor */
+
+/* LCD registers */
+#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
+#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
+#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
+#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
+#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
+#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
+#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
+#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
+#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
+#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
+#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
+#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
+#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
+#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
+#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
+
+#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
+#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
+#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
+#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
+#define CCR __REG(0x44000090) /* Cursor Control Register */
+
+#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
+#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
+
+/*
+ * Memory controller
+ */
+
+#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
+#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
+#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
+#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
+#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
+#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
+#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
+#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+/* memory strength */
+#define BSCNTR0 __REG(0x4800004C)
+#define BSCNTR1 __REG(0x48000050)
+#define LCDBSCNTR __REG(0x48000054)
+#define MDMRSLP __REG(0x48000058) /* Low-power mode */
+#define BSCNTR2 __REG(0x4800005C)
+#define BSCNTR3 __REG(0x48000060)
+
+#define MDMPEN0 (1<<15)
+#define MDMPEN2 (1<<31)
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDCNFG_DE0 (1 << 0) /* SDRAM enable for partition 0 */
+#define MDCNFG_DE1 (1 << 1) /* SDRAM enable for partition 1 */
+#define MDCNFG_DWID0 (1 << 2) /* SDRAM data bus width for partition pair 0/1 */
+#define MDCNFG_DCAC0 (1 << 3) /* Number of Column Address bits for partition pair 0/1 */
+#define MDCNFG_DRAC0 (1 << 5) /* SDRAM row address bit count for partition pair 0/1 */
+#define MDCNFG_DNB0 (1 << 7) /* Number of banks in lower partition pair */
+#define MDCNFG_DTC0 (1 << 8) /* Timing Category for SDRAM pair 0/1 */
+#define MDCNFG_DADDR0 (1 << 10) /* Use alternate addressing for pair 0/1 */
+#define MDCNFG_DLATCH0 (1 << 11) /* Return data from SDRAM latching scheme for pair 0/1 */
+#define MDCNFG_DSA11110 (1 << 12) /* Use SA1111 Addressing Muxing Mode for pair 0/1 */
+#define MDCNFG_DE2 (1 << 16) /* SDRAM enable for partition 2 */
+#define MDCNFG_DE3 (1 << 17) /* SDRAM enable for partition 3 */
+#define MDCNFG_DWID2 (1 << 18) /* SDRAM data bus width for partition pair 2/3 */
+#define MDCNFG_DCAC2 (1 << 19) /* Number of Column Address bits for partition pair 2/3 */
+#define MDCNFG_DRAC2 (1 << 21) /* SDRAM row address bit count for partition pair 2/3 */
+#define MDCNFG_DNB2 (1 << 23) /* Number of banks in upper partition pair */
+#define MDCNFG_DTC2 (1 << 24) /* Timing Category for SDRAM pair 2/3 */
+#define MDCNFG_DADDR2 (1 << 26) /* Use alternate addressing for pair 2/3 */
+#define MDCNFG_DLATCH2 (1 << 27) /* Return data from SDRAM latching scheme for pair 2/3 */
+#define MDCNFG_DSA11112 (1 << 28) /* Use SA1111 Addressing Muxing Mode for pair 2/3 */
+
+#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
+
+
+#ifdef CONFIG_PXA27x
+
+#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
+#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
+#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
+#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
+#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
+
+/*
+ * Keypad
+ */
+#define KPC __REG(0x41500000) /* Keypad Interface Control register */
+#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
+#define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
+#define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */
+#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
+#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+
+#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
+#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
+#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
+#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
+#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
+#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
+#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
+#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
+#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
+#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
+#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
+#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
+#define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
+#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
+#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */
+#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
+#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */
+#define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */
+#define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */
+#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
+#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP (0x1 << 31)
+#define KPDK_DK7 (0x1 << 7)
+#define KPDK_DK6 (0x1 << 6)
+#define KPDK_DK5 (0x1 << 5)
+#define KPDK_DK4 (0x1 << 4)
+#define KPDK_DK3 (0x1 << 3)
+#define KPDK_DK2 (0x1 << 2)
+#define KPDK_DK1 (0x1 << 1)
+#define KPDK_DK0 (0x1 << 0)
+
+#define KPREC_OF1 (0x1 << 31)
+#define kPREC_UF1 (0x1 << 30)
+#define KPREC_OF0 (0x1 << 15)
+#define KPREC_UF0 (0x1 << 14)
+
+#define KPMK_MKP (0x1 << 31)
+#define KPAS_SO (0x1 << 31)
+#define KPASMKPx_SO (0x1 << 31)
+
+/*
+ * UHC: USB Host Controller (OHCI-like) register definitions
+ */
+#define UHC_BASE_PHYS (0x4C000000)
+#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
+#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
+#define UHCHCON_RWE (0x1 << 10) /* Remote Wakeup Enable */
+#define UHCHCON_RWC (0x1 << 9) /* Remote Wakeup Connected */
+#define UHCHCON_IR (0x1 << 8) /* Remote Interrupt Routing */
+/* Host Controller Functional State */
+#define UHCHCON_HCFS_USBRESET (0x0)
+#define UHCHCON_HCFS_USBRESUME (0x1 << 6)
+#define UHCHCON_HCFS_USBOPERATIONAL (0x2 << 6)
+#define UHCHCON_HCFS_USBSUSPEND (0x3 << 6)
+//
+#define UHCHCON_BLE (0x1 << 5) /* Bulk List Enable */
+#define UHCHCON_CLE (0x1 << 4) /* Control List Enable */
+#define UHCHCON_IE (0x1 << 3) /* Isochronous Enable */
+#define UHCHCON_PLE (0x1 << 2) /* Periodic List Enable */
+/* Control Bulk Service Ratio */
+#define UHCHCON_CBSR11 (0x0 << 0)
+#define UHCHCON_CBSR21 (0x1 << 0)
+#define UHCHCON_CBSR31 (0x2 << 0)
+#define UHCHCON_CBSR41 (0x3 << 0)
+//
+#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
+#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
+#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
+#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
+#define UHCINT_MIE (0x1 << 31)
+#define UHCINT_OC (0x1 << 30)
+#define UHCINT_RHSC (0x1 << 6)
+#define UHCINT_FNO (0x1 << 5)
+#define UHCINT_UE (0x1 << 4)
+#define UHCINT_RD (0x1 << 3)
+#define UHCINT_SF (0x1 << 2)
+#define UHCINT_WDH (0x1 << 1)
+#define UHCINT_SO (0x1 << 0)
+//
+
+#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
+#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
+#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
+#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
+#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
+#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
+#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
+#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
+#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
+#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
+#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
+#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
+
+#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
+
+#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
+#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
+#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
+#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
+#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
+
+#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
+#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
+#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
+#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
+#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
+#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
+#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
+#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
+#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
+#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
+
+#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
+#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
+#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
+#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
+#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
+#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
+#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
+#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
+#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
+#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
+#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
+#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
+
+#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
+#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
+#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
+#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
+#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
+#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
+ Interrupt Enable*/
+#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
+#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
+
+#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
+
+/* Camera Interface */
+
+#define CI_REG_SIZE 0x40 /* 0x5000_0000 --- 0x5000_0038 * 64K */
+#define CI_REGS_PHYS 0x50000000 /* Start phyical address of CI registers */
+
+#define CICR0 __REG(0x50000000)
+#define CICR1 __REG(0x50000004)
+#define CICR2 __REG(0x50000008)
+#define CICR3 __REG(0x5000000C)
+#define CICR4 __REG(0x50000010)
+#define CISR __REG(0x50000014)
+#define CIFR __REG(0x50000018)
+#define CITOR __REG(0x5000001C)
+#define CIBR0 __REG(0x50000028)
+#define CIBR1 __REG(0x50000030)
+#define CIBR2 __REG(0x50000038)
+
+#define CICR0_DMAEN (1 << 31) /* DMA request enable */
+#define CICR0_PAR_EN (1 << 30) /* Parity enable */
+#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
+#define CICR0_ENB (1 << 28) /* Camera interface enable */
+#define CICR0_DIS (1 << 27) /* Camera interface disable */
+#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
+#define CICR0_TOM (1 << 9) /* Time-out mask */
+#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
+#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
+#define CICR0_EOLM (1 << 6) /* End-of-line mask */
+#define CICR0_PERRM (1 << 5) /* Parity-error mask */
+#define CICR0_QDM (1 << 4) /* Quick-disable mask */
+#define CICR0_CDM (1 << 3) /* Disable-done mask */
+#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
+#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
+#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
+
+#define CICR1_TBIT (1 << 31) /* Transparency bit */
+#define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */
+#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
+#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
+#define CICR1_RGB_F (1 << 11) /* RGB format */
+#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
+#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
+#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
+#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
+#define CICR1_DW (0x7 << 0) /* Data width mask */
+
+#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
+ wait count mask */
+#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
+ wait count mask */
+#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
+#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
+ wait count mask */
+#define CICR2_FSW (0x7 << 0) /* Frame stabilization
+ wait count mask */
+
+#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
+ wait count mask */
+#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
+ wait count mask */
+#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
+#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
+ wait count mask */
+#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
+
+#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
+#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
+#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
+#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
+#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
+#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
+#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
+#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
+
+#define CISR_FTO (1 << 15) /* FIFO time-out */
+#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
+#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
+#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
+#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
+#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
+#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
+#define CISR_EOL (1 << 8) /* End of line */
+#define CISR_PAR_ERR (1 << 7) /* Parity error */
+#define CISR_CQD (1 << 6) /* Camera interface quick disable */
+#define CISR_CDD (1 << 5) /* Camera interface disable done */
+#define CISR_SOF (1 << 4) /* Start of frame */
+#define CISR_EOF (1 << 3) /* End of frame */
+#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
+#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
+#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
+
+#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
+#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
+#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
+#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
+#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
+#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
+#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
+#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
+
+#define SRAM_SIZE 0x40000 /* 4x64K */
+
+#define SRAM_MEM_PHYS 0x5C000000
+
+#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
+#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
+
+#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
+#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
+#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
+#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
+
+#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
+#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
+#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
+#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
+
+#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
+#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
+#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
+#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
+
+#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
+#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
+#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
+#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
+
+#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
+#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
+#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
+#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
+
+#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
+
+#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
+#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
+#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
+
+#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
+#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
+#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
+
+#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
+#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
+#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
+
+#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
+#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
+#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
+
+#endif
+
+/* PWRMODE register M field values */
+
+#define PWRMODE_IDLE 0x1
+#define PWRMODE_STANDBY 0x2
+#define PWRMODE_SLEEP 0x3
+#define PWRMODE_DEEPSLEEP 0x7
+
+#endif
diff --git a/sound/soc/pxa/Kconfig b/sound/soc/pxa/Kconfig
index f82e106..e307bee 100644
--- a/sound/soc/pxa/Kconfig
+++ b/sound/soc/pxa/Kconfig
@@ -42,6 +42,16 @@ config SND_PXA2XX_SOC_SPITZ
Say Y if you want to add support for SoC audio on Sharp
Zaurus SL-Cxx00 models (Spitz, Borzoi and Akita).
+config SND_PXA2XX_SOC_X50
+ tristate "SoC Audio support for Dell Axim x50/51v"
+ depends on SND_PXA2XX_SOC && MACH_X50
+ select SND_PXA2XX_SOC_I2S
+ select SND_SOC_WM8750
+ help
+ Say Y if you want to add support for SoC audio on Dell
+ Axim x50/51(v) models.
+
+
config SND_PXA2XX_SOC_POODLE
tristate "SoC Audio support for Poodle"
depends on SND_PXA2XX_SOC && MACH_POODLE
diff --git a/sound/soc/pxa/Makefile b/sound/soc/pxa/Makefile
index 08a9f27..bee93f9 100644
--- a/sound/soc/pxa/Makefile
+++ b/sound/soc/pxa/Makefile
@@ -18,6 +18,7 @@ snd-soc-spitz-objs := spitz.o
snd-soc-em-x270-objs := em-x270.o
snd-soc-palm27x-objs := palm27x.o
snd-soc-zylonite-objs := zylonite.o
+snd-soc-aximx50-objs := aximx50-soc.o
obj-$(CONFIG_SND_PXA2XX_SOC_CORGI) += snd-soc-corgi.o
obj-$(CONFIG_SND_PXA2XX_SOC_POODLE) += snd-soc-poodle.o
@@ -27,3 +28,4 @@ obj-$(CONFIG_SND_PXA2XX_SOC_SPITZ) += snd-soc-spitz.o
obj-$(CONFIG_SND_PXA2XX_SOC_EM_X270) += snd-soc-em-x270.o
obj-$(CONFIG_SND_PXA2XX_SOC_PALM27X) += snd-soc-palm27x.o
obj-$(CONFIG_SND_SOC_ZYLONITE) += snd-soc-zylonite.o
+obj-$(CONFIG_SND_PXA2XX_SOC_X50) += snd-soc-aximx50.o
diff --git a/sound/soc/pxa/aximx50-soc.c b/sound/soc/pxa/aximx50-soc.c
new file mode 100644
index 0000000..c97ef72
--- /dev/null
+++ b/sound/soc/pxa/aximx50-soc.c
@@ -0,0 +1,333 @@
+/*
+ * ALSA SoC for Dell Axim x50/x51v
+ *
+ * Copyright (c) 2009 Ertan Deniz
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#include <asm/mach-types.h>
+#include <asm/arch-pxa/aximx50-gpio.h>
+#include <mach/pxa-regs.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
+
+#include "../codecs/wm8750.h"
+#include "pxa2xx-pcm.h"
+#include "pxa2xx-i2s.h"
+
+#define aximx50_HP 1
+#define aximx50_HP_OFF 0
+#define aximx50_SPK_ON 1
+#define aximx50_SPK_OFF 0
+
+ /* audio clock in Hz - rounded from 12.235MHz */
+#define aximx50_AUDIO_CLOCK 12288000
+
+static int aximx50_jack_func;
+static int aximx50_spk_func;
+
+static void aximx50_ext_control(struct snd_soc_codec *codec)
+{
+ /* set up jack connection */
+ if (aximx50_jack_func == aximx50_HP) {
+ /* set = unmute headphone */
+ gpio_set_value(GPIO_NR_X50_MUTE_L, 1);
+ gpio_set_value(GPIO_NR_X50_MUTE_R, 1);
+ snd_soc_dapm_enable_pin(codec, "Headphone Jack");
+ } else {
+ gpio_set_value(GPIO_NR_X50_MUTE_L, 0);
+ gpio_set_value(GPIO_NR_X50_MUTE_R, 0);
+ snd_soc_dapm_disable_pin(codec, "Headphone Jack");
+ }
+
+ /* set the enpoints to their new connetion states */
+ if (aximx50_spk_func == aximx50_SPK_ON)
+ snd_soc_dapm_enable_pin(codec, "Ext Spk");
+ else
+ snd_soc_dapm_disable_pin(codec, "Ext Spk");
+
+ /* signal a DAPM event */
+ snd_soc_dapm_sync(codec);
+}
+
+static int aximx50_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_codec *codec = rtd->socdev->codec;
+
+ /* check the jack status at stream startup */
+ aximx50_ext_control(codec);
+ return 0;
+}
+
+/* we need to unmute the HP at shutdown as the mute burns power on poodle */
+static void aximx50_shutdown(struct snd_pcm_substream *substream)
+{
+ /* set = unmute headphone */
+ gpio_set_value(GPIO_NR_X50_MUTE_L, 1);
+ gpio_set_value(GPIO_NR_X50_MUTE_R, 1);
+}
+
+static int aximx50_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+ unsigned int clk = 0;
+ int ret = 0;
+
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 48000:
+ case 96000:
+ clk = 12288000;
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ clk = 11289600;
+ break;
+ }
+
+ /* set codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ return ret;
+
+ /* set cpu DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ return ret;
+
+ /* set the codec system clock for DAC and ADC */
+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8750_SYSCLK, clk,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ /* set the I2S system clock as input (unused) */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, PXA2XX_I2S_SYSCLK, 0,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static struct snd_soc_ops aximx50_ops = {
+ .startup = aximx50_startup,
+ .hw_params = aximx50_hw_params,
+ .shutdown = aximx50_shutdown,
+};
+
+static int aximx50_get_jack(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = aximx50_jack_func;
+ return 0;
+}
+
+static int aximx50_set_jack(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ if (aximx50_jack_func == ucontrol->value.integer.value[0])
+ return 0;
+
+ aximx50_jack_func = ucontrol->value.integer.value[0];
+ aximx50_ext_control(codec);
+ return 1;
+}
+
+static int aximx50_get_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = aximx50_spk_func;
+ return 0;
+}
+
+static int aximx50_set_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ if (aximx50_spk_func == ucontrol->value.integer.value[0])
+ return 0;
+
+ aximx50_spk_func = ucontrol->value.integer.value[0];
+ aximx50_ext_control(codec);
+ return 1;
+}
+
+static int aximx50_amp_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *k, int event)
+{/*
+ if (SND_SOC_DAPM_EVENT_ON(event))
+ locomo_gpio_write(&aximx50_locomo_device.dev,
+ aximx50_LOCOMO_GPIO_AMP_ON, 0);
+ else
+ locomo_gpio_write(&aximx50_locomo_device.dev,
+ aximx50_LOCOMO_GPIO_AMP_ON, 1);
+*/
+ return 0;
+}
+
+/* poodle machine dapm widgets */
+static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
+SND_SOC_DAPM_HP("Headphone Jack", NULL),
+SND_SOC_DAPM_SPK("Ext Spk", aximx50_amp_event),
+};
+
+/* Corgi machine connections to the codec pins */
+static const struct snd_soc_dapm_route audio_map[] = {
+
+ /* headphone connected to LOUT1, ROUT1 */
+ {"Headphone Jack", NULL, "LOUT1"},
+ {"Headphone Jack", NULL, "ROUT1"},
+
+ /* ext speaker connected to LOUT2, ROUT2 */
+ {"Ext Spk", NULL , "ROUT2"},
+ {"Ext Spk", NULL , "LOUT2"},
+};
+
+static const char *jack_function[] = {"Off", "Headphone"};
+static const char *spk_function[] = {"Off", "On"};
+static const struct soc_enum aximx50_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, jack_function),
+ SOC_ENUM_SINGLE_EXT(2, spk_function),
+};
+
+static const struct snd_kcontrol_new wm8750_aximx50_controls[] = {
+ SOC_ENUM_EXT("Jack Function", aximx50_enum[0], aximx50_get_jack,
+ aximx50_set_jack),
+ SOC_ENUM_EXT("Speaker Function", aximx50_enum[1], aximx50_get_spk,
+ aximx50_set_spk),
+};
+
+/*
+ * Logic for a wm8750 as connected on a Sharp SL-C7x0 Device
+ */
+static int aximx50_wm8750_init(struct snd_soc_codec *codec)
+{
+ int i, err;
+
+ snd_soc_dapm_disable_pin(codec, "RINPUT1");
+ snd_soc_dapm_disable_pin(codec, "LINPUT2");
+ snd_soc_dapm_disable_pin(codec, "RINPUT2");
+ snd_soc_dapm_disable_pin(codec, "LINPUT3");
+ snd_soc_dapm_disable_pin(codec, "RINPUT3");
+ snd_soc_dapm_disable_pin(codec, "OUT3");
+ snd_soc_dapm_disable_pin(codec, "MONO1");
+
+ /* Add poodle specific controls */
+ for (i = 0; i < ARRAY_SIZE(wm8750_aximx50_controls); i++) {
+ err = snd_ctl_add(codec->card,
+ snd_soc_cnew(&wm8750_aximx50_controls[i], codec, NULL));
+ if (err < 0)
+ return err;
+ }
+
+ /* Add poodle specific widgets */
+ snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets,
+ ARRAY_SIZE(wm8750_dapm_widgets));
+
+ /* Set up poodle specific audio path audio_map */
+ snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+
+ snd_soc_dapm_sync(codec);
+ return 0;
+}
+
+/* poodle digital audio interface glue - connects codec <--> CPU */
+static struct snd_soc_dai_link aximx50_dai = {
+ .name = "WM8750",
+ .stream_name = "WM8750",
+ .cpu_dai = &pxa_i2s_dai,
+ .codec_dai = &wm8750_dai,
+ .init = aximx50_wm8750_init,
+ .ops = &aximx50_ops,
+};
+
+/* aximx50 audio machine driver */
+static struct snd_soc_card snd_soc_aximx50 = {
+ .name = "Aximx50",
+ .platform = &pxa2xx_soc_platform,
+ .dai_link = &aximx50_dai,
+ .num_links = 1,
+};
+
+/* aximx50 audio private data */
+static struct wm8750_setup_data aximx50_wm8750_setup = {
+ .i2c_bus = 0,
+ .i2c_address = 0x1a,
+};
+
+/* aximx50 audio subsystem */
+static struct snd_soc_device aximx50_snd_devdata = {
+ .card = &snd_soc_aximx50,
+ .codec_dev = &soc_codec_dev_wm8750,
+ .codec_data = &aximx50_wm8750_setup,
+};
+
+static struct platform_device *aximx50_snd_device;
+
+static int __init aximx50_init(void)
+{
+ int ret;
+
+// if (!machine_is_poodle())
+// return -ENODEV;
+
+/*
+ locomo_gpio_set_dir(&aximx50_locomo_device.dev,
+ aximx50_LOCOMO_GPIO_AMP_ON, 0);*/
+ /* should we mute HP at startup - burning power ?*/
+/* locomo_gpio_set_dir(&aximx50_locomo_device.dev,
+ aximx50_LOCOMO_GPIO_MUTE_L, 0);
+ locomo_gpio_set_dir(&aximx50_locomo_device.dev,
+ aximx50_LOCOMO_GPIO_MUTE_R, 0);*/
+
+ aximx50_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!aximx50_snd_device)
+ return -ENOMEM;
+
+ platform_set_drvdata(aximx50_snd_device, &aximx50_snd_devdata);
+ aximx50_snd_devdata.dev = &aximx50_snd_device->dev;
+ ret = platform_device_add(aximx50_snd_device);
+
+ if (ret)
+ platform_device_put(aximx50_snd_device);
+
+ return ret;
+}
+
+static void __exit aximx50_exit(void)
+{
+ platform_device_unregister(aximx50_snd_device);
+}
+
+module_init(aximx50_init);
+module_exit(aximx50_exit);
+
+/* Module information */
+MODULE_AUTHOR("Ertan Deniz");
+MODULE_DESCRIPTION("ALSA SoC for Dell Axim x50/51v");
+MODULE_LICENSE("GPL");
--
1.6.2.1
Raw
aximx50_bl.c
/*
* LCD backlight support for iPAQ AXIMX50
*
* Copyright (c) 2004 Andrew Zabolotny
* Copyright (c) 2004-6 Matt Reimer
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/platform_device.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/aximx50-gpio.h>
#include <asm/arch/sharpsl.h>
#define AXIMX50_MAX_INTENSITY 0x3ff
static
void aximx50_set_bl_intensity(int intensity)
{
if (intensity < 7) intensity = 0;
PWM_CTRL0 = 1;
PWM_PERVAL0 = AXIMX50_MAX_INTENSITY;
PWM_PWDUTY0 = intensity;
if (intensity) {
pxa_gpio_mode(GPIO16_PWM0_MD);
pxa_set_cken(CKEN0_PWM0, 1);
SET_X50_GPIO(BACKLIGHT_ON, 1);
} else {
pxa_set_cken(CKEN0_PWM0, 0);
SET_X50_GPIO(BACKLIGHT_ON, 0);
}
}
static struct corgibl_machinfo aximx50_bl_machinfo = {
.max_intensity = AXIMX50_MAX_INTENSITY,
.default_intensity = AXIMX50_MAX_INTENSITY,
.limit_mask = 0xff, /* limit brightness to about 1/4 on low battery */
.set_bl_intensity = aximx50_set_bl_intensity,
};
struct platform_device aximx50_bl = {
.name = "corgi-bl",
.dev = {
.platform_data = &aximx50_bl_machinfo,
},
};
static int __init aximx50_bl_init(void)
{
printk("Loading Axim X50 Backlight driver\n");
return platform_device_register(&aximx50_bl);
}
static void __exit aximx50_bl_exit(void)
{
printk("Unloading Axim X50 Backlight driver\n");
platform_device_unregister(&aximx50_bl);
}
module_init(aximx50_bl_init);
module_exit(aximx50_bl_exit);
MODULE_AUTHOR("Andrew Zabolotny, Matt Reimer <mreimer@vpop.net>");
MODULE_DESCRIPTION("Backlight driver for iPAQ AXIMX50");
MODULE_LICENSE("GPL");
Raw
backlight.diff
--- drivers/video/backlight/Makefile 17 Dec 2006 03:43:35 -0000 1.8
+++ drivers/video/backlight/Makefile 14 Mar 2007 20:42:07 -0000
@@ -8,5 +8,6 @@
obj-$(CONFIG_BACKLIGHT_HX2750) += hx2750_bl.o
obj-$(CONFIG_BACKLIGHT_H2200) += h2200_bl.o
obj-$(CONFIG_LCD_H2200) += h2200_lcd.o
+obj-$(CONFIG_BACKLIGHT_AXIMX50) += aximx50_bl.o
obj-$(CONFIG_BACKLIGHT_S3C2410) += s3c2410_lcd.o
--- include/asm-arm/arch-pxa/aximx50-gpio.h 9 Feb 2007 10:17:31 -0000 1.2
+++ include/asm-arm/arch-pxa/aximx50-gpio.h 14 Mar 2007 20:42:08 -0000
@@ -36,6 +36,7 @@
/*********************************************************************/
#define GPIO_NR_X50_AC_IN_N 11 /* Input = 1 when externally powered */
+#define GPIO_NR_X50_BACKLIGHT_ON 17 /* Tied to PWM0 when Alt function == 2 */
#define GPIO_NR_X50_PEN_IRQ_N 94 /* Input = 0 when stylus down */
--- drivers/video/backlight/Kconfig 17 Dec 2006 03:43:35 -0000 1.9
+++ drivers/video/backlight/Kconfig 14 Mar 2007 20:42:07 -0000
@@ -80,6 +80,12 @@
If you have an iPAQ h2200, say Y to enable the backlight driver.
+config BACKLIGHT_AXIMX50
+ tristate "AXIMX50 Backlight Driver"
+ depends on BACKLIGHT_DEVICE && MACH_X50
+ help
+ If you have an Axim x50/51, say Y to enable the backlight driver.
+
config BACKLIGHT_S3C2410
tristate "Samsung S3C2410 Backlight Driver"
depends on (BACKLIGHT_DEVICE || LCD_CLASS_DEVICE) && ARCH_S3C2410
Raw
pxaregs.c
/*
* pxaregs - tool to display and modify PXA250's registers at runtime
*
* (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
* set under the GPLv2
*
* $Id: pxaregs.c,v 1.14 2003/11/12 13:14:43 schurig Exp $
*
* Please send patches to h.schurig, working at mn-logistik.de
* - added fix from Bernhard Nemec
* - i2c registers from Stefan Eletzhofer
*/
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <ctype.h>
//#include <linux/i2c.h>
//#include <linux/i2c-dev.h>
// fd for /dev/mem
static int fd = -1;
typedef unsigned int u32;
struct reg_info {
char *name;
u32 addr;
int shift;
u32 mask;
char type;
char *desc;
};
static struct reg_info regs[] = {
{ "IBMR", 0x40301680, 0, 0xffffffff, 'x', "I2C Bus Monitor Register" },
{ "IBMR_SDAS", 0x40301680, 0, 0x00000001, 'x', "SDA Status" },
{ "IBMR_SCLS", 0x40301680, 1, 0x00000001, 'x', "SDA Status" },
{ "IDBR", 0x40301688, 0, 0xffffffff, 'x', "I2C Data Buffer Register" },
{ "IDBR_IDB", 0x40301688, 0, 0x000000ff, 'x', "I2C Data Buffer" },
{ "ICR", 0x40301690, 0, 0xffffffff, 'x', "I2C Control Register" },
{ "ICR_START", 0x40301690, 0, 1, 'x', " start bit " },
{ "ICR_STOP", 0x40301690, 1, 1, 'x', " stop bit " },
{ "ICR_ACKNAK",0x40301690, 2, 1, 'x', " send ACK(0) or NAK(1)" },
{ "ICR_TB", 0x40301690, 3, 1, 'x', " transfer byte bit " },
{ "ICR_MA", 0x40301690, 4, 1, 'x', " master abort " },
{ "ICR_SCLE", 0x40301690, 5, 1, 'x', " master clock enable " },
{ "ICR_IUE", 0x40301690, 6, 1, 'x', " unit enable " },
{ "ICR_GCD", 0x40301690, 7, 1, 'x', " general call disable " },
{ "ICR_ITEIE", 0x40301690, 8, 1, 'x', " enable tx interrupts " },
{ "ICR_IRFIE", 0x40301690, 9, 1, 'x', " enable rx interrupts " },
{ "ICR_BEIE", 0x40301690, 10, 1, 'x', " enable bus error ints " },
{ "ICR_SSDIE", 0x40301690, 11, 1, 'x', " slave STOP detected int enable " },
{ "ICR_ALDIE", 0x40301690, 12, 1, 'x', " enable arbitration interrupt " },
{ "ICR_SADIE", 0x40301690, 13, 1, 'x', " slave address detected int enable " },
{ "ICR_UR", 0x40301690, 14, 1, 'x', " unit reset " },
{ "ICR_FM", 0x40301690, 15, 1, 'x', " fast mode " },
{ "ISR", 0x40301698, 0, 0xffffffff, 'x', "I2C Status Register" },
{ "ISR_RWM", 0x40301698, 0, 1, 'x', " read/write mode " },
{ "ISR_ACKNAK",0x40301698, 1, 1, 'x', " ack/nak status " },
{ "ISR_UB", 0x40301698, 2, 1, 'x', " unit busy " },
{ "ISR_IBB", 0x40301698, 3, 1, 'x', " bus busy " },
{ "ISR_SSD", 0x40301698, 4, 1, 'x', " slave stop detected " },
{ "ISR_ALD", 0x40301698, 5, 1, 'x', " arbitration loss detected " },
{ "ISR_ITE", 0x40301698, 6, 1, 'x', " tx buffer empty " },
{ "ISR_IRF", 0x40301698, 7, 1, 'x', " rx buffer full " },
{ "ISR_GCAD", 0x40301698, 8, 1, 'x', " general call address detected " },
{ "ISR_SAD", 0x40301698, 9, 1, 'x', " slave address detected " },
{ "ISR_BED", 0x40301698, 10, 1, 'x', " bus error no ACK/NAK " },
{ "ISAR", 0x403016A0, 0, 0xffffffff, 'x', "I2C Slave Address Register" },
{ "ISAR_SA", 0x403016A0, 0, 0x0000007f, 'x', "I2C Slave Address" },
{ "PMCR", 0x40F00000, 0, 0xffffffff, 'x', "Power Manager Control Register (3-23)" },
{ "PMCR_IDAE", 0x40F00000, 0, 0x00000001, 'd', "PM imprecise data abort abort signal" },
{ "PSSR", 0x40F00004, 0, 0xffffffff, 'x', "Power Manager Sleep Status Register (3-29)" },
{ "PSSR_SSS", 0x40F00004, 0, 0x00000001, 'd', "PM chip was in sleep by setting sleep mode bit" },
{ "PSSR_BFS", 0x40F00004, 1, 0x00000001, 'd', "PM nBATT_FAULT has been asserted" },
{ "PSSR_VFS", 0x40F00004, 2, 0x00000001, 'd', "PM nVDD_FAULT was asserted while in Run or Idle" },
{ "PSSR_PH", 0x40F00004, 4, 0x00000001, 'd', "PM GPIO pins are held in their sleep state" },
{ "PSSR_RDH", 0x40F00004, 5, 0x00000001, 'd', "PM receivers of all input GPIO are disabled" },
{ "PSPR", 0x40F00008, 0, 0xffffffff, 'x', "Power Manager Scratch Pad Register (3-30)" },
{ "PWER", 0x40F0000C, 0, 0xffffffff, 'x', "Power Manager Wake-Up Enable Register (3-25)" },
{ "PWER_WE0", 0x40F0000C, 0, 0x00000001, 'd', "PM wake up due to GPIO 0 edge detect enabled" },
{ "PWER_WE1", 0x40F0000C, 1, 0x00000001, 'd', "PM wake up due to GPIO 1 edge detect enabled" },
{ "PWER_WE2", 0x40F0000C, 2, 0x00000001, 'd', "PM wake up due to GPIO 2 edge detect enabled" },
{ "PWER_WE3", 0x40F0000C, 3, 0x00000001, 'd', "PM wake up due to GPIO 3 edge detect enabled" },
{ "PWER_WE4", 0x40F0000C, 4, 0x00000001, 'd', "PM wake up due to GPIO 4 edge detect enabled" },
{ "PWER_WE5", 0x40F0000C, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 edge detect enabled" },
{ "PWER_WE6", 0x40F0000C, 6, 0x00000001, 'd', "PM wake up due to GPIO 6 edge detect enabled" },
{ "PWER_WE7", 0x40F0000C, 7, 0x00000001, 'd', "PM wake up due to GPIO 7 edge detect enabled" },
{ "PWER_WE8", 0x40F0000C, 8, 0x00000001, 'd', "PM wake up due to GPIO 8 edge detect enabled" },
{ "PWER_WE9", 0x40F0000C, 9, 0x00000001, 'd', "PM wake up due to GPIO 9 edge detect enabled" },
{ "PWER_WE10", 0x40F0000C, 10, 0x00000001, 'd', "PM wake up due to GPIO10 edge detect enabled" },
{ "PWER_WE11", 0x40F0000C, 11, 0x00000001, 'd', "PM wake up due to GPIO11 edge detect enabled" },
{ "PWER_WE12", 0x40F0000C, 12, 0x00000001, 'd', "PM wake up due to GPIO12 edge detect enabled" },
{ "PWER_WE13", 0x40F0000C, 13, 0x00000001, 'd', "PM wake up due to GPIO13 edge detect enabled" },
{ "PWER_WE14", 0x40F0000C, 14, 0x00000001, 'd', "PM wake up due to GPIO14 edge detect enabled" },
{ "PWER_WE15", 0x40F0000C, 15, 0x00000001, 'd', "PM wake up due to GPIO15 edge detect enabled" },
{ "PWER_WERTC",0x40F0000C, 31, 0x00000001, 'd', "PM wake up due to RTC alarm enabled" },
{ "PRER", 0x40F00010, 0, 0xffffffff, 'x', "Power Manager Rising Edge Detect Enable Register (3-26)" },
{ "PRER_RE0", 0x40F00010, 0, 0x00000001, 'd', "PM wake up due to GPIO 0 rising edge detect enabled" },
{ "PRER_RE1", 0x40F00010, 1, 0x00000001, 'd', "PM wake up due to GPIO 1 rising edge detect enabled" },
{ "PRER_RE2", 0x40F00010, 2, 0x00000001, 'd', "PM wake up due to GPIO 2 rising edge detect enabled" },
{ "PRER_RE3", 0x40F00010, 3, 0x00000001, 'd', "PM wake up due to GPIO 3 rising edge detect enabled" },
{ "PRER_RE4", 0x40F00010, 4, 0x00000001, 'd', "PM wake up due to GPIO 4 rising edge detect enabled" },
{ "PRER_RE5", 0x40F00010, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 rising edge detect enabled" },
{ "PRER_RE6", 0x40F00010, 6, 0x00000001, 'd', "PM wake up due to GPIO 6 rising edge detect enabled" },
{ "PRER_RE7", 0x40F00010, 7, 0x00000001, 'd', "PM wake up due to GPIO 7 rising edge detect enabled" },
{ "PRER_RE8", 0x40F00010, 8, 0x00000001, 'd', "PM wake up due to GPIO 8 rising edge detect enabled" },
{ "PRER_RE9", 0x40F00010, 9, 0x00000001, 'd', "PM wake up due to GPIO 9 rising edge detect enabled" },
{ "PRER_RE10", 0x40F00010, 10, 0x00000001, 'd', "PM wake up due to GPIO10 rising edge detect enabled" },
{ "PRER_RE11", 0x40F00010, 11, 0x00000001, 'd', "PM wake up due to GPIO11 rising edge detect enabled" },
{ "PRER_RE12", 0x40F00010, 12, 0x00000001, 'd', "PM wake up due to GPIO12 rising edge detect enabled" },
{ "PRER_RE13", 0x40F00010, 13, 0x00000001, 'd', "PM wake up due to GPIO13 rising edge detect enabled" },
{ "PRER_RE14", 0x40F00010, 14, 0x00000001, 'd', "PM wake up due to GPIO14 rising edge detect enabled" },
{ "PRER_RE15", 0x40F00010, 15, 0x00000001, 'd', "PM wake up due to GPIO15 rising edge detect enabled" },
{ "PFER", 0x40F00014, 0, 0xffffffff, 'x', "Power Manager Falling Detect Enable Register (3-27)" },
{ "PFER_FE0", 0x40F00014, 0, 0x00000001, 'd', "PM wake up due to GPIO 0 falling edge detect enabled" },
{ "PFER_FE1", 0x40F00014, 1, 0x00000001, 'd', "PM wake up due to GPIO 1 falling edge detect enabled" },
{ "PFER_FE2", 0x40F00014, 2, 0x00000001, 'd', "PM wake up due to GPIO 2 falling edge detect enabled" },
{ "PFER_FE3", 0x40F00014, 3, 0x00000001, 'd', "PM wake up due to GPIO 3 falling edge detect enabled" },
{ "PFER_FE4", 0x40F00014, 4, 0x00000001, 'd', "PM wake up due to GPIO 4 falling edge detect enabled" },
{ "PFER_FE5", 0x40F00014, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 falling edge detect enabled" },
{ "PFER_FE6", 0x40F00014, 6, 0x00000001, 'd', "PM wake up due to GPIO 6 falling edge detect enabled" },
{ "PFER_FE7", 0x40F00014, 7, 0x00000001, 'd', "PM wake up due to GPIO 7 falling edge detect enabled" },
{ "PFER_FE8", 0x40F00014, 8, 0x00000001, 'd', "PM wake up due to GPIO 8 falling edge detect enabled" },
{ "PFER_FE9", 0x40F00014, 9, 0x00000001, 'd', "PM wake up due to GPIO 9 falling edge detect enabled" },
{ "PFER_FE10", 0x40F00014, 10, 0x00000001, 'd', "PM wake up due to GPIO10 falling edge detect enabled" },
{ "PFER_FE11", 0x40F00014, 11, 0x00000001, 'd', "PM wake up due to GPIO11 falling edge detect enabled" },
{ "PFER_FE12", 0x40F00014, 12, 0x00000001, 'd', "PM wake up due to GPIO12 falling edge detect enabled" },
{ "PFER_FE13", 0x40F00014, 13, 0x00000001, 'd', "PM wake up due to GPIO13 falling edge detect enabled" },
{ "PFER_FE14", 0x40F00014, 14, 0x00000001, 'd', "PM wake up due to GPIO14 falling edge detect enabled" },
{ "PFER_FE15", 0x40F00014, 15, 0x00000001, 'd', "PM wake up due to GPIO15 falling edge detect enabled" },
{ "PEDR", 0x40F00018, 0, 0xffffffff, 'x', "Power Manager Edge Detect Status Register (3-28)" },
{ "PEDR_ED0", 0x40F00018, 0, 0x00000001, 'd', "PM wake up due to edge on GPIO 0 detected" },
{ "PEDR_ED1", 0x40F00018, 1, 0x00000001, 'd', "PM wake up due to edge on GPIO 1 detected" },
{ "PEDR_ED2", 0x40F00018, 2, 0x00000001, 'd', "PM wake up due to edge on GPIO 2 detected" },
{ "PEDR_ED3", 0x40F00018, 3, 0x00000001, 'd', "PM wake up due to edge on GPIO 3 detected" },
{ "PEDR_ED4", 0x40F00018, 4, 0x00000001, 'd', "PM wake up due to edge on GPIO 4 detected" },
{ "PEDR_ED5", 0x40F00018, 5, 0x00000001, 'd', "PM wake up due to edge on GPIO 5 detected" },
{ "PEDR_ED6", 0x40F00018, 6, 0x00000001, 'd', "PM wake up due to edge on GPIO 6 detected" },
{ "PEDR_ED7", 0x40F00018, 7, 0x00000001, 'd', "PM wake up due to edge on GPIO 7 detected" },
{ "PEDR_ED8", 0x40F00018, 8, 0x00000001, 'd', "PM wake up due to edge on GPIO 8 detected" },
{ "PEDR_ED9", 0x40F00018, 9, 0x00000001, 'd', "PM wake up due to edge on GPIO 9 detected" },
{ "PEDR_ED10", 0x40F00018, 10, 0x00000001, 'd', "PM wake up due to edge on GPIO10 detected" },
{ "PEDR_ED11", 0x40F00018, 11, 0x00000001, 'd', "PM wake up due to edge on GPIO11 detected" },
{ "PEDR_ED12", 0x40F00018, 12, 0x00000001, 'd', "PM wake up due to edge on GPIO12 detected" },
{ "PEDR_ED13", 0x40F00018, 13, 0x00000001, 'd', "PM wake up due to edge on GPIO13 detected" },
{ "PEDR_ED14", 0x40F00018, 14, 0x00000001, 'd', "PM wake up due to edge on GPIO14 detected" },
{ "PEDR_ED15", 0x40F00018, 15, 0x00000001, 'd', "PM wake up due to edge on GPIO15 detected" },
{ "PCFR", 0x40F0001C, 0, 0xffffffff, 'x', "Power Manager General Configuration Register (3-24)" },
{ "PCFR_OPDE", 0x40F0001C, 0, 0x00000001, 'd', "PM stop 3.6864 MHz oscillator during sleep" },
{ "PCFR_FP", 0x40F0001C, 1, 0x00000001, 'd', "PM PCMCIA signals float during sleep" },
{ "PCFR_FS", 0x40F0001C, 2, 0x00000001, 'd', "PM static chip select signals float during sleep" },
{ "PGSR0", 0x40F00020, 0, 0xffffffff, 'x', "Power Manager GPIO Sleep State Register 0 (3-32)" },
{ "PGSR_SS0", 0x40F00020, 0, 0x00000001, 'd', "PM GPIO pin 0 is driven to 1 during sleep" },
{ "PGSR_SS1", 0x40F00020, 1, 0x00000001, 'd', "PM GPIO pin 1 is driven to 1 during sleep" },
{ "PGSR_SS2", 0x40F00020, 2, 0x00000001, 'd', "PM GPIO pin 2 is driven to 1 during sleep" },
{ "PGSR_SS3", 0x40F00020, 3, 0x00000001, 'd', "PM GPIO pin 3 is driven to 1 during sleep" },
{ "PGSR_SS4", 0x40F00020, 4, 0x00000001, 'd', "PM GPIO pin 4 is driven to 1 during sleep" },
{ "PGSR_SS5", 0x40F00020, 5, 0x00000001, 'd', "PM GPIO pin 5 is driven to 1 during sleep" },
{ "PGSR_SS6", 0x40F00020, 6, 0x00000001, 'd', "PM GPIO pin 6 is driven to 1 during sleep" },
{ "PGSR_SS7", 0x40F00020, 7, 0x00000001, 'd', "PM GPIO pin 7 is driven to 1 during sleep" },
{ "PGSR_SS8", 0x40F00020, 8, 0x00000001, 'd', "PM GPIO pin 8 is driven to 1 during sleep" },
{ "PGSR_SS9", 0x40F00020, 9, 0x00000001, 'd', "PM GPIO pin 9 is driven to 1 during sleep" },
{ "PGSR_SS10", 0x40F00020, 10, 0x00000001, 'd', "PM GPIO pin 10 is driven to 1 during sleep" },
{ "PGSR_SS11", 0x40F00020, 11, 0x00000001, 'd', "PM GPIO pin 11 is driven to 1 during sleep" },
{ "PGSR_SS12", 0x40F00020, 12, 0x00000001, 'd', "PM GPIO pin 12 is driven to 1 during sleep" },
{ "PGSR_SS13", 0x40F00020, 13, 0x00000001, 'd', "PM GPIO pin 13 is driven to 1 during sleep" },
{ "PGSR_SS14", 0x40F00020, 14, 0x00000001, 'd', "PM GPIO pin 14 is driven to 1 during sleep" },
{ "PGSR_SS15", 0x40F00020, 15, 0x00000001, 'd', "PM GPIO pin 15 is driven to 1 during sleep" },
{ "PGSR_SS16", 0x40F00020, 16, 0x00000001, 'd', "PM GPIO pin 16 is driven to 1 during sleep" },
{ "PGSR_SS17", 0x40F00020, 17, 0x00000001, 'd', "PM GPIO pin 17 is driven to 1 during sleep" },
{ "PGSR_SS18", 0x40F00020, 18, 0x00000001, 'd', "PM GPIO pin 18 is driven to 1 during sleep" },
{ "PGSR_SS19", 0x40F00020, 19, 0x00000001, 'd', "PM GPIO pin 19 is driven to 1 during sleep" },
{ "PGSR_SS20", 0x40F00020, 20, 0x00000001, 'd', "PM GPIO pin 20 is driven to 1 during sleep" },
{ "PGSR_SS21", 0x40F00020, 21, 0x00000001, 'd', "PM GPIO pin 21 is driven to 1 during sleep" },
{ "PGSR_SS22", 0x40F00020, 22, 0x00000001, 'd', "PM GPIO pin 22 is driven to 1 during sleep" },
{ "PGSR_SS23", 0x40F00020, 23, 0x00000001, 'd', "PM GPIO pin 23 is driven to 1 during sleep" },
{ "PGSR_SS24", 0x40F00020, 24, 0x00000001, 'd', "PM GPIO pin 24 is driven to 1 during sleep" },
{ "PGSR_SS25", 0x40F00020, 25, 0x00000001, 'd', "PM GPIO pin 25 is driven to 1 during sleep" },
{ "PGSR_SS26", 0x40F00020, 26, 0x00000001, 'd', "PM GPIO pin 26 is driven to 1 during sleep" },
{ "PGSR_SS27", 0x40F00020, 27, 0x00000001, 'd', "PM GPIO pin 27 is driven to 1 during sleep" },
{ "PGSR_SS28", 0x40F00020, 28, 0x00000001, 'd', "PM GPIO pin 28 is driven to 1 during sleep" },
{ "PGSR_SS29", 0x40F00020, 29, 0x00000001, 'd', "PM GPIO pin 29 is driven to 1 during sleep" },
{ "PGSR_SS30", 0x40F00020, 30, 0x00000001, 'd', "PM GPIO pin 30 is driven to 1 during sleep" },
{ "PGSR_SS31", 0x40F00020, 31, 0x00000001, 'd', "PM GPIO pin 31 is driven to 1 during sleep" },
{ "PGSR1", 0x40F00024, 0, 0xffffffff, 'x', "Power Manager GPIO Sleep State Register 1 (3-32)" },
{ "PGSR_SS32", 0x40F00024, 0, 0x00000001, 'd', "PM GPIO pin 32 is driven to 1 during sleep" },
{ "PGSR_SS33", 0x40F00024, 1, 0x00000001, 'd', "PM GPIO pin 33 is driven to 1 during sleep" },
{ "PGSR_SS34", 0x40F00024, 2, 0x00000001, 'd', "PM GPIO pin 34 is driven to 1 during sleep" },
{ "PGSR_SS35", 0x40F00024, 3, 0x00000001, 'd', "PM GPIO pin 35 is driven to 1 during sleep" },
{ "PGSR_SS36", 0x40F00024, 4, 0x00000001, 'd', "PM GPIO pin 36 is driven to 1 during sleep" },
{ "PGSR_SS37", 0x40F00024, 5, 0x00000001, 'd', "PM GPIO pin 37 is driven to 1 during sleep" },
{ "PGSR_SS38", 0x40F00024, 6, 0x00000001, 'd', "PM GPIO pin 38 is driven to 1 during sleep" },
{ "PGSR_SS39", 0x40F00024, 7, 0x00000001, 'd', "PM GPIO pin 39 is driven to 1 during sleep" },
{ "PGSR_SS40", 0x40F00024, 8, 0x00000001, 'd', "PM GPIO pin 40 is driven to 1 during sleep" },
{ "PGSR_SS41", 0x40F00024, 9, 0x00000001, 'd', "PM GPIO pin 41 is driven to 1 during sleep" },
{ "PGSR_SS42", 0x40F00024, 10, 0x00000001, 'd', "PM GPIO pin 42 is driven to 1 during sleep" },
{ "PGSR_SS43", 0x40F00024, 11, 0x00000001, 'd', "PM GPIO pin 43 is driven to 1 during sleep" },
{ "PGSR_SS44", 0x40F00024, 12, 0x00000001, 'd', "PM GPIO pin 44 is driven to 1 during sleep" },
{ "PGSR_SS45", 0x40F00024, 13, 0x00000001, 'd', "PM GPIO pin 45 is driven to 1 during sleep" },
{ "PGSR_SS46", 0x40F00024, 14, 0x00000001, 'd', "PM GPIO pin 46 is driven to 1 during sleep" },
{ "PGSR_SS47", 0x40F00024, 15, 0x00000001, 'd', "PM GPIO pin 47 is driven to 1 during sleep" },
{ "PGSR_SS48", 0x40F00024, 16, 0x00000001, 'd', "PM GPIO pin 48 is driven to 1 during sleep" },
{ "PGSR_SS49", 0x40F00024, 17, 0x00000001, 'd', "PM GPIO pin 49 is driven to 1 during sleep" },
{ "PGSR_SS50", 0x40F00024, 18, 0x00000001, 'd', "PM GPIO pin 50 is driven to 1 during sleep" },
{ "PGSR_SS51", 0x40F00024, 19, 0x00000001, 'd', "PM GPIO pin 51 is driven to 1 during sleep" },
{ "PGSR_SS52", 0x40F00024, 20, 0x00000001, 'd', "PM GPIO pin 52 is driven to 1 during sleep" },
{ "PGSR_SS53", 0x40F00024, 21, 0x00000001, 'd', "PM GPIO pin 53 is driven to 1 during sleep" },
{ "PGSR_SS54", 0x40F00024, 22, 0x00000001, 'd', "PM GPIO pin 54 is driven to 1 during sleep" },
{ "PGSR_SS55", 0x40F00024, 23, 0x00000001, 'd', "PM GPIO pin 55 is driven to 1 during sleep" },
{ "PGSR_SS56", 0x40F00024, 24, 0x00000001, 'd', "PM GPIO pin 56 is driven to 1 during sleep" },
{ "PGSR_SS57", 0x40F00024, 25, 0x00000001, 'd', "PM GPIO pin 57 is driven to 1 during sleep" },
{ "PGSR_SS58", 0x40F00024, 26, 0x00000001, 'd', "PM GPIO pin 58 is driven to 1 during sleep" },
{ "PGSR_SS59", 0x40F00024, 27, 0x00000001, 'd', "PM GPIO pin 59 is driven to 1 during sleep" },
{ "PGSR_SS60", 0x40F00024, 28, 0x00000001, 'd', "PM GPIO pin 60 is driven to 1 during sleep" },
{ "PGSR_SS61", 0x40F00024, 29, 0x00000001, 'd', "PM GPIO pin 61 is driven to 1 during sleep" },
{ "PGSR_SS62", 0x40F00024, 30, 0x00000001, 'd', "PM GPIO pin 62 is driven to 1 during sleep" },
{ "PGSR_SS63", 0x40F00024, 31, 0x00000001, 'd', "PM GPIO pin 63 is driven to 1 during sleep" },
{ "PGSR2", 0x40F00028, 0, 0xffffffff, 'x', "Power Manager GPIO Sleep State Register 2 (3-33)" },
{ "PGSR_SS64", 0x40F00028, 0, 0x00000001, 'd', "PM GPIO pin 64 is driven to 1 during sleep" },
{ "PGSR_SS65", 0x40F00028, 1, 0x00000001, 'd', "PM GPIO pin 65 is driven to 1 during sleep" },
{ "PGSR_SS66", 0x40F00028, 2, 0x00000001, 'd', "PM GPIO pin 66 is driven to 1 during sleep" },
{ "PGSR_SS67", 0x40F00028, 3, 0x00000001, 'd', "PM GPIO pin 67 is driven to 1 during sleep" },
{ "PGSR_SS68", 0x40F00028, 4, 0x00000001, 'd', "PM GPIO pin 68 is driven to 1 during sleep" },
{ "PGSR_SS69", 0x40F00028, 5, 0x00000001, 'd', "PM GPIO pin 69 is driven to 1 during sleep" },
{ "PGSR_SS70", 0x40F00028, 6, 0x00000001, 'd', "PM GPIO pin 70 is driven to 1 during sleep" },
{ "PGSR_SS71", 0x40F00028, 7, 0x00000001, 'd', "PM GPIO pin 71 is driven to 1 during sleep" },
{ "PGSR_SS72", 0x40F00028, 8, 0x00000001, 'd', "PM GPIO pin 72 is driven to 1 during sleep" },
{ "PGSR_SS73", 0x40F00028, 9, 0x00000001, 'd', "PM GPIO pin 73 is driven to 1 during sleep" },
{ "PGSR_SS74", 0x40F00028, 10, 0x00000001, 'd', "PM GPIO pin 74 is driven to 1 during sleep" },
{ "PGSR_SS75", 0x40F00028, 11, 0x00000001, 'd', "PM GPIO pin 75 is driven to 1 during sleep" },
{ "PGSR_SS76", 0x40F00028, 12, 0x00000001, 'd', "PM GPIO pin 76 is driven to 1 during sleep" },
{ "PGSR_SS77", 0x40F00028, 13, 0x00000001, 'd', "PM GPIO pin 77 is driven to 1 during sleep" },
{ "PGSR_SS78", 0x40F00028, 14, 0x00000001, 'd', "PM GPIO pin 78 is driven to 1 during sleep" },
{ "PGSR_SS79", 0x40F00028, 15, 0x00000001, 'd', "PM GPIO pin 79 is driven to 1 during sleep" },
{ "PGSR_SS80", 0x40F00028, 16, 0x00000001, 'd', "PM GPIO pin 80 is driven to 1 during sleep" },
{ "RCSR", 0x40F00030, 0, 0xffffffff, 'x', "Power Manager Reset Controller Status Register (3-34)" },
{ "RCSR_HWR", 0x40F00030, 0, 0x00000001, 'd', "PM hardware reset occurred" },
{ "RCSR_WDR", 0x40F00030, 1, 0x00000001, 'd', "PM watchdog reset occurred" },
{ "RCSR_SMR", 0x40F00030, 2, 0x00000001, 'd', "PM sleep mode occurred" },
{ "RCSR_GFR", 0x40F00030, 3, 0x00000001, 'd', "PM GPIO reset occurred" },
// PXA255
{ "PMFW", 0x40F00034, 0, 0xffffffff, 'x', "Power Manager Fast Sleep Wakeup Register (3-31)" },
{ "PMFW_FWAKE",0x40F00034, 1, 0x00000001, 'x', "Fast Wakeup Enable" },
{ "CCCR", 0x41300000, 0, 0xffffffff, 'x', "Core Clock Configuration Register (3-35)" },
{ "CCCR_L", 0x41300000, 0, 0x0000001f, 'x', "CM crystal freq to memory freq multiplier" },
{ "CCCR_M", 0x41300000, 5, 0x00000003, 'x', "CM memory freq to run mode freq multiplier" },
{ "CCCR_N", 0x41300000, 7, 0x00000007, 'x', "CM run mode freq to turbo freq multiplier" },
{ "CKEN", 0x41300004, 0, 0xffffffff, 'x', "Clock Enable Register (3-36)" },
{ "CKEN_0", 0x41300004, 0, 0x00000001, 'd', "CM PWM0 clock enabled" },
{ "CKEN_1", 0x41300004, 1, 0x00000001, 'd', "CM PWM1 clock enabled" },
{ "CKEN_2", 0x41300004, 2, 0x00000001, 'd', "CM AC97 clock enabled" },
{ "CKEN_3", 0x41300004, 3, 0x00000001, 'd', "CM SSP clock enabled" },
{ "CKEN_5", 0x41300004, 5, 0x00000001, 'd', "CM STUART clock enabled" },
{ "CKEN_6", 0x41300004, 6, 0x00000001, 'd', "CM FFUART clock enabled" },
{ "CKEN_7", 0x41300004, 7, 0x00000001, 'd', "CM BTUART clock enabled" },
{ "CKEN_8", 0x41300004, 8, 0x00000001, 'd', "CM I2S clock enabled" },
{ "CKEN_11", 0x41300004, 11, 0x00000001, 'd', "CM USB clock enabled" },
{ "CKEN_12", 0x41300004, 12, 0x00000001, 'd', "CM MMC clock enabled" },
{ "CKEN_13", 0x41300004, 13, 0x00000001, 'd', "CM FIPC clock enabled" },
{ "CKEN_14", 0x41300004, 14, 0x00000001, 'd', "CM I2C clock enabled" },
{ "CKEN_16", 0x41300004, 16, 0x00000001, 'd', "CM LCD clock enabled" },
{ "OSCC", 0x41300008, 0, 0xffffffff, 'x', "Oscillator Configuration Register (3-38)" },
{ "OSCC_OOK", 0x41300008, 0, 0x00000001, 'd', "CM 32.768 kHz oscillator enabled and stabilized" },
{ "OSCC_OON", 0x41300008, 1, 0x00000001, 'd', "CM 32.768 kHz oscillator enabled" },
// TODO: CP14-Registers (3-37)
{ "GPLR0", 0x40E00000, 0, 0xffffffff, 'x', "GPIO Pin Level Register 0 (4-7)" },
#if defined(CONFIG_ARCH_RAMSES)
{ "GPLR0_0", 0x40E00000, 0, 0x00000001, 'd', "GPIO 0 (nc) level" },
{ "GPLR0_1", 0x40E00000, 1, 0x00000001, 'd', "GPIO 1 (nPFI) level" },
{ "GPLR0_2", 0x40E00000, 2, 0x00000001, 'd', "GPIO 2 (BAT_DATA) level" },
{ "GPLR0_3", 0x40E00000, 3, 0x00000001, 'd', "GPIO 3 (IRQ_KEY) level" },
{ "GPLR0_4", 0x40E00000, 4, 0x00000001, 'd', "GPIO 4 (IRQ_ETH) level" },
{ "GPLR0_5", 0x40E00000, 5, 0x00000001, 'd', "GPIO 5 (nc) level" },
{ "GPLR0_6", 0x40E00000, 6, 0x00000001, 'd', "GPIO 6 (MMC_CLK) level" },
{ "GPLR0_7", 0x40E00000, 7, 0x00000001, 'd', "GPIO 7 (IRQ_GSM) level" },
{ "GPLR0_8", 0x40E00000, 8, 0x00000001, 'd', "GPIO 8 (nPCC_S1_CD) level" },
{ "GPLR0_9", 0x40E00000, 9, 0x00000001, 'd', "GPIO 9 (MMC_CD) level" },
{ "GPLR0_10", 0x40E00000, 10, 0x00000001, 'd', "GPIO 10 (IRQ_RTC) level" },
{ "GPLR0_11", 0x40E00000, 11, 0x00000001, 'd', "GPIO 11 (nc 3M6) level" },
{ "GPLR0_12", 0x40E00000, 12, 0x00000001, 'd', "GPIO 12 (nc) level" },
{ "GPLR0_13", 0x40E00000, 13, 0x00000001, 'd', "GPIO 13 (IRQ_DOCK) level" },
{ "GPLR0_14", 0x40E00000, 14, 0x00000001, 'd', "GPIO 14 (nc) level" },
{ "GPLR0_15", 0x40E00000, 15, 0x00000001, 'd', "GPIO 15 (nCS1) level" },
{ "GPLR0_16", 0x40E00000, 16, 0x00000001, 'd', "GPIO 16 (PWM0) level" },
{ "GPLR0_17", 0x40E00000, 17, 0x00000001, 'd', "GPIO 17 (PWM1) level" },
{ "GPLR0_18", 0x40E00000, 18, 0x00000001, 'd', "GPIO 18 (RDY) level" },
{ "GPLR0_19", 0x40E00000, 19, 0x00000001, 'd', "GPIO 19 (nc nPCC_S0_IRQ) level" },
{ "GPLR0_20", 0x40E00000, 20, 0x00000001, 'd', "GPIO 20 (nc) level" },
{ "GPLR0_21", 0x40E00000, 21, 0x00000001, 'd', "GPIO 21 (AC97_IRQ) level" },
{ "GPLR0_22", 0x40E00000, 22, 0x00000001, 'd', "GPIO 22 (nPCC_S1_IRQ) level" },
{ "GPLR0_23", 0x40E00000, 23, 0x00000001, 'd', "GPIO 23 (UART_INTA) level" },
{ "GPLR0_24", 0x40E00000, 24, 0x00000001, 'd', "GPIO 24 (UART_INTB) level" },
{ "GPLR0_25", 0x40E00000, 25, 0x00000001, 'd', "GPIO 25 (UART_INTC) level" },
{ "GPLR0_26", 0x40E00000, 26, 0x00000001, 'd', "GPIO 26 (UART_INTD) level" },
{ "GPLR0_27", 0x40E00000, 27, 0x00000001, 'd', "GPIO 27 (nc CPLD_FREE) level" },
{ "GPLR0_28", 0x40E00000, 28, 0x00000001, 'd', "GPIO 28 (AUD_BITCLK) level" },
{ "GPLR0_29", 0x40E00000, 29, 0x00000001, 'd', "GPIO 29 (AUD_SDIN0) level" },
{ "GPLR0_30", 0x40E00000, 30, 0x00000001, 'd', "GPIO 30 (AUD_SDOUT) level" },
{ "GPLR0_31", 0x40E00000, 31, 0x00000001, 'd', "GPIO 31 (AUD_SYNC) level" },
#else
{ "GPLR0_0", 0x40E00000, 0, 0x00000001, 'd', "GPIO 0 level" },
{ "GPLR0_1", 0x40E00000, 1, 0x00000001, 'd', "GPIO 1 level" },
{ "GPLR0_2", 0x40E00000, 2, 0x00000001, 'd', "GPIO 2 level" },
{ "GPLR0_3", 0x40E00000, 3, 0x00000001, 'd', "GPIO 3 level" },
{ "GPLR0_4", 0x40E00000, 4, 0x00000001, 'd', "GPIO 4 level" },
{ "GPLR0_5", 0x40E00000, 5, 0x00000001, 'd', "GPIO 5 level" },
{ "GPLR0_6", 0x40E00000, 6, 0x00000001, 'd', "GPIO 6 level" },
{ "GPLR0_7", 0x40E00000, 7, 0x00000001, 'd', "GPIO 7 level" },
{ "GPLR0_8", 0x40E00000, 8, 0x00000001, 'd', "GPIO 8 level" },
{ "GPLR0_9", 0x40E00000, 9, 0x00000001, 'd', "GPIO 9 level" },
{ "GPLR0_10", 0x40E00000, 10, 0x00000001, 'd', "GPIO 10 level" },
{ "GPLR0_11", 0x40E00000, 11, 0x00000001, 'd', "GPIO 11 level" },
{ "GPLR0_12", 0x40E00000, 12, 0x00000001, 'd', "GPIO 12 level" },
{ "GPLR0_13", 0x40E00000, 13, 0x00000001, 'd', "GPIO 13 level" },
{ "GPLR0_14", 0x40E00000, 14, 0x00000001, 'd', "GPIO 14 level" },
{ "GPLR0_15", 0x40E00000, 15, 0x00000001, 'd', "GPIO 15 level" },
{ "GPLR0_16", 0x40E00000, 16, 0x00000001, 'd', "GPIO 16 level" },
{ "GPLR0_17", 0x40E00000, 17, 0x00000001, 'd', "GPIO 17 level" },
{ "GPLR0_18", 0x40E00000, 18, 0x00000001, 'd', "GPIO 18 level" },
{ "GPLR0_19", 0x40E00000, 19, 0x00000001, 'd', "GPIO 19 level" },
{ "GPLR0_20", 0x40E00000, 20, 0x00000001, 'd', "GPIO 20 level" },
{ "GPLR0_21", 0x40E00000, 21, 0x00000001, 'd', "GPIO 21 level" },
{ "GPLR0_22", 0x40E00000, 22, 0x00000001, 'd', "GPIO 22 level" },
{ "GPLR0_23", 0x40E00000, 23, 0x00000001, 'd', "GPIO 23 level" },
{ "GPLR0_24", 0x40E00000, 24, 0x00000001, 'd', "GPIO 24 level" },
{ "GPLR0_25", 0x40E00000, 25, 0x00000001, 'd', "GPIO 25 level" },
{ "GPLR0_26", 0x40E00000, 26, 0x00000001, 'd', "GPIO 26 level" },
{ "GPLR0_27", 0x40E00000, 27, 0x00000001, 'd', "GPIO 27 level" },
{ "GPLR0_28", 0x40E00000, 28, 0x00000001, 'd', "GPIO 28 level" },
{ "GPLR0_29", 0x40E00000, 29, 0x00000001, 'd', "GPIO 29 level" },
{ "GPLR0_30", 0x40E00000, 30, 0x00000001, 'd', "GPIO 30 level" },
{ "GPLR0_31", 0x40E00000, 31, 0x00000001, 'd', "GPIO 31 level" },
#endif
{ "GPLR1", 0x40E00004, 0, 0xffffffff, 'x', "GPIO Level Register 1 (4-8)" },
#if defined(CONFIG_ARCH_RAMSES)
{ "GPLR1_32", 0x40E00004, 0, 0x00000001, 'd', "GPIO 32 (AUD_SDIN1) level" },
{ "GPLR1_33", 0x40E00004, 1, 0x00000001, 'd', "GPIO 33 (nCS5) level" },
{ "GPLR1_34", 0x40E00004, 2, 0x00000001, 'd', "GPIO 34 (FF_RXD) level" },
{ "GPLR1_35", 0x40E00004, 3, 0x00000001, 'd', "GPIO 35 (FF_CTS) level" },
{ "GPLR1_36", 0x40E00004, 4, 0x00000001, 'd', "GPIO 36 (FF_DCD) level" },
{ "GPLR1_37", 0x40E00004, 5, 0x00000001, 'd', "GPIO 37 (FF_DSR) level" },
{ "GPLR1_38", 0x40E00004, 6, 0x00000001, 'd', "GPIO 38 (FF_RI) level" },
{ "GPLR1_39", 0x40E00004, 7, 0x00000001, 'd', "GPIO 39 (FF_TXD) level" },
{ "GPLR1_40", 0x40E00004, 8, 0x00000001, 'd', "GPIO 40 (FF_DTR) level" },
{ "GPLR1_41", 0x40E00004, 9, 0x00000001, 'd', "GPIO 41 (FF_RTS) level" },
{ "GPLR1_42", 0x40E00004, 10, 0x00000001, 'd', "GPIO 42 (BT_RXD) level" },
{ "GPLR1_43", 0x40E00004, 11, 0x00000001, 'd', "GPIO 43 (BT_TXD) level" },
{ "GPLR1_44", 0x40E00004, 12, 0x00000001, 'd', "GPIO 44 (BT_CTS) level" },
{ "GPLR1_45", 0x40E00004, 13, 0x00000001, 'd', "GPIO 45 (BT_RTS) level" },
{ "GPLR1_46", 0x40E00004, 14, 0x00000001, 'd', "GPIO 46 (IR_RXD) level" },
{ "GPLR1_47", 0x40E00004, 15, 0x00000001, 'd', "GPIO 47 (IR_TXD) level" },
{ "GPLR1_48", 0x40E00004, 16, 0x00000001, 'd', "GPIO 48 (nPOE) level" },
{ "GPLR1_49", 0x40E00004, 17, 0x00000001, 'd', "GPIO 49 (nPWE) level" },
{ "GPLR1_50", 0x40E00004, 18, 0x00000001, 'd', "GPIO 50 (nPIOR) level" },
{ "GPLR1_51", 0x40E00004, 19, 0x00000001, 'd', "GPIO 51 (nPIOW) level" },
{ "GPLR1_52", 0x40E00004, 20, 0x00000001, 'd', "GPIO 52 (nPCE1) level" },
{ "GPLR1_53", 0x40E00004, 21, 0x00000001, 'd', "GPIO 53 (nPCE2) level" },
{ "GPLR1_54", 0x40E00004, 22, 0x00000001, 'd', "GPIO 54 (nPKTSEL) level" },
{ "GPLR1_55", 0x40E00004, 23, 0x00000001, 'd', "GPIO 55 (nPREG) level" },
{ "GPLR1_56", 0x40E00004, 24, 0x00000001, 'd', "GPIO 56 (nPWAIT) level" },
{ "GPLR1_57", 0x40E00004, 25, 0x00000001, 'd', "GPIO 57 (nIOIS16) level" },
{ "GPLR1_58", 0x40E00004, 26, 0x00000001, 'd', "GPIO 58 (LDD0) level" },
{ "GPLR1_59", 0x40E00004, 27, 0x00000001, 'd', "GPIO 59 (LDD1) level" },
{ "GPLR1_60", 0x40E00004, 28, 0x00000001, 'd', "GPIO 60 (LDD2) level" },
{ "GPLR1_61", 0x40E00004, 29, 0x00000001, 'd', "GPIO 61 (LDD3) level" },
{ "GPLR1_62", 0x40E00004, 30, 0x00000001, 'd', "GPIO 62 (LDD4) level" },
{ "GPLR1_63", 0x40E00004, 31, 0x00000001, 'd', "GPIO 63 (LDD5) level" },
#else
{ "GPLR1_32", 0x40E00004, 0, 0x00000001, 'd', "GPIO 32 level" },
{ "GPLR1_33", 0x40E00004, 1, 0x00000001, 'd', "GPIO 33 level" },
{ "GPLR1_34", 0x40E00004, 2, 0x00000001, 'd', "GPIO 34 level" },
{ "GPLR1_35", 0x40E00004, 3, 0x00000001, 'd', "GPIO 35 level" },
{ "GPLR1_36", 0x40E00004, 4, 0x00000001, 'd', "GPIO 36 level" },
{ "GPLR1_37", 0x40E00004, 5, 0x00000001, 'd', "GPIO 37 level" },
{ "GPLR1_38", 0x40E00004, 6, 0x00000001, 'd', "GPIO 38 level" },
{ "GPLR1_39", 0x40E00004, 7, 0x00000001, 'd', "GPIO 39 level" },
{ "GPLR1_40", 0x40E00004, 8, 0x00000001, 'd', "GPIO 40 level" },
{ "GPLR1_41", 0x40E00004, 9, 0x00000001, 'd', "GPIO 41 level" },
{ "GPLR1_42", 0x40E00004, 10, 0x00000001, 'd', "GPIO 42 level" },
{ "GPLR1_43", 0x40E00004, 11, 0x00000001, 'd', "GPIO 43 level" },
{ "GPLR1_44", 0x40E00004, 12, 0x00000001, 'd', "GPIO 44 level" },
{ "GPLR1_45", 0x40E00004, 13, 0x00000001, 'd', "GPIO 45 level" },
{ "GPLR1_46", 0x40E00004, 14, 0x00000001, 'd', "GPIO 46 level" },
{ "GPLR1_47", 0x40E00004, 15, 0x00000001, 'd', "GPIO 47 level" },
{ "GPLR1_48", 0x40E00004, 16, 0x00000001, 'd', "GPIO 48 level" },
{ "GPLR1_49", 0x40E00004, 17, 0x00000001, 'd', "GPIO 49 level" },
{ "GPLR1_50", 0x40E00004, 18, 0x00000001, 'd', "GPIO 50 level" },
{ "GPLR1_51", 0x40E00004, 19, 0x00000001, 'd', "GPIO 51 level" },
{ "GPLR1_52", 0x40E00004, 20, 0x00000001, 'd', "GPIO 52 level" },
{ "GPLR1_53", 0x40E00004, 21, 0x00000001, 'd', "GPIO 53 level" },
{ "GPLR1_54", 0x40E00004, 22, 0x00000001, 'd', "GPIO 54 level" },
{ "GPLR1_55", 0x40E00004, 23, 0x00000001, 'd', "GPIO 55 level" },
{ "GPLR1_56", 0x40E00004, 24, 0x00000001, 'd', "GPIO 56 level" },
{ "GPLR1_57", 0x40E00004, 25, 0x00000001, 'd', "GPIO 57 level" },
{ "GPLR1_58", 0x40E00004, 26, 0x00000001, 'd', "GPIO 58 level" },
{ "GPLR1_59", 0x40E00004, 27, 0x00000001, 'd', "GPIO 59 level" },
{ "GPLR1_60", 0x40E00004, 28, 0x00000001, 'd', "GPIO 60 level" },
{ "GPLR1_61", 0x40E00004, 29, 0x00000001, 'd', "GPIO 61 level" },
{ "GPLR1_62", 0x40E00004, 30, 0x00000001, 'd', "GPIO 62 level" },
{ "GPLR1_63", 0x40E00004, 31, 0x00000001, 'd', "GPIO 63 level" },
#endif
{ "GPLR2", 0x40E00008, 0, 0xffffffff, 'x', "GPIO Level Register 2 (4-8)" },
#if defined(CONFIG_ARCH_RAMSES)
{ "GPLR2_64", 0x40E00008, 0, 0x00000001, 'd', "GPIO 64 (LDD6) level" },
{ "GPLR2_65", 0x40E00008, 1, 0x00000001, 'd', "GPIO 65 (LDD7) level" },
{ "GPLR2_66", 0x40E00008, 2, 0x00000001, 'd', "GPIO 66 (nc) level" },
{ "GPLR2_67", 0x40E00008, 3, 0x00000001, 'd', "GPIO 67 (nc) level" },
{ "GPLR2_68", 0x40E00008, 4, 0x00000001, 'd', "GPIO 68 (nc) level" },
{ "GPLR2_69", 0x40E00008, 5, 0x00000001, 'd', "GPIO 69 (nc) level" },
{ "GPLR2_70", 0x40E00008, 6, 0x00000001, 'd', "GPIO 70 (nc) level" },
{ "GPLR2_71", 0x40E00008, 7, 0x00000001, 'd', "GPIO 71 (nc) level" },
{ "GPLR2_72", 0x40E00008, 8, 0x00000001, 'd', "GPIO 72 (nc) level" },
{ "GPLR2_73", 0x40E00008, 9, 0x00000001, 'd', "GPIO 73 (nc) level" },
{ "GPLR2_74", 0x40E00008, 10, 0x00000001, 'd', "GPIO 74 (FCLK) level" },
{ "GPLR2_75", 0x40E00008, 11, 0x00000001, 'd', "GPIO 75 (LCLK) level" },
{ "GPLR2_76", 0x40E00008, 12, 0x00000001, 'd', "GPIO 76 (PCLK) level" },
{ "GPLR2_77", 0x40E00008, 13, 0x00000001, 'd', "GPIO 77 (BIAS) level" },
{ "GPLR2_78", 0x40E00008, 14, 0x00000001, 'd', "GPIO 78 (nCS2) level" },
{ "GPLR2_79", 0x40E00008, 15, 0x00000001, 'd', "GPIO 79 (nCS3) level" },
{ "GPLR2_80", 0x40E00008, 16, 0x00000001, 'd', "GPIO 80 (nCS4) level" },
{ "GPLR2_81", 0x40E00008, 17, 0x00000001, 'd', "GPIO 81 (nc) level" },
{ "GPLR2_82", 0x40E00008, 18, 0x00000001, 'd', "GPIO 82 (nc) level" },
{ "GPLR2_83", 0x40E00008, 19, 0x00000001, 'd', "GPIO 83 (nc) level" },
{ "GPLR2_84", 0x40E00008, 20, 0x00000001, 'd', "GPIO 84 (nc) level" },
#else
{ "GPLR2_64", 0x40E00008, 0, 0x00000001, 'd', "GPIO 64 level" },
{ "GPLR2_65", 0x40E00008, 1, 0x00000001, 'd', "GPIO 65 level" },
{ "GPLR2_66", 0x40E00008, 2, 0x00000001, 'd', "GPIO 66 level" },
{ "GPLR2_67", 0x40E00008, 3, 0x00000001, 'd', "GPIO 67 level" },
{ "GPLR2_68", 0x40E00008, 4, 0x00000001, 'd', "GPIO 68 level" },
{ "GPLR2_69", 0x40E00008, 5, 0x00000001, 'd', "GPIO 69 level" },
{ "GPLR2_70", 0x40E00008, 6, 0x00000001, 'd', "GPIO 70 level" },
{ "GPLR2_71", 0x40E00008, 7, 0x00000001, 'd', "GPIO 71 level" },
{ "GPLR2_72", 0x40E00008, 8, 0x00000001, 'd', "GPIO 72 level" },
{ "GPLR2_73", 0x40E00008, 9, 0x00000001, 'd', "GPIO 73 level" },
{ "GPLR2_74", 0x40E00008, 10, 0x00000001, 'd', "GPIO 74 level" },
{ "GPLR2_75", 0x40E00008, 11, 0x00000001, 'd', "GPIO 75 level" },
{ "GPLR2_76", 0x40E00008, 12, 0x00000001, 'd', "GPIO 76 level" },
{ "GPLR2_77", 0x40E00008, 13, 0x00000001, 'd', "GPIO 77 level" },
{ "GPLR2_78", 0x40E00008, 14, 0x00000001, 'd', "GPIO 78 level" },
{ "GPLR2_79", 0x40E00008, 15, 0x00000001, 'd', "GPIO 79 level" },
{ "GPLR2_80", 0x40E00008, 16, 0x00000001, 'd', "GPIO 80 level" },
{ "GPLR2_81", 0x40E00008, 17, 0x00000001, 'd', "GPIO 81 level" },
{ "GPLR2_82", 0x40E00008, 18, 0x00000001, 'd', "GPIO 82 level" },
{ "GPLR2_83", 0x40E00008, 19, 0x00000001, 'd', "GPIO 83 level" },
{ "GPLR2_84", 0x40E00008, 20, 0x00000001, 'd', "GPIO 84 level" },
#endif
{ "GPLR3", 0x40E00100, 0, 0xffffffff, 'x', "GPIO Level Register 2 (4-8)" },
{ "GPLR3_96", 0x40E00100, 0, 0x00000001, 'd', "GPIO 96 level" },
{ "GPLR3_97", 0x40E00100, 1, 0x00000001, 'd', "GPIO 97 level" },
{ "GPLR3_98", 0x40E00100, 2, 0x00000001, 'd', "GPIO 98 level" },
{ "GPLR3_99", 0x40E00100, 3, 0x00000001, 'd', "GPIO 99 level" },
{ "GPLR3_100", 0x40E00100, 4, 0x00000001, 'd', "GPIO 100 level" },
{ "GPLR3_101", 0x40E00100, 5, 0x00000001, 'd', "GPIO 101 level" },
{ "GPLR3_102", 0x40E00100, 6, 0x00000001, 'd', "GPIO 102 level" },
{ "GPLR3_103", 0x40E00100, 7, 0x00000001, 'd', "GPIO 103 level" },
{ "GPLR3_104", 0x40E00100, 8, 0x00000001, 'd', "GPIO 104 level" },
{ "GPLR3_105", 0x40E00100, 9, 0x00000001, 'd', "GPIO 105 level" },
{ "GPLR3_106", 0x40E00100, 10, 0x00000001, 'd', "GPIO 106 level" },
{ "GPLR3_107", 0x40E00100, 11, 0x00000001, 'd', "GPIO 107 level" },
{ "GPLR3_108", 0x40E00100, 12, 0x00000001, 'd', "GPIO 108 level" },
{ "GPLR3_109", 0x40E00100, 13, 0x00000001, 'd', "GPIO 109 level" },
{ "GPLR3_110", 0x40E00100, 14, 0x00000001, 'd', "GPIO 110 level" },
{ "GPLR3_111", 0x40E00100, 15, 0x00000001, 'd', "GPIO 111 level" },
{ "GPLR3_112", 0x40E00100, 16, 0x00000001, 'd', "GPIO 112 level" },
{ "GPLR3_113", 0x40E00100, 17, 0x00000001, 'd', "GPIO 113 level" },
{ "GPLR3_114", 0x40E00100, 18, 0x00000001, 'd', "GPIO 114 level" },
{ "GPLR3_115", 0x40E00100, 19, 0x00000001, 'd', "GPIO 115 level" },
{ "GPLR3_116", 0x40E00100, 20, 0x00000001, 'd', "GPIO 116 level" },
{ "GPLR3_117", 0x40E00100, 21, 0x00000001, 'd', "GPIO 117 level" },
{ "GPLR3_118", 0x40E00100, 22, 0x00000001, 'd', "GPIO 118 level" },
{ "GPLR3_119", 0x40E00100, 23, 0x00000001, 'd', "GPIO 119 level" },
{ "GPLR3_120", 0x40E00100, 24, 0x00000001, 'd', "GPIO 120 level" },
{ "GPLR3_121", 0x40E00100, 25, 0x00000001, 'd', "GPIO 121 level" },
{ "GPLR3_122", 0x40E00100, 26, 0x00000001, 'd', "GPIO 122 level" },
{ "GPLR3_123", 0x40E00100, 27, 0x00000001, 'd', "GPIO 123 level" },
{ "GPLR3_124", 0x40E00100, 28, 0x00000001, 'd', "GPIO 124 level" },
{ "GPLR3_125", 0x40E00100, 29, 0x00000001, 'd', "GPIO 125 level" },
{ "GPLR3_126", 0x40E00100, 30, 0x00000001, 'd', "GPIO 126 level" },
{ "GPLR3_127", 0x40E00100, 31, 0x00000001, 'd', "GPIO 127 level" },
{ "GPDR0", 0x40E0000C, 0, 0xffffffff, 'x', "GPIO Direction Register 0 (4-9)" },
{ "GPDR0_0", 0x40E0000C, 0, 0x00000001, 'd', "GPIO 0 i/o direction (1=output)" },
{ "GPDR0_1", 0x40E0000C, 1, 0x00000001, 'd', "GPIO 1 i/o direction (1=output)" },
{ "GPDR0_2", 0x40E0000C, 2, 0x00000001, 'd', "GPIO 2 i/o direction (1=output)" },
{ "GPDR0_3", 0x40E0000C, 3, 0x00000001, 'd', "GPIO 3 i/o direction (1=output)" },
{ "GPDR0_4", 0x40E0000C, 4, 0x00000001, 'd', "GPIO 4 i/o direction (1=output)" },
{ "GPDR0_5", 0x40E0000C, 5, 0x00000001, 'd', "GPIO 5 i/o direction (1=output)" },
{ "GPDR0_6", 0x40E0000C, 6, 0x00000001, 'd', "GPIO 6 i/o direction (1=output)" },
{ "GPDR0_7", 0x40E0000C, 7, 0x00000001, 'd', "GPIO 7 i/o direction (1=output)" },
{ "GPDR0_8", 0x40E0000C, 8, 0x00000001, 'd', "GPIO 8 i/o direction (1=output)" },
{ "GPDR0_9", 0x40E0000C, 9, 0x00000001, 'd', "GPIO 9 i/o direction (1=output)" },
{ "GPDR0_10", 0x40E0000C, 10, 0x00000001, 'd', "GPIO 10 i/o direction (1=output)" },
{ "GPDR0_11", 0x40E0000C, 11, 0x00000001, 'd', "GPIO 11 i/o direction (1=output)" },
{ "GPDR0_12", 0x40E0000C, 12, 0x00000001, 'd', "GPIO 12 i/o direction (1=output)" },
{ "GPDR0_13", 0x40E0000C, 13, 0x00000001, 'd', "GPIO 13 i/o direction (1=output)" },
{ "GPDR0_14", 0x40E0000C, 14, 0x00000001, 'd', "GPIO 14 i/o direction (1=output)" },
{ "GPDR0_15", 0x40E0000C, 15, 0x00000001, 'd', "GPIO 15 i/o direction (1=output)" },
{ "GPDR0_16", 0x40E0000C, 16, 0x00000001, 'd', "GPIO 16 i/o direction (1=output)" },
{ "GPDR0_17", 0x40E0000C, 17, 0x00000001, 'd', "GPIO 17 i/o direction (1=output)" },
{ "GPDR0_18", 0x40E0000C, 18, 0x00000001, 'd', "GPIO 18 i/o direction (1=output)" },
{ "GPDR0_19", 0x40E0000C, 19, 0x00000001, 'd', "GPIO 19 i/o direction (1=output)" },
{ "GPDR0_20", 0x40E0000C, 20, 0x00000001, 'd', "GPIO 20 i/o direction (1=output)" },
{ "GPDR0_21", 0x40E0000C, 21, 0x00000001, 'd', "GPIO 21 i/o direction (1=output)" },
{ "GPDR0_22", 0x40E0000C, 22, 0x00000001, 'd', "GPIO 22 i/o direction (1=output)" },
{ "GPDR0_23", 0x40E0000C, 23, 0x00000001, 'd', "GPIO 23 i/o direction (1=output)" },
{ "GPDR0_24", 0x40E0000C, 24, 0x00000001, 'd', "GPIO 24 i/o direction (1=output)" },
{ "GPDR0_25", 0x40E0000C, 25, 0x00000001, 'd', "GPIO 25 i/o direction (1=output)" },
{ "GPDR0_26", 0x40E0000C, 26, 0x00000001, 'd', "GPIO 26 i/o direction (1=output)" },
{ "GPDR0_27", 0x40E0000C, 27, 0x00000001, 'd', "GPIO 27 i/o direction (1=output)" },
{ "GPDR0_28", 0x40E0000C, 28, 0x00000001, 'd', "GPIO 28 i/o direction (1=output)" },
{ "GPDR0_29", 0x40E0000C, 29, 0x00000001, 'd', "GPIO 29 i/o direction (1=output)" },
{ "GPDR0_30", 0x40E0000C, 30, 0x00000001, 'd', "GPIO 30 i/o direction (1=output)" },
{ "GPDR0_31", 0x40E0000C, 31, 0x00000001, 'd', "GPIO 31 i/o direction (1=output)" },
{ "GPDR1", 0x40E00010, 0, 0xffffffff, 'x', "GPIO Direction Register 1 (4-9)" },
{ "GPDR1_32", 0x40E00010, 0, 0x00000001, 'd', "GPIO 32 i/o direction (1=output)" },
{ "GPDR1_33", 0x40E00010, 1, 0x00000001, 'd', "GPIO 33 i/o direction (1=output)" },
{ "GPDR1_34", 0x40E00010, 2, 0x00000001, 'd', "GPIO 34 i/o direction (1=output)" },
{ "GPDR1_35", 0x40E00010, 3, 0x00000001, 'd', "GPIO 35 i/o direction (1=output)" },
{ "GPDR1_36", 0x40E00010, 4, 0x00000001, 'd', "GPIO 36 i/o direction (1=output)" },
{ "GPDR1_37", 0x40E00010, 5, 0x00000001, 'd', "GPIO 37 i/o direction (1=output)" },
{ "GPDR1_38", 0x40E00010, 6, 0x00000001, 'd', "GPIO 38 i/o direction (1=output)" },
{ "GPDR1_39", 0x40E00010, 7, 0x00000001, 'd', "GPIO 39 i/o direction (1=output)" },
{ "GPDR1_40", 0x40E00010, 8, 0x00000001, 'd', "GPIO 40 i/o direction (1=output)" },
{ "GPDR1_41", 0x40E00010, 9, 0x00000001, 'd', "GPIO 41 i/o direction (1=output)" },
{ "GPDR1_42", 0x40E00010, 10, 0x00000001, 'd', "GPIO 42 i/o direction (1=output)" },
{ "GPDR1_43", 0x40E00010, 11, 0x00000001, 'd', "GPIO 43 i/o direction (1=output)" },
{ "GPDR1_44", 0x40E00010, 12, 0x00000001, 'd', "GPIO 44 i/o direction (1=output)" },
{ "GPDR1_45", 0x40E00010, 13, 0x00000001, 'd', "GPIO 45 i/o direction (1=output)" },
{ "GPDR1_46", 0x40E00010, 14, 0x00000001, 'd', "GPIO 46 i/o direction (1=output)" },
{ "GPDR1_47", 0x40E00010, 15, 0x00000001, 'd', "GPIO 47 i/o direction (1=output)" },
{ "GPDR1_48", 0x40E00010, 16, 0x00000001, 'd', "GPIO 48 i/o direction (1=output)" },
{ "GPDR1_49", 0x40E00010, 17, 0x00000001, 'd', "GPIO 49 i/o direction (1=output)" },
{ "GPDR1_50", 0x40E00010, 18, 0x00000001, 'd', "GPIO 50 i/o direction (1=output)" },
{ "GPDR1_51", 0x40E00010, 19, 0x00000001, 'd', "GPIO 51 i/o direction (1=output)" },
{ "GPDR1_52", 0x40E00010, 20, 0x00000001, 'd', "GPIO 52 i/o direction (1=output)" },
{ "GPDR1_53", 0x40E00010, 21, 0x00000001, 'd', "GPIO 53 i/o direction (1=output)" },
{ "GPDR1_54", 0x40E00010, 22, 0x00000001, 'd', "GPIO 54 i/o direction (1=output)" },
{ "GPDR1_55", 0x40E00010, 23, 0x00000001, 'd', "GPIO 55 i/o direction (1=output)" },
{ "GPDR1_56", 0x40E00010, 24, 0x00000001, 'd', "GPIO 56 i/o direction (1=output)" },
{ "GPDR1_57", 0x40E00010, 25, 0x00000001, 'd', "GPIO 57 i/o direction (1=output)" },
{ "GPDR1_58", 0x40E00010, 26, 0x00000001, 'd', "GPIO 58 i/o direction (1=output)" },
{ "GPDR1_59", 0x40E00010, 27, 0x00000001, 'd', "GPIO 59 i/o direction (1=output)" },
{ "GPDR1_60", 0x40E00010, 28, 0x00000001, 'd', "GPIO 60 i/o direction (1=output)" },
{ "GPDR1_61", 0x40E00010, 29, 0x00000001, 'd', "GPIO 61 i/o direction (1=output)" },
{ "GPDR1_62", 0x40E00010, 30, 0x00000001, 'd', "GPIO 62 i/o direction (1=output)" },
{ "GPDR1_63", 0x40E00010, 31, 0x00000001, 'd', "GPIO 63 i/o direction (1=output)" },
{ "GPDR2", 0x40E00014, 0, 0xffffffff, 'x', "GPIO Direction Register 2 (4-9)" },
{ "GPDR2_64", 0x40E00014, 0, 0x00000001, 'd', "GPIO 64 i/o direction (1=output)" },
{ "GPDR2_65", 0x40E00014, 1, 0x00000001, 'd', "GPIO 65 i/o direction (1=output)" },
{ "GPDR2_66", 0x40E00014, 2, 0x00000001, 'd', "GPIO 66 i/o direction (1=output)" },
{ "GPDR2_67", 0x40E00014, 3, 0x00000001, 'd', "GPIO 67 i/o direction (1=output)" },
{ "GPDR2_68", 0x40E00014, 4, 0x00000001, 'd', "GPIO 68 i/o direction (1=output)" },
{ "GPDR2_69", 0x40E00014, 5, 0x00000001, 'd', "GPIO 69 i/o direction (1=output)" },
{ "GPDR2_70", 0x40E00014, 6, 0x00000001, 'd', "GPIO 70 i/o direction (1=output)" },
{ "GPDR2_71", 0x40E00014, 7, 0x00000001, 'd', "GPIO 71 i/o direction (1=output)" },
{ "GPDR2_72", 0x40E00014, 8, 0x00000001, 'd', "GPIO 72 i/o direction (1=output)" },
{ "GPDR2_73", 0x40E00014, 9, 0x00000001, 'd', "GPIO 73 i/o direction (1=output)" },
{ "GPDR2_74", 0x40E00014, 10, 0x00000001, 'd', "GPIO 74 i/o direction (1=output)" },
{ "GPDR2_75", 0x40E00014, 11, 0x00000001, 'd', "GPIO 75 i/o direction (1=output)" },
{ "GPDR2_76", 0x40E00014, 12, 0x00000001, 'd', "GPIO 76 i/o direction (1=output)" },
{ "GPDR2_77", 0x40E00014, 13, 0x00000001, 'd', "GPIO 77 i/o direction (1=output)" },
{ "GPDR2_78", 0x40E00014, 14, 0x00000001, 'd', "GPIO 78 i/o direction (1=output)" },
{ "GPDR2_79", 0x40E00014, 15, 0x00000001, 'd', "GPIO 79 i/o direction (1=output)" },
{ "GPDR2_80", 0x40E00014, 16, 0x00000001, 'd', "GPIO 80 i/o direction (1=output)" },
{ "GPDR2_81", 0x40E00014, 17, 0x00000001, 'd', "GPIO 81 i/o direction (1=output)" },
{ "GPDR2_82", 0x40E00014, 18, 0x00000001, 'd', "GPIO 82 i/o direction (1=output)" },
{ "GPDR2_83", 0x40E00014, 19, 0x00000001, 'd', "GPIO 83 i/o direction (1=output)" },
{ "GPDR2_84", 0x40E00014, 20, 0x00000001, 'd', "GPIO 84 i/o direction (1=output)" },
{ "GPDR3", 0x40E0010C, 0, 0xffffffff, 'x', "GPIO Direction Register 2 (4-9)" },
{ "GPDR3_96", 0x40E0010C, 0, 0x00000001, 'd', "GPIO 96 i/o direction (1=output)" },
{ "GPDR3_97", 0x40E0010C, 1, 0x00000001, 'd', "GPIO 97 i/o direction (1=output)" },
{ "GPDR3_98", 0x40E0010C, 2, 0x00000001, 'd', "GPIO 98 i/o direction (1=output)" },
{ "GPDR3_99", 0x40E0010C, 3, 0x00000001, 'd', "GPIO 99 i/o direction (1=output)" },
{ "GPDR3_100", 0x40E0010C, 4, 0x00000001, 'd', "GPIO 100 i/o direction (1=output)" },
{ "GPDR3_101", 0x40E0010C, 5, 0x00000001, 'd', "GPIO 101 i/o direction (1=output)" },
{ "GPDR3_102", 0x40E0010C, 6, 0x00000001, 'd', "GPIO 102 i/o direction (1=output)" },
{ "GPDR3_103", 0x40E0010C, 7, 0x00000001, 'd', "GPIO 103 i/o direction (1=output)" },
{ "GPDR3_104", 0x40E0010C, 8, 0x00000001, 'd', "GPIO 104 i/o direction (1=output)" },
{ "GPDR3_105", 0x40E0010C, 9, 0x00000001, 'd', "GPIO 105 i/o direction (1=output)" },
{ "GPDR3_106", 0x40E0010C, 10, 0x00000001, 'd', "GPIO 106 i/o direction (1=output)" },
{ "GPDR3_107", 0x40E0010C, 11, 0x00000001, 'd', "GPIO 107 i/o direction (1=output)" },
{ "GPDR3_108", 0x40E0010C, 12, 0x00000001, 'd', "GPIO 108 i/o direction (1=output)" },
{ "GPDR3_109", 0x40E0010C, 13, 0x00000001, 'd', "GPIO 109 i/o direction (1=output)" },
{ "GPDR3_110", 0x40E0010C, 14, 0x00000001, 'd', "GPIO 110 i/o direction (1=output)" },
{ "GPDR3_111", 0x40E0010C, 15, 0x00000001, 'd', "GPIO 111 i/o direction (1=output)" },
{ "GPDR3_112", 0x40E0010C, 16, 0x00000001, 'd', "GPIO 112 i/o direction (1=output)" },
{ "GPDR3_113", 0x40E0010C, 17, 0x00000001, 'd', "GPIO 113 i/o direction (1=output)" },
{ "GPDR3_114", 0x40E0010C, 18, 0x00000001, 'd', "GPIO 114 i/o direction (1=output)" },
{ "GPDR3_115", 0x40E0010C, 19, 0x00000001, 'd', "GPIO 115 i/o direction (1=output)" },
{ "GPDR3_116", 0x40E0010C, 20, 0x00000001, 'd', "GPIO 116 i/o direction (1=output)" },
{ "GPDR3_117", 0x40E0010C, 21, 0x00000001, 'd', "GPIO 117 i/o direction (1=output)" },
{ "GPDR3_118", 0x40E0010C, 22, 0x00000001, 'd', "GPIO 118 i/o direction (1=output)" },
{ "GPDR3_119", 0x40E0010C, 23, 0x00000001, 'd', "GPIO 119 i/o direction (1=output)" },
{ "GPDR3_120", 0x40E0010C, 24, 0x00000001, 'd', "GPIO 120 i/o direction (1=output)" },
{ "GPDR3_121", 0x40E0010C, 25, 0x00000001, 'd', "GPIO 121 i/o direction (1=output)" },
{ "GPDR3_122", 0x40E0010C, 26, 0x00000001, 'd', "GPIO 122 i/o direction (1=output)" },
{ "GPDR3_123", 0x40E0010C, 27, 0x00000001, 'd', "GPIO 123 i/o direction (1=output)" },
{ "GPDR3_124", 0x40E0010C, 28, 0x00000001, 'd', "GPIO 124 i/o direction (1=output)" },
{ "GPDR3_125", 0x40E0010C, 29, 0x00000001, 'd', "GPIO 125 i/o direction (1=output)" },
{ "GPDR3_126", 0x40E0010C, 30, 0x00000001, 'd', "GPIO 126 i/o direction (1=output)" },
{ "GPDR3_127", 0x40E0010C, 31, 0x00000001, 'd', "GPIO 127 i/o direction (1=output)" },
{ "GPSR0", 0x40E00018, 0, 0xffffffff, 'x', "GPIO Set Register 0 (4-10)" },
{ "GPSR0_0", 0x40E00018, 0, 0x00000001, 'd', "GPIO 0 set" },
{ "GPSR0_1", 0x40E00018, 1, 0x00000001, 'd', "GPIO 1 set" },
{ "GPSR0_2", 0x40E00018, 2, 0x00000001, 'd', "GPIO 2 set" },
{ "GPSR0_3", 0x40E00018, 3, 0x00000001, 'd', "GPIO 3 set" },
{ "GPSR0_4", 0x40E00018, 4, 0x00000001, 'd', "GPIO 4 set" },
{ "GPSR0_5", 0x40E00018, 5, 0x00000001, 'd', "GPIO 5 set" },
{ "GPSR0_6", 0x40E00018, 6, 0x00000001, 'd', "GPIO 6 set" },
{ "GPSR0_7", 0x40E00018, 7, 0x00000001, 'd', "GPIO 7 set" },
{ "GPSR0_8", 0x40E00018, 8, 0x00000001, 'd', "GPIO 8 set" },
{ "GPSR0_9", 0x40E00018, 9, 0x00000001, 'd', "GPIO 9 set" },
{ "GPSR0_10", 0x40E00018, 10, 0x00000001, 'd', "GPIO 10 set" },
{ "GPSR0_11", 0x40E00018, 11, 0x00000001, 'd', "GPIO 11 set" },
{ "GPSR0_12", 0x40E00018, 12, 0x00000001, 'd', "GPIO 12 set" },
{ "GPSR0_13", 0x40E00018, 13, 0x00000001, 'd', "GPIO 13 set" },
{ "GPSR0_14", 0x40E00018, 14, 0x00000001, 'd', "GPIO 14 set" },
{ "GPSR0_15", 0x40E00018, 15, 0x00000001, 'd', "GPIO 15 set" },
{ "GPSR0_16", 0x40E00018, 16, 0x00000001, 'd', "GPIO 16 set" },
{ "GPSR0_17", 0x40E00018, 17, 0x00000001, 'd', "GPIO 17 set" },
{ "GPSR0_18", 0x40E00018, 18, 0x00000001, 'd', "GPIO 18 set" },
{ "GPSR0_19", 0x40E00018, 19, 0x00000001, 'd', "GPIO 19 set" },
{ "GPSR0_20", 0x40E00018, 20, 0x00000001, 'd', "GPIO 20 set" },
{ "GPSR0_21", 0x40E00018, 21, 0x00000001, 'd', "GPIO 21 set" },
{ "GPSR0_22", 0x40E00018, 22, 0x00000001, 'd', "GPIO 22 set" },
{ "GPSR0_23", 0x40E00018, 23, 0x00000001, 'd', "GPIO 23 set" },
{ "GPSR0_24", 0x40E00018, 24, 0x00000001, 'd', "GPIO 24 set" },
{ "GPSR0_25", 0x40E00018, 25, 0x00000001, 'd', "GPIO 25 set" },
{ "GPSR0_26", 0x40E00018, 26, 0x00000001, 'd', "GPIO 26 set" },
{ "GPSR0_27", 0x40E00018, 27, 0x00000001, 'd', "GPIO 27 set" },
{ "GPSR0_28", 0x40E00018, 28, 0x00000001, 'd', "GPIO 28 set" },
{ "GPSR0_29", 0x40E00018, 29, 0x00000001, 'd', "GPIO 29 set" },
{ "GPSR0_30", 0x40E00018, 30, 0x00000001, 'd', "GPIO 30 set" },
{ "GPSR0_31", 0x40E00018, 31, 0x00000001, 'd', "GPIO 31 set" },
{ "GPSR1", 0x40E0001C, 0, 0xffffffff, 'x', "GPIO Set Register 1 (4-10)" },
{ "GPSR1_32", 0x40E0001C, 0, 0x00000001, 'd', "GPIO 32 set" },
{ "GPSR1_33", 0x40E0001C, 1, 0x00000001, 'd', "GPIO 33 set" },
{ "GPSR1_34", 0x40E0001C, 2, 0x00000001, 'd', "GPIO 34 set" },
{ "GPSR1_35", 0x40E0001C, 3, 0x00000001, 'd', "GPIO 35 set" },
{ "GPSR1_36", 0x40E0001C, 4, 0x00000001, 'd', "GPIO 36 set" },
{ "GPSR1_37", 0x40E0001C, 5, 0x00000001, 'd', "GPIO 37 set" },
{ "GPSR1_38", 0x40E0001C, 6, 0x00000001, 'd', "GPIO 38 set" },
{ "GPSR1_39", 0x40E0001C, 7, 0x00000001, 'd', "GPIO 39 set" },
{ "GPSR1_40", 0x40E0001C, 8, 0x00000001, 'd', "GPIO 40 set" },
{ "GPSR1_41", 0x40E0001C, 9, 0x00000001, 'd', "GPIO 41 set" },
{ "GPSR1_42", 0x40E0001C, 10, 0x00000001, 'd', "GPIO 42 set" },
{ "GPSR1_43", 0x40E0001C, 11, 0x00000001, 'd', "GPIO 43 set" },
{ "GPSR1_44", 0x40E0001C, 12, 0x00000001, 'd', "GPIO 44 set" },
{ "GPSR1_45", 0x40E0001C, 13, 0x00000001, 'd', "GPIO 45 set" },
{ "GPSR1_46", 0x40E0001C, 14, 0x00000001, 'd', "GPIO 46 set" },
{ "GPSR1_47", 0x40E0001C, 15, 0x00000001, 'd', "GPIO 47 set" },
{ "GPSR1_48", 0x40E0001C, 16, 0x00000001, 'd', "GPIO 48 set" },
{ "GPSR1_49", 0x40E0001C, 17, 0x00000001, 'd', "GPIO 49 set" },
{ "GPSR1_50", 0x40E0001C, 18, 0x00000001, 'd', "GPIO 50 set" },
{ "GPSR1_51", 0x40E0001C, 19, 0x00000001, 'd', "GPIO 51 set" },
{ "GPSR1_52", 0x40E0001C, 20, 0x00000001, 'd', "GPIO 52 set" },
{ "GPSR1_53", 0x40E0001C, 21, 0x00000001, 'd', "GPIO 53 set" },
{ "GPSR1_54", 0x40E0001C, 22, 0x00000001, 'd', "GPIO 54 set" },
{ "GPSR1_55", 0x40E0001C, 23, 0x00000001, 'd', "GPIO 55 set" },
{ "GPSR1_56", 0x40E0001C, 24, 0x00000001, 'd', "GPIO 56 set" },
{ "GPSR1_57", 0x40E0001C, 25, 0x00000001, 'd', "GPIO 57 set" },
{ "GPSR1_58", 0x40E0001C, 26, 0x00000001, 'd', "GPIO 58 set" },
{ "GPSR1_59", 0x40E0001C, 27, 0x00000001, 'd', "GPIO 59 set" },
{ "GPSR1_60", 0x40E0001C, 28, 0x00000001, 'd', "GPIO 60 set" },
{ "GPSR1_61", 0x40E0001C, 29, 0x00000001, 'd', "GPIO 61 set" },
{ "GPSR1_62", 0x40E0001C, 30, 0x00000001, 'd', "GPIO 62 set" },
{ "GPSR1_63", 0x40E0001C, 31, 0x00000001, 'd', "GPIO 63 set" },
{ "GPSR2", 0x40E00020, 0, 0xffffffff, 'x', "GPIO Set Register 2 (4-11)" },
{ "GPSR2_64", 0x40E00020, 0, 0x00000001, 'd', "GPIO 64 set" },
{ "GPSR2_65", 0x40E00020, 1, 0x00000001, 'd', "GPIO 65 set" },
{ "GPSR2_66", 0x40E00020, 2, 0x00000001, 'd', "GPIO 66 set" },
{ "GPSR2_67", 0x40E00020, 3, 0x00000001, 'd', "GPIO 67 set" },
{ "GPSR2_68", 0x40E00020, 4, 0x00000001, 'd', "GPIO 68 set" },
{ "GPSR2_69", 0x40E00020, 5, 0x00000001, 'd', "GPIO 69 set" },
{ "GPSR2_70", 0x40E00020, 6, 0x00000001, 'd', "GPIO 70 set" },
{ "GPSR2_71", 0x40E00020, 7, 0x00000001, 'd', "GPIO 71 set" },
{ "GPSR2_72", 0x40E00020, 8, 0x00000001, 'd', "GPIO 72 set" },
{ "GPSR2_73", 0x40E00020, 9, 0x00000001, 'd', "GPIO 73 set" },
{ "GPSR2_74", 0x40E00020, 10, 0x00000001, 'd', "GPIO 74 set" },
{ "GPSR2_75", 0x40E00020, 11, 0x00000001, 'd', "GPIO 75 set" },
{ "GPSR2_76", 0x40E00020, 12, 0x00000001, 'd', "GPIO 76 set" },
{ "GPSR2_77", 0x40E00020, 13, 0x00000001, 'd', "GPIO 77 set" },
{ "GPSR2_78", 0x40E00020, 14, 0x00000001, 'd', "GPIO 78 set" },
{ "GPSR2_79", 0x40E00020, 15, 0x00000001, 'd', "GPIO 79 set" },
{ "GPSR2_80", 0x40E00020, 16, 0x00000001, 'd', "GPIO 80 set" },
{ "GPSR2_81", 0x40E00020, 17, 0x00000001, 'd', "GPIO 81 set" },
{ "GPSR2_82", 0x40E00020, 18, 0x00000001, 'd', "GPIO 82 set" },
{ "GPSR2_83", 0x40E00020, 19, 0x00000001, 'd', "GPIO 83 set" },
{ "GPSR2_84", 0x40E00020, 20, 0x00000001, 'd', "GPIO 84 set" },
{ "GPSR2_85", 0x40E00020, 21, 0x00000001, 'd', "GPIO 85 set" },
{ "GPSR2_86", 0x40E00020, 22, 0x00000001, 'd', "GPIO 86 set" },
{ "GPSR2_87", 0x40E00020, 23, 0x00000001, 'd', "GPIO 87 set" },
{ "GPSR2_88", 0x40E00020, 24, 0x00000001, 'd', "GPIO 88 set" },
{ "GPSR2_89", 0x40E00020, 25, 0x00000001, 'd', "GPIO 89 set" },
{ "GPSR2_90", 0x40E00020, 26, 0x00000001, 'd', "GPIO 90 set" },
{ "GPSR2_91", 0x40E00020, 27, 0x00000001, 'd', "GPIO 91 set" },
{ "GPSR2_92", 0x40E00020, 28, 0x00000001, 'd', "GPIO 92 set" },
{ "GPSR2_93", 0x40E00020, 29, 0x00000001, 'd', "GPIO 93 set" },
{ "GPSR2_94", 0x40E00020, 30, 0x00000001, 'd', "GPIO 94 set" },
{ "GPSR2_95", 0x40E00020, 31, 0x00000001, 'd', "GPIO 95 set" },
{ "GPSR3", 0x40E00118, 0, 0xffffffff, 'x', "GPIO Set Register 3 (4-11)" },
{ "GPSR3_96", 0x40E00118, 0, 0x00000001, 'd', "GPIO 96 set" },
{ "GPSR3_97", 0x40E00118, 1, 0x00000001, 'd', "GPIO 97 set" },
{ "GPSR3_98", 0x40E00118, 2, 0x00000001, 'd', "GPIO 98 set" },
{ "GPSR3_99", 0x40E00118, 3, 0x00000001, 'd', "GPIO 99 set" },
{ "GPSR3_100", 0x40E00118, 4, 0x00000001, 'd', "GPIO 100 set" },
{ "GPSR3_101", 0x40E00118, 5, 0x00000001, 'd', "GPIO 101 set" },
{ "GPSR3_102", 0x40E00118, 6, 0x00000001, 'd', "GPIO 102 set" },
{ "GPSR3_103", 0x40E00118, 7, 0x00000001, 'd', "GPIO 103 set" },
{ "GPSR3_104", 0x40E00118, 8, 0x00000001, 'd', "GPIO 104 set" },
{ "GPSR3_105", 0x40E00118, 9, 0x00000001, 'd', "GPIO 105 set" },
{ "GPSR3_106", 0x40E00118, 10, 0x00000001, 'd', "GPIO 106 set" },
{ "GPSR3_107", 0x40E00118, 11, 0x00000001, 'd', "GPIO 107 set" },
{ "GPSR3_108", 0x40E00118, 12, 0x00000001, 'd', "GPIO 108 set" },
{ "GPSR3_109", 0x40E00118, 13, 0x00000001, 'd', "GPIO 109 set" },
{ "GPSR3_110", 0x40E00118, 14, 0x00000001, 'd', "GPIO 110 set" },
{ "GPSR3_111", 0x40E00118, 15, 0x00000001, 'd', "GPIO 111 set" },
{ "GPSR3_112", 0x40E00118, 16, 0x00000001, 'd', "GPIO 112 set" },
{ "GPSR3_113", 0x40E00118, 17, 0x00000001, 'd', "GPIO 113 set" },
{ "GPSR3_114", 0x40E00118, 18, 0x00000001, 'd', "GPIO 114 set" },
{ "GPSR3_115", 0x40E00118, 19, 0x00000001, 'd', "GPIO 115 set" },
{ "GPSR3_116", 0x40E00118, 20, 0x00000001, 'd', "GPIO 116 set" },
{ "GPSR3_117", 0x40E00118, 21, 0x00000001, 'd', "GPIO 117 set" },
{ "GPSR3_118", 0x40E00118, 22, 0x00000001, 'd', "GPIO 118 set" },
{ "GPSR3_119", 0x40E00118, 23, 0x00000001, 'd', "GPIO 119 set" },
{ "GPSR3_120", 0x40E00118, 24, 0x00000001, 'd', "GPIO 120 set" },
{ "GPSR3_121", 0x40E00118, 25, 0x00000001, 'd', "GPIO 121 set" },
{ "GPSR3_122", 0x40E00118, 26, 0x00000001, 'd', "GPIO 122 set" },
{ "GPSR3_123", 0x40E00118, 27, 0x00000001, 'd', "GPIO 123 set" },
{ "GPSR3_124", 0x40E00118, 28, 0x00000001, 'd', "GPIO 124 set" },
{ "GPSR3_125", 0x40E00118, 29, 0x00000001, 'd', "GPIO 125 set" },
{ "GPSR3_126", 0x40E00118, 30, 0x00000001, 'd', "GPIO 126 set" },
{ "GPSR3_127", 0x40E00118, 31, 0x00000001, 'd', "GPIO 127 set" },
{ "GPCR0", 0x40E00024, 0, 0xffffffff, 'x', "GPIO Clear Register 0 (4-11)" },
{ "GPCR0_0", 0x40E00024, 0, 0x00000001, 'd', "GPIO 0 clear" },
{ "GPCR0_1", 0x40E00024, 1, 0x00000001, 'd', "GPIO 1 clear" },
{ "GPCR0_2", 0x40E00024, 2, 0x00000001, 'd', "GPIO 2 clear" },
{ "GPCR0_3", 0x40E00024, 3, 0x00000001, 'd', "GPIO 3 clear" },
{ "GPCR0_4", 0x40E00024, 4, 0x00000001, 'd', "GPIO 4 clear" },
{ "GPCR0_5", 0x40E00024, 5, 0x00000001, 'd', "GPIO 5 clear" },
{ "GPCR0_6", 0x40E00024, 6, 0x00000001, 'd', "GPIO 6 clear" },
{ "GPCR0_7", 0x40E00024, 7, 0x00000001, 'd', "GPIO 7 clear" },
{ "GPCR0_8", 0x40E00024, 8, 0x00000001, 'd', "GPIO 8 clear" },
{ "GPCR0_9", 0x40E00024, 9, 0x00000001, 'd', "GPIO 9 clear" },
{ "GPCR0_10", 0x40E00024, 10, 0x00000001, 'd', "GPIO 10 clear" },
{ "GPCR0_11", 0x40E00024, 11, 0x00000001, 'd', "GPIO 11 clear" },
{ "GPCR0_12", 0x40E00024, 12, 0x00000001, 'd', "GPIO 12 clear" },
{ "GPCR0_13", 0x40E00024, 13, 0x00000001, 'd', "GPIO 13 clear" },
{ "GPCR0_14", 0x40E00024, 14, 0x00000001, 'd', "GPIO 14 clear" },
{ "GPCR0_15", 0x40E00024, 15, 0x00000001, 'd', "GPIO 15 clear" },
{ "GPCR0_16", 0x40E00024, 16, 0x00000001, 'd', "GPIO 16 clear" },
{ "GPCR0_17", 0x40E00024, 17, 0x00000001, 'd', "GPIO 17 clear" },
{ "GPCR0_18", 0x40E00024, 18, 0x00000001, 'd', "GPIO 18 clear" },
{ "GPCR0_19", 0x40E00024, 19, 0x00000001, 'd', "GPIO 19 clear" },
{ "GPCR0_20", 0x40E00024, 20, 0x00000001, 'd', "GPIO 20 clear" },
{ "GPCR0_21", 0x40E00024, 21, 0x00000001, 'd', "GPIO 21 clear" },
{ "GPCR0_22", 0x40E00024, 22, 0x00000001, 'd', "GPIO 22 clear" },
{ "GPCR0_23", 0x40E00024, 23, 0x00000001, 'd', "GPIO 23 clear" },
{ "GPCR0_24", 0x40E00024, 24, 0x00000001, 'd', "GPIO 24 clear" },
{ "GPCR0_25", 0x40E00024, 25, 0x00000001, 'd', "GPIO 25 clear" },
{ "GPCR0_26", 0x40E00024, 26, 0x00000001, 'd', "GPIO 26 clear" },
{ "GPCR0_27", 0x40E00024, 27, 0x00000001, 'd', "GPIO 27 clear" },
{ "GPCR0_28", 0x40E00024, 28, 0x00000001, 'd', "GPIO 28 clear" },
{ "GPCR0_29", 0x40E00024, 29, 0x00000001, 'd', "GPIO 29 clear" },
{ "GPCR0_30", 0x40E00024, 30, 0x00000001, 'd', "GPIO 30 clear" },
{ "GPCR0_31", 0x40E00024, 31, 0x00000001, 'd', "GPIO 31 clear" },
{ "GPCR1", 0x40E00028, 0, 0xffffffff, 'x', "GPIO Clear Register 1 (4-11)" },
{ "GPCR1_32", 0x40E00028, 0, 0x00000001, 'd', "GPIO 32 clear" },
{ "GPCR1_33", 0x40E00028, 1, 0x00000001, 'd', "GPIO 33 clear" },
{ "GPCR1_34", 0x40E00028, 2, 0x00000001, 'd', "GPIO 34 clear" },
{ "GPCR1_35", 0x40E00028, 3, 0x00000001, 'd', "GPIO 35 clear" },
{ "GPCR1_36", 0x40E00028, 4, 0x00000001, 'd', "GPIO 36 clear" },
{ "GPCR1_37", 0x40E00028, 5, 0x00000001, 'd', "GPIO 37 clear" },
{ "GPCR1_38", 0x40E00028, 6, 0x00000001, 'd', "GPIO 38 clear" },
{ "GPCR1_39", 0x40E00028, 7, 0x00000001, 'd', "GPIO 39 clear" },
{ "GPCR1_40", 0x40E00028, 8, 0x00000001, 'd', "GPIO 40 clear" },
{ "GPCR1_41", 0x40E00028, 9, 0x00000001, 'd', "GPIO 41 clear" },
{ "GPCR1_42", 0x40E00028, 10, 0x00000001, 'd', "GPIO 42 clear" },
{ "GPCR1_43", 0x40E00028, 11, 0x00000001, 'd', "GPIO 43 clear" },
{ "GPCR1_44", 0x40E00028, 12, 0x00000001, 'd', "GPIO 44 clear" },
{ "GPCR1_45", 0x40E00028, 13, 0x00000001, 'd', "GPIO 45 clear" },
{ "GPCR1_46", 0x40E00028, 14, 0x00000001, 'd', "GPIO 46 clear" },
{ "GPCR1_47", 0x40E00028, 15, 0x00000001, 'd', "GPIO 47 clear" },
{ "GPCR1_48", 0x40E00028, 16, 0x00000001, 'd', "GPIO 48 clear" },
{ "GPCR1_49", 0x40E00028, 17, 0x00000001, 'd', "GPIO 49 clear" },
{ "GPCR1_50", 0x40E00028, 18, 0x00000001, 'd', "GPIO 50 clear" },
{ "GPCR1_51", 0x40E00028, 19, 0x00000001, 'd', "GPIO 51 clear" },
{ "GPCR1_52", 0x40E00028, 20, 0x00000001, 'd', "GPIO 52 clear" },
{ "GPCR1_53", 0x40E00028, 21, 0x00000001, 'd', "GPIO 53 clear" },
{ "GPCR1_54", 0x40E00028, 22, 0x00000001, 'd', "GPIO 54 clear" },
{ "GPCR1_55", 0x40E00028, 23, 0x00000001, 'd', "GPIO 55 clear" },
{ "GPCR1_56", 0x40E00028, 24, 0x00000001, 'd', "GPIO 56 clear" },
{ "GPCR1_57", 0x40E00028, 25, 0x00000001, 'd', "GPIO 57 clear" },
{ "GPCR1_58", 0x40E00028, 26, 0x00000001, 'd', "GPIO 58 clear" },
{ "GPCR1_59", 0x40E00028, 27, 0x00000001, 'd', "GPIO 59 clear" },
{ "GPCR1_60", 0x40E00028, 28, 0x00000001, 'd', "GPIO 60 clear" },
{ "GPCR1_61", 0x40E00028, 29, 0x00000001, 'd', "GPIO 61 clear" },
{ "GPCR1_62", 0x40E00028, 30, 0x00000001, 'd', "GPIO 62 clear" },
{ "GPCR1_63", 0x40E00028, 31, 0x00000001, 'd', "GPIO 63 clear" },
{ "GPCR2", 0x40E0002C, 0, 0xffffffff, 'x', "GPIO Clear Register 2 (4-12)" },
{ "GPCR2_64", 0x40E0002C, 0, 0x00000001, 'd', "GPIO 64 clear" },
{ "GPCR2_65", 0x40E0002C, 1, 0x00000001, 'd', "GPIO 65 clear" },
{ "GPCR2_66", 0x40E0002C, 2, 0x00000001, 'd', "GPIO 66 clear" },
{ "GPCR2_67", 0x40E0002C, 3, 0x00000001, 'd', "GPIO 67 clear" },
{ "GPCR2_68", 0x40E0002C, 4, 0x00000001, 'd', "GPIO 68 clear" },
{ "GPCR2_69", 0x40E0002C, 5, 0x00000001, 'd', "GPIO 69 clear" },
{ "GPCR2_70", 0x40E0002C, 6, 0x00000001, 'd', "GPIO 70 clear" },
{ "GPCR2_71", 0x40E0002C, 7, 0x00000001, 'd', "GPIO 71 clear" },
{ "GPCR2_72", 0x40E0002C, 8, 0x00000001, 'd', "GPIO 72 clear" },
{ "GPCR2_73", 0x40E0002C, 9, 0x00000001, 'd', "GPIO 73 clear" },
{ "GPCR2_74", 0x40E0002C, 10, 0x00000001, 'd', "GPIO 74 clear" },
{ "GPCR2_75", 0x40E0002C, 11, 0x00000001, 'd', "GPIO 75 clear" },
{ "GPCR2_76", 0x40E0002C, 12, 0x00000001, 'd', "GPIO 76 clear" },
{ "GPCR2_77", 0x40E0002C, 13, 0x00000001, 'd', "GPIO 77 clear" },
{ "GPCR2_78", 0x40E0002C, 14, 0x00000001, 'd', "GPIO 78 clear" },
{ "GPCR2_79", 0x40E0002C, 15, 0x00000001, 'd', "GPIO 79 clear" },
{ "GPCR2_80", 0x40E0002C, 16, 0x00000001, 'd', "GPIO 80 clear" },
{ "GPCR2_81", 0x40E0002C, 17, 0x00000001, 'd', "GPIO 81 clear" },
{ "GPCR2_82", 0x40E0002C, 18, 0x00000001, 'd', "GPIO 82 clear" },
{ "GPCR2_83", 0x40E0002C, 19, 0x00000001, 'd', "GPIO 83 clear" },
{ "GPCR2_84", 0x40E0002C, 20, 0x00000001, 'd', "GPIO 84 clear" },
{ "GPCR2_85", 0x40E0002C, 21, 0x00000001, 'd', "GPIO 85 clear" },
{ "GPCR2_86", 0x40E0002C, 22, 0x00000001, 'd', "GPIO 86 clear" },
{ "GPCR2_87", 0x40E0002C, 23, 0x00000001, 'd', "GPIO 87 clear" },
{ "GPCR2_88", 0x40E0002C, 24, 0x00000001, 'd', "GPIO 88 clear" },
{ "GPCR2_89", 0x40E0002C, 25, 0x00000001, 'd', "GPIO 89 clear" },
{ "GPCR2_90", 0x40E0002C, 26, 0x00000001, 'd', "GPIO 90 clear" },
{ "GPCR2_91", 0x40E0002C, 27, 0x00000001, 'd', "GPIO 91 clear" },
{ "GPCR2_92", 0x40E0002C, 28, 0x00000001, 'd', "GPIO 92 clear" },
{ "GPCR2_93", 0x40E0002C, 29, 0x00000001, 'd', "GPIO 93 clear" },
{ "GPCR2_94", 0x40E0002C, 30, 0x00000001, 'd', "GPIO 94 clear" },
{ "GPCR2_95", 0x40E0002C, 31, 0x00000001, 'd', "GPIO 95 clear" },
{ "GPCR3", 0x40E00124, 0, 0xffffffff, 'x', "GPIO Clear Register 3 (4-12)" },
{ "GPCR3_96", 0x40E00124, 0, 0x00000001, 'd', "GPIO 96 clear" },
{ "GPCR3_97", 0x40E00124, 1, 0x00000001, 'd', "GPIO 97 clear" },
{ "GPCR3_98", 0x40E00124, 2, 0x00000001, 'd', "GPIO 98 clear" },
{ "GPCR3_99", 0x40E00124, 3, 0x00000001, 'd', "GPIO 99 clear" },
{ "GPCR3_100", 0x40E00124, 4, 0x00000001, 'd', "GPIO 100 clear" },
{ "GPCR3_101", 0x40E00124, 5, 0x00000001, 'd', "GPIO 101 clear" },
{ "GPCR3_102", 0x40E00124, 6, 0x00000001, 'd', "GPIO 102 clear" },
{ "GPCR3_103", 0x40E00124, 7, 0x00000001, 'd', "GPIO 103 clear" },
{ "GPCR3_104", 0x40E00124, 8, 0x00000001, 'd', "GPIO 104 clear" },
{ "GPCR3_105", 0x40E00124, 9, 0x00000001, 'd', "GPIO 105 clear" },
{ "GPCR3_106", 0x40E00124, 10, 0x00000001, 'd', "GPIO 106 clear" },
{ "GPCR3_107", 0x40E00124, 11, 0x00000001, 'd', "GPIO 107 clear" },
{ "GPCR3_108", 0x40E00124, 12, 0x00000001, 'd', "GPIO 108 clear" },
{ "GPCR3_109", 0x40E00124, 13, 0x00000001, 'd', "GPIO 109 clear" },
{ "GPCR3_110", 0x40E00124, 14, 0x00000001, 'd', "GPIO 110 clear" },
{ "GPCR3_111", 0x40E00124, 15, 0x00000001, 'd', "GPIO 111 clear" },
{ "GPCR3_112", 0x40E00124, 16, 0x00000001, 'd', "GPIO 112 clear" },
{ "GPCR3_113", 0x40E00124, 17, 0x00000001, 'd', "GPIO 113 clear" },
{ "GPCR3_114", 0x40E00124, 18, 0x00000001, 'd', "GPIO 114 clear" },
{ "GPCR3_115", 0x40E00124, 19, 0x00000001, 'd', "GPIO 115 clear" },
{ "GPCR3_116", 0x40E00124, 20, 0x00000001, 'd', "GPIO 116 clear" },
{ "GPCR3_117", 0x40E00124, 21, 0x00000001, 'd', "GPIO 117 clear" },
{ "GPCR3_118", 0x40E00124, 22, 0x00000001, 'd', "GPIO 118 clear" },
{ "GPCR3_119", 0x40E00124, 23, 0x00000001, 'd', "GPIO 119 clear" },
{ "GPCR3_120", 0x40E00124, 24, 0x00000001, 'd', "GPIO 120 clear" },
{ "GPCR3_121", 0x40E00124, 25, 0x00000001, 'd', "GPIO 121 clear" },
{ "GPCR3_122", 0x40E00124, 26, 0x00000001, 'd', "GPIO 122 clear" },
{ "GPCR3_123", 0x40E00124, 27, 0x00000001, 'd', "GPIO 123 clear" },
{ "GPCR3_124", 0x40E00124, 28, 0x00000001, 'd', "GPIO 124 clear" },
{ "GPCR3_125", 0x40E00124, 29, 0x00000001, 'd', "GPIO 125 clear" },
{ "GPCR3_126", 0x40E00124, 30, 0x00000001, 'd', "GPIO 126 clear" },
{ "GPCR3_127", 0x40E00124, 31, 0x00000001, 'd', "GPIO 127 clear" },
{ "GRER0", 0x40E00030, 0, 0xffffffff, 'x', "GPIO Raising Edge Detect Enable Register 0 (4-13)" },
{ "GRER0_0", 0x40E00030, 0, 0x00000001, 'd', "GPIO 0 raising edge detect enabled" },
{ "GRER0_1", 0x40E00030, 1, 0x00000001, 'd', "GPIO 1 raising edge detect enabled" },
{ "GRER0_2", 0x40E00030, 2, 0x00000001, 'd', "GPIO 2 raising edge detect enabled" },
{ "GRER0_3", 0x40E00030, 3, 0x00000001, 'd', "GPIO 3 raising edge detect enabled" },
{ "GRER0_4", 0x40E00030, 4, 0x00000001, 'd', "GPIO 4 raising edge detect enabled" },
{ "GRER0_5", 0x40E00030, 5, 0x00000001, 'd', "GPIO 5 raising edge detect enabled" },
{ "GRER0_6", 0x40E00030, 6, 0x00000001, 'd', "GPIO 6 raising edge detect enabled" },
{ "GRER0_7", 0x40E00030, 7, 0x00000001, 'd', "GPIO 7 raising edge detect enabled" },
{ "GRER0_8", 0x40E00030, 8, 0x00000001, 'd', "GPIO 8 raising edge detect enabled" },
{ "GRER0_9", 0x40E00030, 9, 0x00000001, 'd', "GPIO 9 raising edge detect enabled" },
{ "GRER0_10", 0x40E00030, 10, 0x00000001, 'd', "GPIO 10 raising edge detect enabled" },
{ "GRER0_11", 0x40E00030, 11, 0x00000001, 'd', "GPIO 11 raising edge detect enabled" },
{ "GRER0_12", 0x40E00030, 12, 0x00000001, 'd', "GPIO 12 raising edge detect enabled" },
{ "GRER0_13", 0x40E00030, 13, 0x00000001, 'd', "GPIO 13 raising edge detect enabled" },
{ "GRER0_14", 0x40E00030, 14, 0x00000001, 'd', "GPIO 14 raising edge detect enabled" },
{ "GRER0_15", 0x40E00030, 15, 0x00000001, 'd', "GPIO 15 raising edge detect enabled" },
{ "GRER0_16", 0x40E00030, 16, 0x00000001, 'd', "GPIO 16 raising edge detect enabled" },
{ "GRER0_17", 0x40E00030, 17, 0x00000001, 'd', "GPIO 17 raising edge detect enabled" },
{ "GRER0_18", 0x40E00030, 18, 0x00000001, 'd', "GPIO 18 raising edge detect enabled" },
{ "GRER0_19", 0x40E00030, 19, 0x00000001, 'd', "GPIO 19 raising edge detect enabled" },
{ "GRER0_20", 0x40E00030, 20, 0x00000001, 'd', "GPIO 20 raising edge detect enabled" },
{ "GRER0_21", 0x40E00030, 21, 0x00000001, 'd', "GPIO 21 raising edge detect enabled" },
{ "GRER0_22", 0x40E00030, 22, 0x00000001, 'd', "GPIO 22 raising edge detect enabled" },
{ "GRER0_23", 0x40E00030, 23, 0x00000001, 'd', "GPIO 23 raising edge detect enabled" },
{ "GRER0_24", 0x40E00030, 24, 0x00000001, 'd', "GPIO 24 raising edge detect enabled" },
{ "GRER0_25", 0x40E00030, 25, 0x00000001, 'd', "GPIO 25 raising edge detect enabled" },
{ "GRER0_26", 0x40E00030, 26, 0x00000001, 'd', "GPIO 26 raising edge detect enabled" },
{ "GRER0_27", 0x40E00030, 27, 0x00000001, 'd', "GPIO 27 raising edge detect enabled" },
{ "GRER0_28", 0x40E00030, 28, 0x00000001, 'd', "GPIO 28 raising edge detect enabled" },
{ "GRER0_29", 0x40E00030, 29, 0x00000001, 'd', "GPIO 29 raising edge detect enabled" },
{ "GRER0_30", 0x40E00030, 30, 0x00000001, 'd', "GPIO 30 raising edge detect enabled" },
{ "GRER0_31", 0x40E00030, 31, 0x00000001, 'd', "GPIO 31 raising edge detect enabled" },
{ "GRER1", 0x40E00034, 0, 0xffffffff, 'x', "GPIO Raising Edge Detect Enable Register 1 (4-13)" },
{ "GRER1_32", 0x40E00034, 0, 0x00000001, 'd', "GPIO 32 raising edge detect enabled" },
{ "GRER1_33", 0x40E00034, 1, 0x00000001, 'd', "GPIO 33 raising edge detect enabled" },
{ "GRER1_34", 0x40E00034, 2, 0x00000001, 'd', "GPIO 34 raising edge detect enabled" },
{ "GRER1_35", 0x40E00034, 3, 0x00000001, 'd', "GPIO 35 raising edge detect enabled" },
{ "GRER1_36", 0x40E00034, 4, 0x00000001, 'd', "GPIO 36 raising edge detect enabled" },
{ "GRER1_37", 0x40E00034, 5, 0x00000001, 'd', "GPIO 37 raising edge detect enabled" },
{ "GRER1_38", 0x40E00034, 6, 0x00000001, 'd', "GPIO 38 raising edge detect enabled" },
{ "GRER1_39", 0x40E00034, 7, 0x00000001, 'd', "GPIO 39 raising edge detect enabled" },
{ "GRER1_40", 0x40E00034, 8, 0x00000001, 'd', "GPIO 40 raising edge detect enabled" },
{ "GRER1_41", 0x40E00034, 9, 0x00000001, 'd', "GPIO 41 raising edge detect enabled" },
{ "GRER1_42", 0x40E00034, 10, 0x00000001, 'd', "GPIO 42 raising edge detect enabled" },
{ "GRER1_43", 0x40E00034, 11, 0x00000001, 'd', "GPIO 43 raising edge detect enabled" },
{ "GRER1_44", 0x40E00034, 12, 0x00000001, 'd', "GPIO 44 raising edge detect enabled" },
{ "GRER1_45", 0x40E00034, 13, 0x00000001, 'd', "GPIO 45 raising edge detect enabled" },
{ "GRER1_46", 0x40E00034, 14, 0x00000001, 'd', "GPIO 46 raising edge detect enabled" },
{ "GRER1_47", 0x40E00034, 15, 0x00000001, 'd', "GPIO 47 raising edge detect enabled" },
{ "GRER1_48", 0x40E00034, 16, 0x00000001, 'd', "GPIO 48 raising edge detect enabled" },
{ "GRER1_49", 0x40E00034, 17, 0x00000001, 'd', "GPIO 49 raising edge detect enabled" },
{ "GRER1_50", 0x40E00034, 18, 0x00000001, 'd', "GPIO 50 raising edge detect enabled" },
{ "GRER1_51", 0x40E00034, 19, 0x00000001, 'd', "GPIO 51 raising edge detect enabled" },
{ "GRER1_52", 0x40E00034, 20, 0x00000001, 'd', "GPIO 52 raising edge detect enabled" },
{ "GRER1_53", 0x40E00034, 21, 0x00000001, 'd', "GPIO 53 raising edge detect enabled" },
{ "GRER1_54", 0x40E00034, 22, 0x00000001, 'd', "GPIO 54 raising edge detect enabled" },
{ "GRER1_55", 0x40E00034, 23, 0x00000001, 'd', "GPIO 55 raising edge detect enabled" },
{ "GRER1_56", 0x40E00034, 24, 0x00000001, 'd', "GPIO 56 raising edge detect enabled" },
{ "GRER1_57", 0x40E00034, 25, 0x00000001, 'd', "GPIO 57 raising edge detect enabled" },
{ "GRER1_58", 0x40E00034, 26, 0x00000001, 'd', "GPIO 58 raising edge detect enabled" },
{ "GRER1_59", 0x40E00034, 27, 0x00000001, 'd', "GPIO 59 raising edge detect enabled" },
{ "GRER1_60", 0x40E00034, 28, 0x00000001, 'd', "GPIO 60 raising edge detect enabled" },
{ "GRER1_61", 0x40E00034, 29, 0x00000001, 'd', "GPIO 61 raising edge detect enabled" },
{ "GRER1_62", 0x40E00034, 30, 0x00000001, 'd', "GPIO 62 raising edge detect enabled" },
{ "GRER1_63", 0x40E00034, 31, 0x00000001, 'd', "GPIO 63 raising edge detect enabled" },
{ "GRER2", 0x40E00038, 0, 0xffffffff, 'x', "GPIO Raising Edge Detect Enable Register 2 (4-13)" },
{ "GRER2_64", 0x40E00038, 0, 0x00000001, 'd', "GPIO 64 raising edge detect enabled" },
{ "GRER2_65", 0x40E00038, 1, 0x00000001, 'd', "GPIO 65 raising edge detect enabled" },
{ "GRER2_66", 0x40E00038, 2, 0x00000001, 'd', "GPIO 66 raising edge detect enabled" },
{ "GRER2_67", 0x40E00038, 3, 0x00000001, 'd', "GPIO 67 raising edge detect enabled" },
{ "GRER2_68", 0x40E00038, 4, 0x00000001, 'd', "GPIO 68 raising edge detect enabled" },
{ "GRER2_69", 0x40E00038, 5, 0x00000001, 'd', "GPIO 69 raising edge detect enabled" },
{ "GRER2_70", 0x40E00038, 6, 0x00000001, 'd', "GPIO 70 raising edge detect enabled" },
{ "GRER2_71", 0x40E00038, 7, 0x00000001, 'd', "GPIO 71 raising edge detect enabled" },
{ "GRER2_72", 0x40E00038, 8, 0x00000001, 'd', "GPIO 72 raising edge detect enabled" },
{ "GRER2_73", 0x40E00038, 9, 0x00000001, 'd', "GPIO 73 raising edge detect enabled" },
{ "GRER2_74", 0x40E00038, 10, 0x00000001, 'd', "GPIO 74 raising edge detect enabled" },
{ "GRER2_75", 0x40E00038, 11, 0x00000001, 'd', "GPIO 75 raising edge detect enabled" },
{ "GRER2_76", 0x40E00038, 12, 0x00000001, 'd', "GPIO 76 raising edge detect enabled" },
{ "GRER2_77", 0x40E00038, 13, 0x00000001, 'd', "GPIO 77 raising edge detect enabled" },
{ "GRER2_78", 0x40E00038, 14, 0x00000001, 'd', "GPIO 78 raising edge detect enabled" },
{ "GRER2_79", 0x40E00038, 15, 0x00000001, 'd', "GPIO 79 raising edge detect enabled" },
{ "GRER2_80", 0x40E00038, 16, 0x00000001, 'd', "GPIO 80 raising edge detect enabled" },
{ "GRER2_81", 0x40E00038, 17, 0x00000001, 'd', "GPIO 81 raising edge detect enabled" },
{ "GRER2_82", 0x40E00038, 18, 0x00000001, 'd', "GPIO 82 raising edge detect enabled" },
{ "GRER2_83", 0x40E00038, 19, 0x00000001, 'd', "GPIO 83 raising edge detect enabled" },
{ "GRER2_84", 0x40E00038, 20, 0x00000001, 'd', "GPIO 84 raising edge detect enabled" },
{ "GFER0", 0x40E0003C, 0, 0xffffffff, 'x', "GPIO Falling Edge Detect Enable Register 0 (4-14)" },
{ "GFER0_0", 0x40E0003C, 0, 0x00000001, 'd', "GPIO 0 falling edge detect enabled" },
{ "GFER0_1", 0x40E0003C, 1, 0x00000001, 'd', "GPIO 1 falling edge detect enabled" },
{ "GFER0_2", 0x40E0003C, 2, 0x00000001, 'd', "GPIO 2 falling edge detect enabled" },
{ "GFER0_3", 0x40E0003C, 3, 0x00000001, 'd', "GPIO 3 falling edge detect enabled" },
{ "GFER0_4", 0x40E0003C, 4, 0x00000001, 'd', "GPIO 4 falling edge detect enabled" },
{ "GFER0_5", 0x40E0003C, 5, 0x00000001, 'd', "GPIO 5 falling edge detect enabled" },
{ "GFER0_6", 0x40E0003C, 6, 0x00000001, 'd', "GPIO 6 falling edge detect enabled" },
{ "GFER0_7", 0x40E0003C, 7, 0x00000001, 'd', "GPIO 7 falling edge detect enabled" },
{ "GFER0_8", 0x40E0003C, 8, 0x00000001, 'd', "GPIO 8 falling edge detect enabled" },
{ "GFER0_9", 0x40E0003C, 9, 0x00000001, 'd', "GPIO 9 falling edge detect enabled" },
{ "GFER0_10", 0x40E0003C, 10, 0x00000001, 'd', "GPIO 10 falling edge detect enabled" },
{ "GFER0_11", 0x40E0003C, 11, 0x00000001, 'd', "GPIO 11 falling edge detect enabled" },
{ "GFER0_12", 0x40E0003C, 12, 0x00000001, 'd', "GPIO 12 falling edge detect enabled" },
{ "GFER0_13", 0x40E0003C, 13, 0x00000001, 'd', "GPIO 13 falling edge detect enabled" },
{ "GFER0_14", 0x40E0003C, 14, 0x00000001, 'd', "GPIO 14 falling edge detect enabled" },
{ "GFER0_15", 0x40E0003C, 15, 0x00000001, 'd', "GPIO 15 falling edge detect enabled" },
{ "GFER0_16", 0x40E0003C, 16, 0x00000001, 'd', "GPIO 16 falling edge detect enabled" },
{ "GFER0_17", 0x40E0003C, 17, 0x00000001, 'd', "GPIO 17 falling edge detect enabled" },
{ "GFER0_18", 0x40E0003C, 18, 0x00000001, 'd', "GPIO 18 falling edge detect enabled" },
{ "GFER0_19", 0x40E0003C, 19, 0x00000001, 'd', "GPIO 19 falling edge detect enabled" },
{ "GFER0_20", 0x40E0003C, 20, 0x00000001, 'd', "GPIO 20 falling edge detect enabled" },
{ "GFER0_21", 0x40E0003C, 21, 0x00000001, 'd', "GPIO 21 falling edge detect enabled" },
{ "GFER0_22", 0x40E0003C, 22, 0x00000001, 'd', "GPIO 22 falling edge detect enabled" },
{ "GFER0_23", 0x40E0003C, 23, 0x00000001, 'd', "GPIO 23 falling edge detect enabled" },
{ "GFER0_24", 0x40E0003C, 24, 0x00000001, 'd', "GPIO 24 falling edge detect enabled" },
{ "GFER0_25", 0x40E0003C, 25, 0x00000001, 'd', "GPIO 25 falling edge detect enabled" },
{ "GFER0_26", 0x40E0003C, 26, 0x00000001, 'd', "GPIO 26 falling edge detect enabled" },
{ "GFER0_27", 0x40E0003C, 27, 0x00000001, 'd', "GPIO 27 falling edge detect enabled" },
{ "GFER0_28", 0x40E0003C, 28, 0x00000001, 'd', "GPIO 28 falling edge detect enabled" },
{ "GFER0_29", 0x40E0003C, 29, 0x00000001, 'd', "GPIO 29 falling edge detect enabled" },
{ "GFER0_30", 0x40E0003C, 30, 0x00000001, 'd', "GPIO 30 falling edge detect enabled" },
{ "GFER0_31", 0x40E0003C, 31, 0x00000001, 'd', "GPIO 31 falling edge detect enabled" },
{ "GFER1", 0x40E00040, 0, 0xffffffff, 'x', "GPIO Falling Edge Detect Enable Register 1 (4-14)" },
{ "GFER1_32", 0x40E00040, 0, 0x00000001, 'd', "GPIO 32 falling edge detect enabled" },
{ "GFER1_33", 0x40E00040, 1, 0x00000001, 'd', "GPIO 33 falling edge detect enabled" },
{ "GFER1_34", 0x40E00040, 2, 0x00000001, 'd', "GPIO 34 falling edge detect enabled" },
{ "GFER1_35", 0x40E00040, 3, 0x00000001, 'd', "GPIO 35 falling edge detect enabled" },
{ "GFER1_36", 0x40E00040, 4, 0x00000001, 'd', "GPIO 36 falling edge detect enabled" },
{ "GFER1_37", 0x40E00040, 5, 0x00000001, 'd', "GPIO 37 falling edge detect enabled" },
{ "GFER1_38", 0x40E00040, 6, 0x00000001, 'd', "GPIO 38 falling edge detect enabled" },
{ "GFER1_39", 0x40E00040, 7, 0x00000001, 'd', "GPIO 39 falling edge detect enabled" },
{ "GFER1_40", 0x40E00040, 8, 0x00000001, 'd', "GPIO 40 falling edge detect enabled" },
{ "GFER1_41", 0x40E00040, 9, 0x00000001, 'd', "GPIO 41 falling edge detect enabled" },
{ "GFER1_42", 0x40E00040, 10, 0x00000001, 'd', "GPIO 42 falling edge detect enabled" },
{ "GFER1_43", 0x40E00040, 11, 0x00000001, 'd', "GPIO 43 falling edge detect enabled" },
{ "GFER1_44", 0x40E00040, 12, 0x00000001, 'd', "GPIO 44 falling edge detect enabled" },
{ "GFER1_45", 0x40E00040, 13, 0x00000001, 'd', "GPIO 45 falling edge detect enabled" },
{ "GFER1_46", 0x40E00040, 14, 0x00000001, 'd', "GPIO 46 falling edge detect enabled" },
{ "GFER1_47", 0x40E00040, 15, 0x00000001, 'd', "GPIO 47 falling edge detect enabled" },
{ "GFER1_48", 0x40E00040, 16, 0x00000001, 'd', "GPIO 48 falling edge detect enabled" },
{ "GFER1_49", 0x40E00040, 17, 0x00000001, 'd', "GPIO 49 falling edge detect enabled" },
{ "GFER1_50", 0x40E00040, 18, 0x00000001, 'd', "GPIO 50 falling edge detect enabled" },
{ "GFER1_51", 0x40E00040, 19, 0x00000001, 'd', "GPIO 51 falling edge detect enabled" },
{ "GFER1_52", 0x40E00040, 20, 0x00000001, 'd', "GPIO 52 falling edge detect enabled" },
{ "GFER1_53", 0x40E00040, 21, 0x00000001, 'd', "GPIO 53 falling edge detect enabled" },
{ "GFER1_54", 0x40E00040, 22, 0x00000001, 'd', "GPIO 54 falling edge detect enabled" },
{ "GFER1_55", 0x40E00040, 23, 0x00000001, 'd', "GPIO 55 falling edge detect enabled" },
{ "GFER1_56", 0x40E00040, 24, 0x00000001, 'd', "GPIO 56 falling edge detect enabled" },
{ "GFER1_57", 0x40E00040, 25, 0x00000001, 'd', "GPIO 57 falling edge detect enabled" },
{ "GFER1_58", 0x40E00040, 26, 0x00000001, 'd', "GPIO 58 falling edge detect enabled" },
{ "GFER1_59", 0x40E00040, 27, 0x00000001, 'd', "GPIO 59 falling edge detect enabled" },
{ "GFER1_60", 0x40E00040, 28, 0x00000001, 'd', "GPIO 60 falling edge detect enabled" },
{ "GFER1_61", 0x40E00040, 29, 0x00000001, 'd', "GPIO 61 falling edge detect enabled" },
{ "GFER1_62", 0x40E00040, 30, 0x00000001, 'd', "GPIO 62 falling edge detect enabled" },
{ "GFER1_63", 0x40E00040, 31, 0x00000001, 'd', "GPIO 63 falling edge detect enabled" },
{ "GFER2", 0x40E00044, 0, 0xffffffff, 'x', "GPIO Falling Edge Detect Enable Register 2 (4-14)" },
{ "GFER2_64", 0x40E00044, 0, 0x00000001, 'd', "GPIO 64 falling edge detect enabled" },
{ "GFER2_65", 0x40E00044, 1, 0x00000001, 'd', "GPIO 65 falling edge detect enabled" },
{ "GFER2_66", 0x40E00044, 2, 0x00000001, 'd', "GPIO 66 falling edge detect enabled" },
{ "GFER2_67", 0x40E00044, 3, 0x00000001, 'd', "GPIO 67 falling edge detect enabled" },
{ "GFER2_68", 0x40E00044, 4, 0x00000001, 'd', "GPIO 68 falling edge detect enabled" },
{ "GFER2_69", 0x40E00044, 5, 0x00000001, 'd', "GPIO 69 falling edge detect enabled" },
{ "GFER2_70", 0x40E00044, 6, 0x00000001, 'd', "GPIO 70 falling edge detect enabled" },
{ "GFER2_71", 0x40E00044, 7, 0x00000001, 'd', "GPIO 71 falling edge detect enabled" },
{ "GFER2_72", 0x40E00044, 8, 0x00000001, 'd', "GPIO 72 falling edge detect enabled" },
{ "GFER2_73", 0x40E00044, 9, 0x00000001, 'd', "GPIO 73 falling edge detect enabled" },
{ "GFER2_74", 0x40E00044, 10, 0x00000001, 'd', "GPIO 74 falling edge detect enabled" },
{ "GFER2_75", 0x40E00044, 11, 0x00000001, 'd', "GPIO 75 falling edge detect enabled" },
{ "GFER2_76", 0x40E00044, 12, 0x00000001, 'd', "GPIO 76 falling edge detect enabled" },
{ "GFER2_77", 0x40E00044, 13, 0x00000001, 'd', "GPIO 77 falling edge detect enabled" },
{ "GFER2_78", 0x40E00044, 14, 0x00000001, 'd', "GPIO 78 falling edge detect enabled" },
{ "GFER2_79", 0x40E00044, 15, 0x00000001, 'd', "GPIO 79 falling edge detect enabled" },
{ "GFER2_80", 0x40E00044, 16, 0x00000001, 'd', "GPIO 80 falling edge detect enabled" },
{ "GFER2_81", 0x40E00044, 17, 0x00000001, 'd', "GPIO 81 falling edge detect enabled" },
{ "GFER2_82", 0x40E00044, 18, 0x00000001, 'd', "GPIO 82 falling edge detect enabled" },
{ "GFER2_83", 0x40E00044, 19, 0x00000001, 'd', "GPIO 83 falling edge detect enabled" },
{ "GFER2_84", 0x40E00044, 20, 0x00000001, 'd', "GPIO 84 falling edge detect enabled" },
{ "GEDR0", 0x40E00048, 0, 0xffffffff, 'x', "GPIO Edge Detect Register 0 (4-15)" },
{ "GEDR0_0", 0x40E00048, 0, 0x00000001, 'd', "GPIO 0 edge detected" },
{ "GEDR0_1", 0x40E00048, 1, 0x00000001, 'd', "GPIO 1 edge detected" },
{ "GEDR0_2", 0x40E00048, 2, 0x00000001, 'd', "GPIO 2 edge detected" },
{ "GEDR0_3", 0x40E00048, 3, 0x00000001, 'd', "GPIO 3 edge detected" },
{ "GEDR0_4", 0x40E00048, 4, 0x00000001, 'd', "GPIO 4 edge detected" },
{ "GEDR0_5", 0x40E00048, 5, 0x00000001, 'd', "GPIO 5 edge detected" },
{ "GEDR0_6", 0x40E00048, 6, 0x00000001, 'd', "GPIO 6 edge detected" },
{ "GEDR0_7", 0x40E00048, 7, 0x00000001, 'd', "GPIO 7 edge detected" },
{ "GEDR0_8", 0x40E00048, 8, 0x00000001, 'd', "GPIO 8 edge detected" },
{ "GEDR0_9", 0x40E00048, 9, 0x00000001, 'd', "GPIO 9 edge detected" },
{ "GEDR0_10", 0x40E00048, 10, 0x00000001, 'd', "GPIO 10 edge detected" },
{ "GEDR0_11", 0x40E00048, 11, 0x00000001, 'd', "GPIO 11 edge detected" },
{ "GEDR0_12", 0x40E00048, 12, 0x00000001, 'd', "GPIO 12 edge detected" },
{ "GEDR0_13", 0x40E00048, 13, 0x00000001, 'd', "GPIO 13 edge detected" },
{ "GEDR0_14", 0x40E00048, 14, 0x00000001, 'd', "GPIO 14 edge detected" },
{ "GEDR0_15", 0x40E00048, 15, 0x00000001, 'd', "GPIO 15 edge detected" },
{ "GEDR0_16", 0x40E00048, 16, 0x00000001, 'd', "GPIO 16 edge detected" },
{ "GEDR0_17", 0x40E00048, 17, 0x00000001, 'd', "GPIO 17 edge detected" },
{ "GEDR0_18", 0x40E00048, 18, 0x00000001, 'd', "GPIO 18 edge detected" },
{ "GEDR0_19", 0x40E00048, 19, 0x00000001, 'd', "GPIO 19 edge detected" },
{ "GEDR0_20", 0x40E00048, 20, 0x00000001, 'd', "GPIO 20 edge detected" },
{ "GEDR0_21", 0x40E00048, 21, 0x00000001, 'd', "GPIO 21 edge detected" },
{ "GEDR0_22", 0x40E00048, 22, 0x00000001, 'd', "GPIO 22 edge detected" },
{ "GEDR0_23", 0x40E00048, 23, 0x00000001, 'd', "GPIO 23 edge detected" },
{ "GEDR0_24", 0x40E00048, 24, 0x00000001, 'd', "GPIO 24 edge detected" },
{ "GEDR0_25", 0x40E00048, 25, 0x00000001, 'd', "GPIO 25 edge detected" },
{ "GEDR0_26", 0x40E00048, 26, 0x00000001, 'd', "GPIO 26 edge detected" },
{ "GEDR0_27", 0x40E00048, 27, 0x00000001, 'd', "GPIO 27 edge detected" },
{ "GEDR0_28", 0x40E00048, 28, 0x00000001, 'd', "GPIO 28 edge detected" },
{ "GEDR0_29", 0x40E00048, 29, 0x00000001, 'd', "GPIO 29 edge detected" },
{ "GEDR0_30", 0x40E00048, 30, 0x00000001, 'd', "GPIO 30 edge detected" },
{ "GEDR0_31", 0x40E00048, 31, 0x00000001, 'd', "GPIO 31 edge detected" },
{ "GEDR1", 0x40E0004C, 0, 0xffffffff, 'x', "GPIO Edge Detect Register 1 (4-16)" },
{ "GEDR1_32", 0x40E0004C, 0, 0x00000001, 'd', "GPIO 32 edge detected" },
{ "GEDR1_33", 0x40E0004C, 1, 0x00000001, 'd', "GPIO 33 edge detected" },
{ "GEDR1_34", 0x40E0004C, 2, 0x00000001, 'd', "GPIO 34 edge detected" },
{ "GEDR1_35", 0x40E0004C, 3, 0x00000001, 'd', "GPIO 35 edge detected" },
{ "GEDR1_36", 0x40E0004C, 4, 0x00000001, 'd', "GPIO 36 edge detected" },
{ "GEDR1_37", 0x40E0004C, 5, 0x00000001, 'd', "GPIO 37 edge detected" },
{ "GEDR1_38", 0x40E0004C, 6, 0x00000001, 'd', "GPIO 38 edge detected" },
{ "GEDR1_39", 0x40E0004C, 7, 0x00000001, 'd', "GPIO 39 edge detected" },
{ "GEDR1_40", 0x40E0004C, 8, 0x00000001, 'd', "GPIO 40 edge detected" },
{ "GEDR1_41", 0x40E0004C, 9, 0x00000001, 'd', "GPIO 41 edge detected" },
{ "GEDR1_42", 0x40E0004C, 10, 0x00000001, 'd', "GPIO 42 edge detected" },
{ "GEDR1_43", 0x40E0004C, 11, 0x00000001, 'd', "GPIO 43 edge detected" },
{ "GEDR1_44", 0x40E0004C, 12, 0x00000001, 'd', "GPIO 44 edge detected" },
{ "GEDR1_45", 0x40E0004C, 13, 0x00000001, 'd', "GPIO 45 edge detected" },
{ "GEDR1_46", 0x40E0004C, 14, 0x00000001, 'd', "GPIO 46 edge detected" },
{ "GEDR1_47", 0x40E0004C, 15, 0x00000001, 'd', "GPIO 47 edge detected" },
{ "GEDR1_48", 0x40E0004C, 16, 0x00000001, 'd', "GPIO 48 edge detected" },
{ "GEDR1_49", 0x40E0004C, 17, 0x00000001, 'd', "GPIO 49 edge detected" },
{ "GEDR1_50", 0x40E0004C, 18, 0x00000001, 'd', "GPIO 50 edge detected" },
{ "GEDR1_51", 0x40E0004C, 19, 0x00000001, 'd', "GPIO 51 edge detected" },
{ "GEDR1_52", 0x40E0004C, 20, 0x00000001, 'd', "GPIO 52 edge detected" },
{ "GEDR1_53", 0x40E0004C, 21, 0x00000001, 'd', "GPIO 53 edge detected" },
{ "GEDR1_54", 0x40E0004C, 22, 0x00000001, 'd', "GPIO 54 edge detected" },
{ "GEDR1_55", 0x40E0004C, 23, 0x00000001, 'd', "GPIO 55 edge detected" },
{ "GEDR1_56", 0x40E0004C, 24, 0x00000001, 'd', "GPIO 56 edge detected" },
{ "GEDR1_57", 0x40E0004C, 25, 0x00000001, 'd', "GPIO 57 edge detected" },
{ "GEDR1_58", 0x40E0004C, 26, 0x00000001, 'd', "GPIO 58 edge detected" },
{ "GEDR1_59", 0x40E0004C, 27, 0x00000001, 'd', "GPIO 59 edge detected" },
{ "GEDR1_60", 0x40E0004C, 28, 0x00000001, 'd', "GPIO 60 edge detected" },
{ "GEDR1_61", 0x40E0004C, 29, 0x00000001, 'd', "GPIO 61 edge detected" },
{ "GEDR1_62", 0x40E0004C, 30, 0x00000001, 'd', "GPIO 62 edge detected" },
{ "GEDR1_63", 0x40E0004C, 31, 0x00000001, 'd', "GPIO 63 edge detected" },
{ "GEDR2", 0x40E00050, 0, 0xffffffff, 'x', "GPIO Edge Detect Register 2 (4-16)" },
{ "GEDR2_64", 0x40E00050, 0, 0x00000001, 'd', "GPIO 64 edge detected" },
{ "GEDR2_65", 0x40E00050, 1, 0x00000001, 'd', "GPIO 65 edge detected" },
{ "GEDR2_66", 0x40E00050, 2, 0x00000001, 'd', "GPIO 66 edge detected" },
{ "GEDR2_67", 0x40E00050, 3, 0x00000001, 'd', "GPIO 67 edge detected" },
{ "GEDR2_68", 0x40E00050, 4, 0x00000001, 'd', "GPIO 68 edge detected" },
{ "GEDR2_69", 0x40E00050, 5, 0x00000001, 'd', "GPIO 69 edge detected" },
{ "GEDR2_70", 0x40E00050, 6, 0x00000001, 'd', "GPIO 70 edge detected" },
{ "GEDR2_71", 0x40E00050, 7, 0x00000001, 'd', "GPIO 71 edge detected" },
{ "GEDR2_72", 0x40E00050, 8, 0x00000001, 'd', "GPIO 72 edge detected" },
{ "GEDR2_73", 0x40E00050, 9, 0x00000001, 'd', "GPIO 73 edge detected" },
{ "GEDR2_74", 0x40E00050, 10, 0x00000001, 'd', "GPIO 74 edge detected" },
{ "GEDR2_75", 0x40E00050, 11, 0x00000001, 'd', "GPIO 75 edge detected" },
{ "GEDR2_76", 0x40E00050, 12, 0x00000001, 'd', "GPIO 76 edge detected" },
{ "GEDR2_77", 0x40E00050, 13, 0x00000001, 'd', "GPIO 77 edge detected" },
{ "GEDR2_78", 0x40E00050, 14, 0x00000001, 'd', "GPIO 78 edge detected" },
{ "GEDR2_79", 0x40E00050, 15, 0x00000001, 'd', "GPIO 79 edge detected" },
{ "GEDR2_80", 0x40E00050, 16, 0x00000001, 'd', "GPIO 80 edge detected" },
{ "GEDR2_81", 0x40E00050, 17, 0x00000001, 'd', "GPIO 81 edge detected" },
{ "GEDR2_82", 0x40E00050, 18, 0x00000001, 'd', "GPIO 82 edge detected" },
{ "GEDR2_83", 0x40E00050, 19, 0x00000001, 'd', "GPIO 83 edge detected" },
{ "GEDR2_84", 0x40E00050, 20, 0x00000001, 'd', "GPIO 84 edge detected" },
{ "GAFR0L", 0x40E00054, 0, 0xffffffff, 'x', "GPIO Alternate Function Register 0 Lower (4-17)" },
{ "GAFR0L_0", 0x40E00054, 0, 0x00000003, 'x', "GPIO 0 alternate function select" },
{ "GAFR0L_1", 0x40E00054, 2, 0x00000003, 'x', "GPIO 1 alternate function select" },
{ "GAFR0L_2", 0x40E00054, 4, 0x00000003, 'x', "GPIO 2 alternate function select" },
{ "GAFR0L_3", 0x40E00054, 6, 0x00000003, 'x', "GPIO 3 alternate function select" },
{ "GAFR0L_4", 0x40E00054, 8, 0x00000003, 'x', "GPIO 4 alternate function select" },
{ "GAFR0L_5", 0x40E00054, 10, 0x00000003, 'x', "GPIO 5 alternate function select" },
{ "GAFR0L_6", 0x40E00054, 12, 0x00000003, 'x', "GPIO 6 alternate function select" },
{ "GAFR0L_7", 0x40E00054, 14, 0x00000003, 'x', "GPIO 7 alternate function select" },
{ "GAFR0L_8", 0x40E00054, 16, 0x00000003, 'x', "GPIO 8 alternate function select" },
{ "GAFR0L_9", 0x40E00054, 18, 0x00000003, 'x', "GPIO 9 alternate function select" },
{ "GAFR0L_10", 0x40E00054, 20, 0x00000003, 'x', "GPIO 10 alternate function select" },
{ "GAFR0L_11", 0x40E00054, 22, 0x00000003, 'x', "GPIO 11 alternate function select" },
{ "GAFR0L_12", 0x40E00054, 24, 0x00000003, 'x', "GPIO 12 alternate function select" },
{ "GAFR0L_13", 0x40E00054, 26, 0x00000003, 'x', "GPIO 13 alternate function select" },
{ "GAFR0L_14", 0x40E00054, 28, 0x00000003, 'x', "GPIO 14 alternate function select" },
{ "GAFR0L_15", 0x40E00054, 30, 0x00000003, 'x', "GPIO 15 alternate function select" },
{ "GAFR0U", 0x40E00058, 0, 0xffffffff, 'x', "GPIO Alternate Function Register 0 Upper (4-18)" },
{ "GAFR0U_16", 0x40E00058, 0, 0x00000003, 'x', "GPIO 16 alternate function select" },
{ "GAFR0U_17", 0x40E00058, 2, 0x00000003, 'x', "GPIO 17 alternate function select" },
{ "GAFR0U_18", 0x40E00058, 4, 0x00000003, 'x', "GPIO 18 alternate function select" },
{ "GAFR0U_19", 0x40E00058, 6, 0x00000003, 'x', "GPIO 19 alternate function select" },
{ "GAFR0U_20", 0x40E00058, 8, 0x00000003, 'x', "GPIO 20 alternate function select" },
{ "GAFR0U_21", 0x40E00058, 10, 0x00000003, 'x', "GPIO 21 alternate function select" },
{ "GAFR0U_22", 0x40E00058, 12, 0x00000003, 'x', "GPIO 22 alternate function select" },
{ "GAFR0U_23", 0x40E00058, 14, 0x00000003, 'x', "GPIO 23 alternate function select" },
{ "GAFR0U_24", 0x40E00058, 16, 0x00000003, 'x', "GPIO 24 alternate function select" },
{ "GAFR0U_25", 0x40E00058, 18, 0x00000003, 'x', "GPIO 25 alternate function select" },
{ "GAFR0U_26", 0x40E00058, 20, 0x00000003, 'x', "GPIO 26 alternate function select" },
{ "GAFR0U_27", 0x40E00058, 22, 0x00000003, 'x', "GPIO 27 alternate function select" },
{ "GAFR0U_28", 0x40E00058, 24, 0x00000003, 'x', "GPIO 28 alternate function select" },
{ "GAFR0U_29", 0x40E00058, 26, 0x00000003, 'x', "GPIO 29 alternate function select" },
{ "GAFR0U_30", 0x40E00058, 28, 0x00000003, 'x', "GPIO 30 alternate function select" },
{ "GAFR0U_31", 0x40E00058, 30, 0x00000003, 'x', "GPIO 31 alternate function select" },
{ "GAFR1L", 0x40E0005C, 0, 0xffffffff, 'x', "GPIO Alternate Function Register 1 Lower (4-18)" },
{ "GAFR1L_32", 0x40E0005C, 0, 0x00000003, 'x', "GPIO 32 alternate function select" },
{ "GAFR1L_33", 0x40E0005C, 2, 0x00000003, 'x', "GPIO 33 alternate function select" },
{ "GAFR1L_34", 0x40E0005C, 4, 0x00000003, 'x', "GPIO 34 alternate function select" },
{ "GAFR1L_35", 0x40E0005C, 6, 0x00000003, 'x', "GPIO 35 alternate function select" },
{ "GAFR1L_36", 0x40E0005C, 8, 0x00000003, 'x', "GPIO 36 alternate function select" },
{ "GAFR1L_37", 0x40E0005C, 10, 0x00000003, 'x', "GPIO 37 alternate function select" },
{ "GAFR1L_38", 0x40E0005C, 12, 0x00000003, 'x', "GPIO 38 alternate function select" },
{ "GAFR1L_39", 0x40E0005C, 14, 0x00000003, 'x', "GPIO 39 alternate function select" },
{ "GAFR1L_40", 0x40E0005C, 16, 0x00000003, 'x', "GPIO 40 alternate function select" },
{ "GAFR1L_41", 0x40E0005C, 18, 0x00000003, 'x', "GPIO 41 alternate function select" },
{ "GAFR1L_42", 0x40E0005C, 20, 0x00000003, 'x', "GPIO 42 alternate function select" },
{ "GAFR1L_43", 0x40E0005C, 22, 0x00000003, 'x', "GPIO 43 alternate function select" },
{ "GAFR1L_44", 0x40E0005C, 24, 0x00000003, 'x', "GPIO 44 alternate function select" },
{ "GAFR1L_45", 0x40E0005C, 26, 0x00000003, 'x', "GPIO 45 alternate function select" },
{ "GAFR1L_46", 0x40E0005C, 28, 0x00000003, 'x', "GPIO 46 alternate function select" },
{ "GAFR1L_47", 0x40E0005C, 30, 0x00000003, 'x', "GPIO 47 alternate function select" },
{ "GAFR1U", 0x40E00060, 0, 0xffffffff, 'x', "GPIO Alternate Function Register 1 Upper (4-19)" },
{ "GAFR1U_48", 0x40E00060, 0, 0x00000003, 'x', "GPIO 48 alternate function select" },
{ "GAFR1U_49", 0x40E00060, 2, 0x00000003, 'x', "GPIO 49 alternate function select" },
{ "GAFR1U_50", 0x40E00060, 4, 0x00000003, 'x', "GPIO 50 alternate function select" },
{ "GAFR1U_51", 0x40E00060, 6, 0x00000003, 'x', "GPIO 51 alternate function select" },
{ "GAFR1U_52", 0x40E00060, 8, 0x00000003, 'x', "GPIO 52 alternate function select" },
{ "GAFR1U_53", 0x40E00060, 10, 0x00000003, 'x', "GPIO 53 alternate function select" },
{ "GAFR1U_54", 0x40E00060, 12, 0x00000003, 'x', "GPIO 54 alternate function select" },
{ "GAFR1U_55", 0x40E00060, 14, 0x00000003, 'x', "GPIO 55 alternate function select" },
{ "GAFR1U_56", 0x40E00060, 16, 0x00000003, 'x', "GPIO 56 alternate function select" },
{ "GAFR1U_57", 0x40E00060, 18, 0x00000003, 'x', "GPIO 57 alternate function select" },
{ "GAFR1U_58", 0x40E00060, 20, 0x00000003, 'x', "GPIO 58 alternate function select" },
{ "GAFR1U_59", 0x40E00060, 22, 0x00000003, 'x', "GPIO 59 alternate function select" },
{ "GAFR1U_60", 0x40E00060, 24, 0x00000003, 'x', "GPIO 60 alternate function select" },
{ "GAFR1U_61", 0x40E00060, 26, 0x00000003, 'x', "GPIO 61 alternate function select" },
{ "GAFR1U_62", 0x40E00060, 28, 0x00000003, 'x', "GPIO 62 alternate function select" },
{ "GAFR1U_63", 0x40E00060, 30, 0x00000003, 'x', "GPIO 63 alternate function select" },
{ "GAFR2L", 0x40E00064, 0, 0xffffffff, 'x', "GPIO Alternate Function Register 2 Lower (4-19)" },
{ "GAFR2L_64", 0x40E00064, 0, 0x00000003, 'x', "GPIO 64 alternate function select" },
{ "GAFR2L_65", 0x40E00064, 2, 0x00000003, 'x', "GPIO 65 alternate function select" },
{ "GAFR2L_66", 0x40E00064, 4, 0x00000003, 'x', "GPIO 66 alternate function select" },
{ "GAFR2L_67", 0x40E00064, 6, 0x00000003, 'x', "GPIO 67 alternate function select" },
{ "GAFR2L_68", 0x40E00064, 8, 0x00000003, 'x', "GPIO 68 alternate function select" },
{ "GAFR2L_69", 0x40E00064, 10, 0x00000003, 'x', "GPIO 69 alternate function select" },
{ "GAFR2L_70", 0x40E00064, 12, 0x00000003, 'x', "GPIO 70 alternate function select" },
{ "GAFR2L_71", 0x40E00064, 14, 0x00000003, 'x', "GPIO 71 alternate function select" },
{ "GAFR2L_72", 0x40E00064, 16, 0x00000003, 'x', "GPIO 72 alternate function select" },
{ "GAFR2L_73", 0x40E00064, 18, 0x00000003, 'x', "GPIO 73 alternate function select" },
{ "GAFR2L_74", 0x40E00064, 20, 0x00000003, 'x', "GPIO 74 alternate function select" },
{ "GAFR2L_75", 0x40E00064, 22, 0x00000003, 'x', "GPIO 75 alternate function select" },
{ "GAFR2L_76", 0x40E00064, 24, 0x00000003, 'x', "GPIO 76 alternate function select" },
{ "GAFR2L_77", 0x40E00064, 26, 0x00000003, 'x', "GPIO 77 alternate function select" },
{ "GAFR2L_78", 0x40E00064, 28, 0x00000003, 'x', "GPIO 78 alternate function select" },
{ "GAFR2L_79", 0x40E00064, 30, 0x00000003, 'x', "GPIO 79 alternate function select" },
{ "GAFR2U", 0x40E00068, 0, 0xffffffff, 'x', "GPIO Alternate Function Register 2 Upper (4-19)" },
{ "GAFR2U_80", 0x40E00068, 0, 0x00000003, 'x', "GPIO 80 alternate function select" },
{ "GAFR2U_81", 0x40E00068, 2, 0x00000003, 'x', "GPIO 81 alternate function select" },
{ "GAFR2U_82", 0x40E00068, 4, 0x00000003, 'x', "GPIO 82 alternate function select" },
{ "GAFR2U_83", 0x40E00068, 6, 0x00000003, 'x', "GPIO 83 alternate function select" },
{ "GAFR2U_84", 0x40E00068, 8, 0x00000003, 'x', "GPIO 84 alternate function select" },
{ "ICMR", 0x40D00004, 0, 0xffffffff, 'x', "Interrupt Controller Mask Register (4-22)" },
{ "ICMR_IM7", 0x40D00004, 7, 0x00000001, 'x', "Pending IRQ 7 (HWUART) unmasked?" },
{ "ICMR_IM8", 0x40D00004, 8, 0x00000001, 'x', "Pending IRQ 8 (GPIO0) unmasked" },
{ "ICMR_IM9", 0x40D00004, 9, 0x00000001, 'x', "Pending IRQ 9 (GPIO1) unmasked" },
{ "ICMR_IM10", 0x40D00004, 10, 0x00000001, 'x', "Pending IRQ 10 (GPIO2_80) unmasked" },
{ "ICMR_IM11", 0x40D00004, 11, 0x00000001, 'x', "Pending IRQ 11 (USB) unmasked" },
{ "ICMR_IM12", 0x40D00004, 12, 0x00000001, 'x', "Pending IRQ 12 (PMU) unmasked" },
{ "ICMR_IM13", 0x40D00004, 13, 0x00000001, 'x', "Pending IRQ 13 (I2S) unmasked" },
{ "ICMR_IM14", 0x40D00004, 14, 0x00000001, 'x', "Pending IRQ 14 (AC97) unmasked" },
{ "ICMR_IM17", 0x40D00004, 17, 0x00000001, 'x', "Pending IRQ 17 (LCD) unmasked" },
{ "ICMR_IM18", 0x40D00004, 18, 0x00000001, 'x', "Pending IRQ 18 (I2C) unmasked" },
{ "ICMR_IM19", 0x40D00004, 19, 0x00000001, 'x', "Pending IRQ 19 (ICP) unmasked" },
{ "ICMR_IM20", 0x40D00004, 20, 0x00000001, 'x', "Pending IRQ 20 (STUART) unmasked" },
{ "ICMR_IM21", 0x40D00004, 21, 0x00000001, 'x', "Pending IRQ 21 (BTUART) unmasked" },
{ "ICMR_IM22", 0x40D00004, 22, 0x00000001, 'x', "Pending IRQ 22 (FFUART) unmasked" },
{ "ICMR_IM23", 0x40D00004, 23, 0x00000001, 'x', "Pending IRQ 23 (MMC) unmasked" },
{ "ICMR_IM24", 0x40D00004, 24, 0x00000001, 'x', "Pending IRQ 24 (SSP) unmasked" },
{ "ICMR_IM25", 0x40D00004, 25, 0x00000001, 'x', "Pending IRQ 25 (DMA) unmasked" },
{ "ICMR_IM26", 0x40D00004, 26, 0x00000001, 'x', "Pending IRQ 26 (OSMR0) unmasked" },
{ "ICMR_IM27", 0x40D00004, 27, 0x00000001, 'x', "Pending IRQ 27 (OSMR1) unmasked" },
{ "ICMR_IM28", 0x40D00004, 28, 0x00000001, 'x', "Pending IRQ 28 (OSMR2) unmasked" },
{ "ICMR_IM29", 0x40D00004, 29, 0x00000001, 'x', "Pending IRQ 29 (OSMR3) unmasked" },
{ "ICMR_IM30", 0x40D00004, 30, 0x00000001, 'x', "Pending IRQ 30 (RTCCLK) unmasked" },
{ "ICMR_IM31", 0x40D00004, 31, 0x00000001, 'x', "Pending IRQ 31 (RTCALM) unmasked" },
{ "ICLR", 0x40D00008, 0, 0xffffffff, 'x', "Interrupt Controller Level Register (4-23)" },
{ "ICLR_IL7", 0x40D00008, 7, 0x00000001, 'x', "IRQ 8 (HWUART) generates FIQ?" },
{ "ICLR_IL8", 0x40D00008, 8, 0x00000001, 'x', "IRQ 8 (GPIO0) generates FIQ" },
{ "ICLR_IL9", 0x40D00008, 9, 0x00000001, 'x', "IRQ 9 (GPIO1) generates FIQ" },
{ "ICLR_IL10", 0x40D00008, 10, 0x00000001, 'x', "IRQ 10 (GPIO2_80) generates FIQ" },
{ "ICLR_IL11", 0x40D00008, 11, 0x00000001, 'x', "IRQ 11 (USB) generates FIQ" },
{ "ICLR_IL12", 0x40D00008, 12, 0x00000001, 'x', "IRQ 12 (PMU) generates FIQ" },
{ "ICLR_IL13", 0x40D00008, 13, 0x00000001, 'x', "IRQ 13 (I2S) generates FIQ" },
{ "ICLR_IL14", 0x40D00008, 14, 0x00000001, 'x', "IRQ 14 (AC97) generates FIQ" },
{ "ICLR_IL17", 0x40D00008, 17, 0x00000001, 'x', "IRQ 17 (LCD) generates FIQ" },
{ "ICLR_IL18", 0x40D00008, 18, 0x00000001, 'x', "IRQ 18 (I2C) generates FIQ" },
{ "ICLR_IL19", 0x40D00008, 19, 0x00000001, 'x', "IRQ 19 (ICP) generates FIQ" },
{ "ICLR_IL20", 0x40D00008, 20, 0x00000001, 'x', "IRQ 10 (STUART) generates FIQ" },
{ "ICLR_IL21", 0x40D00008, 21, 0x00000001, 'x', "IRQ 21 (BTUART) generates FIQ" },
{ "ICLR_IL22", 0x40D00008, 22, 0x00000001, 'x', "IRQ 22 (FFUART) generates FIQ" },
{ "ICLR_IL23", 0x40D00008, 23, 0x00000001, 'x', "IRQ 23 (MMC) generates FIQ" },
{ "ICLR_IL24", 0x40D00008, 24, 0x00000001, 'x', "IRQ 24 (SSP) generates FIQ" },
{ "ICLR_IL25", 0x40D00008, 25, 0x00000001, 'x', "IRQ 25 (DMA) generates FIQ" },
{ "ICLR_IL26", 0x40D00008, 26, 0x00000001, 'x', "IRQ 26 (OSMR0) generates FIQ" },
{ "ICLR_IL27", 0x40D00008, 27, 0x00000001, 'x', "IRQ 27 (OSMR1) generates FIQ" },
{ "ICLR_IL28", 0x40D00008, 28, 0x00000001, 'x', "IRQ 28 (OSMR2) generates FIQ" },
{ "ICLR_IL29", 0x40D00008, 29, 0x00000001, 'x', "IRQ 29 (OSMR3) generates FIQ" },
{ "ICLR_IL30", 0x40D00008, 30, 0x00000001, 'x', "IRQ 30 (RTCCLK) generates FIQ" },
{ "ICLR_IL31", 0x40D00008, 31, 0x00000001, 'x', "IRQ 31 (RTCALM) generates FIQ" },
{ "ICCR", 0x40D00014, 0, 0xffffffff, 'x', "Interrupt Controller Control Register (4-23)" },
{ "ICCR_DIM", 0x40D00014, 8, 0x00000001, 'x', "ONLY enabled and unmasked IRQ bring CPU from idle to run" },
{ "ICIP", 0x40D00000, 0, 0xffffffff, 'x', "Interrupt Controller IRQ Pending Register (4-24)" },
{ "ICFP", 0x40D0000C, 0, 0xffffffff, 'x', "Interrupt Controller FIQ Pending Register (4-24)" },
{ "ICPR", 0x40D00010, 0, 0xffffffff, 'x', "Interrupt Controller Pending Register (4-25)" },
{ "ICPR_IS7", 0x40D00010, 7, 0x00000001, 'x', "IRQ 7 (HWUART) pending" },
{ "ICPR_IS8", 0x40D00010, 8, 0x00000001, 'x', "IRQ 8 (GPIO0) pending" },
{ "ICPR_IS9", 0x40D00010, 9, 0x00000001, 'x', "IRQ 9 (GPIO1) pending" },
{ "ICPR_IS10", 0x40D00010, 10, 0x00000001, 'x', "IRQ 10 (GPIO2_80) pending" },
{ "ICPR_IS11", 0x40D00010, 11, 0x00000001, 'x', "IRQ 11 (USB) pending" },
{ "ICPR_IS12", 0x40D00010, 12, 0x00000001, 'x', "IRQ 12 (PMU) pending" },
{ "ICPR_IS13", 0x40D00010, 13, 0x00000001, 'x', "IRQ 13 (I2S) pending" },
{ "ICPR_IS14", 0x40D00010, 14, 0x00000001, 'x', "IRQ 14 (AC97) pending" },
{ "ICPR_IS17", 0x40D00010, 17, 0x00000001, 'x', "IRQ 17 (LCD) pending" },
{ "ICPR_IS18", 0x40D00010, 18, 0x00000001, 'x', "IRQ 18 (I2C) pending" },
{ "ICPR_IS19", 0x40D00010, 19, 0x00000001, 'x', "IRQ 19 (ICP) pending" },
{ "ICPR_IS20", 0x40D00010, 20, 0x00000001, 'x', "IRQ 10 (STUART) pending" },
{ "ICPR_IS21", 0x40D00010, 21, 0x00000001, 'x', "IRQ 21 (BTUART) pending" },
{ "ICPR_IS22", 0x40D00010, 22, 0x00000001, 'x', "IRQ 22 (FFUART) pending" },
{ "ICPR_IS23", 0x40D00010, 23, 0x00000001, 'x', "IRQ 23 (MMC) pending" },
{ "ICPR_IS24", 0x40D00010, 24, 0x00000001, 'x', "IRQ 24 (SSP) pending" },
{ "ICPR_IS25", 0x40D00010, 25, 0x00000001, 'x', "IRQ 25 (DMA) pending" },
{ "ICPR_IS26", 0x40D00010, 26, 0x00000001, 'x', "IRQ 26 (OSMR0) pending" },
{ "ICPR_IS27", 0x40D00010, 27, 0x00000001, 'x', "IRQ 27 (OSMR1) pending" },
{ "ICPR_IS28", 0x40D00010, 28, 0x00000001, 'x', "IRQ 28 (OSMR2) pending" },
{ "ICPR_IS29", 0x40D00010, 29, 0x00000001, 'x', "IRQ 29 (OSMR3) pending" },
{ "ICPR_IS30", 0x40D00010, 30, 0x00000001, 'x', "IRQ 30 (RTCCLK) pending" },
{ "ICPR_IS31", 0x40D00010, 31, 0x00000001, 'x', "IRQ 31 (RTCALM) pending" },
{ "RTTR", 0x4090000C, 0, 0xffffffff, 'x', "RTC Trim Register (4-30)" },
{ "RTTR_CK_DIV", 0x4090000C, 0, 0x0000ffff, 'x', "RTC Clock Divider Count" },
{ "RTTR_DEL", 0x4090000C, 16, 0x000003ff, 'x', "RTC Trim delete Count" },
{ "RTTR_LCK", 0x4090000C, 31, 0x00000001, 'x', "RTC Locking for RTTR" },
{ "RTAR", 0x40900010, 0, 0xffffffff, 'x', "RTC Alarm Register (4-30)" },
{ "RTAR_RTMV", 0x40900010, 0, 0xffffffff, 'x', "RTC Target Match Value" },
{ "RCNR", 0x40900000, 0, 0xffffffff, 'x', "RTC Counter Register (4-31)" },
{ "RCNR_RCV", 0x40900000, 0, 0xffffffff, 'x', "RTC Count Value" },
{ "RTSR", 0x40900008, 0, 0xffffffff, 'x', "RTC Status Register (4-32)" },
{ "RTSR_AL", 0x40900008, 0, 0x00000001, 'x', "RTC Alarm Interrupt detected" },
{ "RTSR_HZ", 0x40900008, 1, 0x00000001, 'x', "RTC Hz Interrupt detected" },
{ "RTSR_ALE", 0x40900008, 2, 0x00000001, 'x', "RTC Alarm Interrupt Enable" },
{ "RTSR_HZE", 0x40900008, 3, 0x00000001, 'x', "RTC Hz Interrupt Enable" },
{ "OSMR0", 0x40A00000, 0, 0xffffffff, 'x', "OS Timer Match Register 0 (4-36)" },
{ "OSMR1", 0x40A00004, 0, 0xffffffff, 'x', "OS Timer Match Register 1 (4-36)" },
{ "OSMR2", 0x40A00008, 0, 0xffffffff, 'x', "OS Timer Match Register 2 (4-36)" },
{ "OSMR3", 0x40A0000C, 0, 0xffffffff, 'x', "OS Timer Match Register 3 (4-36)" },
{ "OIER", 0x40A0001C, 0, 0xffffffff, 'x', "OS Timer Interrupt Enable Register (4-36)" },
{ "OIER_E0", 0x40A0001C, 0, 0x00000001, 'x', "OS Interrupt for OSMR0 enabled" },
{ "OIER_E1", 0x40A0001C, 1, 0x00000001, 'x', "OS Interrupt for OSMR1 enabled" },
{ "OIER_E2", 0x40A0001C, 2, 0x00000001, 'x', "OS Interrupt for OSMR2 enabled" },
{ "OIER_E3", 0x40A0001C, 3, 0x00000001, 'x', "OS Interrupt for OSMR3 enabled" },
{ "OWER", 0x40A00018, 0, 0xffffffff, 'x', "OS Timer Watchdog Match Enable Register (4-37)" },
{ "OWER_WME", 0x40A00018, 0, 0x00000001, 'x', "OSMR3 match causes a reset" },
{ "OSCR", 0x40A00010, 0, 0xffffffff, 'x', "OS Timer Count Register (4-37)" },
{ "OSCR_OSCV", 0x40A00010, 0, 0xffffffff, 'x', "OS Timer Count Value" },
{ "OSSR", 0x40A00014, 0, 0xffffffff, 'x', "OS Timer Status Register (4-38)" },
{ "OSSR_M0", 0x40A00014, 0, 0x00000001, 'x', "OS OSMR0 matched OSCR0" },
{ "OSSR_M1", 0x40A00014, 1, 0x00000001, 'x', "OS OSMR1 matched OSCR1" },
{ "OSSR_M2", 0x40A00014, 2, 0x00000001, 'x', "OS OSMR2 matched OSCR2" },
{ "OSSR_M3", 0x40A00014, 3, 0x00000001, 'x', "OS OSMR3 matched OSCR3" },
{ "PWMCTL0", 0x40B00000, 0, 0xffffffff, 'x', "PWM Control Register 0 (4-41)" },
{ "PWMCTL0_PRESCALE", 0x40B00000, 0, 0x0000003f, 'd', "PWM0 Prescale Divisor" },
{ "PWMCTL0_SD", 0x40B00000, 5, 0x00000001, 'x', "PWM0 abrupt shutdown" },
{ "PWMDUTY0", 0x40B00004, 0, 0xffffffff, 'x', "PWM Duty Cycle Register 0 (4-42)" },
{ "PWMDUTY0_DCYCLE", 0x40B00004, 0, 0x000003ff, 'd', "PWM0 Duty Cycle" },
{ "PWMDUTY0_FDCYCLE", 0x40B00004, 10, 0x00000001, 'x', "PWM_OUT0 is set high and does not toggle" },
{ "PWMPERVAL0", 0x40B00008, 0, 0xffffffff, 'x', "PWM Period Control Register 0 (4-43)" },
{ "PWMPERVAL0_PV", 0x40B00008, 0, 0x000003ff, 'd', "PWM0 Period Cycle Length" },
{ "PWMCTL1", 0x40C00000, 0, 0xffffffff, 'x', "PWM Control Register 1 (4-41)" },
{ "PWMCTL1_PRESCALE", 0x40C00000, 0, 0x0000003f, 'd', "PWM1 Prescale Divisor" },
{ "PWMCTL1_SD", 0x40C00000, 5, 0x00000001, 'x', "PWM1 abrupt shutdown" },
{ "PWMDUTY1", 0x40C00004, 0, 0xffffffff, 'x', "PWM Duty Cycle Register 1 (4-42)" },
{ "PWMDUTY1_DCYCLE", 0x40C00004, 0, 0x000003ff, 'd', "PWM1 Duty Cycle" },
{ "PWMDUTY1_FDCYCLE", 0x40C00004, 10, 0x00000001, 'x', "PWM_OUT1 is set high and does not toggle" },
{ "PWMPERVAL1", 0x40C00008, 0, 0xffffffff, 'x', "PWM Period Control Register 1 (4-43)" },
{ "PWMPERVAL1_PV", 0x40C00008, 0, 0x000003ff, 'd', "PWM1 Period Cycle Length" },
{ "LCCR0", 0x44000000, 0, 0xffffffff, 'x', "LCD Controller Control Register 0 (7-23)" },
{ "LCCR0_ENB", 0x44000000, 0, 0x00000001, 'd', "LCD controller enable" },
{ "LCCR0_CMS", 0x44000000, 1, 0x00000001, 'd', "LCD monochrome operation enable" },
{ "LCCR0_SDS", 0x44000000, 2, 0x00000001, 'd', "LCD dual panel display enable" },
{ "LCCR0_LDM", 0x44000000, 3, 0x00000001, 'd', "LCD disable done IRQ disable" },
{ "LCCR0_SFM", 0x44000000, 4, 0x00000001, 'd', "LCD start of frame IRQ disable" },
{ "LCCR0_IUM", 0x44000000, 5, 0x00000001, 'd', "LCD fifo underrun error IRQ disable" },
{ "LCCR0_EFM", 0x44000000, 6, 0x00000001, 'd', "LCD end of frame IRQ disable" },
{ "LCCR0_PAS", 0x44000000, 7, 0x00000001, 'd', "LCD active display enable" },
{ "LCCR0_DPD", 0x44000000, 9, 0x00000001, 'd', "LCD send 8 pixel on L_DD[7:0] at each clock" },
{ "LCCR0_DIS", 0x44000000, 10, 0x00000001, 'd', "LCD controller disable" },
{ "LCCR0_QDM", 0x44000000, 11, 0x00000001, 'd', "LCD quick disable IRQ disable" },
{ "LCCR0_PDD", 0x44000000, 12, 0x000000FF, 'd', "LCD palette DMA request delay" },
{ "LCCR0_BM", 0x44000000, 20, 0x00000001, 'd', "LCD branch start IRQ disable" },
{ "LCCR0_OUM", 0x44000000, 21, 0x00000001, 'd', "LCD fifo underrun IRQ disable" },
{ "LCCR1", 0x44000004, 0, 0xffffffff, 'x', "LCD Controller Control Register 1 (7-26)" },
{ "LCCR1_PPL", 0x44000004, 0, 0x000003ff, 'd', "LCD pixels per line (+1)" },
{ "LCCR1_HSW", 0x44000004, 10, 0x0000003f, 'd', "LCD horizontal sync pulse width (+1)" },
{ "LCCR1_ELW", 0x44000004, 16, 0x000000ff, 'd', "LCD end of line pixel clock wait count (+1)" },
{ "LCCR1_BLW", 0x44000004, 24, 0x000000ff, 'd', "LCD beginning of line pixel clock wait count (+1)" },
{ "LCCR2", 0x44000008, 0, 0xffffffff, 'x', "LCD Controller Control Register 2 (7-28)" },
{ "LCCR2_LPP", 0x44000008, 0, 0x000003ff, 'd', "LCD lines per panel (+1)" },
{ "LCCR2_VSW", 0x44000008, 10, 0x0000003f, 'd', "LCD vertical sync pulse width (+1)" },
{ "LCCR2_EFW", 0x44000008, 16, 0x000000ff, 'd', "LCD end of frame line clock wait count (+1)" },
{ "LCCR2_BFW", 0x44000008, 24, 0x000000ff, 'd', "LCD beginning of frame line clock wait count (+1)" },
{ "LCCR3", 0x4400000C, 0, 0xffffffff, 'x', "LCD Controller Control Register 3 (7-31)" },
{ "LCCR3_PCD", 0x4400000C, 0, 0x000000ff, 'd', "LCD pixel clock divisor (+1)" },
{ "LCCR3_ACB", 0x4400000C, 8, 0x000000ff, 'd', "LCD AC bias pin frequency (+1)" },
{ "LCCR3_API", 0x4400000C, 16, 0x0000000f, 'd', "LCD AC bias pin transitions per interrupt" },
{ "LCCR3_VSP", 0x4400000C, 20, 0x00000001, 'd', "LCD L_FCLK vertical sync polarity active low" },
{ "LCCR3_HSP", 0x4400000C, 21, 0x00000001, 'd', "LCD L_LCLK horizontal sync polarity active low" },
{ "LCCR3_PCP", 0x4400000C, 22, 0x00000001, 'd', "LCD data sampled on falling edge of L_PCLK" },
{ "LCCR3_OEP", 0x4400000C, 23, 0x00000001, 'd', "LCD L_BIAS output enable active low" },
{ "LCCR3_BPP", 0x4400000C, 24, 0x00000007, '<', "LCD bits per pixel" },
{ "LCCR3_DPC", 0x4400000C, 27, 0x00000007, 'd', "LCD double pixel clock rate at L_PCLK" },
{ "LCCR4", 0x44000010, 0, 0xffffffff, 'x', "LCD Controller Control Register 4 (7-31)" },
{ "LCCR5", 0x44000014, 0, 0xffffffff, 'x', "LCD Controller Control Register 5 (7-31)" },
{ "FBR0", 0x44000020, 0, 0xffffffff, 'x', "FBR0" },
{ "FBR1", 0x44000020, 0, 0xffffffff, 'x', "FBR1" },
{ "LCSR1", 0x44000034, 0, 0xffffffff, 'x', "LCD Controller Status Register 1 (7-40)" },
{ "LCSR0", 0x44000038, 0, 0xffffffff, 'x', "LCD Controller Status Register 0 (7-40)" },
{ "LIIDR", 0x4400003C, 0, 0xffffffff, 'x', "LCD Controller Interrupt ID Register (7-41)" },
// TODO
{ "TRGBBR", 0x44000040, 0, 0xffffffff, 'x', "TMED RBG Seed Register (7-42)" },
{ "TRGBBR_TRS",0x44000040, 0, 0x000000ff, 'x', "Red Seed" },
{ "TRGBBR_TGS",0x44000040, 8, 0x000000ff, 'x', "Green Seed" },
{ "TRGBBR_TBS",0x44000040, 16, 0x000000ff, 'x', "Blue Seed" },
{ "TCR", 0x44000044, 0, 0xffffffff, 'x', "TMED Control Register (7-44)" },
{ "TCR_COAM", 0x44000044, 0, 0x00000001, 'x', "Color Offset Adjuster Matrix" },
{ "TCR_FNAM", 0x44000044, 1, 0x00000001, 'x', "Frame Number Adjuster Matrix" },
{ "TCR_COAE", 0x44000044, 2, 0x00000001, 'x', "Color Offset Adjuster Enable" },
{ "TCR_FNAME", 0x44000044, 3, 0x00000001, 'x', "Frame Number Adjuster Enable" },
{ "TCR_TVBS", 0x44000044, 4, 0x0000000f, 'd', "Vertical Beat Suppression" },
{ "TCR_THBS", 0x44000044, 8, 0x0000000f, 'd', "Horizontal Beat Suppression" },
{ "TCR_TED", 0x44000044, 14, 0x00000001, 'x', "Energy Distribution Matrix Select" },
{ "FDADR0", 0x44000200, 0, 0xffffffff, 'x', "FDADR0" },
{ "FSADR0", 0x44000204, 0, 0xffffffff, 'x', "FSADR0" },
{ "FIDR0", 0x44000208, 0, 0xffffffff, 'x', "FODR0" },
{ "LDCMD0", 0x4400020C, 0, 0xffffffff, 'x', "LDCMD0" },
{ "FDADR1", 0x44000210, 0, 0xffffffff, 'x', "FDADR1" },
{ "FSADR1", 0x44000214, 0, 0xffffffff, 'x', "FSADR1" },
{ "FIDR1", 0x44000218, 0, 0xffffffff, 'x', "FIDR1" },
{ "LDCMD1", 0x4400021C, 0, 0xffffffff, 'x', "LDCMD1" },
// TODO
{ "MDCNFG", 0x48000000, 0, 0xffffffff, 'x', "SDRAM Configuration Register (6-9)" },
{ "MDCNFG_DE0", 0x48000000, 0, 0x00000001, 'd', "SDRAM enable for partition 0" },
{ "MDCNFG_DE1", 0x48000000, 1, 0x00000001, 'd', "SDRAM enable for partition 1" },
{ "MDCNFG_DWID0", 0x48000000, 2, 0x00000001, 'd', "SDRAM data width (0=32, 1=16)" },
{ "MDCNFG_DCAC0", 0x48000000, 3, 0x00000003, 'd', "Column address bits for partition pair 0/1" },
{ "MDCNFG_DRAC0", 0x48000000, 5, 0x00000003, 'd', "Row address bits for partition pair 0/1" },
{ "MDCNFG_DNB0", 0x48000000, 7, 0x00000001, 'd', "Banks in partition pair 0/1 (0=2, 1=4)" },
{ "MDCNFG_DTC0", 0x48000000, 8, 0x00000003, 'd', "Timing Category for partition pair 0/1" },
{ "MDCNFG_DADDR0", 0x48000000,10, 0x00000001, 'd', "Use alternate addressing for partition pair 0/1" },
{ "MDCNFG_DLATCH0", 0x48000000,11, 0x00000001, 'd', "Return data latching scheme for partition pair 0/1" },
{ "MDCNFG_DSA11110",0x48000000,12, 0x00000001, 'd', "use SA1111 address muxing for partition pair 0/1" },
{ "MDCNFG_DE2", 0x48000000,16, 0x00000001, 'd', "SDRAM enable for partition 2" },
{ "MDCNFG_DE3", 0x48000000,17, 0x00000001, 'd', "SDRAM enable for partition 3" },
{ "MDCNFG_DWID2", 0x48000000,18, 0x00000001, 'd', "SDRAM data width (0=32, 1=16)" },
{ "MDCNFG_DCAC2", 0x48000000,19, 0x00000003, 'd', "Column address bits for partition pair 2/3" },
{ "MDCNFG_DRAC2", 0x48000000,21, 0x00000003, 'd', "Row address bits for partition pair 2/3" },
{ "MDCNFG_DNB2", 0x48000000,23, 0x00000001, 'd', "Banks in partition pair 2/3 (0=2, 1=4)" },
{ "MDCNFG_DTC2", 0x48000000,24, 0x00000003, 'd', "Timing Category for partition pair 2/3" },
{ "MDCNFG_DADDR2", 0x48000000,26, 0x00000001, 'd', "Use alternate addressing for partition pair 2/3" },
{ "MDCNFG_DLATCH2", 0x48000000,27, 0x00000001, 'd', "Return data latching scheme for partition pair 2/3" },
{ "MDCNFG_DSA11112",0x48000000,28, 0x00000001, 'd', "use SA1111 address muxing for partition pair 2/3" },
{ "MDREFR", 0x48000004, 0, 0xffffffff, 'x', "SDRAM Refresh Configuration Register (6-15)" },
{ "MDREFR_DRI", 0x48000004, 0, 0x00000fff, 'x', "SDRAM Refresh intervall, all paritions" },
{ "MDREFR_E0PIN", 0x48000004,12, 0x00000001, 'x', "SDRAM Clock Enable Pin 0 Level" },
{ "MDREFR_K0RUN", 0x48000004,13, 0x00000001, 'x', "SDRAM Clock Run Pin 0" },
{ "MDREFR_K0DB2", 0x48000004,14, 0x00000001, 'x', "SDRAM Clock Pin 0 Divide/2" },
{ "MDREFR_E1PIN", 0x48000004,15, 0x00000001, 'x', "SDRAM Clock Enable Pin 1 Level" },
{ "MDREFR_K1RUN", 0x48000004,16, 0x00000001, 'x', "SDRAM Clock Run Pin 1" },
{ "MDREFR_K1DB2", 0x48000004,17, 0x00000001, 'x', "SDRAM Clock Pin 1 Divide/2" },
{ "MDREFR_K2RUN", 0x48000004,18, 0x00000001, 'x', "SDRAM Clock Run Pin 2" },
{ "MDREFR_K2DB2", 0x48000004,19, 0x00000001, 'x', "SDRAM Clock Pin 2 Divide/2" },
{ "MDREFR_APD", 0x48000004,20, 0x00000001, 'x', "SDRAM Auto Power Down enable" },
{ "MDREFR_SLFRSH", 0x48000004,22, 0x00000001, 'x', "SDRAM Self-Refresh" },
{ "MDREFR_K0FREE", 0x48000004,23, 0x00000001, 'x', "SDRAM Free Running Control for SDCLK0" },
{ "MDREFR_K1FREE", 0x48000004,24, 0x00000001, 'x', "SDRAM Free Running Control for SDCLK1" },
{ "MDREFR_K2FREE", 0x48000004,25, 0x00000001, 'x', "SDRAM Free Running Control for SDCLK2" },
{ "MSC0", 0x48000008, 0, 0xffffffff, 'x', "Asynchronous Static Memory Control Register 0 (6-45)" },
{ "MSC0_RT0", 0x48000008, 0, 0x00000007, 'd', "nCS[0] ROM Type" },
{ "MSC0_RBW0", 0x48000008, 3, 0x00000001, 'd', "nCS[0] ROM Bus Width (1=16bit)" },
{ "MSC0_RDF0", 0x48000008, 4, 0x0000000f, 'd', "nCS[0] ROM Delay First Access" },
{ "MSC0_RDN0", 0x48000008, 8, 0x0000000f, 'd', "nCS[0] ROM Delay Next Access" },
{ "MSC0_RRR0", 0x48000008,12, 0x00000007, 'd', "nCS[0] ROM/SRAM Recovery Time" },
{ "MSC0_RBUFF0", 0x48000008,15, 0x00000001, 'd', "nCS[0] Return Buffer Behavior (1=streaming)" },
{ "MSC0_RT1", 0x48000008,16, 0x00000007, 'd', "nCS[1] ROM Type" },
{ "MSC0_RBW1", 0x48000008,19, 0x00000001, 'd', "nCS[1] ROM Bus Width (1=16bit)" },
{ "MSC0_RDF1", 0x48000008,20, 0x0000000f, 'd', "nCS[1] ROM Delay First Access" },
{ "MSC0_RDN1", 0x48000008,24, 0x0000000f, 'd', "nCS[1] ROM Delay Next Access" },
{ "MSC0_RRR1", 0x48000008,28, 0x00000007, 'd', "nCS[1] ROM/SRAM Recovery Time" },
{ "MSC0_RBUFF1", 0x48000008,31, 0x00000001, 'd', "nCS[1] Return Buffer Behavior (1=streaming)" },
{ "MSC1", 0x4800000C, 0, 0xffffffff, 'x', "Asynchronous Static Memory Control Register 1 (6-45)" },
{ "MSC1_RT2", 0x4800000C, 0, 0x00000007, 'd', "nCS[2] ROM Type" },
{ "MSC1_RBW2", 0x4800000C, 3, 0x00000001, 'd', "nCS[2] ROM Bus Width (1=16bit)" },
{ "MSC1_RDF2", 0x4800000C, 4, 0x0000000f, 'd', "nCS[2] ROM Delay First Access" },
{ "MSC1_RDN2", 0x4800000C, 8, 0x0000000f, 'd', "nCS[2] ROM Delay Next Access" },
{ "MSC1_RRR2", 0x4800000C,12, 0x00000007, 'd', "nCS[2] ROM/SRAM Recovery Time" },
{ "MSC1_RBUFF2", 0x4800000C,15, 0x00000001, 'd', "nCS[2] Return Buffer Behavior (1=streaming)" },
{ "MSC1_RT3", 0x4800000C,16, 0x00000007, 'd', "nCS[3] ROM Type" },
{ "MSC1_RBW3", 0x4800000C,19, 0x00000001, 'd', "nCS[3] ROM Bus Width (1=16bit)" },
{ "MSC1_RDF3", 0x4800000C,20, 0x0000000f, 'd', "nCS[3] ROM Delay First Access" },
{ "MSC1_RDN3", 0x4800000C,24, 0x0000000f, 'd', "nCS[3] ROM Delay Next Access" },
{ "MSC1_RRR3", 0x4800000C,28, 0x00000007, 'd', "nCS[3] ROM/SRAM Recovery Time" },
{ "MSC1_RBUFF3", 0x4800000C,31, 0x00000001, 'd', "nCS[3] Return Buffer Behavior (1=streaming)" },
{ "MSC2", 0x48000010, 0, 0xffffffff, 'x', "Asynchronous Static Memory Control Register 2 (6-45)" },
{ "MSC2_RT4", 0x48000010, 0, 0x00000007, 'd', "nCS[4] ROM Type" },
{ "MSC2_RBW4", 0x48000010, 3, 0x00000001, 'd', "nCS[4] ROM Bus Width (1=16bit)" },
{ "MSC2_RDF4", 0x48000010, 4, 0x0000000f, 'd', "nCS[4] ROM Delay First Access" },
{ "MSC2_RDN4", 0x48000010, 8, 0x0000000f, 'd', "nCS[4] ROM Delay Next Access" },
{ "MSC2_RRR4", 0x48000010,12, 0x00000007, 'd', "nCS[4] ROM/SRAM Recovery Time" },
{ "MSC2_RBUFF4", 0x48000010,15, 0x00000001, 'd', "nCS[4] Return Buffer Behavior (1=streaming)" },
{ "MSC2_RT5", 0x48000010,16, 0x00000007, 'd', "nCS[5] ROM Type" },
{ "MSC2_RBW5", 0x48000010,19, 0x00000001, 'd', "nCS[5] ROM Bus Width (1=16bit)" },
{ "MSC2_RDF5", 0x48000010,20, 0x0000000f, 'd', "nCS[5] ROM Delay First Access" },
{ "MSC2_RDN5", 0x48000010,24, 0x0000000f, 'd', "nCS[5] ROM Delay Next Access" },
{ "MSC2_RRR5", 0x48000010,28, 0x00000007, 'd', "nCS[5] ROM/SRAM Recovery Time" },
{ "MSC2_RBUFF5", 0x48000010,31, 0x00000001, 'd', "nCS[5] Return Buffer Behavior (1=streaming)" },
{ "MECR", 0x48000014, 0, 0xffffffff, 'x', "Expansion Memory Configuration Register (6-61)" },
{ "MECR_NOS", 0x48000014, 0, 0x00000001, 'x', "Number of Sockets (1=2 Sockets)" },
{ "MECR_CIT", 0x48000014, 1, 0x00000001, 'x', "Card inserted" },
{ "SXCNFG", 0x4800001C, 0, 0xffffffff, 'x', "Synchronous Static Memory Configuration Register (6-33)" },
{ "SXCNFG_SXEN0", 0x4800001C, 0, 0x00000001, 'x', "Partition 0 enabled as SX memory" },
{ "SXCNFG_SXEN1", 0x4800001C, 1, 0x00000001, 'x', "Partition 1 enabled as SX memory" },
{ "SXCNFG_SXCL0", 0x4800001C, 2, 0x00000007, 'x', "Partition 0/1 CAS Latency" },
{ "SXCNFG_SXRL0", 0x4800001C, 5, 0x00000007, 'x', "Partition 0/1 RAS Latency" },
{ "SXCNFG_SXRA0", 0x4800001C, 8, 0x00000003, 'x', "Partition 0/1 row address bit count" },
{ "SXCNFG_SXCA0", 0x4800001C,10, 0x00000003, 'x', "Partition 0/1 column address bit count" },
{ "SXCNFG_SXTP0", 0x4800001C,12, 0x00000003, 'x', "Partition 0/1 memory type" },
{ "SXCNFG_SXLATCH0",0x4800001C,14, 0x00000001, 'x', "Partition 0/1 return data with return clock" },
{ "SXCNFG_SXEN2", 0x4800001C,16, 0x00000001, 'x', "Partition 2 enabled as SX memory" },
{ "SXCNFG_SXEN3", 0x4800001C,17, 0x00000001, 'x', "Partition 3 enabled as SX memory" },
{ "SXCNFG_SXCL2", 0x4800001C,18, 0x00000007, 'x', "Partition 2/3 CAS Latency" },
{ "SXCNFG_SXRL2", 0x4800001C,21, 0x00000007, 'x', "Partition 2/3 RAS Latency" },
{ "SXCNFG_SXRA2", 0x4800001C,24, 0x00000003, 'x', "Partition 2/3 row address bit count" },
{ "SXCNFG_SXCA2", 0x4800001C,26, 0x00000003, 'x', "Partition 2/3 column address bit count" },
{ "SXCNFG_SXTP2", 0x4800001C,28, 0x00000003, 'x', "Partition 2/3 memory type" },
{ "SXCNFG_SXLATCH2",0x4800001C,30, 0x00000001, 'x', "Partition 2/3 return data with return clock" },
{ "SXMRS", 0x48000024, 0, 0xffffffff, 'x', "MRS value to be written to SX Memory (6-38)" },
{ "MCMEM0", 0x48000028, 0, 0xffffffff, 'x', "MEM Control for PCMCIA Socket 0 (6-58)" },
{ "MCMEM0_SET", 0x48000028, 0, 0x0000007f, 'd', "Address set time" },
{ "MCMEM0_ASST", 0x48000028, 7, 0x0000001f, 'd', "Command assertion time" },
{ "MCMEM0_HOLD", 0x48000028,14, 0x0000003f, 'd', "Address hold time" },
{ "MCMEM1", 0x4800002C, 0, 0xffffffff, 'x', "MEM Control for PCMCIA Socket 1 (6-58)" },
{ "MCMEM1_SET", 0x4800002C, 0, 0x0000007f, 'd', "Address set time" },
{ "MCMEM1_ASST", 0x4800002C, 7, 0x0000001f, 'd', "Command assertion time" },
{ "MCMEM1_HOLD", 0x4800002C,14, 0x0000003f, 'd', "Address hold time" },
{ "MCATT0", 0x48000030, 0, 0xffffffff, 'x', "ATT Control for PCMCIA Socket 0 (6-59)" },
{ "MCATT0_SET", 0x48000030, 0, 0x0000007f, 'd', "Address set time" },
{ "MCATT0_ASST", 0x48000030, 7, 0x0000001f, 'd', "Command assertion time" },
{ "MCATT0_HOLD", 0x48000030,14, 0x0000003f, 'd', "Address hold time" },
{ "MCATT1", 0x48000034, 0, 0xffffffff, 'x', "ATT Control for PCMCIA Socket 1 (6-59)" },
{ "MCATT1_SET", 0x48000034, 0, 0x0000007f, 'd', "Address set time" },
{ "MCATT1_ASST", 0x48000034, 7, 0x0000001f, 'd', "Command assertion time" },
{ "MCATT1_HOLD", 0x48000034,14, 0x0000003f, 'd', "Address hold time" },
{ "MCIO0", 0x48000038, 0, 0xffffffff, 'x', "I/O Control for PCMCIA Socket 0 (6-59)" },
{ "MCIO0_SET", 0x48000038, 0, 0x0000007f, 'd', "Address set time" },
{ "MCIO0_ASST", 0x48000038, 7, 0x0000001f, 'd', "Command assertion time" },
{ "MCIO0_HOLD", 0x48000038,14, 0x0000003f, 'd', "Address hold time" },
{ "MCIO1", 0x4800003C, 0, 0xffffffff, 'x', "I/O Control for PCMCIA Socket 1 (6-59)" },
{ "MCIO1_SET", 0x4800003C, 0, 0x0000007f, 'd', "Address set time" },
{ "MCIO1_ASST", 0x4800003C, 7, 0x0000001f, 'd', "Command assertion time" },
{ "MCIO1_HOLD", 0x4800003C,14, 0x0000003f, 'd', "Address hold time" },
{ "MDMRS", 0x48000040, 0, 0xffffffff, 'x', "SDRAM Mode Register Set Configuration Register (6-12)" },
{ "MDMRS_MDBL0", 0x48000040, 0, 0x00000007, 'x', "SDRAM Partition 0/1 burst length" },
{ "MDMRS_MDADD0", 0x48000040, 3, 0x00000001, 'x', "SDRAM Partition 0/1 burst type" },
{ "MDMRS_MDCL0", 0x48000040, 4, 0x00000007, 'x', "SDRAM Partition 0/1 CAS latency" },
{ "MDMRS_MDMRS0", 0x48000040, 7, 0x000000ff, 'x', "MRS value to be written to SDRAM Partition 0/1" },
{ "MDMRS_MDBL2", 0x48000040,16, 0x00000007, 'x', "SDRAM Partition 2/3 burst length" },
{ "MDMRS_MDADD2", 0x48000040,19, 0x00000001, 'x', "SDRAM Partition 2/3 burst type" },
{ "MDMRS_MDCL2", 0x48000040,20, 0x00000007, 'x', "SDRAM Partition 2/3 CAS latency" },
{ "MDMRS_MDMRS2", 0x48000040,23, 0x000000ff, 'x', "MRS value to be written to SDRAM Partition 2/3" },
{ "BOOTDEF", 0x48000044, 0, 0xffffffff, 'x', "Boot Time Defaults (6-73)" },
{ "BOOTDEF_BOOTSEL",0x48000044, 0, 0x00000007, 'x', "Boot Configuration at BOOT_SEL pins" },
{ "BOOTDEF_PKGTYPE",0x48000044, 3, 0x00000001, 'x', "Processor type, 1 for PXA250" },
{ "LCDBSCNTR", 0x48000054, 0, 0xffffffff, 'x', "LCD Buffer Strength Control register" },
{ "MDMRSLP", 0x48000058, 0, 0xffffffff, 'x', "Low-Power SDRAM Mode Register Set Configuration Register (6-14)" },
// TODO
{ "MMC_STRPCL", 0x41100000, 0, 0xffffffff, 'x', "MMC Start/Stop Clock (15-23)" },
{ "MMC_STAT", 0x41100004, 0, 0xffffffff, 'x', "MMC Status Register (15-24)" },
{ "MMC_STAT_READ_TIME_OUT", 0x41100004, 0, 0x00000001, 'x', "Read Time Out" },
{ "MMC_STAT_TIME_OUT_RESP", 0x41100004, 1, 0x00000001, 'x', "Time Out Response" },
{ "MMC_STAT_CRC_WRITE_ERROR", 0x41100004, 2, 0x00000001, 'x', "CRC Write Error" },
{ "MMC_STAT_CRC_READ_ERR", 0x41100004, 3, 0x00000001, 'x', "CRC Read Error" },
{ "MMC_STAT_SPI_READ_ERR_TKN", 0x41100004, 4, 0x00000001, 'x', "SPI Read Error Token" },
{ "MMC_STAT_RES_CRC_ERR", 0x41100004, 5, 0x00000001, 'x', "Response CRC Error" },
{ "MMC_STAT_XMIT_FIFO_EMPTY", 0x41100004, 6, 0x00000001, 'x', "Transmit FIFO Empty" },
{ "MMC_STAT_RECV_FIFO_EMPTY", 0x41100004, 7, 0x00000001, 'x', "Receive FIFO Empty" },
{ "MMC_STAT_CLK_EN", 0x41100004, 8, 0x00000001, 'x', "Clock Enabled" },
{ "MMC_STAT_DATA_TRAN_DONE", 0x41100004,11, 0x00000001, 'x', "Data Transmission Done" },
{ "MMC_STAT_PRG_DONE", 0x41100004,12, 0x00000001, 'x', "Program Done" },
{ "MMC_STAT_END_CMD_RES", 0x41100004,13, 0x00000001, 'x', "End Command Response" },
{ "MMC_CLKRT", 0x41100008, 0, 0xffffffff, 'x', "MMC Clock Read Timeout Register (15-26)" },
{ "MMC_CLK_RATE", 0x41100008, 0, 0x00000007, 'x', "Read Time Out bitmask" },
{ "MMC_SPI", 0x4110000c, 0, 0xffffffff, 'x', "MMC SPI mode (15-27)" },
{ "MMC_SPI_EN", 0x4110000c, 0, 0x00000001, 'x', "SPI mode enabled" },
{ "MMC_SPI_CRC_ON", 0x4110000c, 1, 0x00000001, 'x', "CRC generation enabled" },
{ "MMC_SPI_CS_EN", 0x4110000c, 2, 0x00000001, 'x', "SPI chip select enabled" },
{ "MMC_SPI_CS_ADDRESS", 0x4110000c, 3, 0x00000001, 'x', "CS0 enabled" },
{ "MMC_CMDAT", 0x41100010, 0, 0xffffffff, 'x', "MMC Command Data (15-28)" },
{ "MMC_CMDAT_RF", 0x41100010, 0, 0x00000003, 'x', "response format" },
{ "MMC_CMDAT_DATA_EN", 0x41100010, 2, 0x00000001, 'x', "current cmd includes data transfer" },
{ "MMC_CMDAT_WRITE", 0x41100010, 3, 0x00000001, 'x', "data transfer is a write" },
{ "MMC_CMDAT_STREAM", 0x41100010, 4, 0x00000001, 'x', "data transfer is in stream mode" },
{ "MMC_CMDAT_BUSY", 0x41100010, 5, 0x00000001, 'x', "busy signal is expected after data transfer" },
{ "MMC_CMDAT_INIT", 0x41100010, 6, 0x00000001, 'x', "precede cmd with 80 clocks" },
{ "MMC_CMDAT_DMA_EN", 0x41100010, 7, 0x00000001, 'x', "enable DMA mode" },
{ "MMC_RESTO", 0x41100014, 0, 0xffffffff, 'x', "MMC Response Time Out (15-29)" },
{ "MMC_RESTO_TO", 0x41100014, 0, 0x0000007f, 'd', "clocks before a response time out" },
{ "MMC_RDTO", 0x41100018, 0, 0xffffffff, 'x', "MMC Read Time Out (15-29)" },
{ "MMC_RDTO_TO", 0x41100018, 0, 0x0000ffff, 'd', "time until read time out" },
{ "MMC_BLKLEN", 0x4110001C, 0, 0xffffffff, 'x', "MMC Block Len Register (15-30)" },
{ "MMC_BLKLEN_LEN", 0x4110001C, 0, 0x000003ff, 'd', "Number of bytes in the block" },
{ "MMC_NOB", 0x41100020, 0, 0xffffffff, 'x', "MMC Block Number Register (15-30)" },
{ "MMC_NOB_N", 0x41100020, 0, 0x0000ffff, 'd', "number of blocks" },
{ "MMC_PRTBUF", 0x41100024, 0, 0xffffffff, 'x', "MMC Partial Buffer Register (15-31)" },
{ "MMC_PRTBUF_FULL", 0x41100024, 0, 0x00000001, 'x', "Buffer is partially full" },
{ "MMC_IMASK", 0x41100028, 0, 0xffffffff, 'x', "MMC Interrupt Mask Register (15-31)" },
{ "MMC_IMASK_DATATRAN", 0x41100028, 0, 0x00000001, 'x', "Data Transfer Done masked" },
{ "MMC_IMASK_PRGDONE", 0x41100028, 1, 0x00000001, 'x', "Programming Done masked" },
{ "MMC_IMASK_ENDCMD", 0x41100028, 2, 0x00000001, 'x', "End Command Response masked" },
{ "MMC_IMASK_STOPCMD", 0x41100028, 3, 0x00000001, 'x', "Ready for Stop Transaction Command masked" },
{ "MMC_IMASK_CLOCKOFF", 0x41100028, 4, 0x00000001, 'x', "Clock Is Off masked" },
{ "MMC_IMASK_RXFIFO", 0x41100028, 5, 0x00000001, 'x', "Receive FIFO Read Request masked" },
{ "MMC_IMASK_TXFIFO", 0x41100028, 6, 0x00000001, 'x', "Transmit FIFO Write Request masked" },
{ "MMC_IREG", 0x4110002c, 0, 0xffffffff, 'x', "MMC Interrupt Register (15-33)" },
{ "MMC_IREG_DATATRAN", 0x4110002c, 0, 0x00000001, 'x', "Data Transfer Done or Read TimeOut occured" },
{ "MMC_IREG_PRGDONE", 0x4110002c, 1, 0x00000001, 'x', "Card has finished programming" },
{ "MMC_IREG_ENDCMD", 0x4110002c, 2, 0x00000001, 'x', "MMC has received response or Response TimeOut" },
{ "MMC_IREG_STOPCMD", 0x4110002c, 3, 0x00000001, 'x', "MMC is ready for the Stop Transaction Command" },
{ "MMC_IREG_CLOCKOFF", 0x4110002c, 4, 0x00000001, 'x', "MMC clock has been turned off" },
{ "MMC_IREG_RXFIFO", 0x4110002c, 5, 0x00000001, 'x', "Request for data read from receive FIFO" },
{ "MMC_IREG_TXFIFO", 0x4110002c, 6, 0x00000001, 'x', "Request to data write to transmit FIFO" },
{ "MMC_CMD", 0x41100030, 0, 0xffffffff, 'x', "MMC Command Register (15-34)" },
{ "MMC_CMD_INDEX", 0x41100030, 0, 0x0000003f, 'x', "command index" },
{ "MMC_ARGH", 0x41100034, 0, 0xffffffff, 'x', "MMC Higher Argument Register (15-36)" },
{ "MMC_ARGH_ARG", 0x41100034, 0, 0x0000ffff, 'x', "upper 16 bits of command argument" },
{ "MMC_ARGL", 0x41100038, 0, 0xffffffff, 'x', "MMC Lower Argument Register (15-36)" },
{ "MMC_ARGL_ARG", 0x41100038, 0, 0x0000ffff, 'x', "upper 16 bits of command argument" },
#if defined(CONFIG_ARCH_PXA_IDP) || defined(CONFIG_ARCH_RAMSES)
// CS5+0x03C00000 CPLD 0x14000000
// CS1 Alt-Flash 0x04000000
// CS0 Flash 0x00000000
{ "CPLD_PWR", 0x17C00004, 0, 0x000000ff, 'x', "CPLD_PERIPH_PWR" },
{ "CPLD_PWR_CORE", 0x17C00004, 0, 0x00000001, 'd', "Variable core enable - latch value in first" },
#ifdef CONFIG_ARCH_PXA_IDP
{ "CPLD_PWR_MQ", 0x17C00004, 2, 0x00000001, 'd', "MQ1132 power switch" },
#else
{ "CPLD_PWR_SL811HS", 0x17C00004, 2, 0x00000001, 'd', "SL811HS power switch" },
#endif
{ "CPLD_PWR_PER", 0x17C00004, 3, 0x00000001, 'd', "peripheral power enable" },
{ "CPLD_PWR_RST", 0x17C00004, 4, 0x00000001, 'd', "peripheral reset" },
{ "CPLD_LED", 0x17C00008, 0, 0x000000ff, 'x', "CPLD_LED_CONTROL" },
{ "CPLD_LED_CIR", 0x17C00008, 0, 0x00000001, 'd', "CIR" },
{ "CPLD_LED_HB", 0x17C00008, 5, 0x00000001, 'd', "red LED (0=on)" },
{ "CPLD_LED_BUSY", 0x17C00008, 6, 0x00000001, 'd', "green LED (0=on)" },
{ "CPLD_LED_FLASH", 0x17C00008, 7, 0x00000001, 'd', "red LED flash enable" },
{ "CPLD_KBD_COL_HIGH", 0x17C0000C, 0, 0x000000ff, 'x', "CPLD" },
{ "CPLD_KBD_COL_LOW", 0x17C00010, 0, 0x000000ff, 'x', "CPLD" },
{ "CPLD_PCCARD_EN", 0x17C00014, 0, 0x000000ff, 'x', "CPLD PC-Card Enable" },
{ "CPLD_PCC0_ENABLE", 0x17C00014, 0, 0x00000001, 'd', "PC-Card 0 enable" },
{ "CPLD_PCC1_ENABLE", 0x17C00014, 1, 0x00000001, 'd', "PC-Card 1 enable" },
{ "CPLD_PCC0_RESET", 0x17C00014, 6, 0x00000001, 'd', "PC-Card 0 reset" },
{ "CPLD_PCC1_RESET", 0x17C00014, 7, 0x00000001, 'd', "PC-Card 1 reset" },
/*
{ "CPLD_GPIOH_DIR", 0x17C00018, 0, 0xffffffff, 'x', "CPLD" },
{ "CPLD_GPIOH_VALUE", 0x17C0001C, 0, 0xffffffff, 'x', "CPLD" },
{ "CPLD_GPIOL_DIR", 0x17C00020, 0, 0xffffffff, 'x', "CPLD" },
{ "CPLD_GPIOL_VALUE", 0x17C00024, 0, 0xffffffff, 'x', "CPLD" },
WHEN "00110" =>
data(7) <= l3_data_out; -- L3 IIS control bus - direction of data bit
data(6) <= '0';
data(5) <= '0';
data(4) <= '0';
data(3) <= '0';
data(2) <= '0';
data(1) <= gpslow_out(1); -- direction of pld_gpio_09
data(0) <= gpslow_out(0); -- direction of pld_gpio_08
WHEN "00111" => -- gpio on async bus
data(7) <= l3_data_io; -- L3 IIS control bus - always reads pin
data(6) <= l3_clk; -- L3 IIS control bus - read back clock
data(5) <= l3_mode; -- L3 IIS control bus - read back mode
data(4) <= '0';
data(3) <= '0';
data(2) <= '0';
data(1) <= gpslow_io(1); -- gpio on async bus
data(0) <= gpslow_io(0); -- gpio on async bus
WHEN "01000" =>
data <= gp_out; -- direction of pld_gpio_07 through 00
WHEN "01001" => -- gpio on high speed bus
data <= gp_io;
*/
{ "CPLD_PCCARD_PWR", 0x17C00028, 0, 0x000000ff, 'x', "CPLD PC-Card Power" },
{ "CPLD_PCC0_PWR0", 0x17C00028, 0, 0x00000001, 'd', "PC-Card 0 Pwr 0" },
{ "CPLD_PCC0_PWR1", 0x17C00028, 1, 0x00000001, 'd', "PC-Card 0 Pwr 1" },
{ "CPLD_PCC0_PWR2", 0x17C00028, 2, 0x00000001, 'd', "PC-Card 0 Pwr 2" },
{ "CPLD_PCC0_PWR3", 0x17C00028, 3, 0x00000001, 'd', "PC-Card 0 Pwr 3" },
{ "CPLD_PCC1_PWR0", 0x17C00028, 4, 0x00000001, 'd', "PC-Card 1 Pwr 0" },
{ "CPLD_PCC1_PWR1", 0x17C00028, 5, 0x00000001, 'd', "PC-Card 1 Pwr 1" },
{ "CPLD_PCC1_PWR2", 0x17C00028, 6, 0x00000001, 'd', "PC-Card 1 Pwr 2" },
{ "CPLD_PCC1_PWR3", 0x17C00028, 7, 0x00000001, 'd', "PC-Card 1 Pwr 3" },
{ "CPLD_MISC", 0x17C0002C, 0, 0x000000ff, 'x', "CPLD_MISC_CTRL" },
{ "CPLD_MISC_SER1EN", 0x17C0002C, 0, 0x00000001, 'd', "RS-232 on FF UART enable" },
{ "CPLD_MISC_SER2EN", 0x17C0002C, 1, 0x00000001, 'd', "RS-232 on BT UART enable" },
{ "CPLD_MISC_SER3EN", 0x17C0002C, 2, 0x00000001, 'd', "RS-232 on ST UART enable" },
{ "CPLD_MISC_IRDAFIR", 0x17C0002C, 3, 0x00000001, 'd', "IrDA FIR enable" },
{ "CPLD_MISC_IRDAMD0", 0x17C0002C, 4, 0x00000001, 'd', "IrDA mode 0" },
{ "CPLD_MISC_IRDAMD1", 0x17C0002C, 5, 0x00000001, 'd', "IrDA mode 1" },
#ifdef CONFIG_ARCH_PXA_IDP
{ "CPLD_MISC_I2SPWR", 0x17C0002C, 7, 0x00000001, 'd', "UDA1341 power switch" },
#endif
{ "CPLD_LCD", 0x17C00030, 0, 0x000000ff, 'x', "CPLD LCD Control", },
#ifdef CONFIG_ARCH_PXA_IDP
{ "CPLD_LCD_PWR", 0x17C00030, 0, 0x00000001, 'd', "LCD Power" },
{ "CPLD_LCD_BACKLIGHT", 0x17C00030, 1, 0x00000001, 'd', "LCD Backlight" },
{ "CPLD_LCD_VLCD", 0x17C00030, 2, 0x00000001, 'd', "LCD VLCD" },
#else
{ "CPLD_LCD_VCC", 0x17C00030, 0, 0x00000001, 'd', "LCD VCC" },
{ "CPLD_LCD_DISPOFF", 0x17C00030, 2, 0x00000001, 'd', "LCD nDISPOFF" },
#endif
{ "CPLD_FLASH", 0x17C00034, 0, 0x000000ff, 'x', "CPLD Flash Control" },
{ "CPLD_FLASH_WE", 0x17C00034, 0, 0x00000001, 'd', "CPLD StrataFlash Write Enable" },
#ifdef CONFIG_ARCH_PXA_IDP
{ "CPLD_FLASH_MWE", 0x17C00034, 1, 0x00000001, 'd', "CPLD MPlus Write Enable" },
{ "CPLD_FLASH_MOE", 0x17C00034, 2, 0x00000001, 'd', "CPLD MPlus Output Enable" },
{ "CPLD_CS", 0x17C00038, 0, 0x000000ff, 'x', "CPLD Chip Select Register" },
{ "CPLD_CS_CS0EN", 0x17C00038, 0, 0x00000001, 'd', "CPLD Chip Select 0 Enable" },
{ "CPLD_CS_CS1EN", 0x17C00038, 1, 0x00000001, 'd', "CPLD Chip Select 1 Enable" },
{ "CPLD_CS_CS2EN", 0x17C00038, 2, 0x00000001, 'd', "CPLD Chip Select 2 Enable" },
{ "CPLD_CS_CS3EN", 0x17C00038, 3, 0x00000001, 'd', "CPLD Chip Select 3 Enable" },
{ "CPLD_CS_CS4EN", 0x17C00038, 4, 0x00000001, 'd', "CPLD Chip Select 4 Enable" },
//{ "CPLD_CS_CS5EN", 0x17C00038, 4, 0x00000001, 'd', "CPLD Chip Select 5 Enable" },
#endif
{ "CPLD_KB_ROW", 0x17C00050, 0, 0x000000ff, 'x', "CPLD" },
{ "CPLD_PCCARD0_STATUS", 0x17C00054, 0, 0x000000ff, 'x', "CPLD PC-Card 0 Status" },
{ "CPLD_PCC0_VS1", 0x17C00054, 0, 0x00000001, 'd', "PC-Card 0 VS1" },
{ "CPLD_PCC0_VS2", 0x17C00054, 1, 0x00000001, 'd', "PC-Card 0 VS2" },
{ "CPLD_PCC0_BVD1", 0x17C00054, 2, 0x00000001, 'd', "PC-Card 0 BVD1" },
{ "CPLD_PCC0_BVD2", 0x17C00054, 3, 0x00000001, 'd', "PC-Card 0 BVD2" },
{ "CPLD_PCC0_INPACK", 0x17C00054, 4, 0x00000001, 'd', "PC-Card 0 INPACK" },
{ "CPLD_PCC0_IRQ", 0x17C00054, 5, 0x00000001, 'd', "PC-Card 0 IRQ" },
{ "CPLD_PCC0_STRESET", 0x17C00054, 6, 0x00000001, 'd', "PC-Card 0 RESET" },
{ "CPLD_PCC0_WRPROT", 0x17C00054, 7, 0x00000001, 'd', "PC-Card 0 WRPROT" },
{ "CPLD_PCCARD1_STATUS", 0x17C00058, 0, 0x000000ff, 'x', "CPLD PC-Card 1 Status" },
{ "CPLD_PCC1_VS1", 0x17C00058, 0, 0x00000001, 'd', "PC-Card 1 VS1" },
{ "CPLD_PCC1_VS2", 0x17C00058, 1, 0x00000001, 'd', "PC-Card 1 VS2" },
{ "CPLD_PCC1_BVD1", 0x17C00058, 2, 0x00000001, 'd', "PC-Card 1 BVD1" },
{ "CPLD_PCC1_BVD2", 0x17C00058, 3, 0x00000001, 'd', "PC-Card 1 BVD2" },
{ "CPLD_PCC1_INPACK", 0x17C00058, 4, 0x00000001, 'd', "PC-Card 1 INPACK" },
{ "CPLD_PCC1_IRQ", 0x17C00058, 5, 0x00000001, 'd', "PC-Card 1 IRQ" },
{ "CPLD_PCC1_STRESET", 0x17C00058, 6, 0x00000001, 'd', "PC-Card 1 RESET" },
{ "CPLD_PCC1_WRPROT", 0x17C00058, 7, 0x00000001, 'd', "PC-Card 1 WRPROT" },
{ "CPLD_MISC_STATUS", 0x17C0005C, 0, 0x000000ff, 'x', "CPLD Misc Status" },
{ "CPLD_MISC_USB_D_CON", 0x17C0005C, 0, 0x00000001, 'd', "Charge status" },
{ "CPLD_MISC_WALL_IN", 0x17C0005C, 1, 0x00000001, 'd', "Charge status" },
{ "CPLD_MISC_CHG_STS", 0x17C0005C, 2, 0x00000001, 'd', "Charge status" },
{ "CPLD_MISC_MMC_WPROT", 0x17C0005C, 7, 0x00000001, 'd', "MMC write protect" },
{ "CPLD_VER_YEAR", 0x17C00060, 0, 0x000000ff, 'x', "CPLD Year" },
{ "CPLD_VER_MONTH", 0x17C00064, 0, 0x000000ff, 'x', "CPLD Month" },
{ "CPLD_VER_DAY", 0x17C00068, 0, 0x000000ff, 'x', "CPLD Day" },
{ "CPLD_VER_REV", 0x17C0006C, 0, 0x000000ff, 'x', "CPLD Revision" },
{ "CPLD_VSTAT", 0x17C0007C, 0, 0x000000ff, 'x', "CPLD Voltage Status" },
#ifdef CONFIG_ARCH_PXA_IDP
{ "CPLD_BSTAT_V3GOOD", 0x17C0007C, 0, 0x00000001, 'x', "v3good" },
#endif
{ "CPLD_BSTAT_BWE", 0x17C0007C, 1, 0x00000001, 'x', "bwe" },
#endif
#if defined(CONFIG_ARCH_RAMSES)
{ "UARTA_RHR", 0x0C002E00, 0, 0xffffffff, 'x', "UART A RHR/THR" },
{ "UARTA_IER", 0x0C002E04, 0, 0xffffffff, 'x', "UART A IER" },
{ "UARTA_FCR", 0x0C002E08, 0, 0xffffffff, 'x', "UART A FCR/IIR" },
{ "UARTA_LCR", 0x0C002E0C, 0, 0xffffffff, 'x', "UART A LCR" },
{ "UARTA_MCR", 0x0C002E10, 0, 0xffffffff, 'x', "UART A MCR" },
{ "UARTA_LSR", 0x0C002E14, 0, 0xffffffff, 'x', "UART A LSR" },
{ "UARTA_MSR", 0x0C002E18, 0, 0xffffffff, 'x', "UART A MSR" },
{ "UARTA_SPR", 0x0C002E1C, 0, 0xffffffff, 'x', "UART A SPR" },
{ "UARTB_RHR", 0x0C002D00, 0, 0xffffffff, 'x', "UART B RHR/THR" },
{ "UARTB_IER", 0x0C002D04, 0, 0xffffffff, 'x', "UART B IER" },
{ "UARTB_FCR", 0x0C002D08, 0, 0xffffffff, 'x', "UART B FCR/IIR" },
{ "UARTB_LCR", 0x0C002D0C, 0, 0xffffffff, 'x', "UART B LCR" },
{ "UARTB_MCR", 0x0C002D10, 0, 0xffffffff, 'x', "UART B MCR" },
{ "UARTB_LSR", 0x0C002D14, 0, 0xffffffff, 'x', "UART B LSR" },
{ "UARTB_MSR", 0x0C002D18, 0, 0xffffffff, 'x', "UART B MSR" },
{ "UARTB_SPR", 0x0C002D1C, 0, 0xffffffff, 'x', "UART B SPR" },
{ "UARTD_RHR", 0x0C002B00, 0, 0xffffffff, 'x', "UART C RHR/THR" },
{ "UARTD_IER", 0x0C002B04, 0, 0xffffffff, 'x', "UART C IER" },
{ "UARTD_FCR", 0x0C002B08, 0, 0xffffffff, 'x', "UART C FCR/IIR" },
{ "UARTD_LCR", 0x0C002B0C, 0, 0xffffffff, 'x', "UART C LCR" },
{ "UARTD_MCR", 0x0C002B10, 0, 0xffffffff, 'x', "UART C MCR" },
{ "UARTD_LSR", 0x0C002B14, 0, 0xffffffff, 'x', "UART C LSR" },
{ "UARTD_MSR", 0x0C002B18, 0, 0xffffffff, 'x', "UART C MSR" },
{ "UARTD_SPR", 0x0C002B1C, 0, 0xffffffff, 'x', "UART C SPR" },
{ "UARTD_RHR", 0x0C002700, 0, 0xffffffff, 'x', "UART D RHR/THR" },
{ "UARTD_IER", 0x0C002704, 0, 0xffffffff, 'x', "UART D IER" },
{ "UARTD_FCR", 0x0C002708, 0, 0xffffffff, 'x', "UART D FCR/IIR" },
{ "UARTD_LCR", 0x0C00270C, 0, 0xffffffff, 'x', "UART D LCR" },
{ "UARTD_MCR", 0x0C002710, 0, 0xffffffff, 'x', "UART D MCR" },
{ "UARTD_LSR", 0x0C002714, 0, 0xffffffff, 'x', "UART D LSR" },
{ "UARTD_MSR", 0x0C002718, 0, 0xffffffff, 'x', "UART D MSR" },
{ "UARTD_SPR", 0x0C00271C, 0, 0xffffffff, 'x', "UART D SPR" },
#endif
};
#define MAP_SIZE 4096
#define MAP_MASK ( MAP_SIZE - 1 )
static int getmem(u32 addr)
{
void * map, * regaddr;
u32 val;
//printf("getmem(0x%08x)\n", addr);
if (fd == -1) {
fd = open("/dev/mem", O_RDWR | O_SYNC);
if (fd<0) {
perror("open(\"/dev/mem\")");
exit(1);
}
}
map = mmap(0,
MAP_SIZE,
PROT_READ | PROT_WRITE,
MAP_SHARED,
fd,
addr & ~MAP_MASK
);
if (map == (void*)-1 ) {
perror("mmap()");
exit(1);
}
regaddr = map + (addr & MAP_MASK);
val = *(u32*) regaddr;
munmap(0,MAP_SIZE);
return val;
}
static void putmem(u32 addr, u32 val)
{
void *map, *regaddr;
static int fd = -1;
//printf("putmem(0x%08x, 0x%08x)\n", addr, val);
if (fd == -1) {
fd = open("/dev/mem", O_RDWR | O_SYNC);
if (fd<0) {
perror("open(\"/dev/mem\")");
exit(1);
}
}
map = mmap(0,
MAP_SIZE,
PROT_READ | PROT_WRITE,
MAP_SHARED,
fd,
addr & ~MAP_MASK
);
if (map == (void*)-1 ) {
perror("mmap()");
exit(1);
}
regaddr = map + (addr & MAP_MASK);
*(u32*) regaddr = val;
munmap(0,MAP_SIZE);
}
static u32 lastaddr = 0;
static u32 newaddr = 1;
static u32 data = 0;
static u32 shiftdata;
static void dumpentry(int i)
{
int j;
if (regs[i].addr != lastaddr) newaddr = 1;
if (newaddr) {
newaddr = 0;
lastaddr = regs[i].addr;
data = getmem(lastaddr);
printf("\n%s\n", regs[i].desc);
printf("%-24s 0x%08x ", regs[i].name, data);
shiftdata = data;
for (j=32; j>0; j--) {
printf("%c", shiftdata & 0x80000000 ? '1' : '0');
shiftdata = shiftdata << 1;
if (j==9 || j==17 || j==25) printf(" ");
}
printf("\n");
}
if (regs[i].shift != 0 || regs[i].mask != 0xffffffff) {
shiftdata = (data >> regs[i].shift) & regs[i].mask;
printf("%-25s ", regs[i].name);
switch (regs[i].type) {
case 'x': printf("%8x", shiftdata);
break;
case '<': printf("%8u", 1 << shiftdata);
break;
default:
printf("%8u", shiftdata);
}
printf(" %s\n", regs[i].desc);
}
}
static void dumpall(void)
{
int i;
int n=sizeof(regs)/sizeof(struct reg_info);
for (i=0; i<n; i++) {
dumpentry(i);
}
}
static void dumpmatching(char *name)
{
int i;
int n=sizeof(regs)/sizeof(struct reg_info);
for (i=0; i<n; i++) {
if (strstr(regs[i].name, name))
dumpentry(i);
}
}
static void setreg(char *name, u32 val)
{
int i;
u32 mem, mem_old, mem_new;
int found=0;
int count=0;
int n=sizeof(regs)/sizeof(struct reg_info);
for (i=0; i<n; i++) {
if (strcmp(regs[i].name, name)==0) {
found = i;
//printf("Matched %s with %s, count=%d\n", regs[i].name, name, count);
count++;
}
}
if (count!=1) {
printf("No or more than one matching register found\n");
exit(1);
}
mem_old = mem = getmem(regs[found].addr);
//printf("Old contents: 0x%08x\n", mem);
mem &= ~(regs[found].mask << regs[found].shift);
//printf("Unmasked contents: 0x%08x, new value: 0x%08x\n", mem, val);
val &= regs[found].mask;
//printf("mask: 0x%08x, shift: 0x%08x\n", regs[found].mask, regs[found].shift);
//printf("masked val: 0x%08x\n", val);
mem |= val << regs[found].shift;
//printf("Embedded value: 0x%08x\n", mem);
putmem(regs[found].addr, mem);
mem_new = getmem(regs[found].addr);
if (mem_new != mem) {
printf("\t\tError: Unable to update register! 0x%08x != 0x%08x \n", mem, mem_new);
}
}
int main(int argc, char *argv[])
{
char *p;
u32 val;
if (argc == 1) {
dumpall();
return 0;
}
// Uppercase first argument
if (argc >= 2) {
p = argv[1];
while (*p) {
*p = toupper(*p);
p++;
}
}
if (argc == 2) {
dumpmatching(argv[1]);
return 0;
}
if (argc == 3) {
printf ( "Setting: %s, %s\n", argv[1], argv[2]);
if(argv[2][0] == '0' && argv[2][1] == 'x') {
sscanf(argv[2], "%x", &val);
} else {
sscanf(argv[2], "%i", &val);
}
//printf( "sscanf returns 0x%08x\n", val);
setreg(argv[1], val);
return 0;
}
printf("Usage: %s - to dump all known registers\n"
" %s <name> - to dump named register\n"
" %s <name> <value> - to set named register\n",
argv[0], argv[0], argv[0]);
return 1;
}
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment