Created
August 25, 2019 05:26
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Generate a clock from FTDI MPSSE
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from pyftdi.ftdi import Ftdi | |
# Generate a clock output from the D1 pin of an FTDI device that support MPSSE mode (e.g. 232H or 2232H, among others) | |
# The clock runs continuously, assuming nothing is connected to D4 that will pull it low | |
# Which device and which port to use for dual port devices (e.g. 2232H) | |
# See https://eblot.github.io/pyftdi/urlscheme.html | |
device_url = "ftdi://ftdi:2232h/1" | |
# Target frequency | |
# Achievable frequency depends on the particular part number, and available clock div settings | |
frequency = 10e6 | |
TCK_BIT = 0x01 | |
actual_frequency = f.open_mpsse_from_url(device_url, initial=0xFF, direction=TCK_BIT, frequency=frequency) | |
f.write_data(array('B', (Ftdi.DISABLE_CLK_3PHASE, Ftdi.DISABLE_CLK_ADAPTIVE))) | |
f.write_data(array('B', (Ftdi.CLK_WAIT_ON_LOW,))) | |
print("Achieved frequency is %f" % actual_frequency) |
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