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mcejp /
Created May 9, 2022 22:03 — forked from pvieito/
Simulate and view VGA output from a VHDL simulation
#!/usr/bin/env python3
''' - Pedro José Pereira Vieito © 2016
View VGA output from a VHDL simulation.
Ported from VGA Simulator:
by Eric Eastwood <>
More info about how to generate VGA output from VHDL simulation here: