Created
December 14, 2022 20:15
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ndctl cxl test failures pending 2022-12-14 + pending patch
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Log of Meson test suite run on 2022-12-14T20:11:11.930601 | |
Inherited environment: LANG=C.UTF-8 LS_COLORS='rs=0:di=01;34:ln=01;36:mh=00:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:mi=00:su=37;41:sg=30;43:ca=00:tw=30;42:ow=34;42:st=37;44:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arc=01;31:*.arj=01;31:*.taz=01;31:*.lha=01;31:*.lz4=01;31:*.lzh=01;31:*.lzma=01;31:*.tlz=01;31:*.txz=01;31:*.tzo=01;31:*.t7z=01;31:*.zip=01;31:*.z=01;31:*.dz=01;31:*.gz=01;31:*.lrz=01;31:*.lz=01;31:*.lzo=01;31:*.xz=01;31:*.zst=01;31:*.tzst=01;31:*.bz2=01;31:*.bz=01;31:*.tbz=01;31:*.tbz2=01;31:*.tz=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.war=01;31:*.ear=01;31:*.sar=01;31:*.rar=01;31:*.alz=01;31:*.ace=01;31:*.zoo=01;31:*.cpio=01;31:*.7z=01;31:*.rz=01;31:*.cab=01;31:*.wim=01;31:*.swm=01;31:*.dwm=01;31:*.esd=01;31:*.avif=01;35:*.jpg=01;35:*.jpeg=01;35:*.mjpg=01;35:*.mjpeg=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.png=01;35:*.svg=01;35:*.svgz=01;35:*.mng=01;35:*.pcx=01;35:*.mov=01;35:*.mpg=01;35:*.mpeg=01;35:*.m2v=01;35:*.mkv=01;35:*.webm=01;35:*.webp=01;35:*.ogm=01;35:*.mp4=01;35:*.m4v=01;35:*.mp4v=01;35:*.vob=01;35:*.qt=01;35:*.nuv=01;35:*.wmv=01;35:*.asf=01;35:*.rm=01;35:*.rmvb=01;35:*.flc=01;35:*.avi=01;35:*.fli=01;35:*.flv=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:*.yuv=01;35:*.cgm=01;35:*.emf=01;35:*.ogv=01;35:*.ogx=01;35:*.aac=00;36:*.au=00;36:*.flac=00;36:*.m4a=00;36:*.mid=00;36:*.midi=00;36:*.mka=00;36:*.mp3=00;36:*.mpc=00;36:*.ogg=00;36:*.ra=00;36:*.wav=00;36:*.oga=00;36:*.opus=00;36:*.spx=00;36:*.xspf=00;36:*~=00;90:*#=00;90:*.bak=00;90:*.old=00;90:*.orig=00;90:*.part=00;90:*.rej=00;90:*.swp=00;90:*.tmp=00;90:*.dpkg-dist=00;90:*.dpkg-old=00;90:*.ucf-dist=00;90:*.ucf-new=00;90:*.ucf-old=00;90:*.rpmnew=00;90:*.rpmorig=00;90:*.rpmsave=00;90:' TERM=screen.xterm-256color PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin MAIL=/var/mail/root LOGNAME=root USER=root HOME=/root SHELL=/bin/bash SUDO_COMMAND='/usr/bin/meson test -C build --suite cxl' SUDO_USER=vagrant SUDO_UID=1000 SUDO_GID=1000 | |
==================================== 1/5 ===================================== | |
test: ndctl:cxl / cxl-topology.sh | |
start time: 20:11:11 | |
duration: 10.85s | |
result: exit status 0 | |
command: NDCTL=/data/ndctl/build/ndctl/ndctl DATA_PATH=/data/ndctl/test DAXCTL=/data/ndctl/build/daxctl/daxctl MALLOC_PERTURB_=95 TEST_PATH=/data/ndctl/build/test /bin/bash /data/ndctl/test/cxl-topology.sh | |
----------------------------------- stderr ----------------------------------- | |
+ trap 'err $LINENO' ERR | |
+ check_prereq jq | |
+ command -v jq | |
+ modprobe -r cxl_test | |
+ modprobe cxl_test | |
+ rc=1 | |
++ ./cxl/cxl list -b cxl_test | |
+ json='[ | |
{ | |
"bus":"root0", | |
"provider":"cxl_test" | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
++ jq -r '.[] | .bus' | |
+ root=root0 | |
+ port_sort='sort_by(.port | .[4:] | tonumber)' | |
++ ./cxl/cxl list -b cxl_test -BP | |
+ json='[ | |
{ | |
"bus":"root0", | |
"provider":"cxl_test", | |
"ports:root0":[ | |
{ | |
"port":"port1", | |
"host":"cxl_host_bridge.0", | |
"depth":1, | |
"ports:port1":[ | |
{ | |
"port":"port8", | |
"host":"cxl_switch_uport.2", | |
"depth":2 | |
}, | |
{ | |
"port":"port4", | |
"host":"cxl_switch_uport.0", | |
"depth":2 | |
} | |
] | |
}, | |
{ | |
"port":"port3", | |
"host":"cxl_host_bridge.2", | |
"depth":1, | |
"ports:port3":[ | |
{ | |
"port":"port16", | |
"host":"cxl_switch_uport.4", | |
"depth":2 | |
} | |
] | |
}, | |
{ | |
"port":"port2", | |
"host":"cxl_host_bridge.1", | |
"depth":1, | |
"ports:port2":[ | |
{ | |
"port":"port6", | |
"host":"cxl_switch_uport.1", | |
"depth":2 | |
}, | |
{ | |
"port":"port10", | |
"host":"cxl_switch_uport.3", | |
"depth":2 | |
} | |
] | |
} | |
] | |
} | |
]' | |
++ jq '.[] | .["ports:root0"] | length' | |
+ count=3 | |
+ (( count == 2 )) | |
+ (( count == 3 )) | |
+ bridges=3 | |
++ jq -r '.[] | .["ports:root0"] | sort_by(.port | .[4:] | tonumber) | .[0].port' | |
+ bridge[0]=port1 | |
++ jq -r '.[] | .["ports:root0"] | sort_by(.port | .[4:] | tonumber) | .[1].port' | |
+ bridge[1]=port2 | |
+ (( bridges > 2 )) | |
++ jq -r '.[] | .["ports:root0"] | sort_by(.port | .[4:] | tonumber) | .[2].port' | |
+ bridge[2]=port3 | |
+ check_host_bridge port1 2 50 | |
++ ./cxl/cxl list -b cxl_test -T -p port1 | |
+ json='[ | |
{ | |
"port":"port1", | |
"host":"cxl_host_bridge.0", | |
"depth":1, | |
"nr_dports":2, | |
"dports":[ | |
{ | |
"dport":"cxl_root_port.0", | |
"id":0 | |
}, | |
{ | |
"dport":"cxl_root_port.2", | |
"id":2 | |
} | |
] | |
} | |
]' | |
++ jq '.[] | .dports | length' | |
+ count=2 | |
+ (( count == 2 )) | |
+ check_host_bridge port2 2 51 | |
++ ./cxl/cxl list -b cxl_test -T -p port2 | |
+ json='[ | |
{ | |
"port":"port2", | |
"host":"cxl_host_bridge.1", | |
"depth":1, | |
"nr_dports":2, | |
"dports":[ | |
{ | |
"dport":"cxl_root_port.1", | |
"id":1 | |
}, | |
{ | |
"dport":"cxl_root_port.3", | |
"id":3 | |
} | |
] | |
} | |
]' | |
++ jq '.[] | .dports | length' | |
+ count=2 | |
+ (( count == 2 )) | |
+ (( bridges > 2 )) | |
+ check_host_bridge port3 1 52 | |
++ ./cxl/cxl list -b cxl_test -T -p port3 | |
+ json='[ | |
{ | |
"port":"port3", | |
"host":"cxl_host_bridge.2", | |
"depth":1, | |
"nr_dports":1, | |
"dports":[ | |
{ | |
"dport":"cxl_root_port.4", | |
"id":4 | |
} | |
] | |
} | |
]' | |
++ jq '.[] | .dports | length' | |
+ count=1 | |
+ (( count == 1 )) | |
++ ./cxl/cxl list -b cxl_test -P -p port1 | |
+ json='[ | |
{ | |
"port":"port1", | |
"host":"cxl_host_bridge.0", | |
"depth":1, | |
"ports:port1":[ | |
{ | |
"port":"port8", | |
"host":"cxl_switch_uport.2", | |
"depth":2 | |
}, | |
{ | |
"port":"port4", | |
"host":"cxl_switch_uport.0", | |
"depth":2 | |
} | |
] | |
} | |
]' | |
++ jq '.[] | .["ports:port1"] | length' | |
+ count=2 | |
+ (( count == 2 )) | |
++ jq -r '.[] | .["ports:port1"] | sort_by(.port | .[4:] | tonumber) | .[0].host' | |
+ switch[0]=cxl_switch_uport.0 | |
++ jq -r '.[] | .["ports:port1"] | sort_by(.port | .[4:] | tonumber) | .[1].host' | |
+ switch[1]=cxl_switch_uport.2 | |
++ ./cxl/cxl list -b cxl_test -P -p port2 | |
+ json='[ | |
{ | |
"port":"port2", | |
"host":"cxl_host_bridge.1", | |
"depth":1, | |
"ports:port2":[ | |
{ | |
"port":"port6", | |
"host":"cxl_switch_uport.1", | |
"depth":2 | |
}, | |
{ | |
"port":"port10", | |
"host":"cxl_switch_uport.3", | |
"depth":2 | |
} | |
] | |
} | |
]' | |
++ jq '.[] | .["ports:port2"] | length' | |
+ count=2 | |
+ (( count == 2 )) | |
++ jq -r '.[] | .["ports:port2"] | sort_by(.port | .[4:] | tonumber) | .[0].host' | |
+ switch[2]=cxl_switch_uport.1 | |
++ jq -r '.[] | .["ports:port2"] | sort_by(.port | .[4:] | tonumber) | .[1].host' | |
+ switch[3]=cxl_switch_uport.3 | |
++ ./cxl/cxl list -b cxl_test -D -d root | |
+ json='[ | |
{ | |
"decoder":"decoder0.0", | |
"resource":70300293136384, | |
"size":1073741824, | |
"interleave_ways":1, | |
"max_available_extent":1073741824, | |
"volatile_capable":true, | |
"nr_targets":1 | |
}, | |
{ | |
"decoder":"decoder0.1", | |
"resource":70301366878208, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":4096, | |
"max_available_extent":2147483648, | |
"volatile_capable":true, | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder0.2", | |
"resource":70303514361856, | |
"size":1073741824, | |
"interleave_ways":1, | |
"max_available_extent":1073741824, | |
"pmem_capable":true, | |
"nr_targets":1 | |
}, | |
{ | |
"decoder":"decoder0.3", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":4096, | |
"max_available_extent":2147483648, | |
"pmem_capable":true, | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder0.4", | |
"resource":70306735587328, | |
"size":1073741824, | |
"interleave_ways":1, | |
"max_available_extent":1073741824, | |
"pmem_capable":true, | |
"nr_targets":1 | |
}, | |
{ | |
"decoder":"decoder0.5", | |
"resource":70307809329152, | |
"size":268435456, | |
"interleave_ways":1, | |
"max_available_extent":268435456, | |
"volatile_capable":true, | |
"nr_targets":1 | |
} | |
]' | |
+ port_id=0 | |
+ port_id_len=1 | |
+ decoder_sort='sort_by(.decoder | .[9:] | tonumber)' | |
++ jq '[ sort_by(.decoder | .[9:] | tonumber) | .[0] | | |
select(.volatile_capable == true) | | |
select(.size == 268435456) | | |
select(.nr_targets == 1) ] | length' | |
+ count=0 | |
+ '[' 0 -eq 1 ']' | |
+ decoder_base_size=1073741824 | |
+ pmem_size=1073741824 | |
++ jq '[ sort_by(.decoder | .[9:] | tonumber) | .[1] | | |
select(.volatile_capable == true) | | |
select(.size == 2147483648) | | |
select(.nr_targets == 2) ] | length' | |
+ count=1 | |
+ (( count == 1 )) | |
++ jq '[ sort_by(.decoder | .[9:] | tonumber) | .[2] | | |
select(.pmem_capable == true) | | |
select(.size == 1073741824) | | |
select(.nr_targets == 1) ] | length' | |
+ count=1 | |
+ (( count == 1 )) | |
++ jq '[ sort_by(.decoder | .[9:] | tonumber) | .[3] | | |
select(.pmem_capable == true) | | |
select(.size == 2147483648) | | |
select(.nr_targets == 2) ] | length' | |
+ count=1 | |
+ (( count == 1 )) | |
+ (( bridges == 3 )) | |
++ jq '[ sort_by(.decoder | .[9:] | tonumber) | .[4] | | |
select(.pmem_capable == true) | | |
select(.size == 1073741824) | | |
select(.nr_targets == 1) ] | length' | |
+ count=1 | |
+ (( count == 1 )) | |
++ ./cxl/cxl list -b cxl_test -M | |
+ json='[ | |
{ | |
"memdev":"mem10", | |
"ram_size":2147483648, | |
"serial":10, | |
"numa_node":0, | |
"host":"cxl_rcd.10" | |
}, | |
{ | |
"memdev":"mem2", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":2, | |
"numa_node":0, | |
"host":"cxl_mem.2" | |
}, | |
{ | |
"memdev":"mem6", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":6, | |
"numa_node":0, | |
"host":"cxl_mem.6" | |
}, | |
{ | |
"memdev":"mem0", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":0, | |
"numa_node":0, | |
"host":"cxl_mem.0" | |
}, | |
{ | |
"memdev":"mem4", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":4, | |
"numa_node":0, | |
"host":"cxl_mem.4" | |
}, | |
{ | |
"memdev":"mem8", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":8, | |
"numa_node":0, | |
"host":"cxl_mem.8" | |
}, | |
{ | |
"memdev":"mem9", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":9, | |
"numa_node":1, | |
"host":"cxl_mem.9" | |
}, | |
{ | |
"memdev":"mem1", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":1, | |
"numa_node":1, | |
"host":"cxl_mem.1" | |
}, | |
{ | |
"memdev":"mem5", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":5, | |
"numa_node":1, | |
"host":"cxl_mem.5" | |
}, | |
{ | |
"memdev":"mem3", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":3, | |
"numa_node":1, | |
"host":"cxl_mem.3" | |
}, | |
{ | |
"memdev":"mem7", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":7, | |
"numa_node":1, | |
"host":"cxl_mem.7" | |
} | |
]' | |
++ jq 'map(select(.pmem_size == 1073741824)) | length' | |
+ count=10 | |
+ (( bridges == 2 && count == 8 || bridges == 3 && count == 10 || | |
bridges == 4 && count == 11 )) | |
+ for s in ${switch[@]} | |
++ ./cxl/cxl list -M -p cxl_switch_uport.0 | |
+ json='[ | |
{ | |
"memdev":"mem0", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":0, | |
"numa_node":0, | |
"host":"cxl_mem.0" | |
}, | |
{ | |
"memdev":"mem4", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":4, | |
"numa_node":0, | |
"host":"cxl_mem.4" | |
} | |
]' | |
++ jq length | |
+ count=2 | |
+ (( count == 2 )) | |
++ jq -r '.[0] | .memdev' | |
+ mem[0]=mem0 | |
++ jq -r '.[1] | .memdev' | |
+ mem[1]=mem4 | |
+ ./cxl/cxl disable-memdev mem0 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.0 | |
+ json='[ | |
{ | |
"port":"port4", | |
"host":"cxl_switch_uport.0", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-memdev mem4 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.0 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem0 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
+ ./cxl/cxl enable-memdev mem4 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.0 | |
+ json='[ | |
{ | |
"port":"port4", | |
"host":"cxl_switch_uport.0", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-port cxl_switch_uport.0 --force | |
cxl port: cmd_disable_port: disabled 1 port | |
++ ./cxl/cxl list -p cxl_switch_uport.0 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem0 mem4 | |
cxl memdev: cmd_enable_memdev: enabled 2 mems | |
++ ./cxl/cxl list -p cxl_switch_uport.0 | |
+ json='[ | |
{ | |
"port":"port5", | |
"host":"cxl_switch_uport.0", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ for s in ${switch[@]} | |
++ ./cxl/cxl list -M -p cxl_switch_uport.2 | |
+ json='[ | |
{ | |
"memdev":"mem2", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":2, | |
"numa_node":0, | |
"host":"cxl_mem.2" | |
}, | |
{ | |
"memdev":"mem6", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":6, | |
"numa_node":0, | |
"host":"cxl_mem.6" | |
} | |
]' | |
++ jq length | |
+ count=2 | |
+ (( count == 2 )) | |
++ jq -r '.[0] | .memdev' | |
+ mem[0]=mem2 | |
++ jq -r '.[1] | .memdev' | |
+ mem[1]=mem6 | |
+ ./cxl/cxl disable-memdev mem2 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.2 | |
+ json='[ | |
{ | |
"port":"port8", | |
"host":"cxl_switch_uport.2", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-memdev mem6 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.2 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem2 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
+ ./cxl/cxl enable-memdev mem6 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.2 | |
+ json='[ | |
{ | |
"port":"port8", | |
"host":"cxl_switch_uport.2", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-port cxl_switch_uport.2 --force | |
cxl port: cmd_disable_port: disabled 1 port | |
++ ./cxl/cxl list -p cxl_switch_uport.2 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem2 mem6 | |
cxl memdev: cmd_enable_memdev: enabled 2 mems | |
++ ./cxl/cxl list -p cxl_switch_uport.2 | |
+ json='[ | |
{ | |
"port":"port9", | |
"host":"cxl_switch_uport.2", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ for s in ${switch[@]} | |
++ ./cxl/cxl list -M -p cxl_switch_uport.1 | |
+ json='[ | |
{ | |
"memdev":"mem1", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":1, | |
"numa_node":1, | |
"host":"cxl_mem.1" | |
}, | |
{ | |
"memdev":"mem5", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":5, | |
"numa_node":1, | |
"host":"cxl_mem.5" | |
} | |
]' | |
++ jq length | |
+ count=2 | |
+ (( count == 2 )) | |
++ jq -r '.[0] | .memdev' | |
+ mem[0]=mem1 | |
++ jq -r '.[1] | .memdev' | |
+ mem[1]=mem5 | |
+ ./cxl/cxl disable-memdev mem1 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.1 | |
+ json='[ | |
{ | |
"port":"port6", | |
"host":"cxl_switch_uport.1", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-memdev mem5 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.1 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem1 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
+ ./cxl/cxl enable-memdev mem5 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.1 | |
+ json='[ | |
{ | |
"port":"port6", | |
"host":"cxl_switch_uport.1", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-port cxl_switch_uport.1 --force | |
cxl port: cmd_disable_port: disabled 1 port | |
++ ./cxl/cxl list -p cxl_switch_uport.1 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem1 mem5 | |
cxl memdev: cmd_enable_memdev: enabled 2 mems | |
++ ./cxl/cxl list -p cxl_switch_uport.1 | |
+ json='[ | |
{ | |
"port":"port7", | |
"host":"cxl_switch_uport.1", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ for s in ${switch[@]} | |
++ ./cxl/cxl list -M -p cxl_switch_uport.3 | |
+ json='[ | |
{ | |
"memdev":"mem3", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":3, | |
"numa_node":1, | |
"host":"cxl_mem.3" | |
}, | |
{ | |
"memdev":"mem7", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":7, | |
"numa_node":1, | |
"host":"cxl_mem.7" | |
} | |
]' | |
++ jq length | |
+ count=2 | |
+ (( count == 2 )) | |
++ jq -r '.[0] | .memdev' | |
+ mem[0]=mem3 | |
++ jq -r '.[1] | .memdev' | |
+ mem[1]=mem7 | |
+ ./cxl/cxl disable-memdev mem3 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.3 | |
+ json='[ | |
{ | |
"port":"port10", | |
"host":"cxl_switch_uport.3", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-memdev mem7 --force | |
cxl memdev: cmd_disable_memdev: disabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.3 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem3 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
+ ./cxl/cxl enable-memdev mem7 | |
cxl memdev: cmd_enable_memdev: enabled 1 mem | |
++ ./cxl/cxl list -p cxl_switch_uport.3 | |
+ json='[ | |
{ | |
"port":"port10", | |
"host":"cxl_switch_uport.3", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ ./cxl/cxl disable-port cxl_switch_uport.3 --force | |
cxl port: cmd_disable_port: disabled 1 port | |
++ ./cxl/cxl list -p cxl_switch_uport.3 | |
Warning: no matching devices found | |
+ json='[ | |
]' | |
++ jq length | |
+ count=0 | |
+ (( count == 0 )) | |
+ ./cxl/cxl enable-memdev mem3 mem7 | |
cxl memdev: cmd_enable_memdev: enabled 2 mems | |
++ ./cxl/cxl list -p cxl_switch_uport.3 | |
+ json='[ | |
{ | |
"port":"port11", | |
"host":"cxl_switch_uport.3", | |
"depth":2 | |
} | |
]' | |
++ jq length | |
+ count=1 | |
+ (( count == 1 )) | |
+ for b in ${bridge[0]} ${bridge[1]} | |
+ ./cxl/cxl disable-port port1 -f | |
cxl port: cmd_disable_port: disabled 1 port | |
++ ./cxl/cxl list -M -i -p port1 | |
+ json='[ | |
{ | |
"memdev":"mem0", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":0, | |
"numa_node":0, | |
"host":"cxl_mem.0", | |
"state":"disabled" | |
}, | |
{ | |
"memdev":"mem2", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":2, | |
"numa_node":0, | |
"host":"cxl_mem.2", | |
"state":"disabled" | |
}, | |
{ | |
"memdev":"mem4", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":4, | |
"numa_node":0, | |
"host":"cxl_mem.4", | |
"state":"disabled" | |
}, | |
{ | |
"memdev":"mem6", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":6, | |
"numa_node":0, | |
"host":"cxl_mem.6", | |
"state":"disabled" | |
} | |
]' | |
++ jq 'map(select(.state == "disabled")) | length' | |
+ count=4 | |
+ (( count == 4 )) | |
+ ./cxl/cxl enable-port port1 -m | |
cxl port: cmd_enable_port: enabled 1 port | |
++ ./cxl/cxl list -M -p port1 | |
+ json='[ | |
{ | |
"memdev":"mem2", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":2, | |
"numa_node":0, | |
"host":"cxl_mem.2" | |
}, | |
{ | |
"memdev":"mem6", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":6, | |
"numa_node":0, | |
"host":"cxl_mem.6" | |
}, | |
{ | |
"memdev":"mem0", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":0, | |
"numa_node":0, | |
"host":"cxl_mem.0" | |
}, | |
{ | |
"memdev":"mem4", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":4, | |
"numa_node":0, | |
"host":"cxl_mem.4" | |
} | |
]' | |
++ jq length | |
+ count=4 | |
+ (( count == 4 )) | |
+ for b in ${bridge[0]} ${bridge[1]} | |
+ ./cxl/cxl disable-port port2 -f | |
cxl port: cmd_disable_port: disabled 1 port | |
++ ./cxl/cxl list -M -i -p port2 | |
+ json='[ | |
{ | |
"memdev":"mem1", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":1, | |
"numa_node":1, | |
"host":"cxl_mem.1", | |
"state":"disabled" | |
}, | |
{ | |
"memdev":"mem3", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":3, | |
"numa_node":1, | |
"host":"cxl_mem.3", | |
"state":"disabled" | |
}, | |
{ | |
"memdev":"mem5", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":5, | |
"numa_node":1, | |
"host":"cxl_mem.5", | |
"state":"disabled" | |
}, | |
{ | |
"memdev":"mem7", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":7, | |
"numa_node":1, | |
"host":"cxl_mem.7", | |
"state":"disabled" | |
} | |
]' | |
++ jq 'map(select(.state == "disabled")) | length' | |
+ count=4 | |
+ (( count == 4 )) | |
+ ./cxl/cxl enable-port port2 -m | |
cxl port: cmd_enable_port: enabled 1 port | |
++ ./cxl/cxl list -M -p port2 | |
+ json='[ | |
{ | |
"memdev":"mem1", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":1, | |
"numa_node":1, | |
"host":"cxl_mem.1" | |
}, | |
{ | |
"memdev":"mem5", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":5, | |
"numa_node":1, | |
"host":"cxl_mem.5" | |
}, | |
{ | |
"memdev":"mem3", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":3, | |
"numa_node":1, | |
"host":"cxl_mem.3" | |
}, | |
{ | |
"memdev":"mem7", | |
"pmem_size":1073741824, | |
"ram_size":1073741824, | |
"serial":7, | |
"numa_node":1, | |
"host":"cxl_mem.7" | |
} | |
]' | |
++ jq length | |
+ count=4 | |
+ (( count == 4 )) | |
+ ./cxl/cxl disable-bus root0 -f | |
cxl bus: cmd_disable_bus: disabled 1 bus | |
+ check_dmesg 182 | |
+ sleep 1 | |
++ journalctl -r -k --since -12s | |
+ log='Dec 14 20:11:12 cxl kernel: platform cxl_host_bridge.3: host supports CXL (restricted) | |
Dec 14 20:11:12 cxl kernel: platform cxl_host_bridge.2: host supports CXL | |
Dec 14 20:11:12 cxl kernel: platform cxl_host_bridge.1: host supports CXL | |
Dec 14 20:11:12 cxl kernel: platform cxl_host_bridge.0: host supports CXL | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem10: CXL port topology not found | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem9: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem8: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem7: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem6: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem5: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem4: at cxl_root_port.0 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem3: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem2: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem1: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:12 cxl kernel: cxl_mem mem0: at cxl_root_port.0 no parent for dport: platform' | |
+ grep -q 'Call Trace' | |
+ true | |
+ modprobe -r cxl_test | |
============================================================================== | |
==================================== 2/5 ===================================== | |
test: ndctl:cxl / cxl-region-sysfs.sh | |
start time: 20:11:22 | |
duration: 6.50s | |
result: exit status 0 | |
command: NDCTL=/data/ndctl/build/ndctl/ndctl DATA_PATH=/data/ndctl/test MALLOC_PERTURB_=223 DAXCTL=/data/ndctl/build/daxctl/daxctl TEST_PATH=/data/ndctl/build/test /bin/bash /data/ndctl/test/cxl-region-sysfs.sh | |
----------------------------------- stdout ----------------------------------- | |
region3 added 8 targets: decoder9.0 decoder7.0 decoder5.0 decoder11.0 decoder14.0 decoder13.0 decoder12.0 decoder15.0 | |
region3 released 8 targets: decoder9.0 decoder14.0 decoder5.0 decoder12.0 decoder7.0 decoder13.0 decoder11.0 decoder15.0 | |
----------------------------------- stderr ----------------------------------- | |
+ trap 'err $LINENO' ERR | |
+ check_prereq jq | |
+ command -v jq | |
+ modprobe -r cxl_test | |
+ modprobe cxl_test | |
+ rc=1 | |
++ ./cxl/cxl list -b cxl_test -D -d root | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 2) | | |
.decoder' | |
+ decoder=decoder0.3 | |
+ readarray -t mem | |
++ ./cxl/cxl list -M -d decoder0.3 | |
++ jq -r '.[].memdev' | |
+ readarray -t endpoint | |
++ ./cxl/cxl reserve-dpa -t pmem mem2 mem6 mem0 mem4 mem1 mem5 mem3 mem7 -s 268435456 | |
++ jq -r '.[] | .decoder.decoder' | |
cxl memdev: cmd_reserve_dpa: reservation completed on 8 mem devices | |
++ cat /sys/bus/cxl/devices/decoder0.3/create_pmem_region | |
+ region=region3 | |
+ echo region3 | |
+ uuidgen | |
+ nr_targets=8 | |
+ echo 8 | |
++ cat /sys/bus/cxl/devices/decoder0.3/interleave_granularity | |
+ r_ig=4096 | |
+ echo 4096 | |
+ echo 2147483648 | |
++ ./cxl/cxl list -T -d decoder0.3 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 0) | .target' | |
+ port_dev0=cxl_host_bridge.0 | |
++ ./cxl/cxl list -T -d decoder0.3 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 1) | .target' | |
+ port_dev1=cxl_host_bridge.1 | |
+ readarray -t mem_sort0 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.0 | |
++ jq -r '.[] | .memdev' | |
+ readarray -t mem_sort1 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.1 | |
++ jq -r '.[] | .memdev' | |
+ mem_sort=() | |
+ mem_sort[0]=mem2 | |
+ mem_sort[1]=mem1 | |
+ mem_sort[2]=mem0 | |
+ mem_sort[3]=mem3 | |
+ mem_sort[4]=mem6 | |
+ mem_sort[5]=mem5 | |
+ mem_sort[6]=mem4 | |
+ mem_sort[7]=mem7 | |
+ endpoint=() | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 0 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem2 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 1 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem1 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 2 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem0 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 3 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem3 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 4 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem6 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 5 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem5 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 6 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem4 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ for i in ${mem_sort[@]} | |
+ readarray -O 7 -t endpoint | |
++ ./cxl/cxl list -Di -d endpoint -m mem7 | |
++ jq -r '.[] | | |
select(.mode == "pmem") | .decoder' | |
+ pos=0 | |
+ for i in ${endpoint[@]} | |
+ echo decoder9.0 | |
+ pos=1 | |
+ for i in ${endpoint[@]} | |
+ echo decoder7.0 | |
+ pos=2 | |
+ for i in ${endpoint[@]} | |
+ echo decoder5.0 | |
+ pos=3 | |
+ for i in ${endpoint[@]} | |
+ echo decoder11.0 | |
+ pos=4 | |
+ for i in ${endpoint[@]} | |
+ echo decoder14.0 | |
+ pos=5 | |
+ for i in ${endpoint[@]} | |
+ echo decoder13.0 | |
+ pos=6 | |
+ for i in ${endpoint[@]} | |
+ echo decoder12.0 | |
+ pos=7 | |
+ for i in ${endpoint[@]} | |
+ echo decoder15.0 | |
+ pos=8 | |
+ echo 'region3 added 8 targets: decoder9.0' decoder7.0 decoder5.0 decoder11.0 decoder14.0 decoder13.0 decoder12.0 decoder15.0 | |
++ cat /sys/bus/cxl/devices/region3/size | |
+ region_size=0x80000000 | |
++ cat /sys/bus/cxl/devices/region3/resource | |
+ region_base=0x3ff110000000 | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder9.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder9.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder9.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder9.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder7.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder7.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder7.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder7.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder5.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder5.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder5.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder5.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder11.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder11.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder11.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder11.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder14.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder14.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder14.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder14.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder13.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder13.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder13.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder13.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder12.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder12.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder12.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder12.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ for i in ${endpoint[@]} | |
++ cat /sys/bus/cxl/devices/decoder15.0/interleave_ways | |
+ iw=8 | |
++ cat /sys/bus/cxl/devices/decoder15.0/interleave_granularity | |
+ ig=4096 | |
+ '[' 8 -ne 8 ']' | |
+ '[' 4096 -ne '4096]' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 107: [: missing `]' | |
++ cat /sys/bus/cxl/devices/decoder15.0/size | |
+ sz=0x80000000 | |
++ cat /sys/bus/cxl/devices/decoder15.0/start | |
+ res=0x3ff110000000 | |
+ '[' 0x80000000 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 111: [: 0x80000000: integer expression expected | |
+ '[' 0x3ff110000000 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 112: [: 0x3ff110000000: integer expression expected | |
+ nr_switches=4 | |
+ nr_host_bridges=2 | |
+ nr_switch_decoders=6 | |
++ ./cxl/cxl list -D -r region3 -d switch | |
+ json='[ | |
{ | |
"decoder":"decoder1.0", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":8192, | |
"region":"region3", | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder8.0", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":16384, | |
"region":"region3", | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder4.0", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":16384, | |
"region":"region3", | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder2.0", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":8192, | |
"region":"region3", | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder6.0", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":16384, | |
"region":"region3", | |
"nr_targets":2 | |
}, | |
{ | |
"decoder":"decoder10.0", | |
"resource":70304588103680, | |
"size":2147483648, | |
"interleave_ways":2, | |
"interleave_granularity":16384, | |
"region":"region3", | |
"nr_targets":2 | |
} | |
]' | |
+ readarray -t switch_decoders | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[].decoder' | |
+ '[' 6 -ne 6 ']' | |
+ for i in ${switch_decoders[@]} | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[] | select(.decoder == "decoder1.0")' | |
+ decoder='{ | |
"decoder": "decoder1.0", | |
"resource": 70304588103680, | |
"size": 2147483648, | |
"interleave_ways": 2, | |
"interleave_granularity": 8192, | |
"region": "region3", | |
"nr_targets": 2 | |
}' | |
+ id=1.0 | |
+ port_id=1 | |
++ ./cxl/cxl list -p 1 -S | |
++ jq -r '.[].depth' | |
+ depth=1 | |
++ echo '{' '"decoder":' '"decoder1.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_ways | |
+ iw=2 | |
++ echo '{' '"decoder":' '"decoder1.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_granularity | |
+ ig=8192 | |
+ '[' 2 -ne 2 ']' | |
+ '[' 8192 -ne 8192 ']' | |
++ echo '{' '"decoder":' '"decoder1.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .resource | |
+ res=70304588103680 | |
++ echo '{' '"decoder":' '"decoder1.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .size | |
+ sz=2147483648 | |
+ '[' 2147483648 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 141: [: 0x80000000: integer expression expected | |
+ '[' 70304588103680 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 143: [: 0x3ff110000000: integer expression expected | |
+ for i in ${switch_decoders[@]} | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[] | select(.decoder == "decoder8.0")' | |
+ decoder='{ | |
"decoder": "decoder8.0", | |
"resource": 70304588103680, | |
"size": 2147483648, | |
"interleave_ways": 2, | |
"interleave_granularity": 16384, | |
"region": "region3", | |
"nr_targets": 2 | |
}' | |
+ id=8.0 | |
+ port_id=8 | |
++ ./cxl/cxl list -p 8 -S | |
++ jq -r '.[].depth' | |
+ depth=2 | |
++ echo '{' '"decoder":' '"decoder8.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_ways | |
+ iw=2 | |
++ echo '{' '"decoder":' '"decoder8.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_granularity | |
+ ig=16384 | |
+ '[' 2 -ne 2 ']' | |
+ '[' 16384 -ne 16384 ']' | |
++ echo '{' '"decoder":' '"decoder8.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .resource | |
+ res=70304588103680 | |
++ echo '{' '"decoder":' '"decoder8.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .size | |
+ sz=2147483648 | |
+ '[' 2147483648 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 141: [: 0x80000000: integer expression expected | |
+ '[' 70304588103680 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 143: [: 0x3ff110000000: integer expression expected | |
+ for i in ${switch_decoders[@]} | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[] | select(.decoder == "decoder4.0")' | |
+ decoder='{ | |
"decoder": "decoder4.0", | |
"resource": 70304588103680, | |
"size": 2147483648, | |
"interleave_ways": 2, | |
"interleave_granularity": 16384, | |
"region": "region3", | |
"nr_targets": 2 | |
}' | |
+ id=4.0 | |
+ port_id=4 | |
++ ./cxl/cxl list -p 4 -S | |
++ jq -r '.[].depth' | |
+ depth=2 | |
++ echo '{' '"decoder":' '"decoder4.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_ways | |
+ iw=2 | |
++ echo '{' '"decoder":' '"decoder4.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_granularity | |
+ ig=16384 | |
+ '[' 2 -ne 2 ']' | |
+ '[' 16384 -ne 16384 ']' | |
++ echo '{' '"decoder":' '"decoder4.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .resource | |
+ res=70304588103680 | |
++ echo '{' '"decoder":' '"decoder4.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .size | |
+ sz=2147483648 | |
+ '[' 2147483648 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 141: [: 0x80000000: integer expression expected | |
+ '[' 70304588103680 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 143: [: 0x3ff110000000: integer expression expected | |
+ for i in ${switch_decoders[@]} | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[] | select(.decoder == "decoder2.0")' | |
+ decoder='{ | |
"decoder": "decoder2.0", | |
"resource": 70304588103680, | |
"size": 2147483648, | |
"interleave_ways": 2, | |
"interleave_granularity": 8192, | |
"region": "region3", | |
"nr_targets": 2 | |
}' | |
+ id=2.0 | |
+ port_id=2 | |
++ ./cxl/cxl list -p 2 -S | |
++ jq -r '.[].depth' | |
+ depth=1 | |
++ echo '{' '"decoder":' '"decoder2.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_ways | |
+ iw=2 | |
++ echo '{' '"decoder":' '"decoder2.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_granularity | |
+ ig=8192 | |
+ '[' 2 -ne 2 ']' | |
+ '[' 8192 -ne 8192 ']' | |
++ echo '{' '"decoder":' '"decoder2.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .resource | |
+ res=70304588103680 | |
++ echo '{' '"decoder":' '"decoder2.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 8192, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .size | |
+ sz=2147483648 | |
+ '[' 2147483648 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 141: [: 0x80000000: integer expression expected | |
+ '[' 70304588103680 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 143: [: 0x3ff110000000: integer expression expected | |
+ for i in ${switch_decoders[@]} | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[] | select(.decoder == "decoder6.0")' | |
+ decoder='{ | |
"decoder": "decoder6.0", | |
"resource": 70304588103680, | |
"size": 2147483648, | |
"interleave_ways": 2, | |
"interleave_granularity": 16384, | |
"region": "region3", | |
"nr_targets": 2 | |
}' | |
+ id=6.0 | |
+ port_id=6 | |
++ ./cxl/cxl list -p 6 -S | |
++ jq -r '.[].depth' | |
+ depth=2 | |
++ echo '{' '"decoder":' '"decoder6.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_ways | |
+ iw=2 | |
++ echo '{' '"decoder":' '"decoder6.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_granularity | |
+ ig=16384 | |
+ '[' 2 -ne 2 ']' | |
+ '[' 16384 -ne 16384 ']' | |
++ echo '{' '"decoder":' '"decoder6.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .resource | |
+ res=70304588103680 | |
++ echo '{' '"decoder":' '"decoder6.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .size | |
+ sz=2147483648 | |
+ '[' 2147483648 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 141: [: 0x80000000: integer expression expected | |
+ '[' 70304588103680 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 143: [: 0x3ff110000000: integer expression expected | |
+ for i in ${switch_decoders[@]} | |
++ echo '[' '{' '"decoder":"decoder1.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder8.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder4.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder2.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":8192,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder6.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '},' '{' '"decoder":"decoder10.0",' '"resource":70304588103680,' '"size":2147483648,' '"interleave_ways":2,' '"interleave_granularity":16384,' '"region":"region3",' '"nr_targets":2' '}' ']' | |
++ jq -r '.[] | select(.decoder == "decoder10.0")' | |
+ decoder='{ | |
"decoder": "decoder10.0", | |
"resource": 70304588103680, | |
"size": 2147483648, | |
"interleave_ways": 2, | |
"interleave_granularity": 16384, | |
"region": "region3", | |
"nr_targets": 2 | |
}' | |
+ id=10.0 | |
+ port_id=10 | |
++ ./cxl/cxl list -p 10 -S | |
++ jq -r '.[].depth' | |
+ depth=2 | |
++ echo '{' '"decoder":' '"decoder10.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_ways | |
+ iw=2 | |
++ echo '{' '"decoder":' '"decoder10.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .interleave_granularity | |
+ ig=16384 | |
+ '[' 2 -ne 2 ']' | |
+ '[' 16384 -ne 16384 ']' | |
++ echo '{' '"decoder":' '"decoder10.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .resource | |
+ res=70304588103680 | |
++ echo '{' '"decoder":' '"decoder10.0",' '"resource":' 70304588103680, '"size":' 2147483648, '"interleave_ways":' 2, '"interleave_granularity":' 16384, '"region":' '"region3",' '"nr_targets":' 2 '}' | |
++ jq -r .size | |
+ sz=2147483648 | |
+ '[' 2147483648 -ne 0x80000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 141: [: 0x80000000: integer expression expected | |
+ '[' 70304588103680 -ne 0x3ff110000000 ']' | |
/data/ndctl/test/cxl-region-sysfs.sh: line 143: [: 0x3ff110000000: integer expression expected | |
+ echo 1 | |
+ echo 0 | |
+ pos=0 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=1 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=2 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=3 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=4 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=5 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=6 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=7 | |
+ for i in ${endpoint[@]} | |
+ echo '' | |
+ pos=8 | |
+ readarray -t endpoint | |
++ ./cxl/cxl free-dpa -t pmem mem2 mem6 mem0 mem4 mem1 mem5 mem3 mem7 | |
++ jq -r '.[] | .decoder.decoder' | |
cxl memdev: cmd_free_dpa: reservation release completed on 8 mem devices | |
+ echo 'region3 released 8 targets: decoder9.0' decoder14.0 decoder5.0 decoder12.0 decoder7.0 decoder13.0 decoder11.0 decoder15.0 | |
+ check_dmesg 166 | |
+ sleep 1 | |
++ journalctl -r -k --since -8s | |
+ log='Dec 14 20:11:23 cxl kernel: platform cxl_host_bridge.3: host supports CXL (restricted) | |
Dec 14 20:11:23 cxl kernel: platform cxl_host_bridge.2: host supports CXL | |
Dec 14 20:11:23 cxl kernel: platform cxl_host_bridge.1: host supports CXL | |
Dec 14 20:11:23 cxl kernel: platform cxl_host_bridge.0: host supports CXL | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem10: CXL port topology not found | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem9: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem8: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem7: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem6: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem5: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem4: at cxl_root_port.0 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem3: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem2: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem1: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:22 cxl kernel: cxl_mem mem0: at cxl_root_port.0 no parent for dport: platform' | |
+ grep -q 'Call Trace' | |
+ true | |
+ modprobe -r cxl_test | |
============================================================================== | |
==================================== 3/5 ===================================== | |
test: ndctl:cxl / cxl-labels.sh | |
start time: 20:11:29 | |
duration: 4.87s | |
result: exit status 0 | |
command: NDCTL=/data/ndctl/build/ndctl/ndctl DATA_PATH=/data/ndctl/test MALLOC_PERTURB_=77 DAXCTL=/data/ndctl/build/daxctl/daxctl TEST_PATH=/data/ndctl/build/test /bin/bash /data/ndctl/test/cxl-labels.sh | |
----------------------------------- stderr ----------------------------------- | |
+ trap 'err $LINENO' ERR | |
+ check_prereq jq | |
+ command -v jq | |
+ modprobe -r cxl_test | |
+ modprobe cxl_test | |
+ rc=1 | |
+ readarray -t mems | |
++ ./cxl/cxl list -b cxl_test -Mi | |
++ jq -r '.[].memdev' | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem10 | |
+ mem=mem10 | |
++ mktemp /tmp/lsa-read-mem10.XXXX | |
+ lsa_read=/tmp/lsa-read-mem10.Og0w | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem10.Og0w mem10 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem10.Og0w | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem2 | |
+ mem=mem2 | |
++ mktemp /tmp/lsa-read-mem2.XXXX | |
+ lsa_read=/tmp/lsa-read-mem2.xgBD | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem2.xgBD mem2 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem2.xgBD | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem6 | |
+ mem=mem6 | |
++ mktemp /tmp/lsa-read-mem6.XXXX | |
+ lsa_read=/tmp/lsa-read-mem6.6Mch | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem6.6Mch mem6 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem6.6Mch | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem0 | |
+ mem=mem0 | |
++ mktemp /tmp/lsa-read-mem0.XXXX | |
+ lsa_read=/tmp/lsa-read-mem0.zMTP | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem0.zMTP mem0 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem0.zMTP | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem4 | |
+ mem=mem4 | |
++ mktemp /tmp/lsa-read-mem4.XXXX | |
+ lsa_read=/tmp/lsa-read-mem4.5E8f | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem4.5E8f mem4 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem4.5E8f | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem8 | |
+ mem=mem8 | |
++ mktemp /tmp/lsa-read-mem8.XXXX | |
+ lsa_read=/tmp/lsa-read-mem8.eiL6 | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem8.eiL6 mem8 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem8.eiL6 | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem9 | |
+ mem=mem9 | |
++ mktemp /tmp/lsa-read-mem9.XXXX | |
+ lsa_read=/tmp/lsa-read-mem9.x0UE | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem9.x0UE mem9 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem9.x0UE | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem1 | |
+ mem=mem1 | |
++ mktemp /tmp/lsa-read-mem1.XXXX | |
+ lsa_read=/tmp/lsa-read-mem1.fSFM | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem1.fSFM mem1 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem1.fSFM | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem5 | |
+ mem=mem5 | |
++ mktemp /tmp/lsa-read-mem5.XXXX | |
+ lsa_read=/tmp/lsa-read-mem5.1O4L | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem5.1O4L mem5 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem5.1O4L | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem3 | |
+ mem=mem3 | |
++ mktemp /tmp/lsa-read-mem3.XXXX | |
+ lsa_read=/tmp/lsa-read-mem3.kUPE | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem3.kUPE mem3 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem3.kUPE | |
+ for mem in ${mems[@]} | |
+ test_label_ops_cxl mem7 | |
+ mem=mem7 | |
++ mktemp /tmp/lsa-read-mem7.XXXX | |
+ lsa_read=/tmp/lsa-read-mem7.hx7V | |
+ ./cxl/cxl read-labels -o /tmp/lsa-read-mem7.hx7V mem7 | |
cxl memdev: cmd_read_labels: read 1 mem | |
+ rm /tmp/lsa-read-mem7.hx7V | |
+ readarray -t nmems | |
++ /data/ndctl/build/ndctl/ndctl list -b cxl_test -Di | |
++ jq -r '.[].dev' | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem1 | |
+ nmem=nmem1 | |
++ mktemp /tmp/lsa-nmem1.XXXX | |
+ lsa=/tmp/lsa-nmem1.KLUa | |
++ mktemp /tmp/lsa-read-nmem1.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem1.qZq7 | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem1.qZq7 nmem1 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem1.qZq7 | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem1.KLUa bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00248163 s, 52.8 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem1.KLUa nmem1 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem1.qZq7 nmem1 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem1.KLUa /tmp/lsa-read-nmem1.qZq7 | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem1 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem1.KLUa bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00150751 s, 86.9 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem1.qZq7 nmem1 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem1.KLUa /tmp/lsa-read-nmem1.qZq7 | |
+ rm /tmp/lsa-nmem1.KLUa /tmp/lsa-read-nmem1.qZq7 | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem3 | |
+ nmem=nmem3 | |
++ mktemp /tmp/lsa-nmem3.XXXX | |
+ lsa=/tmp/lsa-nmem3.Dp6j | |
++ mktemp /tmp/lsa-read-nmem3.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem3.orgw | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem3.orgw nmem3 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem3.orgw | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem3.Dp6j bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00234063 s, 56.0 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem3.Dp6j nmem3 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem3.orgw nmem3 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem3.Dp6j /tmp/lsa-read-nmem3.orgw | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem3 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem3.Dp6j bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00148677 s, 88.2 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem3.orgw nmem3 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem3.Dp6j /tmp/lsa-read-nmem3.orgw | |
+ rm /tmp/lsa-nmem3.Dp6j /tmp/lsa-read-nmem3.orgw | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem5 | |
+ nmem=nmem5 | |
++ mktemp /tmp/lsa-nmem5.XXXX | |
+ lsa=/tmp/lsa-nmem5.4Qrk | |
++ mktemp /tmp/lsa-read-nmem5.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem5.2VPv | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem5.2VPv nmem5 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem5.2VPv | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem5.4Qrk bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00244377 s, 53.6 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem5.4Qrk nmem5 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem5.2VPv nmem5 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem5.4Qrk /tmp/lsa-read-nmem5.2VPv | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem5 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem5.4Qrk bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00130551 s, 100 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem5.2VPv nmem5 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem5.4Qrk /tmp/lsa-read-nmem5.2VPv | |
+ rm /tmp/lsa-nmem5.4Qrk /tmp/lsa-read-nmem5.2VPv | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem7 | |
+ nmem=nmem7 | |
++ mktemp /tmp/lsa-nmem7.XXXX | |
+ lsa=/tmp/lsa-nmem7.7phY | |
++ mktemp /tmp/lsa-read-nmem7.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem7.AWwi | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem7.AWwi nmem7 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem7.AWwi | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem7.7phY bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00206555 s, 63.5 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem7.7phY nmem7 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem7.AWwi nmem7 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem7.7phY /tmp/lsa-read-nmem7.AWwi | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem7 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem7.7phY bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00155104 s, 84.5 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem7.AWwi nmem7 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem7.7phY /tmp/lsa-read-nmem7.AWwi | |
+ rm /tmp/lsa-nmem7.7phY /tmp/lsa-read-nmem7.AWwi | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem9 | |
+ nmem=nmem9 | |
++ mktemp /tmp/lsa-nmem9.XXXX | |
+ lsa=/tmp/lsa-nmem9.O9Kd | |
++ mktemp /tmp/lsa-read-nmem9.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem9.atsy | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem9.atsy nmem9 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem9.atsy | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem9.O9Kd bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00237036 s, 55.3 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem9.O9Kd nmem9 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem9.atsy nmem9 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem9.O9Kd /tmp/lsa-read-nmem9.atsy | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem9 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem9.O9Kd bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00149997 s, 87.4 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem9.atsy nmem9 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem9.O9Kd /tmp/lsa-read-nmem9.atsy | |
+ rm /tmp/lsa-nmem9.O9Kd /tmp/lsa-read-nmem9.atsy | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem0 | |
+ nmem=nmem0 | |
++ mktemp /tmp/lsa-nmem0.XXXX | |
+ lsa=/tmp/lsa-nmem0.QZ3F | |
++ mktemp /tmp/lsa-read-nmem0.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem0.HWJ6 | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem0.HWJ6 nmem0 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem0.HWJ6 | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem0.QZ3F bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00244166 s, 53.7 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem0.QZ3F nmem0 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem0.HWJ6 nmem0 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem0.QZ3F /tmp/lsa-read-nmem0.HWJ6 | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem0 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem0.QZ3F bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00153977 s, 85.1 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem0.HWJ6 nmem0 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem0.QZ3F /tmp/lsa-read-nmem0.HWJ6 | |
+ rm /tmp/lsa-nmem0.QZ3F /tmp/lsa-read-nmem0.HWJ6 | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem2 | |
+ nmem=nmem2 | |
++ mktemp /tmp/lsa-nmem2.XXXX | |
+ lsa=/tmp/lsa-nmem2.cRDr | |
++ mktemp /tmp/lsa-read-nmem2.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem2.5Nwo | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem2.5Nwo nmem2 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem2.5Nwo | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem2.cRDr bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00257102 s, 51.0 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem2.cRDr nmem2 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem2.5Nwo nmem2 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem2.cRDr /tmp/lsa-read-nmem2.5Nwo | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem2 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem2.cRDr bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00166399 s, 78.8 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem2.5Nwo nmem2 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem2.cRDr /tmp/lsa-read-nmem2.5Nwo | |
+ rm /tmp/lsa-nmem2.cRDr /tmp/lsa-read-nmem2.5Nwo | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem4 | |
+ nmem=nmem4 | |
++ mktemp /tmp/lsa-nmem4.XXXX | |
+ lsa=/tmp/lsa-nmem4.yIfO | |
++ mktemp /tmp/lsa-read-nmem4.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem4.0EQt | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem4.0EQt nmem4 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem4.0EQt | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem4.yIfO bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00249794 s, 52.5 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem4.yIfO nmem4 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem4.0EQt nmem4 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem4.yIfO /tmp/lsa-read-nmem4.0EQt | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem4 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem4.yIfO bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00149275 s, 87.8 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem4.0EQt nmem4 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem4.yIfO /tmp/lsa-read-nmem4.0EQt | |
+ rm /tmp/lsa-nmem4.yIfO /tmp/lsa-read-nmem4.0EQt | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem6 | |
+ nmem=nmem6 | |
++ mktemp /tmp/lsa-nmem6.XXXX | |
+ lsa=/tmp/lsa-nmem6.IKdj | |
++ mktemp /tmp/lsa-read-nmem6.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem6.Jory | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem6.Jory nmem6 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem6.Jory | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem6.IKdj bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00241581 s, 54.3 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem6.IKdj nmem6 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem6.Jory nmem6 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem6.IKdj /tmp/lsa-read-nmem6.Jory | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem6 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem6.IKdj bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00144222 s, 90.9 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem6.Jory nmem6 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem6.IKdj /tmp/lsa-read-nmem6.Jory | |
+ rm /tmp/lsa-nmem6.IKdj /tmp/lsa-read-nmem6.Jory | |
+ for nmem in ${nmems[@]} | |
+ test_label_ops nmem8 | |
+ nmem=nmem8 | |
++ mktemp /tmp/lsa-nmem8.XXXX | |
+ lsa=/tmp/lsa-nmem8.jhTs | |
++ mktemp /tmp/lsa-read-nmem8.XXXX | |
+ lsa_read=/tmp/lsa-read-nmem8.LFA9 | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem8.LFA9 nmem8 | |
read 1 nmem | |
++ stat -c %s /tmp/lsa-read-nmem8.LFA9 | |
+ lsa_size=131072 | |
+ dd if=/dev/urandom of=/tmp/lsa-nmem8.jhTs bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00240778 s, 54.4 MB/s | |
+ /data/ndctl/build/ndctl/ndctl write-labels -i /tmp/lsa-nmem8.jhTs nmem8 | |
wrote 1 nmem | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem8.LFA9 nmem8 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem8.jhTs /tmp/lsa-read-nmem8.LFA9 | |
+ /data/ndctl/build/ndctl/ndctl zero-labels nmem8 | |
zeroed 1 nmem | |
+ dd if=/dev/zero of=/tmp/lsa-nmem8.jhTs bs=131072 count=1 | |
1+0 records in | |
1+0 records out | |
131072 bytes (131 kB, 128 KiB) copied, 0.00152254 s, 86.1 MB/s | |
+ /data/ndctl/build/ndctl/ndctl read-labels -o /tmp/lsa-read-nmem8.LFA9 nmem8 | |
read 1 nmem | |
+ diff /tmp/lsa-nmem8.jhTs /tmp/lsa-read-nmem8.LFA9 | |
+ rm /tmp/lsa-nmem8.jhTs /tmp/lsa-read-nmem8.LFA9 | |
+ check_dmesg 69 | |
+ sleep 1 | |
++ journalctl -r -k --since -5s | |
+ log='Dec 14 20:11:29 cxl kernel: platform cxl_host_bridge.3: host supports CXL (restricted) | |
Dec 14 20:11:29 cxl kernel: platform cxl_host_bridge.2: host supports CXL | |
Dec 14 20:11:29 cxl kernel: platform cxl_host_bridge.1: host supports CXL | |
Dec 14 20:11:29 cxl kernel: platform cxl_host_bridge.0: host supports CXL | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem10: CXL port topology not found | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem9: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem8: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem7: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem6: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem5: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem4: at cxl_root_port.0 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem3: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem2: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem1: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:29 cxl kernel: cxl_mem mem0: at cxl_root_port.0 no parent for dport: platform' | |
+ grep -q 'Call Trace' | |
+ true | |
+ modprobe -r cxl_test | |
============================================================================== | |
==================================== 4/5 ===================================== | |
test: ndctl:cxl / cxl-create-region.sh | |
start time: 20:11:34 | |
duration: 10.86s | |
result: exit status 0 | |
command: NDCTL=/data/ndctl/build/ndctl/ndctl DATA_PATH=/data/ndctl/test MALLOC_PERTURB_=231 DAXCTL=/data/ndctl/build/daxctl/daxctl TEST_PATH=/data/ndctl/build/test /bin/bash /data/ndctl/test/cxl-create-region.sh | |
----------------------------------- stdout ----------------------------------- | |
no suitable decoder found for mem10, skipping | |
no suitable decoder found for mem1, skipping | |
no suitable decoder found for mem5, skipping | |
no suitable decoder found for mem3, skipping | |
no suitable decoder found for mem7, skipping | |
no suitable decoder found for mem10, skipping | |
created 4 subregions: | |
region2 | |
region6 | |
region7 | |
region8 | |
created 4 subregions: | |
region2 | |
region6 | |
region7 | |
region8 | |
created 4 subregions: | |
region2 | |
region6 | |
region7 | |
region8 | |
created 4 subregions: | |
region2 | |
region6 | |
region7 | |
region8 | |
created 4 subregions: | |
region4 | |
region6 | |
region7 | |
region8 | |
created 4 subregions: | |
region4 | |
region6 | |
region7 | |
region8 | |
no suitable decoder found for mem1, skipping | |
no suitable decoder found for mem5, skipping | |
no suitable decoder found for mem3, skipping | |
no suitable decoder found for mem7, skipping | |
----------------------------------- stderr ----------------------------------- | |
+ trap 'err $LINENO' ERR | |
+ check_prereq jq | |
+ command -v jq | |
+ modprobe -r cxl_test | |
+ modprobe cxl_test | |
+ rc=1 | |
+ create_single | |
++ ./cxl/cxl list -b cxl_test -D -d root | |
++ jq -r '.[4] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.4 | |
+ [[ ! -n decoder0.4 ]] | |
++ ./cxl/cxl create-region -d decoder0.4 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region4 | |
+ [[ ! -n region4 ]] | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ readarray -t mems | |
++ ./cxl/cxl list -b cxl_test -M | |
++ jq -r '.[].memdev' | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem10 | |
+ mem=mem10 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem10 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
Warning: no matching devices found | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem10, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem2 | |
+ mem=mem2 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem2 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ ./cxl/cxl disable-region --bus=cxl_test region2 | |
cxl region: cmd_disable_region: disabled 1 region | |
+ ./cxl/cxl enable-region --bus=cxl_test region2 | |
cxl region: cmd_enable_region: enabled 1 region | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem6 | |
+ mem=mem6 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem6 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem6 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ ./cxl/cxl disable-region --bus=cxl_test region2 | |
cxl region: cmd_disable_region: disabled 1 region | |
+ ./cxl/cxl enable-region --bus=cxl_test region2 | |
cxl region: cmd_enable_region: enabled 1 region | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem6 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem0 | |
+ mem=mem0 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem0 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem0 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ ./cxl/cxl disable-region --bus=cxl_test region2 | |
cxl region: cmd_disable_region: disabled 1 region | |
+ ./cxl/cxl enable-region --bus=cxl_test region2 | |
cxl region: cmd_enable_region: enabled 1 region | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem0 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem4 | |
+ mem=mem4 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem4 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem4 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ ./cxl/cxl disable-region --bus=cxl_test region2 | |
cxl region: cmd_disable_region: disabled 1 region | |
+ ./cxl/cxl enable-region --bus=cxl_test region2 | |
cxl region: cmd_enable_region: enabled 1 region | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem4 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region2 | |
+ [[ ! -n region2 ]] | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem8 | |
+ mem=mem8 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem8 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.4 | |
+ [[ ! -n decoder0.4 ]] | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem8 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region4 | |
+ [[ ! -n region4 ]] | |
+ ./cxl/cxl disable-region --bus=cxl_test region4 | |
cxl region: cmd_disable_region: disabled 1 region | |
+ ./cxl/cxl enable-region --bus=cxl_test region4 | |
cxl region: cmd_enable_region: enabled 1 region | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem8 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region4 | |
+ [[ ! -n region4 ]] | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem9 | |
+ mem=mem9 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem9 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.4 | |
+ [[ ! -n decoder0.4 ]] | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem9 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region4 | |
+ [[ ! -n region4 ]] | |
+ ./cxl/cxl disable-region --bus=cxl_test region4 | |
cxl region: cmd_disable_region: disabled 1 region | |
+ ./cxl/cxl enable-region --bus=cxl_test region4 | |
cxl region: cmd_enable_region: enabled 1 region | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem9 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region4 | |
+ [[ ! -n region4 ]] | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem1 | |
+ mem=mem1 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem1 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem1, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem5 | |
+ mem=mem5 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem5 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem5, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem3 | |
+ mem=mem3 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem3 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem3, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_x1_region mem7 | |
+ mem=mem7 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem7 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem7, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_subregions mem10 | |
+ slice=268435456 | |
+ mem=mem10 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem10 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
Warning: no matching devices found | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem10, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_subregions mem2 | |
+ slice=268435456 | |
+ mem=mem2 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem2 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl list -m mem2 | |
++ jq -r '.[].pmem_size' | |
+ size=1073741824 | |
+ [[ ! -n 1073741824 ]] | |
+ num_regions=4 | |
+ declare -a regions | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region2 | |
+ [[ ! -n region2 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region6 | |
+ [[ ! -n region6 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region7 | |
+ [[ ! -n region7 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region8 | |
+ [[ ! -n region8 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo 'created 4 subregions:' | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
+ echo region2 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region6 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region7 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region8 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ (( i = (num_regions - 1) )) | |
+ (( i >= 0 )) | |
+ destroy_regions region8 | |
+ [[ -n region8 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region8 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region7 | |
+ [[ -n region7 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region7 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region6 | |
+ [[ -n region6 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region6 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ for mem in ${mems[@]} | |
+ create_subregions mem6 | |
+ slice=268435456 | |
+ mem=mem6 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem6 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl list -m mem6 | |
++ jq -r '.[].pmem_size' | |
+ size=1073741824 | |
+ [[ ! -n 1073741824 ]] | |
+ num_regions=4 | |
+ declare -a regions | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem6 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region2 | |
+ [[ ! -n region2 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem6 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region6 | |
+ [[ ! -n region6 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem6 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region7 | |
+ [[ ! -n region7 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem6 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region8 | |
+ [[ ! -n region8 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo 'created 4 subregions:' | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
+ echo region2 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region6 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region7 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region8 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ (( i = (num_regions - 1) )) | |
+ (( i >= 0 )) | |
+ destroy_regions region8 | |
+ [[ -n region8 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region8 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region7 | |
+ [[ -n region7 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region7 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region6 | |
+ [[ -n region6 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region6 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ for mem in ${mems[@]} | |
+ create_subregions mem0 | |
+ slice=268435456 | |
+ mem=mem0 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem0 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl list -m mem0 | |
++ jq -r '.[].pmem_size' | |
+ size=1073741824 | |
+ [[ ! -n 1073741824 ]] | |
+ num_regions=4 | |
+ declare -a regions | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem0 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region2 | |
+ [[ ! -n region2 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem0 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region6 | |
+ [[ ! -n region6 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem0 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region7 | |
+ [[ ! -n region7 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem0 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region8 | |
+ [[ ! -n region8 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo 'created 4 subregions:' | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
+ echo region2 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region6 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region7 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region8 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ (( i = (num_regions - 1) )) | |
+ (( i >= 0 )) | |
+ destroy_regions region8 | |
+ [[ -n region8 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region8 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region7 | |
+ [[ -n region7 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region7 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region6 | |
+ [[ -n region6 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region6 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ for mem in ${mems[@]} | |
+ create_subregions mem4 | |
+ slice=268435456 | |
+ mem=mem4 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem4 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.2 | |
+ [[ ! -n decoder0.2 ]] | |
++ ./cxl/cxl list -m mem4 | |
++ jq -r '.[].pmem_size' | |
+ size=1073741824 | |
+ [[ ! -n 1073741824 ]] | |
+ num_regions=4 | |
+ declare -a regions | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem4 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region2 | |
+ [[ ! -n region2 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem4 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region6 | |
+ [[ ! -n region6 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem4 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region7 | |
+ [[ ! -n region7 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem4 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region8 | |
+ [[ ! -n region8 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo 'created 4 subregions:' | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
+ echo region2 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region6 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region7 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region8 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ (( i = (num_regions - 1) )) | |
+ (( i >= 0 )) | |
+ destroy_regions region8 | |
+ [[ -n region8 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region8 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region7 | |
+ [[ -n region7 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region7 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region6 | |
+ [[ -n region6 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region6 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region2 | |
+ [[ -n region2 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region2 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ for mem in ${mems[@]} | |
+ create_subregions mem8 | |
+ slice=268435456 | |
+ mem=mem8 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem8 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.4 | |
+ [[ ! -n decoder0.4 ]] | |
++ ./cxl/cxl list -m mem8 | |
++ jq -r '.[].pmem_size' | |
+ size=1073741824 | |
+ [[ ! -n 1073741824 ]] | |
+ num_regions=4 | |
+ declare -a regions | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem8 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region4 | |
+ [[ ! -n region4 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem8 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region6 | |
+ [[ ! -n region6 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem8 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region7 | |
+ [[ ! -n region7 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem8 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region8 | |
+ [[ ! -n region8 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo 'created 4 subregions:' | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
+ echo region4 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region6 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region7 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region8 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ (( i = (num_regions - 1) )) | |
+ (( i >= 0 )) | |
+ destroy_regions region8 | |
+ [[ -n region8 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region8 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region7 | |
+ [[ -n region7 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region7 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region6 | |
+ [[ -n region6 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region6 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ for mem in ${mems[@]} | |
+ create_subregions mem9 | |
+ slice=268435456 | |
+ mem=mem9 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem9 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.4 | |
+ [[ ! -n decoder0.4 ]] | |
++ ./cxl/cxl list -m mem9 | |
++ jq -r '.[].pmem_size' | |
+ size=1073741824 | |
+ [[ ! -n 1073741824 ]] | |
+ num_regions=4 | |
+ declare -a regions | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem9 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region4 | |
+ [[ ! -n region4 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem9 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region6 | |
+ [[ ! -n region6 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem9 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region7 | |
+ [[ ! -n region7 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
++ ./cxl/cxl create-region -d decoder0.4 -m mem9 -s 268435456 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ regions[$i]=region8 | |
+ [[ ! -n region8 ]] | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo 'created 4 subregions:' | |
+ (( i = 0 )) | |
+ (( i < num_regions )) | |
+ echo region4 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region6 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region7 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ echo region8 | |
+ (( i++ )) | |
+ (( i < num_regions )) | |
+ (( i = (num_regions - 1) )) | |
+ (( i >= 0 )) | |
+ destroy_regions region8 | |
+ [[ -n region8 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region8 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region7 | |
+ [[ -n region7 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region7 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region6 | |
+ [[ -n region6 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region6 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ destroy_regions region4 | |
+ [[ -n region4 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region4 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ (( i-- )) | |
+ (( i >= 0 )) | |
+ for mem in ${mems[@]} | |
+ create_subregions mem1 | |
+ slice=268435456 | |
+ mem=mem1 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem1 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem1, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_subregions mem5 | |
+ slice=268435456 | |
+ mem=mem5 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem5 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem5, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_subregions mem3 | |
+ slice=268435456 | |
+ mem=mem3 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem3 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem3, skipping' | |
+ return | |
+ for mem in ${mems[@]} | |
+ create_subregions mem7 | |
+ slice=268435456 | |
+ mem=mem7 | |
++ ./cxl/cxl list -b cxl_test -D -d root -m mem7 | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder= | |
+ [[ ! -n '' ]] | |
+ echo 'no suitable decoder found for mem7, skipping' | |
+ return | |
+ check_dmesg 152 | |
+ sleep 1 | |
++ journalctl -r -k --since -11s | |
+ log='Dec 14 20:11:43 cxl kernel: cxl_region region8: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:42 cxl kernel: cxl_region region7: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:42 cxl kernel: cxl_region region6: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:42 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:42 cxl kernel: cxl_region region8: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:41 cxl kernel: cxl_region region7: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:41 cxl kernel: cxl_region region6: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:41 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:41 cxl kernel: cxl_region region8: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:41 cxl kernel: cxl_region region7: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:40 cxl kernel: cxl_region region6: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:40 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:40 cxl kernel: cxl_region region8: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:40 cxl kernel: cxl_region region7: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:40 cxl kernel: cxl_region region6: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:40 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:39 cxl kernel: cxl_region region8: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:39 cxl kernel: cxl_region region7: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:39 cxl kernel: cxl_region region6: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:39 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:38 cxl kernel: cxl_region region8: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:38 cxl kernel: cxl_region region7: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:38 cxl kernel: cxl_region region6: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:38 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:37 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:37 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:37 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:37 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:36 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:36 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:36 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:36 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:35 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:35 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:35 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:35 cxl kernel: cxl_region region2: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:34 cxl kernel: cxl_region region4: Bypassing cpu_cache_invalidate_memergion() for testing! | |
Dec 14 20:11:34 cxl kernel: platform cxl_host_bridge.3: host supports CXL (restricted) | |
Dec 14 20:11:34 cxl kernel: platform cxl_host_bridge.2: host supports CXL | |
Dec 14 20:11:34 cxl kernel: platform cxl_host_bridge.1: host supports CXL | |
Dec 14 20:11:34 cxl kernel: platform cxl_host_bridge.0: host supports CXL | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem10: CXL port topology not found | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem9: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem8: at cxl_root_port.4 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem7: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem6: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem5: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem4: at cxl_root_port.0 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem3: at cxl_root_port.3 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem2: at cxl_root_port.2 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem1: at cxl_root_port.1 no parent for dport: platform | |
Dec 14 20:11:34 cxl kernel: cxl_mem mem0: at cxl_root_port.0 no parent for dport: platform' | |
+ grep -q 'Call Trace' | |
+ true | |
+ modprobe -r cxl_test | |
============================================================================== | |
==================================== 5/5 ===================================== | |
test: ndctl:cxl / cxl-xor-region.sh | |
start time: 20:11:45 | |
duration: 2.71s | |
result: exit status 1 | |
command: NDCTL=/data/ndctl/build/ndctl/ndctl DATA_PATH=/data/ndctl/test MALLOC_PERTURB_=102 DAXCTL=/data/ndctl/build/daxctl/daxctl TEST_PATH=/data/ndctl/build/test /bin/bash /data/ndctl/test/cxl-xor-region.sh | |
----------------------------------- stdout ----------------------------------- | |
create-region failed for decoder0.2 | |
test/cxl-xor-region.sh: failed at line 29 | |
----------------------------------- stderr ----------------------------------- | |
+ trap 'err $LINENO' ERR | |
+ check_prereq jq | |
+ command -v jq | |
+ modprobe -r cxl_test | |
+ modprobe cxl_test interleave_arithmetic=1 | |
+ udevadm settle | |
+ setup_x1 | |
++ ./cxl/cxl list -b cxl_test -D -d root | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 1) | | |
.decoder' | |
+ decoder=decoder0.0 | |
++ ./cxl/cxl list -T -d decoder0.0 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 0) | .target' | |
+ port_dev0=cxl_host_bridge.0 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.0 | |
++ jq -r '.[0].memdev' | |
+ mem0=mem2 | |
+ memdevs=mem2 | |
+ create_and_destroy_region | |
++ ./cxl/cxl create-region -d decoder0.0 -m mem2 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region0 | |
+ [[ ! -n region0 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region0 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ setup_x2 | |
++ ./cxl/cxl list -b cxl_test -D -d root | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 2) | | |
.decoder' | |
+ decoder=decoder0.1 | |
++ ./cxl/cxl list -T -d decoder0.1 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 0) | .target' | |
+ port_dev0=cxl_host_bridge.0 | |
++ ./cxl/cxl list -T -d decoder0.1 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 1) | .target' | |
+ port_dev1=cxl_host_bridge.1 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.0 | |
++ jq -r '.[0].memdev' | |
+ mem0=mem2 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.1 | |
++ jq -r '.[0].memdev' | |
+ mem1=mem1 | |
+ memdevs='mem2 mem1' | |
+ create_and_destroy_region | |
++ ./cxl/cxl create-region -d decoder0.1 -m mem2 mem1 | |
++ jq -r .region | |
cxl region: cmd_create_region: created 1 region | |
+ region=region1 | |
+ [[ ! -n region1 ]] | |
+ ./cxl/cxl destroy-region -f -b cxl_test region1 | |
cxl region: cmd_destroy_region: destroyed 1 region | |
+ setup_x4 | |
++ ./cxl/cxl list -b cxl_test -D -d root | |
++ jq -r '.[] | | |
select(.pmem_capable == true) | | |
select(.nr_targets == 4) | | |
.decoder' | |
+ decoder=decoder0.2 | |
++ ./cxl/cxl list -T -d decoder0.2 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 0) | .target' | |
+ port_dev0=cxl_host_bridge.0 | |
++ ./cxl/cxl list -T -d decoder0.2 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 1) | .target' | |
+ port_dev1=cxl_host_bridge.1 | |
++ ./cxl/cxl list -T -d decoder0.2 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 2) | .target' | |
+ port_dev2=cxl_host_bridge.0 | |
++ ./cxl/cxl list -T -d decoder0.2 | |
++ jq -r '.[] | | |
.targets | .[] | select(.position == 3) | .target' | |
+ port_dev3=cxl_host_bridge.1 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.0 | |
++ jq -r '.[0].memdev' | |
+ mem0=mem2 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.1 | |
++ jq -r '.[1].memdev' | |
+ mem1=mem5 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.0 | |
++ jq -r '.[2].memdev' | |
+ mem2=mem0 | |
++ ./cxl/cxl list -M -p cxl_host_bridge.1 | |
++ jq -r '.[3].memdev' | |
+ mem3=mem7 | |
+ memdevs='mem2 mem5 mem0 mem7' | |
+ create_and_destroy_region | |
++ ./cxl/cxl create-region -d decoder0.2 -m mem2 mem5 mem0 mem7 | |
++ jq -r .region | |
cxl region: create_region: region2: failed to set target1 to mem0 | |
cxl region: cmd_create_region: created 0 regions | |
+ region= | |
+ [[ ! -n '' ]] | |
+ echo 'create-region failed for decoder0.2' | |
+ err 29 | |
++ basename /data/ndctl/test/cxl-xor-region.sh | |
+ echo test/cxl-xor-region.sh: failed at line 29 | |
+ '[' -n '' ']' | |
+ exit 1 | |
============================================================================== | |
Summary of Failures: | |
5/5 ndctl:cxl / cxl-xor-region.sh FAIL 2.71s exit status 1 | |
Ok: 4 | |
Expected Fail: 0 | |
Fail: 1 | |
Unexpected Pass: 0 | |
Skipped: 0 | |
Timeout: 0 |
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