testbench

gistfile1.txt

`timescale 1ns / 1ps

module testbench_lms ();

	reg reset_p;
	reg lms_clk;
	
	initial begin
		lms_clk = 0;
		reset_p = 1;
		#15 reset_p = 0;
	end
	
	always begin
		#5 lms_clk = ~lms_clk;
	end

	wire   [11:0]  eout;
	wire 	 [12:0]	y_output;
	wire   [12:0] 	x_wire, d_wire;
	
	integer x_file, scan_x_file;
	integer d_file, scan_d_file;
	reg [11:0] x_data;
	reg [11:0] d_data;
	
	`define NULL 0
	
	assign x_wire = reset_p ? 0 : {0, x_data};
	assign d_wire = reset_p ? 0 : {0, d_data};
	
	initial begin
		x_file = $fopen("C:/input_d.txt", "r");
		if (x_file == `NULL) begin
			$display("x_file handle was NULL");
			$finish;
		end
		
		d_file = $fopen("C:/input_x.txt", "r");
		if (d_file == `NULL) begin
			$display("d_file handle was NULL");
			$finish;
		end
	end

	always @(posedge lms_clk) begin
		scan_x_file = $fscanf(x_file, "%f\n", x_data);
		scan_d_file = $fscanf(d_file, "%f\n", d_data);
		
		if (!$feof(x_file) || !$feof(d_file)) begin
			$display("d: %f, x: %f\n", d_data, x_data);
		end
   end

		
	LMS_Block lms_block_inst
	(
		.clock_i(lms_clk),
		.reset_i(reset_p),
		.x_i(x_wire),		
		.d_i(d_wire),					
		.e_o(eout),		
		.y_o(dac_data)
	);

endmodule