Digital Circuits and Logic Design Lab.

lab1part1.v

// Simple module that connects the SW switches to the LEDR lights
module part1 (SW, LEDR);
	input [17:0] SW;
	// toggle switches
	output [17:0] LEDR; // red LEDs
	assign LEDR = SW;
endmodule

lab1part2.v

module part2 (SW, LEDG);
	input [17:0]SW;
	output [7:0]LEDG;
	assign LEDG[7:0] = (~SW[17] & SW[7:0]) | (SW[17] & SW[15:8]);
endmodule

lab1part3.v

module part3 (SW, LEDG);
	input [17:0]SW;
	output [7:0]LEDG;
	assign LEDG[2:0] = (~SW[17] & ~SW[16] & ~SW[15] & SW[2:0]) | (~SW[17] & ~SW[16] & SW[15] & SW[5:3]) | 
	(~SW[17] & SW[16] & ~SW[15] & SW[8:6]) | (~SW[17] & SW[16] & SW[15] & SW[11:9]) | 
	(SW[17] & SW[16] & SW[15] & SW[14:12]);
endmodule

lab1part4.v

module part4 (SW, HEX3, HEX2, HEX1, HEX0);
	//Write "HELO" in 7 segment display
	input [17:0]SW;
	output [6:0]HEX3; // 7-seg displays
	output [6:0]HEX2;
	output [6:0]HEX1;
	output [6:0]HEX0;
	
	//H letter
	assign HEX3[6] = ~(~SW[2] & ~SW[1] & ~SW[0]);
	assign HEX3[5] = ~(~SW[2] & ~SW[1] & ~SW[0]);
	assign HEX3[4] = ~(~SW[2] & ~SW[1] & ~SW[0]);
	assign HEX3[3] = 1;
	assign HEX3[2] = ~(~SW[2] & ~SW[1] & ~SW[0]);
	assign HEX3[1] = ~(~SW[2] & ~SW[1] & ~SW[0]);
	assign HEX3[0] = 1;
	
	//E letter
	assign HEX2[6] = ~(~SW[2] & ~SW[1] & SW[0]);
	assign HEX2[5] = ~(~SW[2] & ~SW[1] & SW[0]);
	assign HEX2[4] = ~(~SW[2] & ~SW[1] & SW[0]);
	assign HEX2[3] = ~(~SW[2] & ~SW[1] & SW[0]);
	assign HEX2[2] = 1;
	assign HEX2[1] = 1;
	assign HEX2[0] = ~(~SW[2] & ~SW[1] & SW[0]);
	
	//L letter
	assign HEX1[6] = 1;
	assign HEX1[5] = ~(~SW[2] & SW[1] & SW[0]);
	assign HEX1[4] = ~(~SW[2] & SW[1] & SW[0]);
	assign HEX1[3] = ~(~SW[2] & SW[1] & SW[0]);
	assign HEX1[2] = 1;
	assign HEX1[1] = 1;
	assign HEX1[0] = 1;
	
	//O letter
	assign HEX0[6] = 1;
	assign HEX0[5] = ~(~SW[2] & SW[1] & ~SW[0]);
	assign HEX0[4] = ~(~SW[2] & SW[1] & ~SW[0]);
	assign HEX0[3] = ~(~SW[2] & SW[1] & ~SW[0]);
	assign HEX0[2] = ~(~SW[2] & SW[1] & ~SW[0]);
	assign HEX0[1] = ~(~SW[2] & SW[1] & ~SW[0]);
	assign HEX0[0] = ~(~SW[2] & SW[1] & ~SW[0]);
	
endmodule

lab1part5.v

// This is the complete code from Figure 8
module part5 (SW, HEX0);
	input [17:0] SW;		// toggle switches
	output [0:6] HEX0;	// 7-seg displays

	wire [2:0] M;

	// module mux_3bit_5to1 (S, U, V, W, X, Y, M);
	mux_3bit_5to1 M0 (SW[17:15], SW[14:12], SW[11:9], SW[8:6], SW[5:3], SW[2:0], M);

	// module char_7seg (C, Display);
	char_7seg H0 (M, HEX0);
endmodule

// implements a 3-bit wide 5-to-1 multiplexer
module mux_3bit_5to1 (S, U, V, W, X, Y, M);
	input [2:0] S, U, V, W, X, Y;
	output [2:0] M;
	wire [1:3] m_0, m_1, m_2;	// intermediate multiplexers

	// 5-to-1 multiplexer for bit 0
	assign m_0[1] = (!S[0] & U[0]) | (S[0] & V[0]);
	assign m_0[2] = (!S[0] & W[0]) | (S[0] & X[0]);
	assign m_0[3] = (!S[1] & m_0[1]) | (S[1] & m_0[2]);
	assign M[0] = (!S[2] & m_0[3]) | (S[2] & Y[0]); // 5-to-1 multiplexer output

	// 5-to-1 multiplexer for bit 1
	assign m_1[1] = (!S[0] & U[1]) | (S[0] & V[1]);
	assign m_1[2] = (!S[0] & W[1]) | (S[0] & X[1]);
	assign m_1[3] = (!S[1] & m_1[1]) | (S[1] & m_1[2]);
	assign M[1] = (!S[2] & m_1[3]) | (S[2] & Y[1]); // 5-to-1 multiplexer output
	
	// 5-to-1 multiplexer for bit 2
	assign m_2[1] = (!S[0] & U[2]) | (S[0] & V[2]);
	assign m_2[2] = (!S[0] & W[2]) | (S[0] & X[2]);
	assign m_2[3] = (!S[1] & m_2[1]) | (S[1] & m_2[2]);
	assign M[2] = (!S[2] & m_2[3]) | (S[2] & Y[2]); // 5-to-1 multiplexer output
endmodule	

// Converts 3-bit input code on C2-0 into 7-bit code that produces
// a character on a 7-segment display. The conversion is defined by:
// 	 C 2 1 0		Char
// 	----------------
// 	   0 0 0  	'H'
// 		0 0 1		'E'
// 		0 1 0 	'L'
// 		0 1 1		'O'
// 		1 0 0    ' ' Blank
// 		1 0 1    ' ' Blank
// 		1 1 0    ' ' Blank
// 		1 1 1		' ' Blank
//
//    Codes 100, 101, 110 are not used
//
module char_7seg (C, Display);
	input [2:0] C;				// input code
	output [0:6] Display;	// output 7-seg code

	/*
	 *       0  
	 *      ---  
	 *     |   |
	 *    5|   |1
	 *     | 6 |
	 *      ---  
	 *     |   |
	 *    4|   |2
	 *     |   |
	 *      ---  
	 *       3  
	 */
	// the following equations describe display functions in cannonical SOP form
	assign Display[0] = !((!C[2] & !C[1] & C[0]) | (!C[2] & C[1] & C[0])); 
	assign Display[1] = !((!C[2] & !C[1] & !C[0]) | (!C[2] & C[1] & C[0])); 
	assign Display[2] = !((!C[2] & !C[1] & !C[0]) | (!C[2] & C[1] & C[0])); 
	assign Display[3] = !((!C[2] & !C[1] & C[0]) | (!C[2] & C[1] & !C[0]) |
		(!C[2] & C[1] & C[0])); 
	assign Display[4] = !((!C[2] & !C[1] & !C[0]) | (!C[2] & !C[1] & C[0]) | 
		(!C[2] & C[1] & !C[0]) | (!C[2] & C[1] & C[0]));
	assign Display[5] = !((!C[2] & !C[1] & !C[0]) | (!C[2] & !C[1] & C[0]) | 
		(!C[2] & C[1] & !C[0]) | (!C[2] & C[1] & C[0])); 
	assign Display[6] = !((!C[2] & !C[1] & !C[0]) | (!C[2] & !C[1] & C[0]));
endmodule

lab1part6.v

//??????????????????????????????????

lab2part1.v

//Write numbers in 7 segment display

module part1 (SW, HEX3, HEX2, HEX1, HEX0);
	
	input [17:0]SW;
	output [6:0]HEX3; // 7-seg displays
	output [6:0]HEX2;
	output [6:0]HEX1;
	output [6:0]HEX0;
	
	//HEX3 assignments
	assign {HEX3[5],HEX3[4],HEX3[3],HEX3[2],HEX3[1],HEX3[0]} = ~(~SW[15] & ~SW[14] & ~SW[13] & ~SW[12]);
	assign HEX3[6] = 1;
	
endmodule