Cargo.toml

[package]
name = "fielddemo"
version = "0.1.0"
edition = "2021"

[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7"
defmt = "0.3"
defmt-rtt = "0.4"
panic-probe = { version = "0.3", features = ["print-defmt"] }
stm32h7xx-hal = { version = "0.14", features = ["stm32h750v", "rt"] }

[profile.dev]
codegen-units = 1
debug = 2
debug-assertions = true
incremental = false
opt-level = 'z'
overflow-checks = true

config.toml

[target.'cfg(all(target_arch = "arm", target_os = "none"))']
runner = "probe-run --chip STM32H750IBTx"
rustflags = [
    "-C", "linker=flip-link",
    "-C", "link-arg=-Tlink.x",
    "-C", "link-arg=-Tdefmt.x",
    "-C", "link-arg=--nmagic",
]

[build]
target = "thumbv7em-none-eabihf"

main.rs

#![no_main]
#![no_std]

use defmt_rtt as _;
use panic_probe as _;
use stm32h7xx_hal as _;

#[defmt::panic_handler]
fn panic() -> ! {
    cortex_m::asm::udf()
}

#[cortex_m_rt::entry]
fn main() -> ! {
    defmt::println!("hello world");

    loop {
        cortex_m::asm::bkpt();
    }
}

memory.x

MEMORY
{
   FLASH     : ORIGIN = 0x08000000, LENGTH = 128K

   /* DTCM */
   RAM       : ORIGIN = 0x20000000, LENGTH = 128K

   AXISRAM   : ORIGIN = 0x24000000, LENGTH = 512K
   SRAM1     : ORIGIN = 0x30000000, LENGTH = 128K
   SRAM2     : ORIGIN = 0x30020000, LENGTH = 128K
   SRAM3     : ORIGIN = 0x30040000, LENGTH = 32K
   SRAM4     : ORIGIN = 0x38000000, LENGTH = 64K
   BSRAM     : ORIGIN = 0x38800000, LENGTH = 4K
   ITCM      : ORIGIN = 0x00000000, LENGTH = 64K
   SDRAM     : ORIGIN = 0xc0000000, LENGTH = 64M
   QSPIFLASH : ORIGIN = 0x90000000, LENGTH = 8M
}

_stack_start = ORIGIN(RAM) + LENGTH(RAM);

SECTIONS {
  .axisram (NOLOAD) : ALIGN(8) {
    *(.axisram .axisram.*);
    . = ALIGN(8);
    } > AXISRAM
  /* The SRAM1 and SRAM2 section are commonly used as the stack and heap for the
     CM4 core in dualcore versions and should thus not be used in examples*/
  .sram1 (NOLOAD) : ALIGN(4) {
    *(.sram1 .sram1.*);
    . = ALIGN(4);
    } > SRAM1
  .sram2 (NOLOAD) : ALIGN(4) {
    *(.sram2 .sram2.*);
    . = ALIGN(4);
    } > SRAM2
  .sram3 (NOLOAD) : ALIGN(4) {
    *(.sram3 .sram3.*);
    . = ALIGN(4);
    } > SRAM3
  .sram4 (NOLOAD) : ALIGN(4) {
    *(.sram4 .sram4.*);
    . = ALIGN(4);
    } > SRAM4
} INSERT AFTER .bss;