SPI input verilog

spi.v

module counter(input clk, input rst, output reg [7:0] out);
    always @ (posedge clk)
        if (rst)
            out <= 0;
        else
            out <= out + 1;
endmodule

module D_FF(input clk, input rst, input set, output reg D);
    always @ (posedge clk)
        if (rst)
            D <= 0;
        else if (set)
            D <= 1;
endmodule

module ShiftReg(input clk, input rst, input in_data, input ce, output reg [3:0] data);
    always @ (posedge clk) begin
        if (rst)
            data <= 0;
        else if (ce) begin
            data <= data << 1;
            data [0] <= in_data;
        end
    end
endmodule

module Spi(input clk, input rst, input miso, output SCK, output nCS, output reg [3:0] Dout);
    wire [7:0] cntr;
    counter CNTR(.clk(clk), .rst(rst), .out(cntr));
    
    assign SCK = cntr[1];
    
    wire sck_rise;
    assign sck_rise = cntr [1:0] == 1;
    
    wire D_rst;
    assign D_rst = cntr == 3;
    
    wire D_set;
    assign D_set = (cntr == 15) || rst;
    
    D_FF d_ff(.clk(clk), .rst(D_rst), .set(D_set), .D(nCS));
    
    wire shiftreg_ce;
    assign shiftreg_ce = sck_rise & (~nCS);
    
    wire [3:0] shiftreg_data;
    ShiftReg shiftreg(.clk(clk), .rst(rst), .in_data(miso), .ce(shiftreg_ce), .data(shiftreg_data));
    
    always @ (posedge clk)
        if (nCS)
            Dout <= shiftreg_data;
endmodule

spitest.v

module spi_test;  
    reg clk;    
    reg rst;
    reg miso;
    wire SCK;
    wire nCS;
    wire [3:0] Dout;
    
    reg [7:0] timer;
    
    Spi spi(.clk(clk), .rst(rst), .miso(miso), .SCK(SCK), .nCS(nCS), .Dout(Dout));
    
    initial begin
        $dumpvars();
        clk = 0;
        rst = 1;
        miso = 1;
        timer = 0;
        #10
        rst = 0;
        while(timer < 32) begin
            @ (posedge clk);
            timer <= timer + 1;
        end
        $finish();
    end
    
    always #1
        clk <= !clk;
endmodule