LLVM IR code with a bunch of vector load, store and add instructions to test instruction scheduling for RISC-V V instructions

test.ll

define void @test(
          <vscale x 2 x i32> *%pc,
          <vscale x 2 x i32> *%pa,
          <vscale x 2 x i32> *%pb) nounwind
{

  %pai  = ptrtoint <vscale x 2 x i32> *%pa to i32
  %pai1 = add i32 %pai, 16
  %pai2 = add i32 %pai, 32
  %pai3 = add i32 %pai, 48
  %pa1  = inttoptr i32 %pai1 to <vscale x 2 x i32> *
  %pa2  = inttoptr i32 %pai2 to <vscale x 2 x i32> *
  %pa3  = inttoptr i32 %pai3 to <vscale x 2 x i32> *
  %va0  = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pa
  %va1  = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pa1
  %va2  = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pa2
  %va3  = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pa3

  %pbi  = ptrtoint <vscale x 2 x i32> *%pb to i32
  %pbi1 = add i32 %pbi, 16
  %pbi2 = add i32 %pbi, 32
  %pbi3 = add i32 %pbi, 48
  %pb1  = inttoptr i32 %pbi1 to <vscale x 2 x i32> *
  %pb2  = inttoptr i32 %pbi2 to <vscale x 2 x i32> *
  %pb3  = inttoptr i32 %pbi3 to <vscale x 2 x i32> *
  %vb0 = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pb
  %vb1 = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pb1
  %vb2 = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pb2
  %vb3 = load <vscale x 2 x i32>, <vscale x 2 x i32> *%pb3

  %vc0 = add <vscale x 2 x i32> %va0, %vb0
  %vc1 = add <vscale x 2 x i32> %va1, %vb1
  %vc2 = add <vscale x 2 x i32> %va2, %vb2
  %vc3 = add <vscale x 2 x i32> %va3, %vb3

  %pci  = ptrtoint <vscale x 2 x i32> *%pc to i32
  %pci1 = add i32 %pci, 16
  %pci2 = add i32 %pci, 32
  %pci3 = add i32 %pci, 48
  %pc1  = inttoptr i32 %pci1 to <vscale x 2 x i32> *
  %pc2  = inttoptr i32 %pci2 to <vscale x 2 x i32> *
  %pc3  = inttoptr i32 %pci3 to <vscale x 2 x i32> *
  store <vscale x 2 x i32> %vc0, <vscale x 2 x i32> *%pc
  store <vscale x 2 x i32> %vc1, <vscale x 2 x i32> *%pc1
  store <vscale x 2 x i32> %vc2, <vscale x 2 x i32> *%pc2
  store <vscale x 2 x i32> %vc3, <vscale x 2 x i32> *%pc3

  ret void
}