generic makefile for simple c projects

Makefile

SRCS := $(wildcard *.c)
OBJS := $(SRCS:.c=.o)
PROG_NAME := example_placeholder

CFLAGS += -Wall -Wextra -c
LDFLAGS += 

# Production
.PHONY: all
all: CLFAGS += -O2
all: $(PROG_NAME)

# Development
.PHONY: debug
debug: CFLAGS += -O0 -g -fsanitize=address
debug:
	$(CC) $(CFLAGS) $(LDFLAGS) -o $(PROG_NAME) $(SRCS)

%.o: %.c
	@$(CC) $(CFLAGS) -o $@ $?
	@echo "[CC] $@"

$(PROG_NAME): $(OBJS)
	@$(CC) $(LDFLAGS) -o $(PROG_NAME) $^
	@echo "[LD] $@"

.PHONY: clean
clean:
	rm -rf $(OBJS) $(PROG_NAME)