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16-bit compressed instructions for a super regular RISC that encodes constants in immediate blocks
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| # RISC-IB - super regular RISC that encodes constants in immediate blocks | |
| # | |
| # Copyright (C) 2024, Michael Clark <michaeljclark@mac.com> | |
| # | |
| # - 16-bit compressed instruction packets can access 8 x 64-bit registers. | |
| # - (pc,ib) is a special program counter and immediate base register pair. | |
| # - c.ibs adds 32-bit displacement +/-64KiB ib(imm9*4) to switch immediate blocks. | |
| # - c.lib uses unsigned 6-bit displacement to access 64 x 64-bit constants (64*8). | |
| # - c.jalib use unsigned 6-bit displacement to add two 32-bit constants to (pc,ib) | |
| # linking packed i32x2 disp of program counter and immediate base into reg. | |
| # - c.jrib (ret) is an indirect branch which adds packed i32x2 disp to (pc,ib) | |
| # - instruction format is detailed here: https://metaparadigm.com/~mclark/VLI.pdf | |
| # | |
| c.break op0r_imm9_16 op=00000 imm9=000000000 | |
| c.ibs op0r_imm9_16 op=00001 # immediate-block-switch ib+ib(imm9*4,i32) | |
| c.j op0r_imm9_16 op=00010 # jump pcrel9*2 | |
| c.b op0r_imm9_16 op=00011 # branch pcrel9*2 | |
| c.jalib op1r_imm6_16 op=00100 # jump-and-link-ib ib(imm6*8,i32x2) | |
| # (opc,oib) = (pc,ib) | |
| # (pc,ib) += ib(imm6*8,i32x2) | |
| # i32x2(lr) = (pc,ib)-(opc,oib); | |
| c.jrib op1r_imm6_16 op=00101 imm6=000000 # jump-reg-ib reg | |
| # (pc,ib) += i32x2(lr) | |
| c.lib.i64 op1r_imm6_16 op=00110 # load-imm-ib reg,ib(imm6*8,i64) | |
| c.li.i64 op1r_imm6_16 op=00111 # load-imm reg,simm6 | |
| c.addi.i64 op1r_imm6_16 op=01000 # add-imm reg,simm6 | |
| c.srli.i64 op2r_imm3_16 op=01001 # shift-right-logical-imm reg,reg,uimm3 | |
| c.srai.i64 op2r_imm3_16 op=01010 # shift-right-arith-imm reg,reg,uimm3 | |
| c.slli.i64 op2r_imm3_16 op=01011 # shift-left-logical-imm reg,reg,uimm3 | |
| c.load.i8 op2r_imm3_16 op=01100 # load-i8 reg,uimm3(reg) | |
| c.load.i16 op2r_imm3_16 op=01101 # load-i16 reg,uimm3(reg) | |
| c.load.i32 op2r_imm3_16 op=01110 # load-i32 reg,uimm3(reg) | |
| c.load.i64 op2r_imm3_16 op=01111 # load-i64 reg,uimm3(reg) | |
| c.store.i8 op2r_imm3_16 op=10000 # store-i8 reg,uimm3(reg) | |
| c.store.i16 op2r_imm3_16 op=10001 # store-i16 reg,uimm3(reg) | |
| c.store.i32 op2r_imm3_16 op=10010 # store-i32 reg,uimm3(reg) | |
| c.store.i64 op2r_imm3_16 op=10011 # store-i64 reg,uimm3(reg) | |
| c.load.u8 op2r_imm3_16 op=10100 # load-u8 reg,uimm3(reg) | |
| c.load.u16 op2r_imm3_16 op=10101 # load-u16 reg,uimm3(reg) | |
| c.load.u32 op2r_imm3_16 op=10110 # load-u32 reg,uimm3(reg) | |
| c.cmp.lt.i64 op2r_fun3_16 op=10111 fun3=000 # cmp.lt reg,reg | |
| c.cmp.gt.i64 op2r_fun3_16 op=10111 fun3=001 # cmp.gt reg,reg | |
| c.cmp.eq.i64 op2r_fun3_16 op=10111 fun3=010 # cmp.eq reg,reg | |
| c.cmp.ne.i64 op2r_fun3_16 op=10111 fun3=011 # cmp.ne reg,reg | |
| c.cmp.ltu.i64 op2r_fun3_16 op=10111 fun3=100 # cmp.ltu reg,reg | |
| c.cmp.gtu.i64 op2r_fun3_16 op=10111 fun3=101 # cmp.gtu reg,reg | |
| c.add.i64 op3r_16 op=11000 # add reg,reg,reg | |
| c.srl.i64 op3r_16 op=11001 # shift-right-logical reg,reg,reg | |
| c.sra.i64 op3r_16 op=11010 # shift-right-arith reg,reg,reg | |
| c.sll.i64 op3r_16 op=11011 # shift-left-logical reg,reg,reg | |
| c.sub.i64 op3r_16 op=11100 # sub reg,reg,reg | |
| c.and.i64 op3r_16 op=11101 # and reg,reg,reg | |
| c.or.i64 op3r_16 op=11110 # or reg,reg,reg | |
| c.xor.i64 op3r_16 op=11111 # xor reg,reg,reg |
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