basic_comp.v

module multiplexer(Y, A, B, C, D);
	output Y;
	input A, B, C, D;

	assign Y = (A&B)|(C&D);
endmodule

module D_ff(Q, CLK, D);
	output Q;
	input CLK, D;
	reg Q;
	
	always @ (posedge CLK)
		Q <= D;
endmodule

module multi_D_ff(out, CLK, A, B, C, D);
	output out;
	input CLK, A, B, C, D;
	wire multi_output;

	multiplexer multi(multi_output, A, B, C, D);
	D_ff d_ff(out, CLK, multi_output);
endmodule

test_basic_comp.v

module tb_multiplexer;
	wire Y;
	reg A, B, C, D;

	multiplexer M(Y, A, B, C, D);

	initial begin
		A = 0; B = 0; C = 0; D = 0;
		#50 A = 1; B = 1; C = 1; D = 1;
		#50 A = 0; B = 0; C = 0; D = 0;
		#50 A = 1; B = 0; C = 1; D = 0;
		#50 A = 0; B = 1; C = 1; D = 1;
	end

	initial #250 $finish;
endmodule

module tb_D_ff;
	wire Q;
	parameter sec = 25;
	reg D, CLK;

	always #(sec) CLK = ~CLK;
	D_ff d_ff(Q, CLK, D);

	initial begin
		CLK = 1; D = 0; #5;
		D = 0; #50;
		D = 0; #50;
		D = 1; #50;
		D = 0; #50;
		D = 1; #50;
		D = 1; #50;
		D = 0; #50;
		D = 0; #50;
		$finish;
	end
endmodule

module tb_multi_D_ff;
	wire out;
	reg CLK, A, B, C, D;
	parameter sec = 25;

	always #(sec) CLK = ~CLK;
	multi_D_ff multi_d_ff(out, CLK, A, B, C, D);

	initial begin
		CLK = 1; A = 1; B = 1; C = 1; D = 1; #5;
		A = 0; B = 0; C = 0; D = 0; #50;
		A = 1; B = 1; C = 0; D = 0; #50;
		A = 0; B = 0; C = 0; D = 1; #50;
		A = 1; B = 0; C = 0; D = 0; #50;
		A = 0; B = 0; C = 1; D = 1; #50;
		A = 1; B = 0; C = 0; D = 0; #50;
		A = 0; B = 0; C = 0; D = 1; #50;
		A = 1; B = 0; C = 0; D = 0; #50;
		A = 1; B = 1; C = 1; D = 1; #50;
		$finish;
	end
endmodule