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| === trunc | |
| Creating new node: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Creating new node: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Creating new node: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Creating new node: t7: v4i64 = concat_vectors t4, t6 | |
| Creating new node: t8: v4i8 = truncate t7 | |
| Creating new node: t9: i8 = vecreduce_add t8 | |
| Creating constant: t10: i64 = Constant<0> | |
| Creating new node: t11: i64 = undef | |
| Creating new node: t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| Creating new node: t13: ch = AArch64ISD::RET_FLAG t12 | |
| Initial selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 14 nodes: | |
| t0: ch = EntryToken | |
| t10: i64 = Constant<0> | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t7: v4i64 = concat_vectors t4, t6 | |
| t8: v4i8 = truncate t7 | |
| t9: i8 = vecreduce_add t8 | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t12 | |
| Combining: t13: ch = AArch64ISD::RET_FLAG t12 | |
| Combining: t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| Combining: t11: i64 = undef | |
| Combining: t9: i8 = vecreduce_add t8 | |
| Combining: t8: v4i8 = truncate t7 | |
| Combining: t7: v4i64 = concat_vectors t4, t6 | |
| Combining: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Combining: t5: v2i64 = Register %2 | |
| Combining: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Combining: t3: v2i64 = Register %1 | |
| Combining: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Combining: t1: i64 = Register %0 | |
| Combining: t0: ch = EntryToken | |
| Optimized lowered selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 13 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t7: v4i64 = concat_vectors t4, t6 | |
| t8: v4i8 = truncate t7 | |
| t9: i8 = vecreduce_add t8 | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t12 | |
| Legalizing node: t11: i64 = undef | |
| Analyzing result type: i64 | |
| Legal result type | |
| Legally typed node: t11: i64 = undef | |
| Legalizing node: t5: v2i64 = Register %2 | |
| Ignoring node results | |
| Legally typed node: t5: v2i64 = Register %2 | |
| Legalizing node: t3: v2i64 = Register %1 | |
| Ignoring node results | |
| Legally typed node: t3: v2i64 = Register %1 | |
| Legalizing node: t1: i64 = Register %0 | |
| Ignoring node results | |
| Legally typed node: t1: i64 = Register %0 | |
| Legalizing node: t0: ch = EntryToken | |
| Analyzing result type: ch | |
| Legal result type | |
| Legally typed node: t0: ch = EntryToken | |
| Legalizing node: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Analyzing result type: i64 | |
| Legal result type | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Legally typed node: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Legalizing node: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Analyzing result type: v2i64 | |
| Legal result type | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Legally typed node: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Legalizing node: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Analyzing result type: v2i64 | |
| Legal result type | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Legally typed node: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Legalizing node: t7: v4i64 = concat_vectors t4, t6 | |
| Analyzing result type: v4i64 | |
| Split node result: t7: v4i64 = concat_vectors t4, t6 | |
| Legalizing node: t8: v4i8 = truncate t7 | |
| Analyzing result type: v4i8 | |
| Promote integer result: t8: v4i8 = truncate t7 | |
| Creating new node: t14: v2i16 = truncate t4 | |
| Creating new node: t15: v2i16 = truncate t6 | |
| Creating new node: t16: v4i16 = concat_vectors t14, t15 | |
| Legalizing node: t9: i8 = vecreduce_add t8 | |
| Analyzing result type: i8 | |
| Promote integer result: t9: i8 = vecreduce_add t8 | |
| Creating new node: t17: i32 = vecreduce_add t8 | |
| Legalizing node: t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Analyzing operand: t9: i8 = vecreduce_add t8 | |
| Promote integer operand: t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| Creating new node: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t17, t2, undef:i64 | |
| Replacing: t12: ch = store<(store (s8) into %ir.addr)> t0, t9, t2, undef:i64 | |
| with: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t17, t2, undef:i64 | |
| Legalizing node: t17: i32 = vecreduce_add t8 | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t8: v4i8 = truncate t7 | |
| Promote integer operand: t17: i32 = vecreduce_add t8 | |
| Creating new node: t19: i32 = vecreduce_add t16 | |
| Replacing: t17: i32 = vecreduce_add t8 | |
| with: t19: i32 = vecreduce_add t16 | |
| Legalizing node: t15: v2i16 = truncate t6 | |
| Analyzing result type: v2i16 | |
| Promote integer result: t15: v2i16 = truncate t6 | |
| Creating new node: t20: v2i32 = truncate t6 | |
| Legalizing node: t20: v2i32 = truncate t6 | |
| Analyzing result type: v2i32 | |
| Legal result type | |
| Analyzing operand: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Legal operand | |
| Legally typed node: t20: v2i32 = truncate t6 | |
| Legalizing node: t14: v2i16 = truncate t4 | |
| Analyzing result type: v2i16 | |
| Promote integer result: t14: v2i16 = truncate t4 | |
| Creating new node: t21: v2i32 = truncate t4 | |
| Legalizing node: t16: v4i16 = concat_vectors t14, t15 | |
| Analyzing result type: v4i16 | |
| Legal result type | |
| Analyzing operand: t14: v2i16 = truncate t4 | |
| Promote integer operand: t16: v4i16 = concat_vectors t14, t15 | |
| Creating constant: t22: i64 = Constant<0> | |
| Creating new node: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Creating new node: t24: i16 = truncate t23 | |
| Creating constant: t25: i64 = Constant<1> | |
| Creating new node: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Creating new node: t27: i16 = truncate t26 | |
| Creating new node: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Creating new node: t29: i16 = truncate t28 | |
| Creating new node: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Creating new node: t31: i16 = truncate t30 | |
| Creating new node: t32: v4i16 = BUILD_VECTOR t24, t27, t29, t31 | |
| Replacing: t16: v4i16 = concat_vectors t14, t15 | |
| with: t32: v4i16 = BUILD_VECTOR t24, t27, t29, t31 | |
| Legalizing node: t25: i64 = Constant<1> | |
| Analyzing result type: i64 | |
| Legal result type | |
| Legally typed node: t25: i64 = Constant<1> | |
| Legalizing node: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t20: v2i32 = truncate t6 | |
| Legal operand | |
| Analyzing operand: t25: i64 = Constant<1> | |
| Legal operand | |
| Legally typed node: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Legalizing node: t31: i16 = truncate t30 | |
| Analyzing result type: i16 | |
| Promote integer result: t31: i16 = truncate t30 | |
| Legalizing node: t22: i64 = Constant<0> | |
| Analyzing result type: i64 | |
| Legal result type | |
| Legally typed node: t22: i64 = Constant<0> | |
| Legalizing node: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t20: v2i32 = truncate t6 | |
| Legal operand | |
| Analyzing operand: t22: i64 = Constant<0> | |
| Legal operand | |
| Legally typed node: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Legalizing node: t29: i16 = truncate t28 | |
| Analyzing result type: i16 | |
| Promote integer result: t29: i16 = truncate t28 | |
| Legalizing node: t21: v2i32 = truncate t4 | |
| Analyzing result type: v2i32 | |
| Legal result type | |
| Analyzing operand: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Legal operand | |
| Legally typed node: t21: v2i32 = truncate t4 | |
| Legalizing node: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t21: v2i32 = truncate t4 | |
| Legal operand | |
| Analyzing operand: t22: i64 = Constant<0> | |
| Legal operand | |
| Legally typed node: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Legalizing node: t24: i16 = truncate t23 | |
| Analyzing result type: i16 | |
| Promote integer result: t24: i16 = truncate t23 | |
| Legalizing node: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t21: v2i32 = truncate t4 | |
| Legal operand | |
| Analyzing operand: t25: i64 = Constant<1> | |
| Legal operand | |
| Legally typed node: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Legalizing node: t27: i16 = truncate t26 | |
| Analyzing result type: i16 | |
| Promote integer result: t27: i16 = truncate t26 | |
| Legalizing node: t32: v4i16 = BUILD_VECTOR t24, t27, t29, t31 | |
| Analyzing result type: v4i16 | |
| Legal result type | |
| Analyzing operand: t24: i16 = truncate t23 | |
| Promote integer operand: t32: v4i16 = BUILD_VECTOR t24, t27, t29, t31 | |
| Legalizing node: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Analyzing result type: v4i16 | |
| Legal result type | |
| Analyzing operand: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Legal operand | |
| Analyzing operand: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Legal operand | |
| Analyzing operand: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Legal operand | |
| Analyzing operand: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Legal operand | |
| Legally typed node: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Legalizing node: t19: i32 = vecreduce_add t32 | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Legal operand | |
| Legally typed node: t19: i32 = vecreduce_add t32 | |
| Legalizing node: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t19, t2, undef:i64 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Analyzing operand: t19: i32 = vecreduce_add t32 | |
| Legal operand | |
| Analyzing operand: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Legal operand | |
| Analyzing operand: t11: i64 = undef | |
| Legal operand | |
| Legally typed node: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t19, t2, undef:i64 | |
| Legalizing node: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t19, t2, undef:i64 | |
| Legal operand | |
| Legally typed node: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Legalizing node: t65535: ch = handlenode t13 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Legal operand | |
| Legally typed node: t65535: ch = handlenode t13 | |
| Type-legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 20 nodes: | |
| t0: ch = EntryToken | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| t19: i32 = vecreduce_add t32 | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t19, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| Combining: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Combining: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Combining: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Combining: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Combining: t25: i64 = Constant<1> | |
| Combining: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Combining: t22: i64 = Constant<0> | |
| Combining: t21: v2i32 = truncate t4 | |
| Combining: t20: v2i32 = truncate t6 | |
| Combining: t19: i32 = vecreduce_add t32 | |
| Combining: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t19, t2, undef:i64 | |
| Combining: t19: i32 = vecreduce_add t32 | |
| Combining: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Combining: t11: i64 = undef | |
| Combining: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Combining: t5: v2i64 = Register %2 | |
| Combining: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Combining: t3: v2i64 = Register %1 | |
| Combining: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Combining: t1: i64 = Register %0 | |
| Combining: t0: ch = EntryToken | |
| Optimized type-legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 20 nodes: | |
| t0: ch = EntryToken | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| t19: i32 = vecreduce_add t32 | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t19, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| Creating new node: t33: v4i16 = AArch64ISD::UADDV t32 | |
| Creating new node: t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| Vector-legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 21 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| t33: v4i16 = AArch64ISD::UADDV t32 | |
| t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| Legalizing node: t25: i64 = Constant<1> | |
| Analyzing result type: i64 | |
| Legal result type | |
| Legally typed node: t25: i64 = Constant<1> | |
| Legalizing node: t22: i64 = Constant<0> | |
| Analyzing result type: i64 | |
| Legal result type | |
| Legally typed node: t22: i64 = Constant<0> | |
| Legalizing node: t11: i64 = undef | |
| Analyzing result type: i64 | |
| Legal result type | |
| Legally typed node: t11: i64 = undef | |
| Legalizing node: t5: v2i64 = Register %2 | |
| Ignoring node results | |
| Legally typed node: t5: v2i64 = Register %2 | |
| Legalizing node: t3: v2i64 = Register %1 | |
| Ignoring node results | |
| Legally typed node: t3: v2i64 = Register %1 | |
| Legalizing node: t1: i64 = Register %0 | |
| Ignoring node results | |
| Legally typed node: t1: i64 = Register %0 | |
| Legalizing node: t0: ch = EntryToken | |
| Analyzing result type: ch | |
| Legal result type | |
| Legally typed node: t0: ch = EntryToken | |
| Legalizing node: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Analyzing result type: i64 | |
| Legal result type | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Legally typed node: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Legalizing node: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Analyzing result type: v2i64 | |
| Legal result type | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Legally typed node: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Legalizing node: t21: v2i32 = truncate t4 | |
| Analyzing result type: v2i32 | |
| Legal result type | |
| Analyzing operand: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Legal operand | |
| Legally typed node: t21: v2i32 = truncate t4 | |
| Legalizing node: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t21: v2i32 = truncate t4 | |
| Legal operand | |
| Analyzing operand: t22: i64 = Constant<0> | |
| Legal operand | |
| Legally typed node: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Legalizing node: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t21: v2i32 = truncate t4 | |
| Legal operand | |
| Analyzing operand: t25: i64 = Constant<1> | |
| Legal operand | |
| Legally typed node: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Legalizing node: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Analyzing result type: v2i64 | |
| Legal result type | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Legally typed node: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Legalizing node: t20: v2i32 = truncate t6 | |
| Analyzing result type: v2i32 | |
| Legal result type | |
| Analyzing operand: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Legal operand | |
| Legally typed node: t20: v2i32 = truncate t6 | |
| Legalizing node: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t20: v2i32 = truncate t6 | |
| Legal operand | |
| Analyzing operand: t22: i64 = Constant<0> | |
| Legal operand | |
| Legally typed node: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Legalizing node: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t20: v2i32 = truncate t6 | |
| Legal operand | |
| Analyzing operand: t25: i64 = Constant<1> | |
| Legal operand | |
| Legally typed node: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Legalizing node: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Analyzing result type: v4i16 | |
| Legal result type | |
| Analyzing operand: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Legal operand | |
| Analyzing operand: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Legal operand | |
| Analyzing operand: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Legal operand | |
| Analyzing operand: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Legal operand | |
| Legally typed node: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Legalizing node: t33: v4i16 = AArch64ISD::UADDV t32 | |
| Analyzing result type: v4i16 | |
| Legal result type | |
| Analyzing operand: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Legal operand | |
| Legally typed node: t33: v4i16 = AArch64ISD::UADDV t32 | |
| Legalizing node: t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| Analyzing result type: i32 | |
| Legal result type | |
| Analyzing operand: t33: v4i16 = AArch64ISD::UADDV t32 | |
| Legal operand | |
| Analyzing operand: t22: i64 = Constant<0> | |
| Legal operand | |
| Legally typed node: t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| Legalizing node: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t0: ch = EntryToken | |
| Legal operand | |
| Analyzing operand: t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| Legal operand | |
| Analyzing operand: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Legal operand | |
| Analyzing operand: t11: i64 = undef | |
| Legal operand | |
| Legally typed node: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| Legalizing node: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| Legal operand | |
| Legally typed node: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Legalizing node: t65535: ch = handlenode t13 | |
| Analyzing result type: ch | |
| Legal result type | |
| Analyzing operand: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Legal operand | |
| Legally typed node: t65535: ch = handlenode t13 | |
| Vector/type-legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 21 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| t33: v4i16 = AArch64ISD::UADDV t32 | |
| t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| Combining: t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| Combining: t33: v4i16 = AArch64ISD::UADDV t32 | |
| Combining: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Combining: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| Combining: t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| Combining: t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| Combining: t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| Combining: t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| Combining: t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| Combining: t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| Combining: t20: v2i32 = truncate t6 | |
| Combining: t21: v2i32 = truncate t4 | |
| Combining: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Combining: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Combining: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Combining: t25: i64 = Constant<1> | |
| Combining: t22: i64 = Constant<0> | |
| Combining: t11: i64 = undef | |
| Combining: t5: v2i64 = Register %2 | |
| Combining: t3: v2i64 = Register %1 | |
| Combining: t1: i64 = Register %0 | |
| Combining: t0: ch = EntryToken | |
| Optimized vector-legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 21 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t23: i32 = extract_vector_elt t21, Constant:i64<0> | |
| t26: i32 = extract_vector_elt t21, Constant:i64<1> | |
| t28: i32 = extract_vector_elt t20, Constant:i64<0> | |
| t30: i32 = extract_vector_elt t20, Constant:i64<1> | |
| t32: v4i16 = BUILD_VECTOR t23, t26, t28, t30 | |
| t33: v4i16 = AArch64ISD::UADDV t32 | |
| t34: i32 = extract_vector_elt t33, Constant:i64<0> | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t34, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| Creating new node: t35: v8i16 = undef | |
| Creating new node: t36: v8i16 = insert_subvector undef:v8i16, t33, Constant:i64<0> | |
| Creating new node: t37: i32 = extract_vector_elt t36, Constant:i64<0> | |
| Creating new node: t38: v4i16 = bitcast t21 | |
| Creating new node: t39: v4i16 = bitcast t20 | |
| Creating new node: t40: v4i16 = undef | |
| Creating new node: t41: v4i16 = vector_shuffle<0,2,4,6> t38, t39 | |
| Creating new node: t42: v4i16 = AArch64ISD::UZP1 t38, t39 | |
| Legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 20 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t38: v4i16 = bitcast t21 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t39: v4i16 = bitcast t20 | |
| t42: v4i16 = AArch64ISD::UZP1 t38, t39 | |
| t33: v4i16 = AArch64ISD::UADDV t42 | |
| t36: v8i16 = insert_subvector undef:v8i16, t33, Constant:i64<0> | |
| t37: i32 = extract_vector_elt t36, Constant:i64<0> | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t37, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| Combining: t42: v4i16 = AArch64ISD::UZP1 t38, t39 | |
| Combining: t39: v4i16 = bitcast t20 | |
| Combining: t38: v4i16 = bitcast t21 | |
| Combining: t37: i32 = extract_vector_elt t36, Constant:i64<0> | |
| Combining: t36: v8i16 = insert_subvector undef:v8i16, t33, Constant:i64<0> | |
| Combining: t35: v8i16 = undef | |
| Combining: t13: ch = AArch64ISD::RET_FLAG t18 | |
| Combining: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t37, t2, undef:i64 | |
| Combining: t37: i32 = extract_vector_elt t36, Constant:i64<0> | |
| Combining: t33: v4i16 = AArch64ISD::UADDV t42 | |
| Combining: t20: v2i32 = truncate t6 | |
| Combining: t21: v2i32 = truncate t4 | |
| Combining: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| Combining: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| Combining: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| Combining: t22: i64 = Constant<0> | |
| Combining: t11: i64 = undef | |
| Combining: t5: v2i64 = Register %2 | |
| Combining: t3: v2i64 = Register %1 | |
| Combining: t1: i64 = Register %0 | |
| Combining: t0: ch = EntryToken | |
| Optimized legalized selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 20 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = truncate t4 | |
| t38: v4i16 = bitcast t21 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = truncate t6 | |
| t39: v4i16 = bitcast t20 | |
| t42: v4i16 = AArch64ISD::UZP1 t38, t39 | |
| t33: v4i16 = AArch64ISD::UADDV t42 | |
| t36: v8i16 = insert_subvector undef:v8i16, t33, Constant:i64<0> | |
| t37: i32 = extract_vector_elt t36, Constant:i64<0> | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t37, t2, undef:i64 | |
| t13: ch = AArch64ISD::RET_FLAG t18 | |
| ===== Instruction selection begins: %bb.0 '' | |
| ISEL: Starting selection on root node: t13: ch = AArch64ISD::RET_FLAG t18 | |
| ISEL: Starting pattern match | |
| Morphed node: t13: ch = RET_ReallyLR t18 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t18: ch = store<(store (s8) into %ir.addr), trunc to i8> t0, t37, t2, undef:i64 | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 209050 | |
| Match failed at index 209077 | |
| Continuing at 209181 | |
| Match failed at index 209202 | |
| Continuing at 209215 | |
| Continuing at 209216 | |
| Match failed at index 209218 | |
| Continuing at 209367 | |
| Match failed at index 209369 | |
| Continuing at 209518 | |
| Match failed at index 209520 | |
| Continuing at 209669 | |
| Match failed at index 209671 | |
| Continuing at 209820 | |
| Match failed at index 209822 | |
| Continuing at 209971 | |
| Match failed at index 209972 | |
| Continuing at 210007 | |
| Match failed at index 210008 | |
| Continuing at 210041 | |
| Match failed at index 210042 | |
| Continuing at 210092 | |
| Match failed at index 210093 | |
| Continuing at 210143 | |
| Match failed at index 210144 | |
| Continuing at 210192 | |
| Match failed at index 210193 | |
| Continuing at 210241 | |
| Match failed at index 210242 | |
| Continuing at 210290 | |
| Match failed at index 210291 | |
| Continuing at 210339 | |
| Continuing at 210340 | |
| Match failed at index 210361 | |
| Continuing at 210375 | |
| Match failed at index 210376 | |
| Continuing at 210390 | |
| Continuing at 210391 | |
| Match failed at index 210392 | |
| Continuing at 210426 | |
| Continuing at 210427 | |
| Match failed at index 210428 | |
| Continuing at 210475 | |
| Skipped scope entry (due to false predicate) at index 210480, continuing at 210494 | |
| Creating constant: t43: i64 = TargetConstant<0> | |
| Morphed node: t18: ch = STRBBui<Mem:(store (s8) into %ir.addr)> t37, t2, TargetConstant:i64<0>, t0 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t37: i32 = extract_vector_elt t36, Constant:i64<0> | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 6 | |
| OpcodeSwitch from 11 to 32337 | |
| OpcodeSwitch from 32343 to 32348 | |
| Match failed at index 32352 | |
| Continuing at 32589 | |
| TypeSwitch[v8i16] from 32596 to 32644 | |
| Creating new machine node: t44: v4i16 = IMPLICIT_DEF | |
| Created node: t44: v4i16 = IMPLICIT_DEF | |
| Creating new machine node: t45: bf16 = ADDVv4i16v t42 | |
| Created node: t45: bf16 = ADDVv4i16v t42 | |
| Creating constant: t46: i32 = TargetConstant<7> | |
| Creating new machine node: t47: v4i16 = INSERT_SUBREG IMPLICIT_DEF:v4i16, t45, TargetConstant:i32<7> | |
| Created node: t47: v4i16 = INSERT_SUBREG IMPLICIT_DEF:v4i16, t45, TargetConstant:i32<7> | |
| Creating constant: t48: i32 = TargetConstant<12> | |
| Morphed node: t37: i32 = EXTRACT_SUBREG t47, TargetConstant:i32<12> | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t42: v4i16 = AArch64ISD::UZP1 t38, t39 | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 431919 | |
| TypeSwitch[v4i16] from 431921 to 431948 | |
| Morphed node: t42: v4i16 = UZP1v4i16 t38, t39 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t39: v4i16 = bitcast t20 | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 353821 | |
| Match failed at index 353825 | |
| Continuing at 354146 | |
| Match failed at index 354149 | |
| Continuing at 354291 | |
| Skipped scope entry (due to false predicate) at index 354296, continuing at 354303 | |
| Skipped scope entry (due to false predicate) at index 354304, continuing at 354311 | |
| TypeSwitch[v4i16] from 354315 to 354358 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t38: v4i16 = bitcast t21 | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 353821 | |
| Match failed at index 353825 | |
| Continuing at 354146 | |
| Match failed at index 354149 | |
| Continuing at 354291 | |
| Skipped scope entry (due to false predicate) at index 354296, continuing at 354303 | |
| Skipped scope entry (due to false predicate) at index 354304, continuing at 354311 | |
| TypeSwitch[v4i16] from 354315 to 354358 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t20: v2i32 = truncate t6 | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 352712 | |
| Match failed at index 352715 | |
| Continuing at 352728 | |
| Match failed at index 352731 | |
| Continuing at 353749 | |
| TypeSwitch[v2i32] from 353751 to 353776 | |
| Morphed node: t20: v2i32 = XTNv2i32 t6 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t21: v2i32 = truncate t4 | |
| ISEL: Starting pattern match | |
| Initial Opcode index to 352712 | |
| Match failed at index 352715 | |
| Continuing at 352728 | |
| Match failed at index 352731 | |
| Continuing at 353749 | |
| TypeSwitch[v2i32] from 353751 to 353776 | |
| Morphed node: t21: v2i32 = XTNv2i32 t4 | |
| ISEL: Match complete! | |
| ISEL: Starting selection on root node: t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| ISEL: Starting selection on root node: t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| ISEL: Starting selection on root node: t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| ISEL: Starting selection on root node: t5: v2i64 = Register %2 | |
| ISEL: Starting selection on root node: t3: v2i64 = Register %1 | |
| ISEL: Starting selection on root node: t1: i64 = Register %0 | |
| ISEL: Starting selection on root node: t0: ch = EntryToken | |
| ===== Instruction selection ends: | |
| Selected selection DAG: %bb.0 'trunc:' | |
| SelectionDAG has 19 nodes: | |
| t0: ch = EntryToken | |
| t4: v2i64,ch = CopyFromReg t0, Register:v2i64 %1 | |
| t21: v2i32 = XTNv2i32 t4 | |
| t6: v2i64,ch = CopyFromReg t0, Register:v2i64 %2 | |
| t20: v2i32 = XTNv2i32 t6 | |
| t42: v4i16 = UZP1v4i16 t21, t20 | |
| t45: bf16 = ADDVv4i16v t42 | |
| t47: v4i16 = INSERT_SUBREG IMPLICIT_DEF:v4i16, t45, TargetConstant:i32<7> | |
| t37: i32 = EXTRACT_SUBREG t47, TargetConstant:i32<12> | |
| t2: i64,ch = CopyFromReg t0, Register:i64 %0 | |
| t18: ch = STRBBui<Mem:(store (s8) into %ir.addr)> t37, t2, TargetConstant:i64<0>, t0 | |
| t13: ch = RET_ReallyLR t18 | |
| Total amount of phi nodes to update: 0 | |
| *** MachineFunction at end of ISel *** | |
| # Machine code for function trunc: IsSSA, TracksLiveness | |
| Function Live Ins: $x0 in %0, $q0 in %1, $q1 in %2 | |
| bb.0 (%ir-block.0): | |
| liveins: $x0, $q0, $q1 | |
| %2:fpr128 = COPY $q1 | |
| %1:fpr128 = COPY $q0 | |
| %0:gpr64common = COPY $x0 | |
| %3:fpr64 = XTNv2i32 %2:fpr128 | |
| %4:fpr64 = XTNv2i32 %1:fpr128 | |
| %5:fpr64 = UZP1v4i16 killed %4:fpr64, killed %3:fpr64 | |
| %6:fpr16 = ADDVv4i16v killed %5:fpr64 | |
| %8:fpr64 = IMPLICIT_DEF | |
| %7:fpr64 = INSERT_SUBREG %8:fpr64(tied-def 0), killed %6:fpr16, %subreg.hsub | |
| %9:gpr32 = COPY %7.ssub:fpr64 | |
| STRBBui killed %9:gpr32, %0:gpr64common, 0 :: (store (s8) into %ir.addr) | |
| RET_ReallyLR | |
| # End machine code for function trunc. |
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