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Xiaomi Redmi Note 7 (lavender) Device Tree Sources (preprocessed and included files list)
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| /dts-v1/; | |
| / { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L MTP F7A overlay"; | |
| compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; | |
| qcom,msm-id = <0x13d 0x0>; | |
| interrupt-parent = <0x1>; | |
| qcom,board-id = <0x20008 0x0>; | |
| qcom,pmic-id = <0x1001b 0x101011a 0x0 0x0 0x1001b 0x201011a 0x0 0x0 0x1001b 0x102001a 0x0 0x0>; | |
| cpus { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x0>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0x2>; | |
| qcom,lmh-dcvs = <0x3>; | |
| qcom,ea = <0x4>; | |
| efficiency = <0x400>; | |
| next-level-cache = <0x5>; | |
| linux,phandle = <0x13>; | |
| phandle = <0x13>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x2>; | |
| qcom,dump-size = <0x0>; | |
| linux,phandle = <0x5>; | |
| phandle = <0x5>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x89>; | |
| phandle = <0x89>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x91>; | |
| phandle = <0x91>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x2800>; | |
| linux,phandle = <0x99>; | |
| phandle = <0x99>; | |
| }; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x1>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0x2>; | |
| qcom,lmh-dcvs = <0x3>; | |
| qcom,ea = <0x6>; | |
| efficiency = <0x400>; | |
| next-level-cache = <0x5>; | |
| linux,phandle = <0x14>; | |
| phandle = <0x14>; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x8a>; | |
| phandle = <0x8a>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x92>; | |
| phandle = <0x92>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x2800>; | |
| linux,phandle = <0x9a>; | |
| phandle = <0x9a>; | |
| }; | |
| }; | |
| cpu@2 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x2>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0x2>; | |
| qcom,lmh-dcvs = <0x3>; | |
| qcom,ea = <0x7>; | |
| efficiency = <0x400>; | |
| next-level-cache = <0x5>; | |
| linux,phandle = <0x15>; | |
| phandle = <0x15>; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x8b>; | |
| phandle = <0x8b>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x93>; | |
| phandle = <0x93>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x2800>; | |
| linux,phandle = <0x9b>; | |
| phandle = <0x9b>; | |
| }; | |
| }; | |
| cpu@3 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x3>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0x2>; | |
| qcom,lmh-dcvs = <0x3>; | |
| qcom,ea = <0x8>; | |
| efficiency = <0x400>; | |
| next-level-cache = <0x5>; | |
| linux,phandle = <0x16>; | |
| phandle = <0x16>; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x8c>; | |
| phandle = <0x8c>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x9040>; | |
| linux,phandle = <0x94>; | |
| phandle = <0x94>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x2800>; | |
| linux,phandle = <0x9c>; | |
| phandle = <0x9c>; | |
| }; | |
| }; | |
| cpu@100 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x100>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0x9>; | |
| qcom,lmh-dcvs = <0xa>; | |
| qcom,ea = <0xb>; | |
| efficiency = <0x666>; | |
| next-level-cache = <0xc>; | |
| linux,phandle = <0x17>; | |
| phandle = <0x17>; | |
| l2-cache { | |
| compatible = "arm,arch-cache"; | |
| cache-level = <0x2>; | |
| linux,phandle = <0xc>; | |
| phandle = <0xc>; | |
| }; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x8d>; | |
| phandle = <0x8d>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x95>; | |
| phandle = <0x95>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x4800>; | |
| linux,phandle = <0x9d>; | |
| phandle = <0x9d>; | |
| }; | |
| }; | |
| cpu@101 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x101>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0xd>; | |
| qcom,lmh-dcvs = <0xa>; | |
| qcom,ea = <0xe>; | |
| efficiency = <0x666>; | |
| next-level-cache = <0xc>; | |
| linux,phandle = <0x18>; | |
| phandle = <0x18>; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x8e>; | |
| phandle = <0x8e>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x96>; | |
| phandle = <0x96>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x4800>; | |
| linux,phandle = <0x9e>; | |
| phandle = <0x9e>; | |
| }; | |
| }; | |
| cpu@102 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x102>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0xf>; | |
| qcom,lmh-dcvs = <0xa>; | |
| qcom,ea = <0x10>; | |
| efficiency = <0x666>; | |
| next-level-cache = <0xc>; | |
| linux,phandle = <0x19>; | |
| phandle = <0x19>; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x8f>; | |
| phandle = <0x8f>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x97>; | |
| phandle = <0x97>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x4800>; | |
| linux,phandle = <0x9f>; | |
| phandle = <0x9f>; | |
| }; | |
| }; | |
| cpu@103 { | |
| device_type = "cpu"; | |
| compatible = "arm,armv8"; | |
| reg = <0x0 0x103>; | |
| enable-method = "psci"; | |
| qcom,limits-info = <0x11>; | |
| qcom,lmh-dcvs = <0xa>; | |
| qcom,ea = <0x12>; | |
| efficiency = <0x666>; | |
| next-level-cache = <0xc>; | |
| linux,phandle = <0x1a>; | |
| phandle = <0x1a>; | |
| l1-icache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x90>; | |
| phandle = <0x90>; | |
| }; | |
| l1-dcache { | |
| compatible = "arm,arch-cache"; | |
| qcom,dump-size = <0x12000>; | |
| linux,phandle = <0x98>; | |
| phandle = <0x98>; | |
| }; | |
| l1-tlb { | |
| qcom,dump-size = <0x4800>; | |
| linux,phandle = <0xa0>; | |
| phandle = <0xa0>; | |
| }; | |
| }; | |
| cpu-map { | |
| cluster0 { | |
| core0 { | |
| cpu = <0x13>; | |
| }; | |
| core1 { | |
| cpu = <0x14>; | |
| }; | |
| core2 { | |
| cpu = <0x15>; | |
| }; | |
| core3 { | |
| cpu = <0x16>; | |
| }; | |
| }; | |
| cluster1 { | |
| core0 { | |
| cpu = <0x17>; | |
| }; | |
| core1 { | |
| cpu = <0x18>; | |
| }; | |
| core2 { | |
| cpu = <0x19>; | |
| }; | |
| core3 { | |
| cpu = <0x1a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| soc { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges = <0x0 0x0 0x0 0xffffffff>; | |
| compatible = "simple-bus"; | |
| linux,phandle = <0x294>; | |
| phandle = <0x294>; | |
| qcom,smp2p-modem@17911008 { | |
| compatible = "qcom,smp2p"; | |
| reg = <0x17911008 0x4>; | |
| qcom,remote-pid = <0x1>; | |
| qcom,irq-bitmask = <0x4000>; | |
| interrupts = <0x0 0x1c3 0x1>; | |
| }; | |
| qcom,smp2p-adsp@17911008 { | |
| compatible = "qcom,smp2p"; | |
| reg = <0x17911008 0x4>; | |
| qcom,remote-pid = <0x2>; | |
| qcom,irq-bitmask = <0x400>; | |
| interrupts = <0x0 0x9e 0x1>; | |
| }; | |
| qcom,smp2p-cdsp@17911008 { | |
| compatible = "qcom,smp2p"; | |
| reg = <0x17911008 0x4>; | |
| qcom,remote-pid = <0x5>; | |
| qcom,irq-bitmask = <0x40000000>; | |
| interrupts = <0x0 0x202 0x1>; | |
| }; | |
| qcom,smp2pgpio-smp2p-15-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0xf>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1b>; | |
| phandle = <0x1b>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_15_in { | |
| compatible = "qcom,smp2pgpio_test_smp2p_15_in"; | |
| gpios = <0x1b 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-15-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0xf>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1c>; | |
| phandle = <0x1c>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_15_out { | |
| compatible = "qcom,smp2pgpio_test_smp2p_15_out"; | |
| gpios = <0x1c 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0x1>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1d>; | |
| phandle = <0x1d>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_in { | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_in"; | |
| gpios = <0x1d 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0x1>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1e>; | |
| phandle = <0x1e>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_1_out { | |
| compatible = "qcom,smp2pgpio_test_smp2p_1_out"; | |
| gpios = <0x1e 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0x2>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1f>; | |
| phandle = <0x1f>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_in { | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_in"; | |
| gpios = <0x1f 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0x2>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x20>; | |
| phandle = <0x20>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_2_out { | |
| compatible = "qcom,smp2pgpio_test_smp2p_2_out"; | |
| gpios = <0x20 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-sleepstate-gpio-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "sleepstate"; | |
| qcom,remote-pid = <0x2>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x21>; | |
| phandle = <0x21>; | |
| }; | |
| qcom,smp2pgpio-sleepstate-2-out { | |
| compatible = "qcom,smp2pgpio-sleepstate-out"; | |
| gpios = <0x21 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-5-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0x5>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x22>; | |
| phandle = <0x22>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_5_in { | |
| compatible = "qcom,smp2pgpio_test_smp2p_5_in"; | |
| gpios = <0x22 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-smp2p-5-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "smp2p"; | |
| qcom,remote-pid = <0x5>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x23>; | |
| phandle = <0x23>; | |
| }; | |
| qcom,smp2pgpio_test_smp2p_5_out { | |
| compatible = "qcom,smp2pgpio_test_smp2p_5_out"; | |
| gpios = <0x23 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "slave-kernel"; | |
| qcom,remote-pid = <0x1>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x102>; | |
| phandle = <0x102>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "master-kernel"; | |
| qcom,remote-pid = <0x1>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x103>; | |
| phandle = <0x103>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "slave-kernel"; | |
| qcom,remote-pid = <0x2>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0xfc>; | |
| phandle = <0xfc>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "master-kernel"; | |
| qcom,remote-pid = <0x2>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0xfd>; | |
| phandle = <0xfd>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-5-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "slave-kernel"; | |
| qcom,remote-pid = <0x5>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0xff>; | |
| phandle = <0xff>; | |
| }; | |
| qcom,smp2pgpio-ssr-smp2p-5-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "master-kernel"; | |
| qcom,remote-pid = <0x5>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x100>; | |
| phandle = <0x100>; | |
| }; | |
| tmc@6048000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6048000 0x1000 0x6064000 0x15000>; | |
| reg-names = "tmc-base", "bam-base"; | |
| arm,buffer-size = <0x400000>; | |
| arm,sg-enable; | |
| arm,default-sink; | |
| coresight-ctis = <0x24 0x25>; | |
| coresight-name = "coresight-tmc-etr"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x295>; | |
| phandle = <0x295>; | |
| port { | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x27>; | |
| linux,phandle = <0x28>; | |
| phandle = <0x28>; | |
| }; | |
| }; | |
| }; | |
| replicator@6046000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b909>; | |
| reg = <0x6046000 0x1000>; | |
| reg-names = "replicator-base"; | |
| coresight-name = "coresight-replicator"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x296>; | |
| phandle = <0x296>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x28>; | |
| linux,phandle = <0x27>; | |
| phandle = <0x27>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x29>; | |
| linux,phandle = <0x2a>; | |
| phandle = <0x2a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tmc@6047000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b961>; | |
| reg = <0x6047000 0x1000>; | |
| reg-names = "tmc-base"; | |
| coresight-name = "coresight-tmc-etf"; | |
| coresight-ctis = <0x24 0x25>; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x297>; | |
| phandle = <0x297>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x2a>; | |
| linux,phandle = <0x29>; | |
| phandle = <0x29>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2b>; | |
| linux,phandle = <0x2c>; | |
| phandle = <0x2c>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6045000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6045000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-merg"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x298>; | |
| phandle = <0x298>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x2c>; | |
| linux,phandle = <0x2b>; | |
| phandle = <0x2b>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2d>; | |
| linux,phandle = <0x2f>; | |
| phandle = <0x2f>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x1>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x2e>; | |
| linux,phandle = <0x33>; | |
| phandle = <0x33>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6041000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6041000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-in0"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x299>; | |
| phandle = <0x299>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x2f>; | |
| linux,phandle = <0x2d>; | |
| phandle = <0x2d>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x6>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x30>; | |
| linux,phandle = <0x51>; | |
| phandle = <0x51>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x7>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x31>; | |
| linux,phandle = <0x45>; | |
| phandle = <0x45>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x32>; | |
| linux,phandle = <0x77>; | |
| phandle = <0x77>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@6042000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6042000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-in1"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x29a>; | |
| phandle = <0x29a>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x33>; | |
| linux,phandle = <0x2e>; | |
| phandle = <0x2e>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x2>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x34>; | |
| linux,phandle = <0x62>; | |
| phandle = <0x62>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x5>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x35>; | |
| linux,phandle = <0x75>; | |
| phandle = <0x75>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x6>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x36>; | |
| linux,phandle = <0x38>; | |
| phandle = <0x38>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x4>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x37>; | |
| linux,phandle = <0x78>; | |
| phandle = <0x78>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@7b70000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x7b70000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-apss-merg"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x29b>; | |
| phandle = <0x29b>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x38>; | |
| linux,phandle = <0x36>; | |
| phandle = <0x36>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x39>; | |
| linux,phandle = <0x3c>; | |
| phandle = <0x3c>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x1>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x3a>; | |
| linux,phandle = <0x6b>; | |
| phandle = <0x6b>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x3>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x3b>; | |
| linux,phandle = <0x64>; | |
| phandle = <0x64>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| funnel@7b60000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x7b60000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-apss"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x29c>; | |
| phandle = <0x29c>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x3c>; | |
| linux,phandle = <0x39>; | |
| phandle = <0x39>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x3d>; | |
| linux,phandle = <0x46>; | |
| phandle = <0x46>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x1>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x3e>; | |
| linux,phandle = <0x47>; | |
| phandle = <0x47>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x2>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x3f>; | |
| linux,phandle = <0x48>; | |
| phandle = <0x48>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x3>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x40>; | |
| linux,phandle = <0x49>; | |
| phandle = <0x49>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x4>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x41>; | |
| linux,phandle = <0x4a>; | |
| phandle = <0x4a>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x5>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x42>; | |
| linux,phandle = <0x4b>; | |
| phandle = <0x4b>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0x6>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x43>; | |
| linux,phandle = <0x4c>; | |
| phandle = <0x4c>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0x7>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x44>; | |
| linux,phandle = <0x4d>; | |
| phandle = <0x4d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| stm@6002000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b962>; | |
| reg = <0x6002000 0x1000 0x16280000 0x180000>; | |
| reg-names = "stm-base", "stm-data-base"; | |
| coresight-name = "coresight-stm"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x29d>; | |
| phandle = <0x29d>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x45>; | |
| linux,phandle = <0x31>; | |
| phandle = <0x31>; | |
| }; | |
| }; | |
| }; | |
| etm@7840000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7840000 0x1000>; | |
| cpu = <0x13>; | |
| coresight-name = "coresight-etm0"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x29e>; | |
| phandle = <0x29e>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x46>; | |
| linux,phandle = <0x3d>; | |
| phandle = <0x3d>; | |
| }; | |
| }; | |
| }; | |
| etm@7940000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7940000 0x1000>; | |
| cpu = <0x14>; | |
| coresight-name = "coresight-etm1"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x29f>; | |
| phandle = <0x29f>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x47>; | |
| linux,phandle = <0x3e>; | |
| phandle = <0x3e>; | |
| }; | |
| }; | |
| }; | |
| etm@7a40000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7a40000 0x1000>; | |
| cpu = <0x15>; | |
| coresight-name = "coresight-etm2"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2a0>; | |
| phandle = <0x2a0>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x48>; | |
| linux,phandle = <0x3f>; | |
| phandle = <0x3f>; | |
| }; | |
| }; | |
| }; | |
| etm@7b40000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7b40000 0x1000>; | |
| cpu = <0x16>; | |
| coresight-name = "coresight-etm3"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2a1>; | |
| phandle = <0x2a1>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x49>; | |
| linux,phandle = <0x40>; | |
| phandle = <0x40>; | |
| }; | |
| }; | |
| }; | |
| etm@7c40000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7c40000 0x1000>; | |
| cpu = <0x17>; | |
| coresight-name = "coresight-etm4"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2a2>; | |
| phandle = <0x2a2>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4a>; | |
| linux,phandle = <0x41>; | |
| phandle = <0x41>; | |
| }; | |
| }; | |
| }; | |
| etm@7d40000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7d40000 0x1000>; | |
| cpu = <0x18>; | |
| coresight-name = "coresight-etm5"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2a3>; | |
| phandle = <0x2a3>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4b>; | |
| linux,phandle = <0x42>; | |
| phandle = <0x42>; | |
| }; | |
| }; | |
| }; | |
| etm@7e40000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7e40000 0x1000>; | |
| cpu = <0x19>; | |
| coresight-name = "coresight-etm6"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2a4>; | |
| phandle = <0x2a4>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4c>; | |
| linux,phandle = <0x43>; | |
| phandle = <0x43>; | |
| }; | |
| }; | |
| }; | |
| etm@7f40000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b95d>; | |
| reg = <0x7f40000 0x1000>; | |
| cpu = <0x1a>; | |
| coresight-name = "coresight-etm7"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2a5>; | |
| phandle = <0x2a5>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x4d>; | |
| linux,phandle = <0x44>; | |
| phandle = <0x44>; | |
| }; | |
| }; | |
| }; | |
| cti@6010000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6010000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti0"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x24>; | |
| phandle = <0x24>; | |
| }; | |
| cti@6011000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6011000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti1"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2a6>; | |
| phandle = <0x2a6>; | |
| }; | |
| cti@6012000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6012000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti2"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,cti-gpio-trigout = <0x4>; | |
| pinctrl-names = "cti-trigout-pctrl"; | |
| pinctrl-0 = <0x4e>; | |
| linux,phandle = <0x2a7>; | |
| phandle = <0x2a7>; | |
| }; | |
| cti@6013000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6013000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti3"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2a8>; | |
| phandle = <0x2a8>; | |
| }; | |
| cti@6014000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6014000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti4"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2a9>; | |
| phandle = <0x2a9>; | |
| }; | |
| cti@6015000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6015000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti5"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2aa>; | |
| phandle = <0x2aa>; | |
| }; | |
| cti@6016000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6016000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti6"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ab>; | |
| phandle = <0x2ab>; | |
| }; | |
| cti@6017000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6017000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti7"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ac>; | |
| phandle = <0x2ac>; | |
| }; | |
| cti@6018000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6018000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti8"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x25>; | |
| phandle = <0x25>; | |
| }; | |
| cti@6019000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x6019000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti9"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ad>; | |
| phandle = <0x2ad>; | |
| }; | |
| cti@601a000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601a000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti10"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ae>; | |
| phandle = <0x2ae>; | |
| }; | |
| cti@601b000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601b000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti11"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2af>; | |
| phandle = <0x2af>; | |
| }; | |
| cti@601c000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601c000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti12"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b0>; | |
| phandle = <0x2b0>; | |
| }; | |
| cti@601d000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601d000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti13"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b1>; | |
| phandle = <0x2b1>; | |
| }; | |
| cti@601e000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601e000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti14"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b2>; | |
| phandle = <0x2b2>; | |
| }; | |
| cti@601f000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x601f000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti15"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b3>; | |
| phandle = <0x2b3>; | |
| }; | |
| cti@7820000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7820000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu0"; | |
| cpu = <0x13>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b4>; | |
| phandle = <0x2b4>; | |
| }; | |
| cti@7920000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7920000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu1"; | |
| cpu = <0x14>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b5>; | |
| phandle = <0x2b5>; | |
| }; | |
| cti@7a20000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7a20000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu2"; | |
| cpu = <0x15>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b6>; | |
| phandle = <0x2b6>; | |
| }; | |
| cti@7b20000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7b20000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu3"; | |
| cpu = <0x16>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b7>; | |
| phandle = <0x2b7>; | |
| }; | |
| cti@7c20000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7c20000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu4"; | |
| cpu = <0x17>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b8>; | |
| phandle = <0x2b8>; | |
| }; | |
| cti@7d20000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7d20000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu5"; | |
| cpu = <0x18>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2b9>; | |
| phandle = <0x2b9>; | |
| }; | |
| cti@7e20000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7e20000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu6"; | |
| cpu = <0x19>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ba>; | |
| phandle = <0x2ba>; | |
| }; | |
| cti@7f20000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7f20000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-cpu7"; | |
| cpu = <0x1a>; | |
| qcom,cti-save; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2bb>; | |
| phandle = <0x2bb>; | |
| }; | |
| cti@7b80000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7b80000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-apss"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2bc>; | |
| phandle = <0x2bc>; | |
| }; | |
| cti@7bc1000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7bc1000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-apss-dl"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2bd>; | |
| phandle = <0x2bd>; | |
| }; | |
| cti@7b91000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7b91000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-olc"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2be>; | |
| phandle = <0x2be>; | |
| }; | |
| cti@7068000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7068000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-turing"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2bf>; | |
| phandle = <0x2bf>; | |
| }; | |
| cti@71a4000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x71a4000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-wcss0"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c0>; | |
| phandle = <0x2c0>; | |
| }; | |
| cti@71a5000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x71a5000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-wcss1"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c1>; | |
| phandle = <0x2c1>; | |
| }; | |
| cti@71a6000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x71a6000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-wcss2"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c2>; | |
| phandle = <0x2c2>; | |
| }; | |
| cti@7188000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7188000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-mmss"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c3>; | |
| phandle = <0x2c3>; | |
| }; | |
| cti@7121000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7121000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-isdb"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c4>; | |
| phandle = <0x2c4>; | |
| }; | |
| cti@7048000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7048000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-rpm"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c5>; | |
| phandle = <0x2c5>; | |
| }; | |
| cti@7041000 { | |
| compatible = "arm,coresight-cti"; | |
| reg = <0x7041000 0x1000>; | |
| reg-names = "cti-base"; | |
| coresight-name = "coresight-cti-mss"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c6>; | |
| phandle = <0x2c6>; | |
| }; | |
| qpdi@1fc1000 { | |
| compatible = "qcom,coresight-qpdi"; | |
| reg = <0x1fc1000 0x4>; | |
| reg-names = "qpdi-base"; | |
| coresight-name = "coresight-qpdi"; | |
| vdd-supply = <0x4f>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| qcom,vdd-current-level = <0x3a98 0xdbba0>; | |
| vdd-io-supply = <0x50>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>; | |
| qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
| linux,phandle = <0x2c7>; | |
| phandle = <0x2c7>; | |
| }; | |
| funnel@6005000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x6005000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-qatb"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2c8>; | |
| phandle = <0x2c8>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x51>; | |
| linux,phandle = <0x30>; | |
| phandle = <0x30>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x52>; | |
| linux,phandle = <0x54>; | |
| phandle = <0x54>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x3>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x53>; | |
| linux,phandle = <0x6f>; | |
| phandle = <0x6f>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@6004000 { | |
| compatible = "qcom,coresight-tpda"; | |
| reg = <0x6004000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda"; | |
| qcom,tpda-atid = <0x41>; | |
| qcom,bc-elem-size = <0x8 0x20 0xa 0x20>; | |
| qcom,tc-elem-size = <0x4 0x20 0x7 0x20 0xa 0x20>; | |
| qcom,dsb-elem-size = <0x2 0x20 0x8 0x20 0xa 0x20 0xb 0x20>; | |
| qcom,cmb-elem-size = <0x4 0x20 0x5 0x20 0x6 0x20 0xa 0x40>; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2c9>; | |
| phandle = <0x2c9>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x54>; | |
| linux,phandle = <0x52>; | |
| phandle = <0x52>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x2>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x55>; | |
| linux,phandle = <0x6e>; | |
| phandle = <0x6e>; | |
| }; | |
| }; | |
| port@3 { | |
| reg = <0x4>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x56>; | |
| linux,phandle = <0x5c>; | |
| phandle = <0x5c>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x5>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x57>; | |
| linux,phandle = <0x5d>; | |
| phandle = <0x5d>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x6>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x58>; | |
| linux,phandle = <0x5e>; | |
| phandle = <0x5e>; | |
| }; | |
| }; | |
| port@6 { | |
| reg = <0x8>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x59>; | |
| linux,phandle = <0x5f>; | |
| phandle = <0x5f>; | |
| }; | |
| }; | |
| port@7 { | |
| reg = <0xa>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x5a>; | |
| linux,phandle = <0x60>; | |
| phandle = <0x60>; | |
| }; | |
| }; | |
| port@8 { | |
| reg = <0xb>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x5b>; | |
| linux,phandle = <0x61>; | |
| phandle = <0x61>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@7038000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7038000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-vsense"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ca>; | |
| phandle = <0x2ca>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5c>; | |
| linux,phandle = <0x56>; | |
| phandle = <0x56>; | |
| }; | |
| }; | |
| }; | |
| tpdm@7054000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7054000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-dcc"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2cb>; | |
| phandle = <0x2cb>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5d>; | |
| linux,phandle = <0x57>; | |
| phandle = <0x57>; | |
| }; | |
| }; | |
| }; | |
| tpdm@704c000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x704c000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-prng"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2cc>; | |
| phandle = <0x2cc>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5e>; | |
| linux,phandle = <0x58>; | |
| phandle = <0x58>; | |
| }; | |
| }; | |
| }; | |
| tpdm@71d0000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x71d0000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-qm"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2cd>; | |
| phandle = <0x2cd>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x5f>; | |
| linux,phandle = <0x59>; | |
| phandle = <0x59>; | |
| }; | |
| }; | |
| }; | |
| tpdm@7050000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7050000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-pimem"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2ce>; | |
| phandle = <0x2ce>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x60>; | |
| linux,phandle = <0x5a>; | |
| phandle = <0x5a>; | |
| }; | |
| }; | |
| }; | |
| tpdm@6006000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x6006000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2cf>; | |
| phandle = <0x2cf>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x61>; | |
| linux,phandle = <0x5b>; | |
| phandle = <0x5b>; | |
| }; | |
| }; | |
| }; | |
| tpda@7191000 { | |
| compatible = "qcom,coresight-tpda"; | |
| reg = <0x7191000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-nav"; | |
| qcom,tpda-atid = <0x44>; | |
| qcom,cmb-elem-size = <0x0 0x20>; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d0>; | |
| phandle = <0x2d0>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x62>; | |
| linux,phandle = <0x34>; | |
| phandle = <0x34>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x63>; | |
| linux,phandle = <0x6a>; | |
| phandle = <0x6a>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpda@7bc2000 { | |
| compatible = "qcom,coresight-tpda"; | |
| reg = <0x7bc2000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-apss"; | |
| qcom,tpda-atid = <0x42>; | |
| qcom,dsb-elem-size = <0x0 0x20>; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d1>; | |
| phandle = <0x2d1>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x64>; | |
| linux,phandle = <0x3b>; | |
| phandle = <0x3b>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x65>; | |
| linux,phandle = <0x66>; | |
| phandle = <0x66>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@7bc0000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7bc0000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-apss"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d2>; | |
| phandle = <0x2d2>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x66>; | |
| linux,phandle = <0x65>; | |
| phandle = <0x65>; | |
| }; | |
| }; | |
| }; | |
| tpda@7043000 { | |
| compatible = "qcom,coresight-tpda"; | |
| reg = <0x7043000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-mss"; | |
| qcom,tpda-atid = <0x43>; | |
| qcom,dsb-elem-size = <0x0 0x20>; | |
| qcom,cmb-elem-size = <0x0 0x20>; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d3>; | |
| phandle = <0x2d3>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x67>; | |
| linux,phandle = <0x72>; | |
| phandle = <0x72>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x68>; | |
| linux,phandle = <0x69>; | |
| phandle = <0x69>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@7042000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7042000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-mss"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d4>; | |
| phandle = <0x2d4>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x69>; | |
| linux,phandle = <0x68>; | |
| phandle = <0x68>; | |
| }; | |
| }; | |
| }; | |
| tpdm@7190000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7190000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-nav"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d5>; | |
| phandle = <0x2d5>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6a>; | |
| linux,phandle = <0x63>; | |
| phandle = <0x63>; | |
| }; | |
| }; | |
| }; | |
| tpda@7b92000 { | |
| compatible = "qcom,coresight-tpda"; | |
| reg = <0x7b92000 0x1000>; | |
| reg-names = "tpda-base"; | |
| coresight-name = "coresight-tpda-olc"; | |
| qcom,tpda-atid = <0x45>; | |
| qcom,cmb-elem-size = <0x0 0x40>; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d6>; | |
| phandle = <0x2d6>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x6b>; | |
| linux,phandle = <0x3a>; | |
| phandle = <0x3a>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x6c>; | |
| linux,phandle = <0x6d>; | |
| phandle = <0x6d>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@7b90000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x7b90000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-olc"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d7>; | |
| phandle = <0x2d7>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x6d>; | |
| linux,phandle = <0x6c>; | |
| phandle = <0x6c>; | |
| }; | |
| }; | |
| }; | |
| funnel@71c3000 { | |
| compatible = "arm,primecell"; | |
| arm,primecell-periphid = <0x3b908>; | |
| reg = <0x71c3000 0x1000>; | |
| reg-names = "funnel-base"; | |
| coresight-name = "coresight-funnel-dlct"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "apb_pclk", "core_a_clk"; | |
| linux,phandle = <0x2d8>; | |
| phandle = <0x2d8>; | |
| ports { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| port@0 { | |
| reg = <0x0>; | |
| endpoint { | |
| remote-endpoint = <0x6e>; | |
| linux,phandle = <0x55>; | |
| phandle = <0x55>; | |
| }; | |
| }; | |
| port@1 { | |
| reg = <0x1>; | |
| endpoint { | |
| remote-endpoint = <0x6f>; | |
| linux,phandle = <0x53>; | |
| phandle = <0x53>; | |
| }; | |
| }; | |
| port@2 { | |
| reg = <0x0>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x70>; | |
| linux,phandle = <0x73>; | |
| phandle = <0x73>; | |
| }; | |
| }; | |
| port@4 { | |
| reg = <0x1>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x71>; | |
| linux,phandle = <0x76>; | |
| phandle = <0x76>; | |
| }; | |
| }; | |
| port@5 { | |
| reg = <0x2>; | |
| endpoint { | |
| slave-mode; | |
| remote-endpoint = <0x72>; | |
| linux,phandle = <0x67>; | |
| phandle = <0x67>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| tpdm@71c2000 { | |
| compatible = "qcom,coresight-tpdm"; | |
| reg = <0x71c2000 0x1000>; | |
| reg-names = "tpdm-base"; | |
| coresight-name = "coresight-tpdm-dlct"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| linux,phandle = <0x2d9>; | |
| phandle = <0x2d9>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x73>; | |
| linux,phandle = <0x70>; | |
| phandle = <0x70>; | |
| }; | |
| }; | |
| }; | |
| hwevent@158000 { | |
| compatible = "qcom,coresight-hwevent"; | |
| reg = <0x158000 0x80 0x17091000 0x80 0x1730200c 0x4 0xc90137c 0x4 0xc828018 0x80 0x1c00058 0x80 0x5e02038 0x4 0x5e02028 0x10 0x1fcb360 0x80 0x1fcb760 0x80 0x1fcbf60 0x80 0xa8f8860 0x4 0x500c260 0x4 0x500d040 0x4 0x1da6400 0x80>; | |
| reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", "vbif-stm", "vbif-stm-en", "ufs-mux"; | |
| coresight-name = "coresight-hwevent"; | |
| clocks = <0x26 0x8 0x26 0x9 0x74 0xa7>; | |
| clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; | |
| qcom,hwevent-clks = "core_mmss_clk"; | |
| linux,phandle = <0x2da>; | |
| phandle = <0x2da>; | |
| }; | |
| csr@6001000 { | |
| compatible = "qcom,coresight-csr"; | |
| reg = <0x6001000 0x1000>; | |
| reg-names = "csr-base"; | |
| coresight-name = "coresight-csr"; | |
| qcom,blk-size = <0x1>; | |
| linux,phandle = <0x2db>; | |
| phandle = <0x2db>; | |
| }; | |
| modem_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-modem-etm0"; | |
| qcom,inst-id = <0x2>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x75>; | |
| linux,phandle = <0x35>; | |
| phandle = <0x35>; | |
| }; | |
| }; | |
| }; | |
| audio_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-audio-etm0"; | |
| qcom,inst-id = <0x5>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x76>; | |
| linux,phandle = <0x71>; | |
| phandle = <0x71>; | |
| }; | |
| }; | |
| }; | |
| rpm_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-rpm-etm0"; | |
| qcom,inst-id = <0x4>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x77>; | |
| linux,phandle = <0x32>; | |
| phandle = <0x32>; | |
| }; | |
| }; | |
| }; | |
| turing_etm0 { | |
| compatible = "qcom,coresight-remote-etm"; | |
| coresight-name = "coresight-turing-etm0"; | |
| qcom,inst-id = <0xd>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x78>; | |
| linux,phandle = <0x37>; | |
| phandle = <0x37>; | |
| }; | |
| }; | |
| }; | |
| interrupt-controller@17a00000 { | |
| compatible = "arm,gic-v3"; | |
| reg = <0x17a00000 0x10000 0x17b00000 0x100000>; | |
| #interrupt-cells = <0x3>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| interrupt-controller; | |
| #redistributor-regions = <0x1>; | |
| redistributor-stride = <0x0 0x20000>; | |
| interrupts = <0x1 0x9 0x4>; | |
| linux,phandle = <0x1>; | |
| phandle = <0x1>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupts = <0x1 0x1 0xf08 0x1 0x2 0xf08 0x1 0x3 0xf08 0x1 0x0 0xf08>; | |
| clock-frequency = <0x124f800>; | |
| }; | |
| qcom,sps-dma@0xc144000 { | |
| #dma-cells = <0x4>; | |
| compatible = "qcom,sps-dma"; | |
| reg = <0xc144000 0x1f000>; | |
| interrupts = <0x0 0xee 0x0>; | |
| qcom,summing-threshold = <0x10>; | |
| linux,phandle = <0x17a>; | |
| phandle = <0x17a>; | |
| }; | |
| qcom,sps-dma@0xc184000 { | |
| #dma-cells = <0x4>; | |
| compatible = "qcom,sps-dma"; | |
| reg = <0xc184000 0x1f000>; | |
| interrupts = <0x0 0xef 0x0>; | |
| qcom,summing-threshold = <0x10>; | |
| linux,phandle = <0x18b>; | |
| phandle = <0x18b>; | |
| }; | |
| restart@10ac000 { | |
| compatible = "qcom,pshold"; | |
| reg = <0x10ac000 0x4 0x1fd3000 0x4>; | |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; | |
| }; | |
| qcom,spmi@800f000 { | |
| compatible = "qcom,spmi-pmic-arb"; | |
| reg = <0x800f000 0x1000 0x8400000 0x1000000 0x9400000 0x1000000 0xa400000 0x220000 0x800a000 0x3000>; | |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
| interrupt-names = "periph_irq"; | |
| interrupts = <0x0 0x146 0x0>; | |
| qcom,ee = <0x0>; | |
| qcom,channel = <0x0>; | |
| qcom,reserved-chan = <0x1ff>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x4>; | |
| cell-index = <0x0>; | |
| status = "ok"; | |
| linux,phandle = <0x87>; | |
| phandle = <0x87>; | |
| qcom,pm660@0 { | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x0 0x0>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100 0x100>; | |
| qcom,fab-id-valid; | |
| qcom,tp-rev-valid; | |
| linux,phandle = <0x7a>; | |
| phandle = <0x7a>; | |
| }; | |
| qcom,misc@900 { | |
| compatible = "qcom,qpnp-misc"; | |
| reg = <0x900 0x100>; | |
| linux,phandle = <0x81>; | |
| phandle = <0x81>; | |
| }; | |
| qcom,power-on@800 { | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| interrupts = <0x0 0x8 0x0 0x0 0x0 0x8 0x1 0x0 0x0 0x8 0x4 0x0 0x0 0x8 0x5 0x0>; | |
| interrupt-names = "kpdpwr", "resin", "resin-bark", "kpdpwr-resin-bark"; | |
| qcom,pon-dbc-delay = <0x3d09>; | |
| qcom,kpdpwr-sw-debounce; | |
| qcom,system-reset; | |
| qcom,store-hard-reset-reason; | |
| qcom,pon_1 { | |
| qcom,pon-type = <0x0>; | |
| qcom,pull-up = <0x1>; | |
| linux,code = <0x74>; | |
| qcom,support-reset = <0x1>; | |
| qcom,s1-timer = <0x1180>; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,s2-type = <0x7>; | |
| }; | |
| qcom,pon_2 { | |
| qcom,pon-type = <0x1>; | |
| qcom,pull-up = <0x1>; | |
| linux,code = <0x72>; | |
| }; | |
| qcom,pon_3 { | |
| qcom,pon-type = <0x3>; | |
| qcom,pull-up = <0x1>; | |
| qcom,support-reset = <0x1>; | |
| qcom,s1-timer = <0xc00>; | |
| qcom,s2-timer = <0x7d0>; | |
| qcom,s2-type = <0x1>; | |
| qcom,use-bark; | |
| }; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| compatible = "qcom,qpnp-temp-alarm"; | |
| reg = <0x2400 0x100>; | |
| interrupts = <0x0 0x24 0x0 0x1>; | |
| label = "pm660_tz"; | |
| qcom,channel-num = <0x6>; | |
| qcom,temp_alarm-vadc = <0x79>; | |
| }; | |
| gpios { | |
| compatible = "qcom,qpnp-pin"; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| label = "pm660-gpio"; | |
| linux,phandle = <0x192>; | |
| phandle = <0x192>; | |
| gpio@c000 { | |
| reg = <0xc000 0x100>; | |
| qcom,pin-num = <0x1>; | |
| status = "disabled"; | |
| }; | |
| gpio@c100 { | |
| reg = <0xc100 0x100>; | |
| qcom,pin-num = <0x2>; | |
| status = "disabled"; | |
| }; | |
| gpio@c200 { | |
| reg = <0xc200 0x100>; | |
| qcom,pin-num = <0x3>; | |
| status = "ok"; | |
| qcom,mode = <0x1>; | |
| qcom,pull = <0x4>; | |
| qcom,vin-sel = <0x0>; | |
| qcom,src-sel = <0x2>; | |
| qcom,master-en = <0x1>; | |
| qcom,out-strength = <0x2>; | |
| }; | |
| gpio@c300 { | |
| reg = <0xc300 0x100>; | |
| qcom,pin-num = <0x4>; | |
| status = "okay"; | |
| qcom,mode = <0x0>; | |
| qcom,vin-sel = <0x1>; | |
| qcom,src-sel = <0x0>; | |
| qcom,master-en = <0x1>; | |
| }; | |
| gpio@c400 { | |
| reg = <0xc400 0x100>; | |
| qcom,pin-num = <0x5>; | |
| status = "disabled"; | |
| }; | |
| gpio@c500 { | |
| reg = <0xc500 0x100>; | |
| qcom,pin-num = <0x6>; | |
| status = "disabled"; | |
| }; | |
| gpio@c600 { | |
| reg = <0xc600 0x100>; | |
| qcom,pin-num = <0x7>; | |
| status = "disabled"; | |
| }; | |
| gpio@c700 { | |
| reg = <0xc700 0x100>; | |
| qcom,pin-num = <0x8>; | |
| status = "disabled"; | |
| }; | |
| gpio@c800 { | |
| reg = <0xc800 0x100>; | |
| qcom,pin-num = <0x9>; | |
| status = "disabled"; | |
| }; | |
| gpio@c900 { | |
| reg = <0xc900 0x100>; | |
| qcom,pin-num = <0xa>; | |
| status = "disabled"; | |
| }; | |
| gpio@ca00 { | |
| reg = <0xca00 0x100>; | |
| qcom,pin-num = <0xb>; | |
| status = "okay"; | |
| qcom,mode = <0x0>; | |
| qcom,pull = <0x0>; | |
| qcom,vin-sel = <0x0>; | |
| qcom,src-sel = <0x0>; | |
| qcom,out-strength = <0x1>; | |
| }; | |
| gpio@cb00 { | |
| reg = <0xcb00 0x100>; | |
| qcom,pin-num = <0xc>; | |
| status = "disabled"; | |
| }; | |
| gpio@cc00 { | |
| reg = <0xcc00 0x100>; | |
| qcom,pin-num = <0xd>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| qcom,coincell@2800 { | |
| compatible = "qcom,qpnp-coincell"; | |
| reg = <0x2800 0x100>; | |
| qcom,charge-enable = <0x0>; | |
| linux,phandle = <0x2dc>; | |
| phandle = <0x2dc>; | |
| }; | |
| qcom,pm660_rtc { | |
| compatible = "qcom,qpnp-rtc"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| qcom,qpnp-rtc-write = <0x0>; | |
| qcom,qpnp-rtc-alarm-pwrup = <0x0>; | |
| linux,phandle = <0x2dd>; | |
| phandle = <0x2dd>; | |
| qcom,pm660_rtc_rw@6000 { | |
| reg = <0x6000 0x100>; | |
| }; | |
| qcom,pm660_rtc_alarm@6100 { | |
| reg = <0x6100 0x100>; | |
| interrupts = <0x0 0x61 0x1 0x0>; | |
| }; | |
| }; | |
| vadc@3100 { | |
| compatible = "qcom,qpnp-vadc-hc"; | |
| reg = <0x3100 0x100>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| interrupts = <0x0 0x31 0x0 0x1>; | |
| interrupt-names = "eoc-int-en-set"; | |
| qcom,adc-bit-resolution = <0xf>; | |
| qcom,adc-vdd-reference = <0x753>; | |
| linux,phandle = <0x79>; | |
| phandle = <0x79>; | |
| chan@6 { | |
| label = "die_temp"; | |
| reg = <0x6>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x3>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,cal-val = <0x0>; | |
| }; | |
| chan@0 { | |
| label = "ref_gnd"; | |
| reg = <0x0>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x0>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,cal-val = <0x0>; | |
| }; | |
| chan@1 { | |
| label = "ref_1250v"; | |
| reg = <0x1>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x0>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,cal-val = <0x0>; | |
| }; | |
| chan@83 { | |
| label = "vph_pwr"; | |
| reg = <0x83>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x1>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x0>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| }; | |
| chan@85 { | |
| label = "vcoin"; | |
| reg = <0x85>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x1>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x0>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| }; | |
| chan@4c { | |
| label = "xo_therm"; | |
| reg = <0x4c>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x4>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,fast-avg-setup = <0x0>; | |
| }; | |
| chan@4d { | |
| label = "msm_therm"; | |
| reg = <0x4d>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,fast-avg-setup = <0x0>; | |
| }; | |
| chan@50 { | |
| label = "backlight_therm"; | |
| reg = <0x50>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,vadc-thermal-node; | |
| }; | |
| chan@51 { | |
| label = "quiet_therm"; | |
| reg = <0x51>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,fast-avg-setup = <0x0>; | |
| }; | |
| chan@4e { | |
| label = "emmc_therm"; | |
| reg = <0x4e>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,vadc-thermal-node; | |
| }; | |
| chan@4f { | |
| label = "pa_therm0"; | |
| reg = <0x4f>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,vadc-thermal-node; | |
| }; | |
| chan@1d { | |
| label = "drax_temp"; | |
| reg = <0x1d>; | |
| qcom,decimation = <0x2>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x3>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| qcom,cal-val = <0x0>; | |
| }; | |
| }; | |
| qcom,qpnp-smb2 { | |
| compatible = "qcom,qpnp-smb2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| qcom,pmic-revid = <0x7a>; | |
| io-channels = <0x7b 0x8 0x7b 0xa 0x7b 0x3 0x7b 0x4>; | |
| io-channel-names = "charger_temp", "charger_temp_max", "usbin_i", "usbin_v"; | |
| qcom,wipower-max-uw = <0x4c4b40>; | |
| dpdm-supply = <0x7c>; | |
| qcom,usb-icl-ua = <0x2c4020>; | |
| qcom,otg-cl-ua = <0x16e360>; | |
| qcom,dc-icl-ua = <0x2c4020>; | |
| qcom,fcc-max-ua = <0x2c4020>; | |
| qcom,fv-max-uv = <0x432380>; | |
| qcom,sw-jeita-enable; | |
| qcom,thermal-mitigation = <0x2c4020 0x249f00 0x1e8480 0x16e360 0xc3500 0x7a120 0x186a0>; | |
| linux,phandle = <0x2de>; | |
| phandle = <0x2de>; | |
| qcom,chgr@1000 { | |
| reg = <0x1000 0x100>; | |
| interrupts = <0x0 0x10 0x0 0x1 0x0 0x10 0x1 0x1 0x0 0x10 0x2 0x1 0x0 0x10 0x3 0x1 0x0 0x10 0x4 0x1>; | |
| interrupt-names = "chg-error", "chg-state-change", "step-chg-state-change", "step-chg-soc-update-fail", "step-chg-soc-update-request"; | |
| }; | |
| qcom,otg@1100 { | |
| reg = <0x1100 0x100>; | |
| interrupts = <0x0 0x11 0x0 0x3 0x0 0x11 0x1 0x3 0x0 0x11 0x2 0x3 0x0 0x11 0x3 0x3>; | |
| interrupt-names = "otg-fail", "otg-overcurrent", "otg-oc-dis-sw-sts", "testmode-change-detect"; | |
| }; | |
| qcom,bat-if@1200 { | |
| reg = <0x1200 0x100>; | |
| interrupts = <0x0 0x12 0x0 0x1 0x0 0x12 0x1 0x3 0x0 0x12 0x2 0x3 0x0 0x12 0x3 0x3 0x0 0x12 0x4 0x3 0x0 0x12 0x5 0x3>; | |
| interrupt-names = "bat-temp", "bat-ocp", "bat-ov", "bat-low", "bat-therm-or-id-missing", "bat-terminal-missing"; | |
| }; | |
| qcom,usb-chgpth@1300 { | |
| reg = <0x1300 0x100>; | |
| interrupts = <0x0 0x13 0x0 0x3 0x0 0x13 0x1 0x3 0x0 0x13 0x2 0x3 0x0 0x13 0x3 0x3 0x0 0x13 0x4 0x3 0x0 0x13 0x5 0x1 0x0 0x13 0x6 0x1 0x0 0x13 0x7 0x1>; | |
| interrupt-names = "usbin-collapse", "usbin-lt-3p6v", "usbin-uv", "usbin-ov", "usbin-plugin", "usbin-src-change", "usbin-icl-change", "type-c-change"; | |
| }; | |
| qcom,dc-chgpth@1400 { | |
| reg = <0x1400 0x100>; | |
| interrupts = <0x0 0x14 0x0 0x3 0x0 0x14 0x1 0x3 0x0 0x14 0x2 0x3 0x0 0x14 0x3 0x3 0x0 0x14 0x4 0x3 0x0 0x14 0x5 0x3 0x0 0x14 0x6 0x1>; | |
| interrupt-names = "dcin-collapse", "dcin-lt-3p6v", "dcin-uv", "dcin-ov", "dcin-plugin", "div2-en-dg", "dcin-icl-change"; | |
| }; | |
| qcom,chgr-misc@1600 { | |
| reg = <0x1600 0x100>; | |
| interrupts = <0x0 0x16 0x0 0x1 0x0 0x16 0x1 0x1 0x0 0x16 0x2 0x3 0x0 0x16 0x3 0x3 0x0 0x16 0x4 0x3 0x0 0x16 0x5 0x3 0x0 0x16 0x6 0x2 0x0 0x16 0x7 0x3>; | |
| interrupt-names = "wdog-snarl", "wdog-bark", "aicl-fail", "aicl-done", "high-duty-cycle", "input-current-limiting", "temperature-change", "switcher-power-ok"; | |
| }; | |
| qcom,smb2-vbus { | |
| regulator-name = "smb2-vbus"; | |
| linux,phandle = <0x7e>; | |
| phandle = <0x7e>; | |
| }; | |
| qcom,smb2-vconn { | |
| regulator-name = "smb2-vconn"; | |
| linux,phandle = <0x7f>; | |
| phandle = <0x7f>; | |
| }; | |
| }; | |
| qcom,usb-pdphy@1700 { | |
| compatible = "qcom,qpnp-pdphy"; | |
| reg = <0x1700 0x100>; | |
| vdd-pdphy-supply = <0x7d>; | |
| vbus-supply = <0x7e>; | |
| vconn-supply = <0x7f>; | |
| interrupts = <0x0 0x17 0x0 0x1 0x0 0x17 0x1 0x1 0x0 0x17 0x2 0x1 0x0 0x17 0x3 0x1 0x0 0x17 0x4 0x1 0x0 0x17 0x5 0x1 0x0 0x17 0x6 0x1>; | |
| interrupt-names = "sig-tx", "sig-rx", "msg-tx", "msg-rx", "msg-tx-failed", "msg-tx-discarded", "msg-rx-discarded"; | |
| qcom,default-sink-caps = <0x1388 0xbb8 0x2328 0xbb8>; | |
| linux,phandle = <0x176>; | |
| phandle = <0x176>; | |
| }; | |
| vadc@3400 { | |
| compatible = "qcom,qpnp-adc-tm-hc"; | |
| reg = <0x3400 0x100>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| interrupts = <0x0 0x34 0x0 0x1>; | |
| interrupt-names = "eoc-int-en-set"; | |
| qcom,adc-bit-resolution = <0xf>; | |
| qcom,adc-vdd-reference = <0x753>; | |
| qcom,adc_tm-vadc = <0x79>; | |
| qcom,decimation = <0x0>; | |
| qcom,fast-avg-setup = <0x0>; | |
| linux,phandle = <0x2df>; | |
| phandle = <0x2df>; | |
| chan@83 { | |
| label = "vph_pwr"; | |
| reg = <0x83>; | |
| qcom,pre-div-channel-scaling = <0x1>; | |
| qcom,calibration-type = "absolute"; | |
| qcom,scale-function = <0x0>; | |
| qcom,hw-settle-time = <0x0>; | |
| qcom,btm-channel-number = <0x60>; | |
| }; | |
| chan@4d { | |
| label = "msm_therm"; | |
| reg = <0x4d>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,btm-channel-number = <0x68>; | |
| qcom,thermal-node; | |
| }; | |
| chan@51 { | |
| label = "quiet_therm"; | |
| reg = <0x51>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x2>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,btm-channel-number = <0x70>; | |
| qcom,thermal-node; | |
| }; | |
| chan@4c { | |
| label = "xo_therm"; | |
| reg = <0x4c>; | |
| qcom,pre-div-channel-scaling = <0x0>; | |
| qcom,calibration-type = "ratiometric"; | |
| qcom,scale-function = <0x4>; | |
| qcom,hw-settle-time = <0x2>; | |
| qcom,btm-channel-number = <0x78>; | |
| qcom,thermal-node; | |
| }; | |
| }; | |
| rradc@4500 { | |
| compatible = "qcom,rradc"; | |
| reg = <0x4500 0x100>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| #io-channel-cells = <0x1>; | |
| qcom,pmic-revid = <0x7a>; | |
| linux,phandle = <0x7b>; | |
| phandle = <0x7b>; | |
| }; | |
| qpnp,fg { | |
| compatible = "qcom,fg-gen3"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| qcom,pmic-revid = <0x7a>; | |
| io-channels = <0x7b 0x0 0x7b 0x7>; | |
| io-channel-names = "rradc_batt_id", "rradc_die_temp"; | |
| qcom,rradc-base = <0x4500>; | |
| qcom,fg-cutoff-voltage = <0xd48>; | |
| qcom,fg-chg-term-current = <0xc8>; | |
| qcom,fg-sys-term-current = <0x12c>; | |
| qcom,fg-recharge-voltage = <0x10fe>; | |
| qcom,fg-esr-timer-awake = <0x60 0x60>; | |
| qcom,fg-esr-timer-asleep = <0x100 0x100>; | |
| qcom,fg-esr-timer-charging = <0x0 0x60>; | |
| qcom,cycle-counter-en; | |
| qcom,fg-jeita-thresholds = <0x0 0xf 0x2d 0x3c>; | |
| qcom,fg-jeita-hyst-temp = <0x0>; | |
| qcom,battery-thermal-coefficients = [d2 50 ff]; | |
| status = "okay"; | |
| qcom,battery-data = <0x80>; | |
| linux,phandle = <0x2e0>; | |
| phandle = <0x2e0>; | |
| qcom,fg-batt-soc@4000 { | |
| status = "okay"; | |
| reg = <0x4000 0x100>; | |
| interrupts = <0x0 0x40 0x0 0x3 0x0 0x40 0x1 0x3 0x0 0x40 0x2 0x1 0x0 0x40 0x3 0x1 0x0 0x40 0x4 0x3 0x0 0x40 0x5 0x1 0x0 0x40 0x6 0x3 0x0 0x40 0x7 0x3>; | |
| interrupt-names = "soc-update", "soc-ready", "bsoc-delta", "msoc-delta", "msoc-low", "msoc-empty", "msoc-high", "msoc-full"; | |
| }; | |
| qcom,fg-batt-info@4100 { | |
| status = "okay"; | |
| reg = <0x4100 0x100>; | |
| interrupts = <0x0 0x41 0x0 0x3 0x0 0x41 0x1 0x3 0x0 0x41 0x2 0x3 0x0 0x41 0x3 0x3 0x0 0x41 0x6 0x3>; | |
| interrupt-names = "vbatt-pred-delta", "vbatt-low", "esr-delta", "batt-missing", "batt-temp-delta"; | |
| }; | |
| qcom,fg-memif@4400 { | |
| status = "okay"; | |
| reg = <0x4400 0x100>; | |
| interrupts = <0x0 0x44 0x0 0x3 0x0 0x44 0x1 0x3 0x0 0x44 0x2 0x3>; | |
| interrupt-names = "ima-rdy", "mem-xcp", "dma-grant"; | |
| }; | |
| }; | |
| bcl@4200 { | |
| compatible = "qcom,msm-bcl-lmh"; | |
| reg = <0x4200 0xff 0x4300 0xff>; | |
| reg-names = "fg_user_adc", "fg_lmh"; | |
| interrupts = <0x0 0x42 0x0 0x0 0x0 0x42 0x2 0x0>; | |
| interrupt-names = "bcl-high-ibat-int", "bcl-low-vbat-int"; | |
| qcom,vbat-polling-delay-ms = <0x64>; | |
| qcom,ibat-polling-delay-ms = <0x64>; | |
| }; | |
| }; | |
| qcom,pm660@1 { | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x1 0x0>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| qcom,haptic@c000 { | |
| compatible = "qcom,qpnp-haptic"; | |
| reg = <0xc000 0x100>; | |
| interrupts = <0x1 0xc0 0x0 0x3 0x1 0xc0 0x1 0x3>; | |
| interrupt-names = "sc-irq", "play-irq"; | |
| qcom,pmic-revid = <0x7a>; | |
| qcom,pmic-misc = <0x81>; | |
| qcom,misc-clk-trim-error-reg = <0xf3>; | |
| qcom,actuator-type = "erm"; | |
| qcom,play-mode = "direct"; | |
| qcom,vmax-mv = <0xc80>; | |
| qcom,ilim-ma = <0x320>; | |
| qcom,wave-shape = "square"; | |
| qcom,wave-play-rate-us = <0x1a0b>; | |
| qcom,int-pwm-freq-khz = <0x1f9>; | |
| qcom,sc-deb-cycles = <0x8>; | |
| qcom,en-brake; | |
| qcom,brake-pattern = <0x3030000>; | |
| qcom,lra-high-z = "opt0"; | |
| qcom,lra-auto-res-mode = "qwd"; | |
| qcom,lra-calibrate-at-eop = <0x0>; | |
| qcom,correct-lra-drive-freq; | |
| linux,phandle = <0x2e1>; | |
| phandle = <0x2e1>; | |
| }; | |
| }; | |
| qcom,pm660l@2 { | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x2 0x0>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| qcom,revid@100 { | |
| compatible = "qcom,qpnp-revid"; | |
| reg = <0x100 0x100>; | |
| linux,phandle = <0x85>; | |
| phandle = <0x85>; | |
| }; | |
| qcom,pbs@7300 { | |
| compatible = "qcom,qpnp-pbs"; | |
| reg = <0x7300 0x100>; | |
| linux,phandle = <0x86>; | |
| phandle = <0x86>; | |
| }; | |
| qcom,power-on@800 { | |
| compatible = "qcom,qpnp-power-on"; | |
| reg = <0x800 0x100>; | |
| qcom,secondary-pon-reset; | |
| qcom,hard-reset-poweroff-type = <0x4>; | |
| }; | |
| qcom,temp-alarm@2400 { | |
| compatible = "qcom,qpnp-temp-alarm"; | |
| reg = <0x2400 0x100>; | |
| interrupts = <0x2 0x24 0x0 0x1>; | |
| label = "pm660l_tz"; | |
| }; | |
| gpios { | |
| compatible = "qcom,qpnp-pin"; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| label = "pm660l-gpio"; | |
| linux,phandle = <0x264>; | |
| phandle = <0x264>; | |
| gpio@c000 { | |
| reg = <0xc000 0x100>; | |
| qcom,pin-num = <0x1>; | |
| status = "disabled"; | |
| }; | |
| gpio@c100 { | |
| reg = <0xc100 0x100>; | |
| qcom,pin-num = <0x2>; | |
| status = "disabled"; | |
| }; | |
| gpio@c200 { | |
| reg = <0xc200 0x100>; | |
| qcom,pin-num = <0x3>; | |
| status = "ok"; | |
| qcom,mode = <0x1>; | |
| qcom,pull = <0x5>; | |
| qcom,vin-sel = <0x0>; | |
| qcom,src-sel = <0x0>; | |
| qcom,invert = <0x0>; | |
| qcom,master-en = <0x1>; | |
| }; | |
| gpio@c300 { | |
| reg = <0xc300 0x100>; | |
| qcom,pin-num = <0x4>; | |
| status = "ok"; | |
| qcom,mode = <0x1>; | |
| qcom,pull = <0x5>; | |
| qcom,vin-sel = <0x0>; | |
| qcom,src-sel = <0x0>; | |
| qcom,invert = <0x0>; | |
| qcom,master-en = <0x1>; | |
| }; | |
| gpio@c400 { | |
| reg = <0xc400 0x100>; | |
| qcom,pin-num = <0x5>; | |
| status = "disabled"; | |
| }; | |
| gpio@c500 { | |
| reg = <0xc500 0x100>; | |
| qcom,pin-num = <0x6>; | |
| status = "disabled"; | |
| }; | |
| gpio@c600 { | |
| reg = <0xc600 0x100>; | |
| qcom,pin-num = <0x7>; | |
| status = "okay"; | |
| qcom,mode = <0x0>; | |
| qcom,pull = <0x0>; | |
| qcom,vin-sel = <0x0>; | |
| qcom,src-sel = <0x0>; | |
| qcom,out-strength = <0x1>; | |
| }; | |
| gpio@c700 { | |
| reg = <0xc700 0x100>; | |
| qcom,pin-num = <0x8>; | |
| status = "disabled"; | |
| }; | |
| gpio@c800 { | |
| reg = <0xc800 0x100>; | |
| qcom,pin-num = <0x9>; | |
| status = "disabled"; | |
| }; | |
| gpio@c900 { | |
| reg = <0xc900 0x100>; | |
| qcom,pin-num = <0xa>; | |
| status = "disabled"; | |
| }; | |
| gpio@ca00 { | |
| reg = <0xca00 0x100>; | |
| qcom,pin-num = <0xb>; | |
| status = "disabled"; | |
| }; | |
| gpio@cb00 { | |
| reg = <0xcb00 0x100>; | |
| qcom,pin-num = <0xc>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| }; | |
| qcom,pm660l@3 { | |
| compatible = "qcom,spmi-pmic"; | |
| reg = <0x3 0x0>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| linux,phandle = <0x2e2>; | |
| phandle = <0x2e2>; | |
| pwm@b100 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg = <0xb100 0x100 0xb042 0x7e>; | |
| reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x1>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| qcom,supported-sizes = <0x6 0x9>; | |
| qcom,ramp-index = <0x0>; | |
| #pwm-cells = <0x2>; | |
| linux,phandle = <0x84>; | |
| phandle = <0x84>; | |
| }; | |
| pwm@b200 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg = <0xb200 0x100 0xb042 0x7e>; | |
| reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x2>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| qcom,supported-sizes = <0x6 0x9>; | |
| qcom,ramp-index = <0x1>; | |
| #pwm-cells = <0x2>; | |
| linux,phandle = <0x83>; | |
| phandle = <0x83>; | |
| }; | |
| pwm@b300 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg = <0xb300 0x100 0xb042 0x7e>; | |
| reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x3>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| qcom,supported-sizes = <0x6 0x9>; | |
| qcom,ramp-index = <0x2>; | |
| #pwm-cells = <0x2>; | |
| qcom,period = <0x5b8d80>; | |
| linux,phandle = <0x82>; | |
| phandle = <0x82>; | |
| qcom,lpg { | |
| label = "lpg"; | |
| cell-index = <0x0>; | |
| qcom,duty-percents = <0x1 0xa 0x14 0x1e 0x28 0x32 0x3c 0x46 0x50 0x5a 0x64 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e 0x14 0xa 0x1>; | |
| }; | |
| }; | |
| pwm@b400 { | |
| compatible = "qcom,qpnp-pwm"; | |
| reg = <0xb400 0x100 0xb042 0x7e>; | |
| reg-names = "qpnp-lpg-channel-base", "qpnp-lpg-lut-base"; | |
| qcom,channel-id = <0x4>; | |
| qcom,lpg-lut-size = <0x7e>; | |
| qcom,supported-sizes = <0x6 0x9>; | |
| qcom,ramp-index = <0x3>; | |
| #pwm-cells = <0x2>; | |
| status = "disabled"; | |
| linux,phandle = <0x2e3>; | |
| phandle = <0x2e3>; | |
| }; | |
| qcom,leds@d000 { | |
| compatible = "qcom,leds-qpnp"; | |
| reg = <0xd000 0x100>; | |
| label = "rgb"; | |
| qcom,rgb_0 { | |
| label = "rgb"; | |
| qcom,id = <0x3>; | |
| qcom,mode = "pwm"; | |
| pwms = <0x82 0x0 0x0>; | |
| qcom,pwm-us = <0x3e8>; | |
| qcom,max-current = <0xc>; | |
| qcom,default-state = "off"; | |
| linux,name = "red"; | |
| qcom,start-idx = <0x0>; | |
| qcom,idx-len = <0x15>; | |
| qcom,duty-pcts = [00 19 32 4b 64 64 4b 32 19 00]; | |
| qcom,use-blink; | |
| linux,phandle = <0x2e4>; | |
| phandle = <0x2e4>; | |
| }; | |
| qcom,rgb_1 { | |
| label = "rgb"; | |
| qcom,id = <0x4>; | |
| qcom,mode = "pwm"; | |
| pwms = <0x83 0x0 0x0>; | |
| qcom,pwm-us = <0x3e8>; | |
| qcom,max-current = <0xc>; | |
| qcom,default-state = "off"; | |
| linux,name = "green"; | |
| linux,phandle = <0x2e5>; | |
| phandle = <0x2e5>; | |
| }; | |
| qcom,rgb_2 { | |
| label = "rgb"; | |
| qcom,id = <0x5>; | |
| qcom,mode = "pwm"; | |
| pwms = <0x84 0x0 0x0>; | |
| qcom,pwm-us = <0x3e8>; | |
| qcom,max-current = <0xc>; | |
| qcom,default-state = "off"; | |
| linux,name = "blue"; | |
| linux,phandle = <0x2e6>; | |
| phandle = <0x2e6>; | |
| }; | |
| }; | |
| qcom,leds@d800 { | |
| compatible = "qcom,qpnp-wled"; | |
| reg = <0xd800 0x100 0xd900 0x100>; | |
| reg-names = "qpnp-wled-ctrl-base", "qpnp-wled-sink-base"; | |
| interrupts = <0x3 0xd8 0x1 0x1>; | |
| interrupt-names = "ovp-irq"; | |
| linux,name = "wled"; | |
| linux,default-trigger = "bkl-trigger"; | |
| qcom,fdbk-output = "auto"; | |
| qcom,vref-uv = <0x1f20c>; | |
| qcom,switch-freq-khz = <0x320>; | |
| qcom,ovp-mv = <0x73a0>; | |
| qcom,ilim-ma = <0x3ca>; | |
| qcom,boost-duty-ns = <0x1a>; | |
| qcom,mod-freq-khz = <0x2580>; | |
| qcom,dim-mode = "hybrid"; | |
| qcom,hyb-thres = <0x271>; | |
| qcom,sync-dly-us = <0x320>; | |
| qcom,fs-curr-ua = <0x4e20>; | |
| qcom,cons-sync-write-delay-us = <0x3e8>; | |
| qcom,led-strings-list = [00 01]; | |
| qcom,loop-auto-gm-en; | |
| qcom,en-cabc; | |
| qcom,pmic-revid = <0x85>; | |
| status = "ok"; | |
| linux,phandle = <0x2e7>; | |
| phandle = <0x2e7>; | |
| }; | |
| qcom,leds@d300 { | |
| compatible = "qcom,qpnp-flash-led-v2"; | |
| reg = <0xd300 0x100>; | |
| label = "flash"; | |
| interrupts = <0x3 0xd3 0x0 0x1 0x3 0xd3 0x3 0x1 0x3 0xd3 0x4 0x1>; | |
| interrupt-names = "led-fault-irq", "all-ramp-down-done-irq", "all-ramp-up-done-irq"; | |
| qcom,hdrm-auto-mode; | |
| qcom,short-circuit-det; | |
| qcom,open-circuit-det; | |
| qcom,vph-droop-det; | |
| qcom,thermal-derate-en; | |
| qcom,thermal-derate-current = <0xc8 0x1f4 0x3e8>; | |
| qcom,isc-delay = <0xc0>; | |
| qcom,pmic-revid = <0x85>; | |
| linux,phandle = <0x2e8>; | |
| phandle = <0x2e8>; | |
| qcom,flash_0 { | |
| label = "flash"; | |
| qcom,led-name = "led:flash_0"; | |
| qcom,max-current = <0x5dc>; | |
| qcom,default-led-trigger = "flash0_trigger"; | |
| qcom,id = <0x0>; | |
| qcom,current-ma = <0x384>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| linux,phandle = <0x284>; | |
| phandle = <0x284>; | |
| }; | |
| qcom,flash_1 { | |
| label = "flash"; | |
| qcom,led-name = "led:flash_1"; | |
| qcom,max-current = <0x5dc>; | |
| qcom,default-led-trigger = "flash1_trigger"; | |
| qcom,id = <0x1>; | |
| qcom,current-ma = <0x384>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| linux,phandle = <0x285>; | |
| phandle = <0x285>; | |
| }; | |
| qcom,flash_2 { | |
| label = "flash"; | |
| qcom,led-name = "led:flash_2"; | |
| qcom,max-current = <0x64>; | |
| qcom,default-led-trigger = "flash2_trigger"; | |
| qcom,id = <0x2>; | |
| qcom,current-ma = <0x5a>; | |
| qcom,duration-ms = <0x500>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| linux,phandle = <0x2e9>; | |
| phandle = <0x2e9>; | |
| }; | |
| qcom,torch_0 { | |
| label = "torch"; | |
| qcom,led-name = "led:torch_0"; | |
| qcom,max-current = <0x3e8>; | |
| qcom,default-led-trigger = "torch0_trigger"; | |
| qcom,id = <0x0>; | |
| qcom,current-ma = <0x64>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| linux,phandle = <0x286>; | |
| phandle = <0x286>; | |
| }; | |
| qcom,torch_1 { | |
| label = "torch"; | |
| qcom,led-name = "led:torch_1"; | |
| qcom,max-current = <0x3e8>; | |
| qcom,default-led-trigger = "torch1_trigger"; | |
| qcom,id = <0x1>; | |
| qcom,current-ma = <0x64>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| linux,phandle = <0x287>; | |
| phandle = <0x287>; | |
| }; | |
| qcom,torch_2 { | |
| label = "torch"; | |
| qcom,led-name = "led:torch_2"; | |
| qcom,max-current = <0x96>; | |
| qcom,default-led-trigger = "torch2_trigger"; | |
| qcom,id = <0x2>; | |
| qcom,current-ma = <0x5a>; | |
| qcom,ires-ua = <0x30d4>; | |
| qcom,hdrm-voltage-mv = <0x145>; | |
| qcom,hdrm-vol-hi-lo-win-mv = <0x64>; | |
| linux,phandle = <0x2ea>; | |
| phandle = <0x2ea>; | |
| }; | |
| qcom,flashlight_0 { | |
| label = "flashlight"; | |
| qcom,led-name = "flashlight"; | |
| qcom,torch-name = "led:torch_0", "led:torch_1"; | |
| qcom,switch-name = "led:switch_0"; | |
| qcom,id = <0x0>; | |
| }; | |
| qcom,led_switch_0 { | |
| label = "switch"; | |
| qcom,led-name = "led:switch_0"; | |
| qcom,led-mask = <0x3>; | |
| qcom,default-led-trigger = "switch0_trigger"; | |
| linux,phandle = <0x288>; | |
| phandle = <0x288>; | |
| }; | |
| qcom,led_switch_1 { | |
| label = "switch"; | |
| qcom,led-name = "led:switch_1"; | |
| qcom,led-mask = <0x4>; | |
| qcom,default-led-trigger = "switch1_trigger"; | |
| linux,phandle = <0x2eb>; | |
| phandle = <0x2eb>; | |
| }; | |
| }; | |
| qpnp-lcdb@ec00 { | |
| compatible = "qcom,qpnp-lcdb-regulator"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| reg = <0xec00 0x100>; | |
| interrupts = <0x3 0xec 0x1 0x1>; | |
| interrupt-names = "sc-irq"; | |
| qcom,pmic-revid = <0x85>; | |
| linux,phandle = <0x2ec>; | |
| phandle = <0x2ec>; | |
| ldo { | |
| label = "ldo"; | |
| regulator-name = "lcdb_ldo"; | |
| qcom,ldo-ilim-ma = <0x104>; | |
| regulator-min-microvolt = <0x3d0900>; | |
| regulator-max-microvolt = <0x5b8d80>; | |
| linux,phandle = <0x273>; | |
| phandle = <0x273>; | |
| }; | |
| ncp { | |
| label = "ncp"; | |
| regulator-name = "lcdb_ncp"; | |
| qcom,ncp-ilim-ma = <0x104>; | |
| regulator-min-microvolt = <0x3d0900>; | |
| regulator-max-microvolt = <0x5b8d80>; | |
| linux,phandle = <0x274>; | |
| phandle = <0x274>; | |
| }; | |
| }; | |
| qpnp-oledb@e000 { | |
| compatible = "qcom,qpnp-oledb-regulator"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| qcom,pmic-revid = <0x85>; | |
| reg = <0xe000 0x100>; | |
| qcom,pbs-client = <0x86>; | |
| label = "oledb"; | |
| regulator-name = "regulator-oledb"; | |
| regulator-min-microvolt = <0x4c4b40>; | |
| regulator-max-microvolt = <0x7b98a0>; | |
| qcom,swire-control; | |
| qcom,ext-pin-control; | |
| status = "disabled"; | |
| linux,phandle = <0x2ed>; | |
| phandle = <0x2ed>; | |
| }; | |
| qpnp-labibb-regulator { | |
| compatible = "qcom,qpnp-labibb-regulator"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| qcom,pmic-revid = <0x85>; | |
| qcom,swire-control; | |
| status = "disabled"; | |
| linux,phandle = <0x2ee>; | |
| phandle = <0x2ee>; | |
| qcom,ibb@dc00 { | |
| reg = <0xdc00 0x100>; | |
| reg-names = "ibb_reg"; | |
| regulator-name = "ibb_reg"; | |
| regulator-min-microvolt = <0x3d0900>; | |
| regulator-max-microvolt = <0x602160>; | |
| qcom,qpnp-ibb-min-voltage = <0x155cc0>; | |
| qcom,qpnp-ibb-step-size = <0x186a0>; | |
| qcom,qpnp-ibb-slew-rate = <0x1e8480>; | |
| qcom,qpnp-ibb-init-voltage = <0x3d0900>; | |
| qcom,qpnp-ibb-init-amoled-voltage = <0x3d0900>; | |
| linux,phandle = <0x2ef>; | |
| phandle = <0x2ef>; | |
| }; | |
| qcom,lab@de00 { | |
| reg = <0xde00 0x100>; | |
| reg-names = "lab"; | |
| regulator-name = "lab_reg"; | |
| regulator-min-microvolt = <0x4630c0>; | |
| regulator-max-microvolt = <0x5d1420>; | |
| qcom,qpnp-lab-min-voltage = <0x4630c0>; | |
| qcom,qpnp-lab-step-size = <0x186a0>; | |
| qcom,qpnp-lab-slew-rate = <0x1388>; | |
| qcom,qpnp-lab-init-voltage = <0x4630c0>; | |
| qcom,qpnp-lab-init-amoled-voltage = <0x4630c0>; | |
| qcom,notify-lab-vreg-ok-sts; | |
| linux,phandle = <0x2f0>; | |
| phandle = <0x2f0>; | |
| }; | |
| }; | |
| analog-codec@f000 { | |
| status = "okay"; | |
| compatible = "qcom,pmic-analog-codec"; | |
| reg = <0xf000 0x200>; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| interrupt-parent = <0x87>; | |
| interrupts = <0x3 0xf0 0x0 0x0 0x3 0xf0 0x1 0x0 0x3 0xf0 0x2 0x0 0x3 0xf0 0x3 0x0 0x3 0xf0 0x4 0x0 0x3 0xf0 0x5 0x0 0x3 0xf0 0x6 0x0 0x3 0xf0 0x7 0x0 0x3 0xf1 0x0 0x0 0x3 0xf1 0x1 0x0 0x3 0xf1 0x2 0x0 0x3 0xf1 0x3 0x0 0x3 0xf1 0x4 0x0 0x3 0xf1 0x5 0x0>; | |
| interrupt-names = "spk_cnp_int", "spk_clip_int", "spk_ocp_int", "ins_rem_det1", "but_rel_det", "but_press_det", "ins_rem_det", "mbhc_int", "ear_ocp_int", "hphr_ocp_int", "hphl_ocp_det", "ear_cnp_int", "hphr_cnp_int", "hphl_cnp_int"; | |
| cdc-vdda-cp-supply = <0x88>; | |
| qcom,cdc-vdda-cp-voltage = <0x1cfde0 0x1f47d0>; | |
| qcom,cdc-vdda-cp-current = <0xc350>; | |
| cdc-vdd-pa-supply = <0x88>; | |
| qcom,cdc-vdd-pa-voltage = <0x1f20c0 0x1f20c0>; | |
| qcom,cdc-vdd-pa-current = <0x3f7a0>; | |
| cdc-vdd-mic-bias-supply = <0x7d>; | |
| qcom,cdc-vdd-mic-bias-voltage = <0x2f1e80 0x2f1e80>; | |
| qcom,cdc-vdd-mic-bias-current = <0x1388>; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| qcom,cdc-static-supplies = "cdc-vdda-cp", "cdc-vdd-pa"; | |
| qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; | |
| linux,phandle = <0x246>; | |
| phandle = <0x246>; | |
| msm-dig-codec { | |
| compatible = "qcom,msm-digital-codec"; | |
| reg = <0x152c0000 0x0>; | |
| linux,phandle = <0x245>; | |
| phandle = <0x245>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| cpuss_dump { | |
| compatible = "qcom,cpuss-dump"; | |
| qcom,l1_i_cache0 { | |
| qcom,dump-node = <0x89>; | |
| qcom,dump-id = <0x60>; | |
| }; | |
| qcom,l1_i_cache1 { | |
| qcom,dump-node = <0x8a>; | |
| qcom,dump-id = <0x61>; | |
| }; | |
| qcom,l1_i_cache2 { | |
| qcom,dump-node = <0x8b>; | |
| qcom,dump-id = <0x62>; | |
| }; | |
| qcom,l1_i_cache3 { | |
| qcom,dump-node = <0x8c>; | |
| qcom,dump-id = <0x63>; | |
| }; | |
| qcom,l1_i_cache100 { | |
| qcom,dump-node = <0x8d>; | |
| qcom,dump-id = <0x64>; | |
| }; | |
| qcom,l1_i_cache101 { | |
| qcom,dump-node = <0x8e>; | |
| qcom,dump-id = <0x65>; | |
| }; | |
| qcom,l1_i_cache102 { | |
| qcom,dump-node = <0x8f>; | |
| qcom,dump-id = <0x66>; | |
| }; | |
| qcom,l1_i_cache103 { | |
| qcom,dump-node = <0x90>; | |
| qcom,dump-id = <0x67>; | |
| }; | |
| qcom,l1_d_cache0 { | |
| qcom,dump-node = <0x91>; | |
| qcom,dump-id = <0x80>; | |
| }; | |
| qcom,l1_d_cache1 { | |
| qcom,dump-node = <0x92>; | |
| qcom,dump-id = <0x81>; | |
| }; | |
| qcom,l1_d_cache2 { | |
| qcom,dump-node = <0x93>; | |
| qcom,dump-id = <0x82>; | |
| }; | |
| qcom,l1_d_cache3 { | |
| qcom,dump-node = <0x94>; | |
| qcom,dump-id = <0x83>; | |
| }; | |
| qcom,l1_d_cache100 { | |
| qcom,dump-node = <0x95>; | |
| qcom,dump-id = <0x84>; | |
| }; | |
| qcom,l1_d_cache101 { | |
| qcom,dump-node = <0x96>; | |
| qcom,dump-id = <0x85>; | |
| }; | |
| qcom,l1_d_cache102 { | |
| qcom,dump-node = <0x97>; | |
| qcom,dump-id = <0x86>; | |
| }; | |
| qcom,l1_d_cache103 { | |
| qcom,dump-node = <0x98>; | |
| qcom,dump-id = <0x87>; | |
| }; | |
| qcom,l1_tlb_dump0 { | |
| qcom,dump-node = <0x99>; | |
| qcom,dump-id = <0x20>; | |
| }; | |
| qcom,l1_tlb_dump1 { | |
| qcom,dump-node = <0x9a>; | |
| qcom,dump-id = <0x21>; | |
| }; | |
| qcom,l1_tlb_dump2 { | |
| qcom,dump-node = <0x9b>; | |
| qcom,dump-id = <0x22>; | |
| }; | |
| qcom,l1_tlb_dump3 { | |
| qcom,dump-node = <0x9c>; | |
| qcom,dump-id = <0x23>; | |
| }; | |
| qcom,l1_tlb_dump100 { | |
| qcom,dump-node = <0x9d>; | |
| qcom,dump-id = <0x24>; | |
| }; | |
| qcom,l1_tlb_dump101 { | |
| qcom,dump-node = <0x9e>; | |
| qcom,dump-id = <0x25>; | |
| }; | |
| qcom,l1_tlb_dump102 { | |
| qcom,dump-node = <0x9f>; | |
| qcom,dump-id = <0x26>; | |
| }; | |
| qcom,l1_tlb_dump103 { | |
| qcom,dump-node = <0xa0>; | |
| qcom,dump-id = <0x27>; | |
| }; | |
| }; | |
| qcom,wdt@17817000 { | |
| compatible = "qcom,msm-watchdog"; | |
| reg = <0x17817000 0x1000>; | |
| reg-names = "wdt-base"; | |
| interrupts = <0x0 0x3 0x0 0x0 0x4 0x0>; | |
| qcom,bark-time = <0x2af8>; | |
| qcom,pet-time = <0x2710>; | |
| qcom,ipi-ping; | |
| qcom,wakeup-enable; | |
| qcom,scandump-size = <0x40000>; | |
| linux,phandle = <0x2f1>; | |
| phandle = <0x2f1>; | |
| }; | |
| qcom,sps { | |
| compatible = "qcom,msm_sps_4k"; | |
| qcom,pipe-attr-ee; | |
| }; | |
| qcom,memshare { | |
| compatible = "qcom,memshare"; | |
| qcom,client_1 { | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x200000>; | |
| qcom,client-id = <0x0>; | |
| qcom,allocate-boot-time; | |
| label = "modem"; | |
| }; | |
| qcom,client_2 { | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0x300000>; | |
| qcom,client-id = <0x2>; | |
| label = "modem"; | |
| }; | |
| qcom,client_3 { | |
| compatible = "qcom,memshare-peripheral"; | |
| qcom,peripheral-size = <0xf00000>; | |
| qcom,client-id = <0x1>; | |
| qcom,allocate-boot-time; | |
| label = "modem"; | |
| linux,phandle = <0x2f2>; | |
| phandle = <0x2f2>; | |
| }; | |
| }; | |
| tsens@10ad000 { | |
| compatible = "qcom,sdm660-tsens"; | |
| reg = <0x10ad000 0x2000 0x784240 0x1000>; | |
| reg-names = "tsens_physical", "tsens_eeprom_physical"; | |
| interrupts = <0x0 0xb8 0x0 0x0 0x1ae 0x0>; | |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; | |
| qcom,client-id = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd>; | |
| qcom,sensor-id = <0x0 0xa 0xb 0x4 0x5 0x6 0x7 0x8 0xd 0x2 0x3 0xc 0x9 0x1>; | |
| qcom,sensors = <0xe>; | |
| qcom,slope = <0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80 0xc80>; | |
| linux,phandle = <0x2f3>; | |
| phandle = <0x2f3>; | |
| }; | |
| serial@0c170000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0xc170000 0x1000>; | |
| interrupts = <0x0 0x6c 0x0>; | |
| status = "ok"; | |
| clocks = <0xa1 0x2d 0xa1 0x23>; | |
| clock-names = "core", "iface"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0xa2>; | |
| linux,phandle = <0x2f4>; | |
| phandle = <0x2f4>; | |
| }; | |
| qcom,sensor-information { | |
| compatible = "qcom,sensor-information"; | |
| qcom,sensor-information-0 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor0"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2f5>; | |
| phandle = <0x2f5>; | |
| }; | |
| qcom,sensor-information-1 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor1"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0xa3>; | |
| phandle = <0xa3>; | |
| }; | |
| qcom,sensor-information-2 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor2"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2f6>; | |
| phandle = <0x2f6>; | |
| }; | |
| qcom,sensor-information-3 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor3"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0xa4>; | |
| phandle = <0xa4>; | |
| }; | |
| qcom,sensor-information-4 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor4"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0xa5>; | |
| phandle = <0xa5>; | |
| }; | |
| qcom,sensor-information-5 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor5"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0xa6>; | |
| phandle = <0xa6>; | |
| }; | |
| qcom,sensor-information-6 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor6"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0xa7>; | |
| phandle = <0xa7>; | |
| }; | |
| qcom,sensor-information-7 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor7"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2f7>; | |
| phandle = <0x2f7>; | |
| }; | |
| qcom,sensor-information-8 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor8"; | |
| qcom,scaling-factor = <0xa>; | |
| qcom,alias-name = "gpu"; | |
| linux,phandle = <0x2f8>; | |
| phandle = <0x2f8>; | |
| }; | |
| qcom,sensor-information-9 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor9"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2f9>; | |
| phandle = <0x2f9>; | |
| }; | |
| qcom,sensor-information-10 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor10"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2fa>; | |
| phandle = <0x2fa>; | |
| }; | |
| qcom,sensor-information-11 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor11"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2fb>; | |
| phandle = <0x2fb>; | |
| }; | |
| qcom,sensor-information-12 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor12"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2fc>; | |
| phandle = <0x2fc>; | |
| }; | |
| qcom,sensor-information-13 { | |
| qcom,sensor-type = "tsens"; | |
| qcom,sensor-name = "tsens_tz_sensor13"; | |
| qcom,scaling-factor = <0xa>; | |
| linux,phandle = <0x2fd>; | |
| phandle = <0x2fd>; | |
| }; | |
| qcom,sensor-information-14 { | |
| qcom,sensor-type = "alarm"; | |
| qcom,sensor-name = "pm660_tz"; | |
| qcom,scaling-factor = <0x3e8>; | |
| linux,phandle = <0x2fe>; | |
| phandle = <0x2fe>; | |
| }; | |
| qcom,sensor-information-15 { | |
| qcom,sensor-type = "adc"; | |
| qcom,sensor-name = "msm_therm"; | |
| linux,phandle = <0x2ff>; | |
| phandle = <0x2ff>; | |
| }; | |
| qcom,sensor-information-16 { | |
| qcom,sensor-type = "adc"; | |
| qcom,sensor-name = "xo_therm"; | |
| linux,phandle = <0x300>; | |
| phandle = <0x300>; | |
| }; | |
| qcom,sensor-information-17 { | |
| qcom,sensor-type = "adc"; | |
| qcom,sensor-name = "pa_therm0"; | |
| linux,phandle = <0x301>; | |
| phandle = <0x301>; | |
| }; | |
| qcom,sensor-information-18 { | |
| qcom,sensor-type = "adc"; | |
| qcom,sensor-name = "pa_therm1"; | |
| linux,phandle = <0x302>; | |
| phandle = <0x302>; | |
| }; | |
| qcom,sensor-information-19 { | |
| qcom,sensor-type = "adc"; | |
| qcom,sensor-name = "quiet_therm"; | |
| linux,phandle = <0x303>; | |
| phandle = <0x303>; | |
| }; | |
| qcom,sensor-information-20 { | |
| qcom,sensor-type = "llm"; | |
| qcom,sensor-name = "limits_sensor-00"; | |
| linux,phandle = <0x304>; | |
| phandle = <0x304>; | |
| }; | |
| qcom,sensor-information-21 { | |
| qcom,sensor-type = "llm"; | |
| qcom,sensor-name = "limits_sensor-01"; | |
| linux,phandle = <0x305>; | |
| phandle = <0x305>; | |
| }; | |
| qcom,sensor-information-22 { | |
| qcom,sensor-type = "adc"; | |
| qcom,sensor-name = "backlight_therm"; | |
| linux,phandle = <0x306>; | |
| phandle = <0x306>; | |
| }; | |
| }; | |
| qcom,limit_info-0 { | |
| qcom,temperature-sensor = <0xa3>; | |
| qcom,hotplug-mitigation-enable; | |
| linux,phandle = <0x2>; | |
| phandle = <0x2>; | |
| }; | |
| qcom,limit_info-1 { | |
| qcom,temperature-sensor = <0xa4>; | |
| qcom,hotplug-mitigation-enable; | |
| linux,phandle = <0x9>; | |
| phandle = <0x9>; | |
| }; | |
| qcom,limit_info-2 { | |
| qcom,temperature-sensor = <0xa5>; | |
| qcom,hotplug-mitigation-enable; | |
| linux,phandle = <0xd>; | |
| phandle = <0xd>; | |
| }; | |
| qcom,limit_info-3 { | |
| qcom,temperature-sensor = <0xa6>; | |
| qcom,hotplug-mitigation-enable; | |
| linux,phandle = <0xf>; | |
| phandle = <0xf>; | |
| }; | |
| qcom,limit_info-4 { | |
| qcom,temperature-sensor = <0xa7>; | |
| qcom,hotplug-mitigation-enable; | |
| linux,phandle = <0x11>; | |
| phandle = <0x11>; | |
| }; | |
| qcom,msm-thermal { | |
| compatible = "qcom,msm-thermal"; | |
| qcom,sensor-id = <0x1>; | |
| qcom,poll-ms = <0x64>; | |
| qcom,therm-reset-temp = <0x73>; | |
| qcom,core-limit-temp = <0x46>; | |
| qcom,core-temp-hysteresis = <0xa>; | |
| qcom,hotplug-temp = <0x69>; | |
| qcom,hotplug-temp-hysteresis = <0x14>; | |
| qcom,online-hotplug-core; | |
| qcom,synchronous-cluster-id = <0x0 0x1>; | |
| qcom,synchronous-cluster-map = <0x0 0x4 0x13 0x14 0x15 0x16 0x1 0x4 0x17 0x18 0x19 0x1a>; | |
| clock-names = "osm"; | |
| clocks = <0xa8 0x1>; | |
| qcom,cxip-lm-enable = <0x1>; | |
| qcom,vdd-restriction-temp = <0x5>; | |
| qcom,vdd-restriction-temp-hysteresis = <0xa>; | |
| vdd-dig-supply = <0xa9>; | |
| vdd-gfx-supply = <0xaa>; | |
| qcom,vdd-dig-rstr { | |
| qcom,vdd-rstr-reg = "vdd-dig"; | |
| qcom,levels = <0x100 0x180 0x180>; | |
| qcom,min-level = <0x0>; | |
| }; | |
| qcom,vdd-gfx-rstr { | |
| qcom,vdd-rstr-reg = "vdd-gfx"; | |
| qcom,levels = <0x5 0x6 0x6>; | |
| qcom,min-level = <0x1>; | |
| }; | |
| qcom,vdd-apps-rstr { | |
| qcom,vdd-rstr-reg = "vdd-apps"; | |
| qcom,levels = <0x130b00>; | |
| qcom,freq-req; | |
| linux,phandle = <0x307>; | |
| phandle = <0x307>; | |
| }; | |
| }; | |
| cx_ipeak@1fe5040 { | |
| compatible = "qcom,cx-ipeak-sdm660"; | |
| reg = <0x1fe5040 0x28>; | |
| linux,phandle = <0x16d>; | |
| phandle = <0x16d>; | |
| }; | |
| qcom,bcl { | |
| compatible = "qcom,bcl"; | |
| qcom,bcl-enable; | |
| qcom,bcl-framework-interface; | |
| qcom,bcl-hotplug-list = <0x19 0x1a>; | |
| qcom,bcl-soc-hotplug-list = <0x18 0x1a>; | |
| qcom,ibat-monitor { | |
| qcom,low-threshold-uamp = <0x33e140>; | |
| qcom,high-threshold-uamp = <0x401640>; | |
| qcom,vph-high-threshold-uv = <0x3567e0>; | |
| qcom,vph-low-threshold-uv = <0x325aa0>; | |
| qcom,soc-low-threshold = <0xa>; | |
| }; | |
| }; | |
| qcom,lmh { | |
| compatible = "qcom,lmh_v1"; | |
| interrupts = <0x0 0x86 0x4>; | |
| }; | |
| qcom,msm-core@780000 { | |
| compatible = "qcom,apss-core-ea"; | |
| reg = <0x780000 0x1000>; | |
| qcom,low-hyst-temp = <0x64>; | |
| qcom,high-hyst-temp = <0x64>; | |
| ea0 { | |
| sensor = <0xa3>; | |
| linux,phandle = <0x4>; | |
| phandle = <0x4>; | |
| }; | |
| ea1 { | |
| sensor = <0xa3>; | |
| linux,phandle = <0x6>; | |
| phandle = <0x6>; | |
| }; | |
| ea2 { | |
| sensor = <0xa3>; | |
| linux,phandle = <0x7>; | |
| phandle = <0x7>; | |
| }; | |
| ea3 { | |
| sensor = <0xa3>; | |
| linux,phandle = <0x8>; | |
| phandle = <0x8>; | |
| }; | |
| ea4 { | |
| sensor = <0xa4>; | |
| linux,phandle = <0xb>; | |
| phandle = <0xb>; | |
| }; | |
| ea5 { | |
| sensor = <0xa5>; | |
| linux,phandle = <0xe>; | |
| phandle = <0xe>; | |
| }; | |
| ea6 { | |
| sensor = <0xa6>; | |
| linux,phandle = <0x10>; | |
| phandle = <0x10>; | |
| }; | |
| ea7 { | |
| sensor = <0xa7>; | |
| linux,phandle = <0x12>; | |
| phandle = <0x12>; | |
| }; | |
| }; | |
| serial@0c1b0000 { | |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| reg = <0xc1b0000 0x1000>; | |
| interrupts = <0x0 0x72 0x0>; | |
| status = "disabled"; | |
| clocks = <0xa1 0x38 0xa1 0x2e>; | |
| clock-names = "core", "iface"; | |
| linux,phandle = <0x308>; | |
| phandle = <0x308>; | |
| }; | |
| slim@151c0000 { | |
| cell-index = <0x1>; | |
| compatible = "qcom,slim-ngd"; | |
| reg = <0x151c0000 0x2c000 0x15184000 0x2a000>; | |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; | |
| interrupts = <0x0 0xa3 0x0 0x0 0xa4 0x0>; | |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; | |
| qcom,apps-ch-pipes = <0x7e0000>; | |
| qcom,ea-pc = <0x260>; | |
| status = "disabled"; | |
| linux,phandle = <0x309>; | |
| phandle = <0x309>; | |
| tasha_codec { | |
| compatible = "qcom,tasha-slim-pgd"; | |
| elemental-addr = [00 01 a0 01 17 02]; | |
| interrupt-parent = <0xab>; | |
| interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>; | |
| qcom,wcd-rst-gpio-node = <0xac>; | |
| clock-names = "wcd_clk", "wcd_native_clk"; | |
| clocks = <0xad 0x0 0xad 0x3>; | |
| cdc-vdd-mic-bias-supply = <0xae>; | |
| qcom,cdc-vdd-mic-bias-voltage = <0x325aa0 0x325aa0>; | |
| qcom,cdc-vdd-mic-bias-current = <0x76c0>; | |
| qcom,cdc-static-supplies = "cdc-vdd-mic-bias"; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| qcom,cdc-slim-ifd = "tasha-slim-ifd"; | |
| qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; | |
| qcom,cdc-dmic-sample-rate = <0x493e00>; | |
| qcom,cdc-mad-dmic-rate = <0x927c0>; | |
| status = "disabled"; | |
| linux,phandle = <0x30a>; | |
| phandle = <0x30a>; | |
| msm_cdc_pinctrll { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xaf>; | |
| pinctrl-1 = <0xb0>; | |
| linux,phandle = <0xb7>; | |
| phandle = <0xb7>; | |
| }; | |
| msm_cdc_pinctrlr { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xb1>; | |
| pinctrl-1 = <0xb2>; | |
| linux,phandle = <0xb8>; | |
| phandle = <0xb8>; | |
| }; | |
| msm_cdc_pinctrl_hph_en0 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xb3>; | |
| pinctrl-1 = <0xb4>; | |
| linux,phandle = <0x1ea>; | |
| phandle = <0x1ea>; | |
| }; | |
| msm_cdc_pinctrl_hph_en1 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xb5>; | |
| pinctrl-1 = <0xb6>; | |
| linux,phandle = <0x1eb>; | |
| phandle = <0x1eb>; | |
| }; | |
| swr_master { | |
| compatible = "qcom,swr-wcd"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| wsa881x@20170211 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x20170211>; | |
| qcom,spkr-sd-n-node = <0xb7>; | |
| linux,phandle = <0x229>; | |
| phandle = <0x229>; | |
| }; | |
| wsa881x@20170212 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x20170212>; | |
| qcom,spkr-sd-n-node = <0xb8>; | |
| linux,phandle = <0x22a>; | |
| phandle = <0x22a>; | |
| }; | |
| wsa881x@21170213 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x21170213>; | |
| qcom,spkr-sd-n-node = <0xb7>; | |
| linux,phandle = <0x22b>; | |
| phandle = <0x22b>; | |
| }; | |
| wsa881x@21170214 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x21170214>; | |
| qcom,spkr-sd-n-node = <0xb8>; | |
| linux,phandle = <0x22c>; | |
| phandle = <0x22c>; | |
| }; | |
| }; | |
| }; | |
| tavil_codec { | |
| compatible = "qcom,tavil-slim-pgd"; | |
| elemental-addr = [00 01 50 02 17 02]; | |
| interrupt-parent = <0xab>; | |
| interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>; | |
| qcom,wcd-rst-gpio-node = <0xac>; | |
| clock-names = "wcd_clk"; | |
| clocks = <0xb9 0x0>; | |
| cdc-vdd-mic-bias-supply = <0xae>; | |
| qcom,cdc-vdd-mic-bias-voltage = <0x325aa0 0x325aa0>; | |
| qcom,cdc-vdd-mic-bias-current = <0x76c0>; | |
| qcom,cdc-static-supplies = "cdc-vdd-mic-bias"; | |
| qcom,cdc-micbias1-mv = <0x708>; | |
| qcom,cdc-micbias2-mv = <0x708>; | |
| qcom,cdc-micbias3-mv = <0x708>; | |
| qcom,cdc-micbias4-mv = <0x708>; | |
| qcom,cdc-mclk-clk-rate = <0x927c00>; | |
| qcom,cdc-slim-ifd = "tavil-slim-ifd"; | |
| qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; | |
| qcom,cdc-dmic-sample-rate = <0x493e00>; | |
| qcom,cdc-mad-dmic-rate = <0x927c0>; | |
| qcom,wdsp-cmpnt-dev-name = "tavil_codec"; | |
| status = "disabled"; | |
| linux,phandle = <0x1e6>; | |
| phandle = <0x1e6>; | |
| wcd_pinctrl@5 { | |
| compatible = "qcom,wcd-pinctrl"; | |
| qcom,num-gpios = <0x5>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| linux,phandle = <0x30b>; | |
| phandle = <0x30b>; | |
| us_euro_sw_wcd_active { | |
| linux,phandle = <0xbe>; | |
| phandle = <0xbe>; | |
| mux { | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| output-high; | |
| }; | |
| }; | |
| us_euro_sw_wcd_sleep { | |
| linux,phandle = <0xbf>; | |
| phandle = <0xbf>; | |
| mux { | |
| pins = "gpio1"; | |
| }; | |
| config { | |
| pins = "gpio1"; | |
| output-low; | |
| }; | |
| }; | |
| spkr_1_wcd_en_active { | |
| linux,phandle = <0xba>; | |
| phandle = <0xba>; | |
| mux { | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| output-high; | |
| }; | |
| }; | |
| spkr_1_wcd_en_sleep { | |
| linux,phandle = <0xbb>; | |
| phandle = <0xbb>; | |
| mux { | |
| pins = "gpio2"; | |
| }; | |
| config { | |
| pins = "gpio2"; | |
| input-enable; | |
| }; | |
| }; | |
| spkr_2_sd_n_active { | |
| linux,phandle = <0xbc>; | |
| phandle = <0xbc>; | |
| mux { | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| output-high; | |
| }; | |
| }; | |
| spkr_2_sd_n_sleep { | |
| linux,phandle = <0xbd>; | |
| phandle = <0xbd>; | |
| mux { | |
| pins = "gpio3"; | |
| }; | |
| config { | |
| pins = "gpio3"; | |
| input-enable; | |
| }; | |
| }; | |
| hph_en0_wcd_active { | |
| linux,phandle = <0xc0>; | |
| phandle = <0xc0>; | |
| mux { | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| output-high; | |
| }; | |
| }; | |
| hph_en0_wcd_sleep { | |
| linux,phandle = <0xc1>; | |
| phandle = <0xc1>; | |
| mux { | |
| pins = "gpio4"; | |
| }; | |
| config { | |
| pins = "gpio4"; | |
| output-low; | |
| }; | |
| }; | |
| hph_en1_wcd_active { | |
| linux,phandle = <0xc2>; | |
| phandle = <0xc2>; | |
| mux { | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| output-high; | |
| }; | |
| }; | |
| hph_en1_wcd_sleep { | |
| linux,phandle = <0xc3>; | |
| phandle = <0xc3>; | |
| mux { | |
| pins = "gpio5"; | |
| }; | |
| config { | |
| pins = "gpio5"; | |
| output-low; | |
| }; | |
| }; | |
| }; | |
| msm_cdc_pinctrll { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xba>; | |
| pinctrl-1 = <0xbb>; | |
| linux,phandle = <0xc4>; | |
| phandle = <0xc4>; | |
| }; | |
| msm_cdc_pinctrlr { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xbc>; | |
| pinctrl-1 = <0xbd>; | |
| linux,phandle = <0xc5>; | |
| phandle = <0xc5>; | |
| }; | |
| msm_cdc_pinctrl_us_euro_sw { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xbe>; | |
| pinctrl-1 = <0xbf>; | |
| linux,phandle = <0x22d>; | |
| phandle = <0x22d>; | |
| }; | |
| msm_cdc_pinctrl_hph_en0 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xc0>; | |
| pinctrl-1 = <0xc1>; | |
| linux,phandle = <0x22e>; | |
| phandle = <0x22e>; | |
| }; | |
| msm_cdc_pinctrl_hph_en1 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0xc2>; | |
| pinctrl-1 = <0xc3>; | |
| linux,phandle = <0x22f>; | |
| phandle = <0x22f>; | |
| }; | |
| swr_master { | |
| compatible = "qcom,swr-wcd"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| wsa881x@20170211 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x20170211>; | |
| qcom,spkr-sd-n-node = <0xc4>; | |
| linux,phandle = <0x230>; | |
| phandle = <0x230>; | |
| }; | |
| wsa881x@20170212 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x20170212>; | |
| qcom,spkr-sd-n-node = <0xc5>; | |
| linux,phandle = <0x231>; | |
| phandle = <0x231>; | |
| }; | |
| wsa881x@21170213 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x21170213>; | |
| qcom,spkr-sd-n-node = <0xc4>; | |
| linux,phandle = <0x232>; | |
| phandle = <0x232>; | |
| }; | |
| wsa881x@21170214 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x21170214>; | |
| qcom,spkr-sd-n-node = <0xc5>; | |
| linux,phandle = <0x233>; | |
| phandle = <0x233>; | |
| }; | |
| }; | |
| wcd_spi { | |
| compatible = "qcom,wcd-spi-v2"; | |
| qcom,master-bus-num = <0x7>; | |
| qcom,chip-select = <0x0>; | |
| qcom,max-frequency = <0x16e3600>; | |
| qcom,mem-base-addr = <0x100000>; | |
| linux,phandle = <0x1e7>; | |
| phandle = <0x1e7>; | |
| }; | |
| }; | |
| msm_dai_slim { | |
| compatible = "qcom,msm-dai-slim"; | |
| elemental-addr = [ff ff ff fe 17 02]; | |
| status = "disabled"; | |
| linux,phandle = <0x30c>; | |
| phandle = <0x30c>; | |
| }; | |
| }; | |
| slim@15240000 { | |
| cell-index = <0x3>; | |
| compatible = "qcom,slim-ngd"; | |
| reg = <0x15240000 0x2c000 0x15204000 0x20000>; | |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; | |
| interrupts = <0x0 0x123 0x0 0x0 0x124 0x0>; | |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; | |
| qcom,apps-ch-pipes = <0x1800>; | |
| linux,phandle = <0x30d>; | |
| phandle = <0x30d>; | |
| wcn3990 { | |
| compatible = "qcom,btfmslim_slave"; | |
| elemental-addr = [00 01 20 02 17 02]; | |
| qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; | |
| qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; | |
| linux,phandle = <0x30e>; | |
| phandle = <0x30e>; | |
| }; | |
| }; | |
| timer@17920000 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| compatible = "arm,armv7-timer-mem"; | |
| reg = <0x17920000 0x1000>; | |
| clock-frequency = <0x124f800>; | |
| frame@17921000 { | |
| frame-number = <0x0>; | |
| interrupts = <0x0 0x8 0x4 0x0 0x7 0x4>; | |
| reg = <0x17921000 0x1000 0x17922000 0x1000>; | |
| }; | |
| frame@17923000 { | |
| frame-number = <0x1>; | |
| interrupts = <0x0 0x9 0x4>; | |
| reg = <0x17923000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17924000 { | |
| frame-number = <0x2>; | |
| interrupts = <0x0 0xa 0x4>; | |
| reg = <0x17924000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17925000 { | |
| frame-number = <0x3>; | |
| interrupts = <0x0 0xb 0x4>; | |
| reg = <0x17925000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17926000 { | |
| frame-number = <0x4>; | |
| interrupts = <0x0 0xc 0x4>; | |
| reg = <0x17926000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17927000 { | |
| frame-number = <0x5>; | |
| interrupts = <0x0 0xd 0x4>; | |
| reg = <0x17927000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| frame@17928000 { | |
| frame-number = <0x6>; | |
| interrupts = <0x0 0xe 0x4>; | |
| reg = <0x17928000 0x1000>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| arm64-cpu-erp { | |
| compatible = "arm,arm64-cpu-erp"; | |
| interrupts = <0x0 0x2b 0x4 0x0 0x2c 0x4 0x0 0x29 0x4 0x0 0x2a 0x4>; | |
| interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq"; | |
| poll-delay-ms = <0x1388>; | |
| }; | |
| qcom,rpmcc { | |
| compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x26>; | |
| phandle = <0x26>; | |
| }; | |
| clock-controller@100000 { | |
| compatible = "qcom,gcc-sdm660", "syscon"; | |
| reg = <0x100000 0x94000>; | |
| vdd_dig-supply = <0xc6>; | |
| vdd_dig_ao-supply = <0xc7>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| linux,phandle = <0xa1>; | |
| phandle = <0xa1>; | |
| }; | |
| clock-controller@c8c0000 { | |
| compatible = "qcom,mmcc-sdm660"; | |
| reg = <0xc8c0000 0x40000>; | |
| vdd_mx_mmss-supply = <0xc8>; | |
| vdd_dig_mmss-supply = <0xc6>; | |
| vdda-supply = <0xc9>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| linux,phandle = <0x74>; | |
| phandle = <0x74>; | |
| }; | |
| clock-controller@5065000 { | |
| compatible = "qcom,gpu-sdm660"; | |
| reg = <0x5065000 0x10000>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| linux,phandle = <0x15e>; | |
| phandle = <0x15e>; | |
| }; | |
| gfx@5065000 { | |
| compatible = "qcom,gpucc-sdm660"; | |
| reg = <0x5065000 0x10000>; | |
| vdd_dig_gfx-supply = <0xc6>; | |
| vdd_mx_gfx-supply = <0xc8>; | |
| vdd_gfx-supply = <0xaa>; | |
| qcom,gfxfreq-corner = <0x0 0x0 0x9896800 0x1 0xfdad680 0x2 0x160dc080 0x3 0x1bb75640 0x4 0x230c2b00 0x5 0x26906fc0 0x6 0x29b92700 0x7 0x2cb41780 0x7>; | |
| #clock-cells = <0x1>; | |
| #reset-cells = <0x1>; | |
| linux,phandle = <0x169>; | |
| phandle = <0x169>; | |
| }; | |
| syscon@1791101c { | |
| compatible = "syscon"; | |
| reg = <0x1791101c 0x4>; | |
| linux,phandle = <0xca>; | |
| phandle = <0xca>; | |
| }; | |
| syscon@05065120 { | |
| compatible = "syscon"; | |
| reg = <0x5065120 0x4>; | |
| linux,phandle = <0xcc>; | |
| phandle = <0xcc>; | |
| }; | |
| syscon@c8c0900 { | |
| compatible = "syscon"; | |
| reg = <0xc8c0900 0x4>; | |
| linux,phandle = <0xcb>; | |
| phandle = <0xcb>; | |
| }; | |
| qcom,cc-debug@62000 { | |
| compatible = "qcom,gcc-debug-sdm660"; | |
| reg = <0x62000 0x4>; | |
| reg-names = "dbg_offset"; | |
| clocks = <0x26 0x0>; | |
| clock-names = "xo_clk_src"; | |
| qcom,cc-count = <0x4>; | |
| qcom,gcc = <0xa1>; | |
| qcom,cpu = <0xca>; | |
| qcom,mmss = <0xcb>; | |
| qcom,gpu = <0xcc>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0x30f>; | |
| phandle = <0x30f>; | |
| }; | |
| qcom,cpubw { | |
| compatible = "qcom,devbw"; | |
| governor = "performance"; | |
| qcom,src-dst-ports = <0x1 0x200>; | |
| qcom,active-only; | |
| qcom,bw-tbl = <0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x142b 0x172b 0x1ae1>; | |
| linux,phandle = <0xcd>; | |
| phandle = <0xcd>; | |
| }; | |
| qcom,cpu-bwmon { | |
| compatible = "qcom,bimc-bwmon4"; | |
| reg = <0x1008000 0x300 0x1001000 0x200>; | |
| reg-names = "base", "global_base"; | |
| interrupts = <0x0 0xb7 0x4>; | |
| qcom,mport = <0x0>; | |
| qcom,hw-timer-hz = <0x124f800>; | |
| qcom,target-dev = <0xcd>; | |
| linux,phandle = <0x310>; | |
| phandle = <0x310>; | |
| }; | |
| qcom,mincpubw { | |
| compatible = "qcom,devbw"; | |
| governor = "powersave"; | |
| qcom,src-dst-ports = <0x1 0x200>; | |
| qcom,active-only; | |
| qcom,bw-tbl = <0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x142b 0x172b 0x1ae1>; | |
| linux,phandle = <0xd0>; | |
| phandle = <0xd0>; | |
| }; | |
| qcom,memlat-cpu0 { | |
| compatible = "qcom,devbw"; | |
| governor = "powersave"; | |
| qcom,src-dst-ports = <0x1 0x200>; | |
| qcom,active-only; | |
| qcom,bw-tbl = <0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x142b 0x172b 0x1ae1>; | |
| linux,phandle = <0xce>; | |
| phandle = <0xce>; | |
| }; | |
| qcom,memlat-cpu4 { | |
| compatible = "qcom,devbw"; | |
| governor = "powersave"; | |
| qcom,src-dst-ports = <0x1 0x200>; | |
| qcom,active-only; | |
| qcom,bw-tbl = <0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x142b 0x172b 0x1ae1>; | |
| linux,phandle = <0xcf>; | |
| phandle = <0xcf>; | |
| }; | |
| qcom,arm-memlat-mon-0 { | |
| compatible = "qcom,arm-memlat-mon"; | |
| qcom,cpulist = <0x13 0x14 0x15 0x16>; | |
| qcom,target-dev = <0xce>; | |
| qcom,core-dev-table = <0xdc500 0x2fa 0x156300 0x826 0x1cb600 0xf27>; | |
| linux,phandle = <0x311>; | |
| phandle = <0x311>; | |
| }; | |
| qcom,arm-memlat-mon-4 { | |
| compatible = "qcom,arm-memlat-mon"; | |
| qcom,cpulist = <0x17 0x18 0x19 0x1a>; | |
| qcom,target-dev = <0xcf>; | |
| qcom,core-dev-table = <0x10fe00 0x2fa 0x156300 0xf27 0x20d000 0x172b 0x258000 0x1ae1>; | |
| linux,phandle = <0x312>; | |
| phandle = <0x312>; | |
| }; | |
| devfreq-cpufreq { | |
| linux,phandle = <0x313>; | |
| phandle = <0x313>; | |
| mincpubw-cpufreq { | |
| target-dev = <0xd0>; | |
| cpu-to-dev-map-0 = <0x9ab00 0x2fa 0x156300 0x623 0x1cb600 0xb71>; | |
| cpu-to-dev-map-4 = <0x10fe00 0x2fa 0x156300 0x826 0x1aa900 0xb71 0x20d000 0xf27 0x258000 0x1ae1>; | |
| }; | |
| }; | |
| qcom,clk-cpu-660@179c0000 { | |
| compatible = "qcom,clk-cpu-osm"; | |
| reg = <0x179c0000 0x4000 0x17916000 0x1000 0x17816000 0x1000 0x179d1000 0x1000 0x784130 0x8 0x784130 0x8>; | |
| reg-names = "osm", "pwrcl_pll", "perfcl_pll", "apcs_common", "pwrcl_efuse", "perfcl_efuse"; | |
| vdd-pwrcl-supply = <0xd1>; | |
| vdd-perfcl-supply = <0xd2>; | |
| interrupts = <0x0 0x23 0x1 0x0 0x24 0x1>; | |
| interrupt-names = "pwrcl-irq", "perfcl-irq"; | |
| qcom,pwrcl-speedbin0-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x25c3f800 0x5040021 0x3200020 0x1 0x2 0x35c98800 0x404002f 0x4260026 0x1 0x3 0x42603000 0x404003a 0x52e002e 0x2 0x4 0x538ab800 0x4040049 0x73a003a 0x2 0x5 0x5b8d8000 0x4040050 0x8400040 0x2 0x6 0x68242800 0x404005b 0x9480048 0x2 0x7 0x6ddd0000 0x4040060 0x94c004c 0x3 0x8>; | |
| qcom,pwrcl-speedbin1-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x25c3f800 0x5040021 0x3200020 0x1 0x2 0x35c98800 0x404002f 0x4260026 0x1 0x3 0x42603000 0x404003a 0x52e002e 0x2 0x4 0x538ab800 0x4040049 0x73a003a 0x2 0x5 0x5b8d8000 0x4040050 0x8400040 0x2 0x6 0x68242800 0x404005b 0x9480048 0x2 0x7 0x6ddd0000 0x4040060 0x94c004c 0x3 0x8>; | |
| qcom,pwrcl-speedbin3-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x25c3f800 0x5040021 0x3200020 0x1 0x2 0x35c98800 0x404002f 0x4260026 0x1 0x3 0x42603000 0x404003a 0x52e002e 0x2 0x4 0x538ab800 0x4040049 0x73a003a 0x2 0x5 0x5b8d8000 0x4040050 0x8400040 0x2 0x6 0x60216000 0x4040054 0x9430043 0x2 0x7>; | |
| qcom,pwrcl-speedbin4-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x25c3f800 0x5040021 0x3200020 0x1 0x2 0x35c98800 0x404002f 0x4260026 0x1 0x3 0x42603000 0x404003a 0x52e002e 0x2 0x4 0x538ab800 0x4040049 0x73a003a 0x2 0x5 0x5b8d8000 0x4040050 0x8400040 0x2 0x6 0x68242800 0x404005b 0x9480048 0x2 0x7 0x6ddd0000 0x4040060 0x94c004c 0x3 0x8>; | |
| qcom,perfcl-speedbin0-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x42603000 0x404003a 0x52e002e 0x1 0x2 0x538ab800 0x4040049 0x73a003a 0x2 0x3 0x68242800 0x404005b 0x9480048 0x2 0x4 0x74bad000 0x4040066 0xa510051 0x2 0x5 0x802c8000 0x4040070 0xb590059 0x2 0x6 0x927c0000 0x4040080 0xc660066 0x3 0x7>; | |
| qcom,perfcl-speedbin1-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x42603000 0x404003a 0x52e002e 0x1 0x2 0x538ab800 0x4040049 0x73a003a 0x2 0x3 0x68242800 0x404005b 0x9480048 0x2 0x4 0x74bad000 0x4040066 0xa510051 0x2 0x5 0x802c8000 0x4040070 0xb590059 0x2 0x6 0x839b6800 0x4040073 0xb5c005c 0x3 0x7>; | |
| qcom,perfcl-speedbin3-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x42603000 0x404003a 0x52e002e 0x1 0x2 0x538ab800 0x4040049 0x73a003a 0x2 0x3 0x68242800 0x404005b 0x9480048 0x2 0x4 0x6b931000 0x404005e 0x94b004b 0x2 0x5>; | |
| qcom,perfcl-speedbin4-v0 = <0x11e1a300 0x4000f 0x1200020 0x1 0x1 0x42603000 0x404003a 0x52e002e 0x1 0x2 0x538ab800 0x4040049 0x73a003a 0x2 0x3 0x68242800 0x404005b 0x9480048 0x2 0x4 0x74bad000 0x4040066 0xa510051 0x2 0x5>; | |
| qcom,up-timer = <0x3e8 0x3e8>; | |
| qcom,down-timer = <0x3e8 0x3e8>; | |
| qcom,set-ret-inactive; | |
| qcom,enable-llm-freq-vote; | |
| qcom,llm-freq-up-timer = <0x4fffb 0x4fffb>; | |
| qcom,llm-freq-down-timer = <0x4fffb 0x4fffb>; | |
| qcom,enable-llm-volt-vote; | |
| qcom,llm-volt-up-timer = <0x4fffb 0x4fffb>; | |
| qcom,llm-volt-down-timer = <0x4fffb 0x4fffb>; | |
| qcom,cc-reads = <0xa>; | |
| qcom,cc-delay = <0x5>; | |
| qcom,cc-factor = <0x64>; | |
| qcom,osm-clk-rate = <0xbebc200>; | |
| qcom,xo-clk-rate = <0x124f800>; | |
| qcom,l-val-base = <0x17916004 0x17816004>; | |
| qcom,apcs-itm-present = <0x179d143c 0x179d143c>; | |
| qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; | |
| qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; | |
| qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; | |
| qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; | |
| qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; | |
| qcom,apm-threshold-voltage = <0xd4e40>; | |
| qcom,boost-fsm-en; | |
| qcom,safe-fsm-en; | |
| qcom,ps-fsm-en; | |
| qcom,droop-fsm-en; | |
| qcom,wfx-fsm-en; | |
| qcom,pc-fsm-en; | |
| clock-names = "aux_clk", "xo_a"; | |
| clocks = <0xa1 0xa1 0x26 0x1>; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0xa8>; | |
| phandle = <0xa8>; | |
| qcom,limits-dcvs@0 { | |
| compatible = "qcom,msm-hw-limits"; | |
| interrupts = <0x0 0x25 0x4>; | |
| linux,phandle = <0x3>; | |
| phandle = <0x3>; | |
| }; | |
| qcom,limits-dcvs@1 { | |
| compatible = "qcom,msm-hw-limits"; | |
| interrupts = <0x0 0x26 0x4>; | |
| linux,phandle = <0xa>; | |
| phandle = <0xa>; | |
| }; | |
| }; | |
| qcom,msm-cpufreq { | |
| compatible = "qcom,msm-cpufreq"; | |
| clock-names = "cpu0_clk", "cpu4_clk"; | |
| clocks = <0xa8 0x1 0xa8 0x2>; | |
| qcom,governor-per-policy; | |
| qcom,cpufreq-table-0 = <0x9ab00 0xdc500 0x10fe00 0x156300 0x177000 0x189c00 0x1aa900 0x1c2000>; | |
| qcom,cpufreq-table-4 = <0x10fe00 0x156300 0x1aa900 0x1b8a00 0x1de200 0x20d000 0x21b100 0x258000>; | |
| linux,phandle = <0x314>; | |
| phandle = <0x314>; | |
| }; | |
| sdhci@c0c4000 { | |
| compatible = "qcom,sdhci-msm-v5"; | |
| reg = <0xc0c4000 0x1000 0xc0c5000 0x1000>; | |
| reg-names = "hc_mem", "cmdq_mem"; | |
| interrupts = <0x0 0x6e 0x0 0x0 0x70 0x0>; | |
| interrupt-names = "hc_irq", "pwr_irq"; | |
| qcom,bus-width = <0x8>; | |
| qcom,large-address-bus; | |
| sdhc-msm-crypto = <0xd3>; | |
| qcom,devfreq,freq-table = <0x2faf080 0xbebc200>; | |
| qcom,msm-bus,name = "sdhc1"; | |
| qcom,msm-bus,num-cases = <0x9>; | |
| qcom,msm-bus,num-paths = <0x2>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x0 0x0 0x1 0x25e 0x0 0x0 0x4e 0x200 0x416 0x640 0x1 0x25e 0x640 0x640 0x4e 0x200 0xcc3e 0x13880 0x1 0x25e 0x13880 0x13880 0x4e 0x200 0xff50 0x186a0 0x1 0x25e 0x186a0 0x186a0 0x4e 0x200 0x1fe9e 0x30d40 0x1 0x25e 0x208c8 0x208c8 0x4e 0x200 0x1fe9e 0x30d40 0x1 0x25e 0x249f0 0x249f0 0x4e 0x200 0x3fd3e 0x61a80 0x1 0x25e 0x493e0 0x493e0 0x4e 0x200 0x3fd3e 0x61a80 0x1 0x25e 0x493e0 0x493e0 0x4e 0x200 0x146cc2 0x3e8000 0x1 0x25e 0x146cc2 0x3e8000>; | |
| qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0x17d78400 0xffffffff>; | |
| clocks = <0xa1 0x5a 0xa1 0x5b 0xa1 0x5c>; | |
| clock-names = "iface_clk", "core_clk", "ice_core_clk"; | |
| qcom,ice-clk-rates = <0x11e1a300 0x47868c0>; | |
| status = "ok"; | |
| qcom,pm-qos-irq-type = "affine_irq"; | |
| qcom,pm-qos-irq-latency = <0x2b 0x206>; | |
| qcom,pm-qos-cpu-groups = <0xf 0xf0>; | |
| qcom,pm-qos-cmdq-latency-us = <0x2b 0x206 0x28 0x206>; | |
| qcom,pm-qos-legacy-latency-us = <0x2b 0x206 0x28 0x206>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xb71b000 0x16e36000>; | |
| qcom,nonremovable; | |
| qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; | |
| qcom,scaling-lower-bus-speed-mode = "DDR52"; | |
| vdd-supply = <0xd4>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| qcom,vdd-current-level = <0xc8 0x8b290>; | |
| vdd-io-supply = <0xd5>; | |
| qcom,vdd-io-always-on; | |
| qcom,vdd-io-lpm-sup; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x1b7740>; | |
| qcom,vdd-io-current-level = <0xc8 0x4f588>; | |
| pinctrl-names = "active", "sleep"; | |
| pinctrl-0 = <0xd6 0xd7 0xd8 0xd9>; | |
| pinctrl-1 = <0xda 0xdb 0xdc 0xdd>; | |
| linux,phandle = <0x315>; | |
| phandle = <0x315>; | |
| }; | |
| sdhci@c084000 { | |
| compatible = "qcom,sdhci-msm-v5"; | |
| reg = <0xc084000 0x1000>; | |
| reg-names = "hc_mem"; | |
| interrupts = <0x0 0x1 0x2>; | |
| interrupt-names = "hc_irq", "pwr_irq", "status_irq"; | |
| qcom,bus-width = <0x4>; | |
| qcom,large-address-bus; | |
| qcom,msm-bus,name = "sdhc2"; | |
| qcom,msm-bus,num-cases = <0x8>; | |
| qcom,msm-bus,num-paths = <0x2>; | |
| qcom,msm-bus,vectors-KBps = <0x51 0x200 0x0 0x0 0x1 0x260 0x0 0x0 0x51 0x200 0x416 0x640 0x1 0x260 0x640 0x640 0x51 0x200 0xcc3e 0x13880 0x1 0x260 0x13880 0x13880 0x51 0x200 0xff50 0x186a0 0x1 0x260 0x186a0 0x186a0 0x51 0x200 0x1fe9e 0x30d40 0x1 0x260 0x208c8 0x208c8 0x51 0x200 0x3fd3e 0x30d40 0x1 0x260 0x249f0 0x249f0 0x51 0x200 0x3fd3e 0x61a80 0x1 0x260 0x493e0 0x493e0 0x51 0x200 0x146cc2 0x3e8000 0x1 0x260 0x146cc2 0x3e8000>; | |
| qcom,bus-bw-vectors-bps = <0x0 0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; | |
| qcom,devfreq,freq-table = <0x2faf080 0xbebc200>; | |
| clocks = <0xa1 0x5d 0xa1 0x5e>; | |
| clock-names = "iface_clk", "core_clk"; | |
| status = "ok"; | |
| qcom,pm-qos-irq-type = "affine_irq"; | |
| qcom,pm-qos-irq-latency = <0x2b 0x206>; | |
| qcom,pm-qos-cpu-groups = <0xf 0xf0>; | |
| qcom,pm-qos-legacy-latency-us = <0x2b 0x206 0x28 0x206>; | |
| qcom,clk-rates = <0x61a80 0x1312d00 0x17d7840 0x2faf080 0x5f5e100 0xbebc200>; | |
| qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; | |
| vdd-supply = <0x4f>; | |
| qcom,vdd-voltage-level = <0x2d0370 0x2d0370>; | |
| qcom,vdd-current-level = <0x3a98 0xc3500>; | |
| vdd-io-supply = <0x50>; | |
| qcom,vdd-io-voltage-level = <0x1b7740 0x2d0370>; | |
| qcom,vdd-io-current-level = <0xc8 0x55f0>; | |
| pinctrl-names = "active", "sleep"; | |
| pinctrl-0 = <0xde 0xdf 0xe0 0xe1>; | |
| pinctrl-1 = <0xe2 0xe3 0xe4 0xe5>; | |
| #address-cells = <0x0>; | |
| interrupt-parent = <0xe6>; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0xffffffff>; | |
| interrupt-map = <0x0 0x1 0x0 0x0 0x7d 0x0 0x1 0x1 0x0 0x0 0xdd 0x0 0x2 0xe7 0x36 0x0>; | |
| cd-gpios = <0xe7 0x36 0x0>; | |
| linux,phandle = <0xe6>; | |
| phandle = <0xe6>; | |
| }; | |
| qcom,ipa@14780000 { | |
| compatible = "qcom,ipa"; | |
| reg = <0x14780000 0x4effc 0x14784000 0x26934>; | |
| reg-names = "ipa-base", "bam-base"; | |
| interrupts = <0x0 0x14d 0x0 0x0 0x1b0 0x0>; | |
| interrupt-names = "ipa-irq", "bam-irq"; | |
| qcom,ipa-hw-ver = <0x6>; | |
| qcom,ipa-hw-mode = <0x0>; | |
| qcom,wan-rx-ring-size = <0xc0>; | |
| qcom,lan-rx-ring-size = <0xc0>; | |
| clocks = <0x26 0x22 0x26 0x59>; | |
| clock-names = "core_clk", "smmu_clk"; | |
| qcom,arm-smmu; | |
| qcom,smmu-disable-htw; | |
| qcom,smmu-s1-bypass; | |
| qcom,ee = <0x0>; | |
| qcom,use-ipa-tethering-bridge; | |
| qcom,modem-cfg-emb-pipe-flt; | |
| qcom,ipa-wdi2; | |
| qcom,use-dma-zone; | |
| qcom,msm-bus,name = "ipa"; | |
| qcom,msm-bus,num-cases = <0x4>; | |
| qcom,msm-bus,num-paths = <0x2>; | |
| qcom,msm-bus,vectors-KBps = <0x5a 0x200 0x0 0x0 0x1 0x2a4 0x0 0x0 0x5a 0x200 0x13880 0x9c400 0x1 0x2a4 0x13880 0x13880 0x5a 0x200 0x324b0 0xea600 0x1 0x2a4 0x324b0 0x27100 0x5a 0x200 0x324b0 0xea600 0x1 0x2a4 0x324b0 0x27100>; | |
| qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO"; | |
| qcom,rx-polling-sleep-ms = <0x1>; | |
| qcom,ipa-polling-iteration = <0x28>; | |
| linux,phandle = <0x316>; | |
| phandle = <0x316>; | |
| ipa_smmu_ap { | |
| compatible = "qcom,ipa-smmu-ap-cb"; | |
| iommus = <0xe8 0x19c0>; | |
| qcom,iova-mapping = <0x10000000 0x40000000>; | |
| linux,phandle = <0x317>; | |
| phandle = <0x317>; | |
| }; | |
| ipa_smmu_wlan { | |
| status = "disabled"; | |
| compatible = "qcom,ipa-smmu-wlan-cb"; | |
| iommus = <0xe8 0x19c1>; | |
| linux,phandle = <0x318>; | |
| phandle = <0x318>; | |
| }; | |
| ipa_smmu_uc { | |
| compatible = "qcom,ipa-smmu-uc-cb"; | |
| iommus = <0xe8 0x19c2>; | |
| qcom,iova-mapping = <0x40000000 0x20000000>; | |
| linux,phandle = <0x319>; | |
| phandle = <0x319>; | |
| }; | |
| }; | |
| qcom,rmtfs_sharedmem@85e00000 { | |
| compatible = "qcom,sharedmem-uio"; | |
| reg = <0x85e00000 0x200000>; | |
| reg-names = "rmtfs"; | |
| qcom,client-id = <0x1>; | |
| }; | |
| qcom,rmnet-ipa { | |
| compatible = "qcom,rmnet-ipa"; | |
| qcom,rmnet-ipa-ssr; | |
| qcom,ipa-loaduC; | |
| qcom,ipa-advertise-sg-support; | |
| }; | |
| qcom,ipc-spinlock@1f40000 { | |
| compatible = "qcom,ipc-spinlock-sfpb"; | |
| reg = <0x1f40000 0x8000>; | |
| qcom,num-locks = <0x8>; | |
| }; | |
| qcom,smem@86000000 { | |
| compatible = "qcom,smem"; | |
| reg = <0x86000000 0x200000 0x17911008 0x4 0x778000 0x7000 0x1fd4000 0x8>; | |
| reg-names = "smem", "irq-reg-base", "aux-mem1", "smem_targ_info_reg"; | |
| qcom,mpu-enabled; | |
| }; | |
| qcom,msm-cdsp-loader { | |
| compatible = "qcom,cdsp-loader"; | |
| qcom,proc-img-to-load = "cdsp"; | |
| }; | |
| qcom,msm-adsprpc-mem { | |
| compatible = "qcom,msm-adsprpc-mem-region"; | |
| memory-region = <0xe9>; | |
| }; | |
| qcom,msm_fastrpc { | |
| compatible = "qcom,msm-fastrpc-adsp"; | |
| qcom,fastrpc-glink; | |
| qcom,fastrpc-vmid-heap-shared; | |
| qcom,msm_fastrpc_compute_cb1 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "adsprpc-smd"; | |
| iommus = <0xea 0x3>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb2 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "adsprpc-smd"; | |
| iommus = <0xea 0x7>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb3 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "adsprpc-smd"; | |
| iommus = <0xea 0x8>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb4 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "adsprpc-smd"; | |
| iommus = <0xea 0x9>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb5 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x3>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb6 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x4>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb7 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x5>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb8 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x6>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb9 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x7>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb10 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x8>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb11 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0x9>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb12 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0xa>; | |
| dma-coherent; | |
| }; | |
| qcom,msm_fastrpc_compute_cb13 { | |
| compatible = "qcom,msm-fastrpc-compute-cb"; | |
| label = "cdsprpc-smd"; | |
| iommus = <0xeb 0xb>; | |
| dma-coherent; | |
| }; | |
| }; | |
| dcc@10b3000 { | |
| compatible = "qcom,dcc"; | |
| reg = <0x10b3000 0x1000 0x10b4000 0x2000>; | |
| reg-names = "dcc-base", "dcc-ram-base"; | |
| clocks = <0xa1 0x3c>; | |
| clock-names = "dcc_clk"; | |
| linux,phandle = <0x31a>; | |
| phandle = <0x31a>; | |
| }; | |
| qcom,glink-smem-native-xprt-modem@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg = <0x86000000 0x200000 0x17911008 0x4>; | |
| reg-names = "smem", "irq-reg-base"; | |
| qcom,irq-mask = <0x8000>; | |
| interrupts = <0x0 0x1c4 0x1>; | |
| label = "mpss"; | |
| }; | |
| qcom,glink-smem-native-xprt-adsp@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg = <0x86000000 0x200000 0x17911008 0x4>; | |
| reg-names = "smem", "irq-reg-base"; | |
| qcom,irq-mask = <0x200>; | |
| interrupts = <0x0 0x9d 0x1>; | |
| label = "lpass"; | |
| qcom,qos-config = <0xec>; | |
| qcom,ramp-time = <0xaf>; | |
| }; | |
| qcom,glink-qos-config-adsp { | |
| compatible = "qcom,glink-qos-config"; | |
| qcom,flow-info = <0x3c 0x0 0x3c 0x0 0x3c 0x0 0x3c 0x0>; | |
| qcom,mtu-size = <0x800>; | |
| qcom,tput-stats-cycle = <0xa>; | |
| linux,phandle = <0xec>; | |
| phandle = <0xec>; | |
| }; | |
| qcom,glink-smem-native-xprt-cdsp@86000000 { | |
| compatible = "qcom,glink-smem-native-xprt"; | |
| reg = <0x86000000 0x200000 0x17911008 0x4>; | |
| reg-names = "smem", "irq-reg-base"; | |
| qcom,irq-mask = <0x20000000>; | |
| interrupts = <0x0 0x201 0x1>; | |
| label = "cdsp"; | |
| }; | |
| qcom,glink-smem-native-xprt-rpm@778000 { | |
| compatible = "qcom,glink-rpm-native-xprt"; | |
| reg = <0x778000 0x7000 0x17911008 0x4>; | |
| reg-names = "msgram", "irq-reg-base"; | |
| qcom,irq-mask = <0x1>; | |
| interrupts = <0x0 0xa8 0x1>; | |
| label = "rpm"; | |
| }; | |
| qcom,glink-ssr-modem { | |
| compatible = "qcom,glink_ssr"; | |
| label = "modem"; | |
| qcom,edge = "mpss"; | |
| qcom,notify-edges = <0xed 0xee 0xef>; | |
| qcom,xprt = "smem"; | |
| linux,phandle = <0xf0>; | |
| phandle = <0xf0>; | |
| }; | |
| qcom,glink-ssr-adsp { | |
| compatible = "qcom,glink_ssr"; | |
| label = "adsp"; | |
| qcom,edge = "lpass"; | |
| qcom,notify-edges = <0xf0 0xee 0xef>; | |
| qcom,xprt = "smem"; | |
| linux,phandle = <0xed>; | |
| phandle = <0xed>; | |
| }; | |
| qcom,glink-ssr-rpm { | |
| compatible = "qcom,glink_ssr"; | |
| label = "rpm"; | |
| qcom,edge = "rpm"; | |
| qcom,notify-edges = <0xed 0xf0 0xef>; | |
| qcom,xprt = "smem"; | |
| linux,phandle = <0xee>; | |
| phandle = <0xee>; | |
| }; | |
| qcom,glink-ssr-cdsp { | |
| compatible = "qcom,glink_ssr"; | |
| label = "cdsp"; | |
| qcom,edge = "cdsp"; | |
| qcom,notify-edges = <0xed 0xf0 0xee>; | |
| qcom,xprt = "smem"; | |
| linux,phandle = <0xef>; | |
| phandle = <0xef>; | |
| }; | |
| qcom,glink-spi-xprt-wdsp { | |
| compatible = "qcom,glink-spi-xprt"; | |
| label = "wdsp"; | |
| qcom,remote-fifo-config = <0xf1>; | |
| qcom,qos-config = <0xf2>; | |
| qcom,ramp-time = <0x10 0x20 0x30 0x40>; | |
| status = "disabled"; | |
| linux,phandle = <0x1e8>; | |
| phandle = <0x1e8>; | |
| }; | |
| qcom,glink-fifo-config-wdsp { | |
| compatible = "qcom,glink-fifo-config"; | |
| qcom,out-read-idx-reg = <0x12000>; | |
| qcom,out-write-idx-reg = <0x12004>; | |
| qcom,in-read-idx-reg = <0x1200c>; | |
| qcom,in-write-idx-reg = <0x12010>; | |
| status = "disabled"; | |
| linux,phandle = <0xf1>; | |
| phandle = <0xf1>; | |
| }; | |
| qcom,glink-qos-config-wdsp { | |
| compatible = "qcom,glink-qos-config"; | |
| qcom,flow-info = <0x80 0x0 0x70 0x1 0x60 0x2 0x50 0x3>; | |
| qcom,mtu-size = <0x800>; | |
| qcom,tput-stats-cycle = <0xa>; | |
| status = "disabled"; | |
| linux,phandle = <0xf2>; | |
| phandle = <0xf2>; | |
| }; | |
| qcom,glink_pkt { | |
| compatible = "qcom,glinkpkt"; | |
| qcom,glinkpkt-at-mdm0 { | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-ch-name = "DS"; | |
| qcom,glinkpkt-dev-name = "at_mdm0"; | |
| }; | |
| qcom,glinkpkt-loopback_cntl { | |
| qcom,glinkpkt-transport = "lloop"; | |
| qcom,glinkpkt-edge = "local"; | |
| qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; | |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; | |
| }; | |
| qcom,glinkpkt-loopback_data { | |
| qcom,glinkpkt-transport = "lloop"; | |
| qcom,glinkpkt-edge = "local"; | |
| qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; | |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback"; | |
| }; | |
| qcom,glinkpkt-apr-apps2 { | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "adsp"; | |
| qcom,glinkpkt-ch-name = "apr_apps2"; | |
| qcom,glinkpkt-dev-name = "apr_apps2"; | |
| }; | |
| qcom,glinkpkt-data40-cntl { | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; | |
| qcom,glinkpkt-dev-name = "smdcntl8"; | |
| }; | |
| qcom,glinkpkt-data1 { | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-ch-name = "DATA1"; | |
| qcom,glinkpkt-dev-name = "smd7"; | |
| }; | |
| qcom,glinkpkt-data4 { | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-ch-name = "DATA4"; | |
| qcom,glinkpkt-dev-name = "smd8"; | |
| }; | |
| qcom,glinkpkt-data11 { | |
| qcom,glinkpkt-transport = "smem"; | |
| qcom,glinkpkt-edge = "mpss"; | |
| qcom,glinkpkt-ch-name = "DATA11"; | |
| qcom,glinkpkt-dev-name = "smd11"; | |
| }; | |
| }; | |
| qcom,rpm-smd { | |
| compatible = "qcom,rpm-glink"; | |
| qcom,glink-edge = "rpm"; | |
| rpm-channel-name = "rpm_requests"; | |
| linux,phandle = <0x31b>; | |
| phandle = <0x31b>; | |
| rpm-regulator-smpa4 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x4>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s4 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_s4"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b8ac8>; | |
| regulator-max-microvolt = <0x1f20c0>; | |
| linux,phandle = <0x88>; | |
| phandle = <0x88>; | |
| }; | |
| }; | |
| rpm-regulator-smpa5 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x5>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s5 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_s5"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x12ad40>; | |
| regulator-max-microvolt = <0x149970>; | |
| linux,phandle = <0x289>; | |
| phandle = <0x289>; | |
| }; | |
| }; | |
| rpm-regulator-smpa6 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "smpa"; | |
| qcom,resource-id = <0x6>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s6 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_s6"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x7b0c0>; | |
| regulator-max-microvolt = <0xf2300>; | |
| linux,phandle = <0x31c>; | |
| phandle = <0x31c>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa1 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x1>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l1 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l1"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x118c30>; | |
| regulator-max-microvolt = <0x1312d0>; | |
| linux,phandle = <0x109>; | |
| phandle = <0x109>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa2 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x2>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l2 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l2"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0xe7ef0>; | |
| regulator-max-microvolt = <0xf6950>; | |
| linux,phandle = <0x31d>; | |
| phandle = <0x31d>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa3 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x3>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l3 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l3"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0xe7ef0>; | |
| regulator-max-microvolt = <0xf6950>; | |
| linux,phandle = <0x31e>; | |
| phandle = <0x31e>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa5 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x5>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l5 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l5"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x802c8>; | |
| regulator-max-microvolt = <0xe7ef0>; | |
| linux,phandle = <0xf5>; | |
| phandle = <0xf5>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa6 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x6>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l6 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l6"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x14e790>; | |
| linux,phandle = <0x291>; | |
| phandle = <0x291>; | |
| }; | |
| regulator-l6-pin-ctrl { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l6_pin_ctrl"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x14e790>; | |
| qcom,init-pin-ctrl-mode = <0x2>; | |
| qcom,enable-with-pin-ctrl = <0x0 0x2>; | |
| linux,phandle = <0xf7>; | |
| phandle = <0xf7>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa7 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x7>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l7 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l7"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x124f80>; | |
| linux,phandle = <0x31f>; | |
| phandle = <0x31f>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa8 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x8>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l8 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l8"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1ab3f0>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| linux,phandle = <0xd5>; | |
| phandle = <0xd5>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa9 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x9>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l9 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l9"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1ab3f0>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| linux,phandle = <0x290>; | |
| phandle = <0x290>; | |
| }; | |
| regulator-l9-pin-ctrl { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l9_pin_ctrl"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x1ab3f0>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| qcom,init-pin-ctrl-mode = <0x2>; | |
| qcom,enable-with-pin-ctrl = <0x0 0x2>; | |
| linux,phandle = <0xf6>; | |
| phandle = <0xf6>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa10 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0xa>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l10 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l10"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| proxy-supply = <0xc9>; | |
| qcom,proxy-consumer-enable; | |
| qcom,proxy-consumer-current = <0x36b0>; | |
| regulator-min-microvolt = <0x1b2920>; | |
| regulator-max-microvolt = <0x1dc130>; | |
| linux,phandle = <0xc9>; | |
| phandle = <0xc9>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa11 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0xb>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l11 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l11"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b2920>; | |
| regulator-max-microvolt = <0x1dc130>; | |
| linux,phandle = <0x17e>; | |
| phandle = <0x17e>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa12 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0xc>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l12 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l12"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b2920>; | |
| regulator-max-microvolt = <0x1dc130>; | |
| linux,phandle = <0x320>; | |
| phandle = <0x320>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa13 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0xd>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l13 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l13"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1b2920>; | |
| regulator-max-microvolt = <0x1dc130>; | |
| linux,phandle = <0x28b>; | |
| phandle = <0x28b>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa14 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0xe>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l14 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l14"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1a17b0>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| linux,phandle = <0x321>; | |
| phandle = <0x321>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa15 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0xf>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l15 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l15"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x192d50>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| linux,phandle = <0x322>; | |
| phandle = <0x322>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa17 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x11>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l17 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l17"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x192d50>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| linux,phandle = <0x323>; | |
| phandle = <0x323>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa19 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldoa"; | |
| qcom,resource-id = <0x13>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l19 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l19"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x30d400>; | |
| regulator-max-microvolt = <0x33e140>; | |
| linux,phandle = <0x292>; | |
| phandle = <0x292>; | |
| }; | |
| regulator-l19-pin-ctrl { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660_l19_pin_ctrl"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x30d400>; | |
| regulator-max-microvolt = <0x33e140>; | |
| qcom,init-pin-ctrl-mode = <0x2>; | |
| qcom,enable-with-pin-ctrl = <0x0 0x2>; | |
| linux,phandle = <0xf8>; | |
| phandle = <0xf8>; | |
| }; | |
| }; | |
| rpm-regulator-smpb1 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "smpb"; | |
| qcom,resource-id = <0x1>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s1 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s1"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x112a88>; | |
| regulator-max-microvolt = <0x112a88>; | |
| linux,phandle = <0x324>; | |
| phandle = <0x324>; | |
| }; | |
| }; | |
| rpm-regulator-smpb2 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "smpb"; | |
| qcom,resource-id = <0x2>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s2 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s2"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x100590>; | |
| regulator-max-microvolt = <0x100590>; | |
| linux,phandle = <0x325>; | |
| phandle = <0x325>; | |
| }; | |
| }; | |
| rpm-regulator-smpb3 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "rwcx"; | |
| qcom,resource-id = <0x0>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s3 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s3"; | |
| qcom,set = <0x3>; | |
| status = "disabled"; | |
| }; | |
| regulator-s3-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s3_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0xc6>; | |
| phandle = <0xc6>; | |
| }; | |
| regulator-s3-floor-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s3_floor_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-floor-level; | |
| qcom,always-send-voltage; | |
| linux,phandle = <0xa9>; | |
| phandle = <0xa9>; | |
| }; | |
| regulator-s3-level-ao { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s3_level_ao"; | |
| qcom,set = <0x1>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0xc7>; | |
| phandle = <0xc7>; | |
| }; | |
| }; | |
| rpm-regulator-smpb5 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "rwmx"; | |
| qcom,resource-id = <0x0>; | |
| qcom,regulator-type = <0x1>; | |
| status = "okay"; | |
| regulator-s5 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s5"; | |
| qcom,set = <0x3>; | |
| status = "disabled"; | |
| }; | |
| regulator-s5-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s5_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0xc8>; | |
| phandle = <0xc8>; | |
| }; | |
| regulator-s5-floor-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s5_floor_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-floor-level; | |
| qcom,always-send-voltage; | |
| linux,phandle = <0x326>; | |
| phandle = <0x326>; | |
| }; | |
| regulator-s5-level-ao { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_s5_level_ao"; | |
| qcom,set = <0x1>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0x327>; | |
| phandle = <0x327>; | |
| }; | |
| }; | |
| rpm-regulator-ldob1 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x1>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l1 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l1"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0xc3500>; | |
| regulator-max-microvolt = <0xe1d48>; | |
| linux,phandle = <0x105>; | |
| phandle = <0x105>; | |
| }; | |
| }; | |
| rpm-regulator-ldob2 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x2>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l2 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l2"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x55730>; | |
| regulator-max-microvolt = <0x2f4d60>; | |
| linux,phandle = <0x50>; | |
| phandle = <0x50>; | |
| }; | |
| }; | |
| rpm-regulator-ldob3 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x3>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l3 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l3"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1a17b0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| regulator-always-on; | |
| linux,phandle = <0x28a>; | |
| phandle = <0x28a>; | |
| }; | |
| }; | |
| rpm-regulator-ldob4 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x4>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l4 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l4"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x19f0a0>; | |
| regulator-max-microvolt = <0x2d0370>; | |
| linux,phandle = <0xd4>; | |
| phandle = <0xd4>; | |
| }; | |
| }; | |
| rpm-regulator-ldob5 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x5>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l5 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l5"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x1a42a8>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| linux,phandle = <0x4f>; | |
| phandle = <0x4f>; | |
| }; | |
| }; | |
| rpm-regulator-ldob6 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x6>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l6 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l6"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x19f0a0>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| linux,phandle = <0x197>; | |
| phandle = <0x197>; | |
| }; | |
| }; | |
| rpm-regulator-ldob7 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x7>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l7 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l7"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x2932e0>; | |
| regulator-max-microvolt = <0x2faf08>; | |
| parent-supply = <0xc9>; | |
| linux,phandle = <0x7d>; | |
| phandle = <0x7d>; | |
| }; | |
| }; | |
| rpm-regulator-ldob8 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "ldob"; | |
| qcom,resource-id = <0x8>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l8 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l8"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x30d400>; | |
| regulator-max-microvolt = <0x33e140>; | |
| linux,phandle = <0x328>; | |
| phandle = <0x328>; | |
| }; | |
| }; | |
| rpm-regulator-ldob9 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "rwlc"; | |
| qcom,resource-id = <0x0>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l9 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l9"; | |
| qcom,set = <0x3>; | |
| status = "disabled"; | |
| }; | |
| regulator-l9-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l9_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0xfa>; | |
| phandle = <0xfa>; | |
| }; | |
| regulator-l9-floor-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l9_floor_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-floor-level; | |
| qcom,always-send-voltage; | |
| linux,phandle = <0x329>; | |
| phandle = <0x329>; | |
| }; | |
| }; | |
| rpm-regulator-ldob10 { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "rwlm"; | |
| qcom,resource-id = <0x0>; | |
| qcom,regulator-type = <0x0>; | |
| status = "okay"; | |
| regulator-l10 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l10"; | |
| qcom,set = <0x3>; | |
| status = "disabled"; | |
| }; | |
| regulator-l10-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l10_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-level; | |
| linux,phandle = <0x32a>; | |
| phandle = <0x32a>; | |
| }; | |
| regulator-l10-floor-level { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_l10_floor_level"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x10>; | |
| regulator-max-microvolt = <0x180>; | |
| qcom,use-voltage-floor-level; | |
| qcom,always-send-voltage; | |
| linux,phandle = <0x32b>; | |
| phandle = <0x32b>; | |
| }; | |
| }; | |
| rpm-regulator-bobb { | |
| compatible = "qcom,rpm-smd-regulator-resource"; | |
| qcom,resource-name = "bobb"; | |
| qcom,resource-id = <0x1>; | |
| qcom,regulator-type = <0x4>; | |
| status = "okay"; | |
| regulator-bob { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_bob"; | |
| qcom,set = <0x3>; | |
| status = "okay"; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| qcom,pwm-threshold-current = <0x1e8480>; | |
| qcom,init-bob-mode = <0x2>; | |
| linux,phandle = <0xae>; | |
| phandle = <0xae>; | |
| }; | |
| regulator-bob-pin1 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_bob_pin1"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| qcom,pwm-threshold-current = <0x1e8480>; | |
| qcom,init-bob-mode = <0x2>; | |
| qcom,use-pin-ctrl-voltage1; | |
| linux,phandle = <0x293>; | |
| phandle = <0x293>; | |
| }; | |
| regulator-bob-pin2 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_bob_pin2"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| qcom,pwm-threshold-current = <0x1e8480>; | |
| qcom,init-bob-mode = <0x2>; | |
| qcom,use-pin-ctrl-voltage2; | |
| linux,phandle = <0x32c>; | |
| phandle = <0x32c>; | |
| }; | |
| regulator-bob-pin3 { | |
| compatible = "qcom,rpm-smd-regulator"; | |
| regulator-name = "pm660l_bob_pin3"; | |
| qcom,set = <0x3>; | |
| regulator-min-microvolt = <0x325aa0>; | |
| regulator-max-microvolt = <0x36ee80>; | |
| qcom,pwm-threshold-current = <0x1e8480>; | |
| qcom,init-bob-mode = <0x2>; | |
| qcom,use-pin-ctrl-voltage3; | |
| linux,phandle = <0x32d>; | |
| phandle = <0x32d>; | |
| }; | |
| }; | |
| rpm-regulator-ldoa16 { | |
| status = "okay"; | |
| regulator-l16 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| status = "okay"; | |
| regulator-always-on; | |
| linux,phandle = <0x32e>; | |
| phandle = <0x32e>; | |
| }; | |
| }; | |
| }; | |
| qcom,ipc_router { | |
| compatible = "qcom,ipc_router"; | |
| qcom,node-id = <0x1>; | |
| }; | |
| qcom,ipc_router_modem_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,xprt-remote = "mpss"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-linkid = <0x1>; | |
| qcom,xprt-version = <0x1>; | |
| qcom,fragmented-data; | |
| }; | |
| qcom,ipc_router_q6_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,xprt-remote = "lpass"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-linkid = <0x1>; | |
| qcom,xprt-version = <0x1>; | |
| qcom,fragmented-data; | |
| }; | |
| qcom,ipc_router_cdsp_xprt { | |
| compatible = "qcom,ipc_router_glink_xprt"; | |
| qcom,ch-name = "IPCRTR"; | |
| qcom,xprt-remote = "cdsp"; | |
| qcom,glink-xprt = "smem"; | |
| qcom,xprt-linkid = <0x1>; | |
| qcom,xprt-version = <0x1>; | |
| qcom,fragmented-data; | |
| }; | |
| qcom,venus@cce0000 { | |
| compatible = "qcom,pil-tz-generic"; | |
| reg = <0xcce0000 0x4000>; | |
| vdd-supply = <0xf3>; | |
| qcom,proxy-reg-names = "vdd"; | |
| clocks = <0x74 0xb6 0x74 0xa9 0x74 0xb4 0x26 0x3c 0x74 0xb5>; | |
| clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", "noc_axi_clk", "bus_clk"; | |
| qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", "noc_axi_clk", "bus_clk"; | |
| qcom,msm-bus,name = "pil-venus"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x3f 0x200 0x0 0x0 0x3f 0x200 0x0 0x4a380>; | |
| qcom,pas-id = <0x9>; | |
| qcom,proxy-timeout-ms = <0x64>; | |
| qcom,firmware-name = "venus"; | |
| memory-region = <0xf4>; | |
| status = "ok"; | |
| }; | |
| qcom,icnss@18800000 { | |
| compatible = "qcom,icnss"; | |
| reg = <0x18800000 0x800000 0xa0000000 0x10000000 0xb0000000 0x10000>; | |
| reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; | |
| iommus = <0xe8 0x1a00 0xe8 0x1a01>; | |
| clocks = <0x26 0x14>; | |
| clock-names = "cxo_ref_clk_pin"; | |
| interrupts = <0x0 0x19d 0x0 0x0 0x19e 0x0 0x0 0x19f 0x0 0x0 0x1a0 0x0 0x0 0x1a1 0x0 0x0 0x1a2 0x0 0x0 0x1a4 0x0 0x0 0x1a5 0x0 0x0 0x1a6 0x0 0x0 0x1a7 0x0 0x0 0x1a8 0x0 0x0 0x1a9 0x0>; | |
| vdd-0.8-cx-mx-supply = <0xf5>; | |
| vdd-1.8-xo-supply = <0xf6>; | |
| vdd-1.3-rfa-supply = <0xf7>; | |
| vdd-3.3-ch0-supply = <0xf8>; | |
| qcom,vdd-0.8-cx-mx-config = <0xcf080 0xcf080>; | |
| qcom,vdd-1.8-xo-config = <0x1ab3f0 0x1cfde0>; | |
| qcom,vdd-1.3-rfa-config = <0x124f80 0x14e790>; | |
| qcom,vdd-3.3-ch0-config = <0x30d400 0x33e140>; | |
| qcom,wlan-msa-memory = <0x100000>; | |
| qcom,wlan-msa-fixed-region = <0xf9>; | |
| qcom,smmu-s1-bypass; | |
| }; | |
| qcom,lpass@15700000 { | |
| compatible = "qcom,pil-tz-generic"; | |
| reg = <0x15700000 0x100>; | |
| reg-names = "base_reg"; | |
| interrupts = <0x0 0xa2 0x1>; | |
| vdd_cx-supply = <0xfa>; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
| clocks = <0x26 0x52>; | |
| clock-names = "xo"; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,pas-id = <0x1>; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| qcom,smem-id = <0x1a7>; | |
| qcom,sysmon-id = <0x1>; | |
| qcom,ssctl-instance-id = <0x14>; | |
| qcom,firmware-name = "adsp"; | |
| memory-region = <0xfb>; | |
| qcom,gpio-err-fatal = <0xfc 0x0 0x0>; | |
| qcom,gpio-proxy-unvote = <0xfc 0x2 0x0>; | |
| qcom,gpio-err-ready = <0xfc 0x1 0x0>; | |
| qcom,gpio-stop-ack = <0xfc 0x3 0x0>; | |
| qcom,gpio-force-stop = <0xfd 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,turing@1a300000 { | |
| compatible = "qcom,pil-tz-generic"; | |
| reg = <0x1a300000 0x100>; | |
| reg-names = "base_reg"; | |
| interrupts = <0x0 0x206 0x1>; | |
| vdd_cx-supply = <0xc6>; | |
| qcom,proxy-reg-names = "vdd_cx"; | |
| qcom,vdd_cx-uV-uA = <0x180 0x186a0>; | |
| clocks = <0x26 0x54>; | |
| clock-names = "xo"; | |
| qcom,proxy-clock-names = "xo"; | |
| qcom,pas-id = <0x12>; | |
| qcom,proxy-timeout-ms = <0x2710>; | |
| qcom,smem-id = <0x259>; | |
| qcom,sysmon-id = <0x7>; | |
| qcom,ssctl-instance-id = <0x17>; | |
| qcom,firmware-name = "cdsp"; | |
| memory-region = <0xfe>; | |
| qcom,gpio-err-fatal = <0xff 0x0 0x0>; | |
| qcom,gpio-proxy-unvote = <0xff 0x2 0x0>; | |
| qcom,gpio-err-ready = <0xff 0x1 0x0>; | |
| qcom,gpio-stop-ack = <0xff 0x3 0x0>; | |
| qcom,gpio-force-stop = <0x100 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,mss@4080000 { | |
| compatible = "qcom,pil-q6v55-mss"; | |
| reg = <0x4080000 0x100 0x1f63000 0x8 0x1f65000 0x8 0x1f64000 0x8 0x4180000 0x40 0x179000 0x4 0x1fe5048 0x4>; | |
| reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg", "cxip_lm_vote_clear"; | |
| clocks = <0x26 0x0 0xa1 0x4d 0xa1 0x22 0xa1 0x39 0xa1 0xb2 0xa1 0x51 0xa1 0x4f 0x26 0x8>; | |
| clock-names = "xo", "iface_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", "qdss_clk"; | |
| qcom,proxy-clock-names = "xo", "qdss_clk"; | |
| qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk"; | |
| interrupts = <0x0 0x1c0 0x1>; | |
| vdd_cx-supply = <0xc6>; | |
| vdd_cx-voltage = <0x180>; | |
| vdd_mx-supply = <0xc8>; | |
| vdd_mx-uV = <0x180>; | |
| qcom,firmware-name = "modem"; | |
| qcom,pil-self-auth; | |
| qcom,sysmon-id = <0x0>; | |
| qcom,minidump-id = <0x0>; | |
| qcom,ssctl-instance-id = <0x12>; | |
| qcom,qdsp6v62-1-5; | |
| memory-region = <0x101>; | |
| qcom,mem-protect-id = <0xf>; | |
| qcom,cx-ipeak-vote; | |
| qcom,gpio-err-fatal = <0x102 0x0 0x0>; | |
| qcom,gpio-err-ready = <0x102 0x1 0x0>; | |
| qcom,gpio-proxy-unvote = <0x102 0x2 0x0>; | |
| qcom,gpio-stop-ack = <0x102 0x3 0x0>; | |
| qcom,gpio-shutdown-ack = <0x102 0x7 0x0>; | |
| qcom,gpio-force-stop = <0x103 0x0 0x0>; | |
| status = "ok"; | |
| linux,phandle = <0x32f>; | |
| phandle = <0x32f>; | |
| qcom,mba-mem@0 { | |
| compatible = "qcom,pil-mba-mem"; | |
| memory-region = <0x104>; | |
| }; | |
| }; | |
| qcom,msm-rtb { | |
| compatible = "qcom,msm-rtb"; | |
| qcom,rtb-size = <0x100000>; | |
| }; | |
| qcom,mpm2-sleep-counter@10a3000 { | |
| compatible = "qcom,mpm2-sleep-counter"; | |
| reg = <0x10a3000 0x1000>; | |
| clock-frequency = <0x8000>; | |
| }; | |
| qcom,msm-imem@146bf000 { | |
| compatible = "qcom,msm-imem"; | |
| reg = <0x146bf000 0x1000>; | |
| ranges = <0x0 0x146bf000 0x1000>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| mem_dump_table@10 { | |
| compatible = "qcom,msm-imem-mem_dump_table"; | |
| reg = <0x10 0x8>; | |
| }; | |
| dload_type@1c { | |
| compatible = "qcom,msm-imem-dload-type"; | |
| reg = <0x1c 0x4>; | |
| }; | |
| restart_reason@65c { | |
| compatible = "qcom,msm-imem-restart_reason"; | |
| reg = <0x65c 0x4>; | |
| }; | |
| boot_stats@6b0 { | |
| compatible = "qcom,msm-imem-boot_stats"; | |
| reg = <0x6b0 0x20>; | |
| }; | |
| kaslr_offset@6d0 { | |
| compatible = "qcom,msm-imem-kaslr_offset"; | |
| reg = <0x6d0 0xc>; | |
| }; | |
| pil@94c { | |
| compatible = "qcom,msm-imem-pil"; | |
| reg = <0x94c 0xc8>; | |
| }; | |
| diag_dload@c8 { | |
| compatible = "qcom,msm-imem-diag-dload"; | |
| reg = <0xc8 0xc8>; | |
| }; | |
| ss_mdump@b88 { | |
| compatible = "qcom,msm-imem-minidump"; | |
| reg = <0xb88 0x1c>; | |
| }; | |
| }; | |
| qcom,ghd { | |
| compatible = "qcom,gladiator-hang-detect"; | |
| qcom,threshold-arr = <0x179d141c 0x179d1420 0x179d1424 0x179d1428 0x179d142c 0x179d1430>; | |
| qcom,config-reg = <0x179d1434>; | |
| }; | |
| qcom,msm-gladiator-v2@17900000 { | |
| compatible = "qcom,msm-gladiator-v2"; | |
| reg = <0x17900000 0xe000>; | |
| reg-names = "gladiator_base"; | |
| interrupts = <0x0 0x16 0x0>; | |
| clock-names = "atb_clk"; | |
| clocks = <0x26 0x8>; | |
| }; | |
| cpu-pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| qcom,irq-is-percpu; | |
| interrupts = <0x1 0x6 0x4>; | |
| linux,phandle = <0x330>; | |
| phandle = <0x330>; | |
| }; | |
| qseecom@86d00000 { | |
| compatible = "qcom,qseecom"; | |
| reg = <0x86d00000 0x2200000>; | |
| reg-names = "secapp-region"; | |
| qcom,hlos-num-ce-hw-instances = <0x1>; | |
| qcom,hlos-ce-hw-instance = <0x0>; | |
| qcom,qsee-ce-hw-instance = <0x0>; | |
| qcom,disk-encrypt-pipe-pair = <0x2>; | |
| qcom,support-fde; | |
| qcom,fde-key-size; | |
| qcom,no-clock-support; | |
| qcom,msm-bus,name = "qseecom-noc"; | |
| qcom,msm-bus,num-cases = <0x4>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x30d40 0x61a80 0x37 0x200 0x493e0 0xc3500 0x37 0x200 0x61a80 0xf4240>; | |
| clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
| clocks = <0x26 0x4b 0x26 0x4b 0x26 0x4b 0x26 0x4b>; | |
| qcom,ce-opp-freq = <0xa37d070>; | |
| qcom,qsee-reentrancy-support = <0x0>; | |
| linux,phandle = <0x331>; | |
| phandle = <0x331>; | |
| }; | |
| qcedev@1de0000 { | |
| compatible = "qcom,qcedev"; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| reg-names = "crypto-base", "crypto-bam-base"; | |
| interrupts = <0x0 0xce 0x0>; | |
| qcom,bam-pipe-pair = <0x1>; | |
| qcom,ce-hw-instance = <0x0>; | |
| qcom,ce-device = <0x0>; | |
| qcom,ce-hw-shared; | |
| qcom,bam-ee = <0x0>; | |
| qcom,msm-bus,name = "qcedev-noc"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x60180 0x60180>; | |
| clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
| clocks = <0x26 0x49 0x26 0x49 0x26 0x49 0x26 0x49>; | |
| qcom,ce-opp-freq = <0xa37d070>; | |
| linux,phandle = <0x332>; | |
| phandle = <0x332>; | |
| }; | |
| qcrypto@1de0000 { | |
| compatible = "qcom,qcrypto"; | |
| reg = <0x1de0000 0x20000 0x1dc4000 0x24000>; | |
| reg-names = "crypto-base", "crypto-bam-base"; | |
| interrupts = <0x0 0xce 0x0>; | |
| qcom,bam-pipe-pair = <0x2>; | |
| qcom,ce-hw-instance = <0x0>; | |
| qcom,ce-device = <0x0>; | |
| qcom,bam-ee = <0x0>; | |
| qcom,ce-hw-shared; | |
| qcom,clk-mgmt-sus-res; | |
| qcom,msm-bus,name = "qcrypto-noc"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x37 0x200 0x0 0x0 0x37 0x200 0x60180 0x60180>; | |
| clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; | |
| clocks = <0x26 0x4a 0x26 0x4a 0x26 0x4a 0x26 0x4a>; | |
| qcom,ce-opp-freq = <0xa37d070>; | |
| qcom,use-sw-aes-cbc-ecb-ctr-algo; | |
| qcom,use-sw-aes-xts-algo; | |
| qcom,use-sw-aes-ccm-algo; | |
| qcom,use-sw-ahash-algo; | |
| qcom,use-sw-aead-algo; | |
| qcom,use-sw-hmac-algo; | |
| linux,phandle = <0x333>; | |
| phandle = <0x333>; | |
| }; | |
| tz-log@146bf720 { | |
| compatible = "qcom,tz-log"; | |
| reg = <0x146bf720 0x3000>; | |
| qcom,hyplog-enabled; | |
| hyplog-address-offset = <0x410>; | |
| hyplog-size-offset = <0x414>; | |
| linux,phandle = <0x334>; | |
| phandle = <0x334>; | |
| }; | |
| qrng@793000 { | |
| compatible = "qcom,msm-rng"; | |
| reg = <0x793000 0x1000>; | |
| qcom,msm-rng-iface-clk; | |
| qcom,no-qrng-config; | |
| qcom,msm-bus,name = "msm-rng-noc"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x1 0x26a 0x0 0x0 0x1 0x26a 0x0 0x320>; | |
| clocks = <0xa1 0x54>; | |
| clock-names = "iface_clk"; | |
| linux,phandle = <0x335>; | |
| phandle = <0x335>; | |
| }; | |
| qcom,chd_silver { | |
| compatible = "qcom,core-hang-detect"; | |
| label = "silver"; | |
| qcom,threshold-arr = <0x179880b0 0x179980b0 0x179a80b0 0x179b80b0>; | |
| qcom,config-arr = <0x179880b8 0x179980b8 0x179a80b8 0x179b80b8>; | |
| }; | |
| qcom,chd_gold { | |
| compatible = "qcom,core-hang-detect"; | |
| label = "gold"; | |
| qcom,threshold-arr = <0x178880b0 0x178980b0 0x178a80b0 0x178b80b0>; | |
| qcom,config-arr = <0x178880b8 0x178980b8 0x178a80b8 0x178b80b8>; | |
| }; | |
| ufsphy@1da7000 { | |
| compatible = "qcom,ufs-phy-qmp-v3-660"; | |
| reg = <0x1da7000 0xdb8>; | |
| reg-names = "phy_mem"; | |
| #phy-cells = <0x0>; | |
| clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; | |
| clocks = <0x26 0x2e 0xa1 0x61 0xa1 0x63>; | |
| status = "ok"; | |
| vdda-phy-supply = <0x105>; | |
| vdda-pll-supply = <0xc9>; | |
| vdda-phy-max-microamp = <0xc8c8>; | |
| vdda-pll-max-microamp = <0x3778>; | |
| linux,phandle = <0x106>; | |
| phandle = <0x106>; | |
| }; | |
| ufshc@1da4000 { | |
| compatible = "qcom,ufshc"; | |
| reg = <0x1da4000 0x3000>; | |
| interrupts = <0x0 0x109 0x0>; | |
| phys = <0x106>; | |
| phy-names = "ufsphy"; | |
| ufs-qcom-crypto = <0x107>; | |
| clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; | |
| clocks = <0xa1 0x60 0xa1 0x1e 0xa1 0x5f 0xa1 0x67 0xa1 0x62 0x26 0x2e 0xa1 0x66 0xa1 0x64>; | |
| freq-table-hz = <0x2faf080 0xbebc200 0x0 0x0 0x0 0x0 0x23c3460 0x8f0d180 0x47868c0 0x11e1a300 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| lanes-per-direction = <0x1>; | |
| spm-level = <0x5>; | |
| non-removable; | |
| qcom,msm-bus,name = "ufs1"; | |
| qcom,msm-bus,num-cases = <0xc>; | |
| qcom,msm-bus,num-paths = <0x2>; | |
| qcom,msm-bus,vectors-KBps = <0x5f 0x200 0x0 0x0 0x1 0x28a 0x0 0x0 0x5f 0x200 0x39a 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x734 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0xe68 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1cd0 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x1f334 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x3e667 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x200000 0x0 0x1 0x28a 0x19000 0x0 0x5f 0x200 0x247ae 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x48ccd 0x0 0x1 0x28a 0x3e8 0x0 0x5f 0x200 0x200000 0x0 0x1 0x28a 0x19000 0x0 0x5f 0x200 0x74a000 0x0 0x1 0x28a 0x4b000 0x0>; | |
| qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "MAX"; | |
| resets = <0xa1 0x2>; | |
| reset-names = "core_reset"; | |
| status = "ok"; | |
| qcom,pm-qos-cpu-groups = <0xf 0xf0>; | |
| qcom,pm-qos-cpu-group-latency-us = <0x1a 0x1a>; | |
| qcom,pm-qos-default-cpu = <0x0>; | |
| vdd-hba-supply = <0x108>; | |
| vdd-hba-fixed-regulator; | |
| vcc-supply = <0xd4>; | |
| vccq2-supply = <0xd5>; | |
| vcc-max-microamp = <0x7a120>; | |
| vccq2-max-microamp = <0x927c0>; | |
| qcom,vddp-ref-clk-supply = <0x109>; | |
| qcom,vddp-ref-clk-max-microamp = <0x64>; | |
| linux,phandle = <0x336>; | |
| phandle = <0x336>; | |
| }; | |
| jtagfuse@786040 { | |
| compatible = "qcom,jtag-fuse-v4"; | |
| reg = <0x786040 0x8>; | |
| reg-names = "fuse-base"; | |
| linux,phandle = <0x337>; | |
| phandle = <0x337>; | |
| }; | |
| snfuse@0xA4128 { | |
| compatible = "qcom,sn-fuse"; | |
| reg = <0x786134 0x4 0x78607c 0x4>; | |
| reg-names = "sn-base", "fuse-state"; | |
| linux,phandle = <0x338>; | |
| phandle = <0x338>; | |
| }; | |
| jtagmm@7840000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7840000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x13>; | |
| linux,phandle = <0x339>; | |
| phandle = <0x339>; | |
| }; | |
| jtagmm@7940000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7940000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x14>; | |
| linux,phandle = <0x33a>; | |
| phandle = <0x33a>; | |
| }; | |
| jtagmm@7a40000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7a40000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x15>; | |
| linux,phandle = <0x33b>; | |
| phandle = <0x33b>; | |
| }; | |
| jtagmm@7b40000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7b40000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x16>; | |
| linux,phandle = <0x33c>; | |
| phandle = <0x33c>; | |
| }; | |
| jtagmm@7c40000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7c40000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x17>; | |
| linux,phandle = <0x33d>; | |
| phandle = <0x33d>; | |
| }; | |
| jtagmm@7d40000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7d40000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x18>; | |
| linux,phandle = <0x33e>; | |
| phandle = <0x33e>; | |
| }; | |
| jtagmm@7e40000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7e40000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x19>; | |
| linux,phandle = <0x33f>; | |
| phandle = <0x33f>; | |
| }; | |
| jtagmm@7f40000 { | |
| compatible = "qcom,jtagv8-mm"; | |
| reg = <0x7f40000 0x1000>; | |
| reg-names = "etm-base"; | |
| clocks = <0x26 0x8 0x26 0x9>; | |
| clock-names = "core_clk", "core_a_clk"; | |
| qcom,coresight-jtagmm-cpu = <0x1a>; | |
| linux,phandle = <0x340>; | |
| phandle = <0x340>; | |
| }; | |
| qcom,ion { | |
| compatible = "qcom,msm-ion"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,ion-heap@25 { | |
| reg = <0x19>; | |
| qcom,ion-heap-type = "SYSTEM"; | |
| linux,phandle = <0x341>; | |
| phandle = <0x341>; | |
| }; | |
| qcom,ion-heap@22 { | |
| reg = <0x16>; | |
| memory-region = <0xe9>; | |
| qcom,ion-heap-type = "DMA"; | |
| }; | |
| qcom,ion-heap@27 { | |
| reg = <0x1b>; | |
| memory-region = <0x10a>; | |
| qcom,ion-heap-type = "DMA"; | |
| }; | |
| qcom,ion-heap@10 { | |
| reg = <0xa>; | |
| memory-region = <0x10b>; | |
| qcom,ion-heap-type = "HYP_CMA"; | |
| }; | |
| qcom,ion-heap@9 { | |
| reg = <0x9>; | |
| qcom,ion-heap-type = "SYSTEM_SECURE"; | |
| }; | |
| }; | |
| ad-hoc-bus { | |
| compatible = "qcom,msm-bus-device"; | |
| reg = <0x1620000 0x20000 0x1000000 0x80000 0x1500000 0x10000 0x1700000 0x20000 0x17900000 0xe000 0x1740000 0x10000 0x1740000 0x10000>; | |
| reg-names = "snoc-base", "bimc-base", "cnoc-base", "a2noc-base", "gnoc-base", "mmnoc-ahb-base", "mnoc-base"; | |
| linux,phandle = <0x342>; | |
| phandle = <0x342>; | |
| fab-a2noc { | |
| cell-id = <0x1803>; | |
| label = "fab-a2noc"; | |
| qcom,fab-dev; | |
| qcom,base-name = "a2noc-base"; | |
| qcom,bus-type = <0x1>; | |
| qcom,qos-off = <0x1000>; | |
| qcom,base-offset = <0x4000>; | |
| clock-names = "bus_clk", "bus_a_clk"; | |
| clocks = <0x26 0x57 0x26 0x58>; | |
| linux,phandle = <0x10d>; | |
| phandle = <0x10d>; | |
| qcom,node-qos-clks { | |
| clock-names = "clk-ipa-clk", "clk-ufs-axi-clk", "clk-aggre2-ufs-axi-no-rate", "clk-aggre2-usb3-axi-cfg-no-rate", "clk-cfg-noc-usb2-axi-no-rate"; | |
| clocks = <0x26 0x22 0xa1 0x60 0xa1 0x1e 0xa1 0x1f 0xa1 0x3a>; | |
| }; | |
| }; | |
| fab-bimc { | |
| cell-id = <0x0>; | |
| label = "fab-bimc"; | |
| qcom,fab-dev; | |
| qcom,base-name = "bimc-base"; | |
| qcom,bus-type = <0x2>; | |
| qcom,util-fact = <0x99>; | |
| clock-names = "bus_clk", "bus_a_clk"; | |
| clocks = <0x26 0x3f 0x26 0x40>; | |
| linux,phandle = <0x110>; | |
| phandle = <0x110>; | |
| }; | |
| fab-cnoc { | |
| cell-id = <0x1400>; | |
| label = "fab-cnoc"; | |
| qcom,fab-dev; | |
| qcom,base-name = "cnoc-base"; | |
| qcom,bus-type = <0x1>; | |
| clock-names = "bus_clk", "bus_a_clk"; | |
| clocks = <0x26 0x41 0x26 0x42>; | |
| linux,phandle = <0x134>; | |
| phandle = <0x134>; | |
| }; | |
| fab-gnoc { | |
| cell-id = <0x1804>; | |
| label = "fab-gnoc"; | |
| qcom,virt-dev; | |
| qcom,base-name = "gnoc-base"; | |
| linux,phandle = <0x138>; | |
| phandle = <0x138>; | |
| }; | |
| fab-mnoc { | |
| cell-id = <0x800>; | |
| label = "fab-mnoc"; | |
| qcom,fab-dev; | |
| qcom,base-name = "mnoc-base"; | |
| qcom,bus-type = <0x1>; | |
| qcom,qos-off = <0x1000>; | |
| qcom,base-offset = <0x5000>; | |
| qcom,util-fact = <0x99>; | |
| clock-names = "bus_clk", "bus_a_clk"; | |
| clocks = <0x26 0x3c 0x26 0x3d>; | |
| linux,phandle = <0x148>; | |
| phandle = <0x148>; | |
| qcom,node-qos-clks { | |
| clock-names = "clk-mmssnoc-axi-no-rate", "clk-mmss-noc-cfg-ahb-no-rate"; | |
| clocks = <0x26 0x3c 0xa1 0x4b>; | |
| }; | |
| }; | |
| fab-snoc { | |
| cell-id = <0x400>; | |
| label = "fab-snoc"; | |
| qcom,fab-dev; | |
| qcom,base-name = "snoc-base"; | |
| qcom,bus-type = <0x1>; | |
| qcom,qos-off = <0x1000>; | |
| qcom,base-offset = <0x6000>; | |
| clock-names = "bus_clk", "bus_a_clk"; | |
| clocks = <0x26 0x4d 0x26 0x4e>; | |
| linux,phandle = <0x14c>; | |
| phandle = <0x14c>; | |
| }; | |
| fab-mnoc-ahb { | |
| cell-id = <0x801>; | |
| label = "fab-mnoc-ahb"; | |
| qcom,fab-dev; | |
| qcom,base-name = "mmnoc-ahb-base"; | |
| qcom,setrate-only-clk; | |
| qcom,bus-type = <0x1>; | |
| clock-names = "bus_clk", "bus_a_clk"; | |
| clocks = <0x74 0x5 0x74 0x5>; | |
| linux,phandle = <0x145>; | |
| phandle = <0x145>; | |
| }; | |
| mas-ipa { | |
| cell-id = <0x5a>; | |
| label = "mas-ipa"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x3>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x10c>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x3b>; | |
| linux,phandle = <0x343>; | |
| phandle = <0x343>; | |
| }; | |
| mas-cnoc-a2noc { | |
| cell-id = <0x76>; | |
| label = "mas-cnoc-a2noc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,connections = <0x10c>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x92>; | |
| qcom,blacklist = <0x10e>; | |
| linux,phandle = <0x156>; | |
| phandle = <0x156>; | |
| }; | |
| mas-sdcc-1 { | |
| cell-id = <0x4e>; | |
| label = "mas-sdcc-1"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x10c>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x21>; | |
| linux,phandle = <0x344>; | |
| phandle = <0x344>; | |
| }; | |
| mas-sdcc-2 { | |
| cell-id = <0x51>; | |
| label = "mas-sdcc-2"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x10c>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x23>; | |
| linux,phandle = <0x345>; | |
| phandle = <0x345>; | |
| }; | |
| mas-blsp-1 { | |
| cell-id = <0x56>; | |
| label = "mas-blsp-1"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x10c>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x29>; | |
| linux,phandle = <0x346>; | |
| phandle = <0x346>; | |
| }; | |
| mas-blsp-2 { | |
| cell-id = <0x54>; | |
| label = "mas-blsp-2"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x10c>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x27>; | |
| linux,phandle = <0x347>; | |
| phandle = <0x347>; | |
| }; | |
| mas-ufs { | |
| cell-id = <0x5f>; | |
| label = "mas-ufs"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x4>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x10c>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x44>; | |
| linux,phandle = <0x348>; | |
| phandle = <0x348>; | |
| }; | |
| mas-usb-hs { | |
| cell-id = <0x57>; | |
| label = "mas-usb-hs"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x1>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x10c>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x2a>; | |
| linux,phandle = <0x349>; | |
| phandle = <0x349>; | |
| }; | |
| mas-usb3 { | |
| cell-id = <0x3d>; | |
| label = "mas-usb3"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x2>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x10c>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x20>; | |
| linux,phandle = <0x34a>; | |
| phandle = <0x34a>; | |
| }; | |
| mas-crypto-c0 { | |
| cell-id = <0x37>; | |
| label = "mas-crypto-c0"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,qport = <0xb>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x10c>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,mas-rpm-id = <0x17>; | |
| linux,phandle = <0x34b>; | |
| phandle = <0x34b>; | |
| }; | |
| mas-gnoc-bimc { | |
| cell-id = <0x74>; | |
| label = "mas-gnoc-bimc"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x0>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x10f>; | |
| qcom,prio-lvl = <0x0>; | |
| qcom,prio-rd = <0x0>; | |
| qcom,prio-wr = <0x0>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,mas-rpm-id = <0x90>; | |
| linux,phandle = <0x159>; | |
| phandle = <0x159>; | |
| }; | |
| mas-oxili { | |
| cell-id = <0x1a>; | |
| label = "mas-oxili"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x1>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x111 0x10f 0x112>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,mas-rpm-id = <0x6>; | |
| linux,phandle = <0x34c>; | |
| phandle = <0x34c>; | |
| }; | |
| mas-mnoc-bimc { | |
| cell-id = <0x272b>; | |
| label = "mas-mnoc-bimc"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x2>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x111 0x10f 0x112>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,mas-rpm-id = <0x2>; | |
| linux,phandle = <0x15b>; | |
| phandle = <0x15b>; | |
| }; | |
| mas-snoc-bimc { | |
| cell-id = <0x272f>; | |
| label = "mas-snoc-bimc"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,connections = <0x111 0x10f>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,mas-rpm-id = <0x3>; | |
| linux,phandle = <0x15c>; | |
| phandle = <0x15c>; | |
| }; | |
| mas-pimem { | |
| cell-id = <0x7b>; | |
| label = "mas-pimem"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x4>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x111 0x10f>; | |
| qcom,prio-lvl = <0x1>; | |
| qcom,prio-rd = <0x1>; | |
| qcom,prio-wr = <0x1>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,mas-rpm-id = <0x71>; | |
| linux,phandle = <0x34d>; | |
| phandle = <0x34d>; | |
| }; | |
| mas-snoc-cnoc { | |
| cell-id = <0x2733>; | |
| label = "mas-snoc-cnoc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,connections = <0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11a 0x11b 0x11c 0x11d 0x11e 0x11f 0x120 0x121 0x122 0x123 0x124 0x125 0x126 0x127 0x128 0x129 0x12a 0x12b 0x12c 0x12d 0x12e 0x12f 0x130 0x131 0x132 0x133>; | |
| qcom,bus-dev = <0x134>; | |
| qcom,mas-rpm-id = <0x34>; | |
| linux,phandle = <0x15d>; | |
| phandle = <0x15d>; | |
| }; | |
| mas-qdss-dap { | |
| cell-id = <0x4c>; | |
| label = "mas-qdss-dap"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,connections = <0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11a 0x11b 0x11c 0x11d 0x11e 0x11f 0x120 0x121 0x122 0x123 0x124 0x125 0x126 0x127 0x128 0x129 0x12a 0x12b 0x12c 0x12d 0x12e 0x12f 0x130 0x131 0x135 0x132 0x133>; | |
| qcom,bus-dev = <0x134>; | |
| qcom,mas-rpm-id = <0x31>; | |
| linux,phandle = <0x34e>; | |
| phandle = <0x34e>; | |
| }; | |
| mas-apps-proc { | |
| cell-id = <0x1>; | |
| label = "mas-apps-proc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,connections = <0x136 0x137>; | |
| qcom,bus-dev = <0x138>; | |
| qcom,mas-rpm-id = <0x0>; | |
| linux,phandle = <0x34f>; | |
| phandle = <0x34f>; | |
| }; | |
| mas-cnoc-mnoc-mmss-cfg { | |
| cell-id = <0x66>; | |
| label = "mas-cnoc-mnoc-mmss-cfg"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,connections = <0x139 0x13a 0x13b 0x13c 0x13d 0x13e 0x13f 0x140 0x141 0x142 0x143 0x144>; | |
| qcom,bus-dev = <0x145>; | |
| qcom,mas-rpm-id = <0x4>; | |
| linux,phandle = <0x158>; | |
| phandle = <0x158>; | |
| }; | |
| mas-cnoc-mnoc-cfg { | |
| cell-id = <0x67>; | |
| label = "mas-cnoc-mnoc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,connections = <0x146>; | |
| qcom,bus-dev = <0x145>; | |
| qcom,mas-rpm-id = <0x5>; | |
| linux,phandle = <0x157>; | |
| phandle = <0x157>; | |
| }; | |
| mas-cpp { | |
| cell-id = <0x6a>; | |
| label = "mas-cpp"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x4>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x147>; | |
| qcom,bus-dev = <0x148>; | |
| qcom,mas-rpm-id = <0x73>; | |
| linux,phandle = <0x350>; | |
| phandle = <0x350>; | |
| }; | |
| mas-jpeg { | |
| cell-id = <0x3e>; | |
| label = "mas-jpeg"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x6>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x147>; | |
| qcom,bus-dev = <0x148>; | |
| qcom,mas-rpm-id = <0x7>; | |
| linux,phandle = <0x351>; | |
| phandle = <0x351>; | |
| }; | |
| mas-mdp-p0 { | |
| cell-id = <0x16>; | |
| label = "mas-mdp-p0"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x0>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x147>; | |
| qcom,bus-dev = <0x148>; | |
| qcom,vrail-comp = <0x32>; | |
| qcom,mas-rpm-id = <0x8>; | |
| linux,phandle = <0x352>; | |
| phandle = <0x352>; | |
| }; | |
| mas-mdp-p1 { | |
| cell-id = <0x17>; | |
| label = "mas-mdp-p1"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x1>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x147>; | |
| qcom,bus-dev = <0x148>; | |
| qcom,vrail-comp = <0x32>; | |
| qcom,mas-rpm-id = <0x3d>; | |
| linux,phandle = <0x353>; | |
| phandle = <0x353>; | |
| }; | |
| mas-venus { | |
| cell-id = <0x3f>; | |
| label = "mas-venus"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x2>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x147>; | |
| qcom,bus-dev = <0x148>; | |
| qcom,mas-rpm-id = <0x9>; | |
| linux,phandle = <0x354>; | |
| phandle = <0x354>; | |
| }; | |
| mas-vfe { | |
| cell-id = <0x1d>; | |
| label = "mas-vfe"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x5>; | |
| qcom,qos-mode = "bypass"; | |
| qcom,connections = <0x147>; | |
| qcom,bus-dev = <0x148>; | |
| qcom,mas-rpm-id = <0xb>; | |
| linux,phandle = <0x355>; | |
| phandle = <0x355>; | |
| }; | |
| mas-qdss-etr { | |
| cell-id = <0x3c>; | |
| label = "mas-qdss-etr"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x1>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x149 0x14a 0x10e 0x14b>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,mas-rpm-id = <0x1f>; | |
| linux,phandle = <0x356>; | |
| phandle = <0x356>; | |
| }; | |
| mas-qdss-bam { | |
| cell-id = <0x35>; | |
| label = "mas-qdss-bam"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,qport = <0x0>; | |
| qcom,qos-mode = "fixed"; | |
| qcom,connections = <0x149 0x14a 0x10e 0x14b>; | |
| qcom,prio1 = <0x1>; | |
| qcom,prio0 = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,mas-rpm-id = <0x13>; | |
| linux,phandle = <0x357>; | |
| phandle = <0x357>; | |
| }; | |
| mas-snoc-cfg { | |
| cell-id = <0x36>; | |
| label = "mas-snoc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x14d>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,mas-rpm-id = <0x14>; | |
| linux,phandle = <0x358>; | |
| phandle = <0x358>; | |
| }; | |
| mas-bimc-snoc { | |
| cell-id = <0x2720>; | |
| label = "mas-bimc-snoc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x149 0x14e 0x14f 0x150 0x151 0x152 0x10e 0x153 0x14a>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,mas-rpm-id = <0x15>; | |
| linux,phandle = <0x155>; | |
| phandle = <0x155>; | |
| }; | |
| mas-a2noc-snoc { | |
| cell-id = <0x2750>; | |
| label = "mas-a2noc-snoc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x149 0x14e 0x14f 0x150 0x151 0x14b 0x152 0x10e 0x153 0x14a>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,mas-rpm-id = <0x70>; | |
| linux,phandle = <0x154>; | |
| phandle = <0x154>; | |
| }; | |
| slv-a2noc-snoc { | |
| cell-id = <0x2751>; | |
| label = "slv-a2noc-snoc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x10d>; | |
| qcom,connections = <0x154>; | |
| qcom,slv-rpm-id = <0x8f>; | |
| linux,phandle = <0x10c>; | |
| phandle = <0x10c>; | |
| }; | |
| slv-ebi { | |
| cell-id = <0x200>; | |
| label = "slv-ebi"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,slv-rpm-id = <0x0>; | |
| linux,phandle = <0x10f>; | |
| phandle = <0x10f>; | |
| }; | |
| slv-hmss-l3 { | |
| cell-id = <0x2a8>; | |
| label = "slv-hmss-l3"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,slv-rpm-id = <0xa0>; | |
| linux,phandle = <0x111>; | |
| phandle = <0x111>; | |
| }; | |
| slv-bimc-snoc { | |
| cell-id = <0x2721>; | |
| label = "slv-bimc-snoc"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x110>; | |
| qcom,connections = <0x155>; | |
| qcom,slv-rpm-id = <0x2>; | |
| linux,phandle = <0x112>; | |
| phandle = <0x112>; | |
| }; | |
| slv-cnoc-a2noc { | |
| cell-id = <0x2d5>; | |
| label = "slv-cnoc-a2noc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,connections = <0x156>; | |
| qcom,slv-rpm-id = <0xd0>; | |
| linux,phandle = <0x135>; | |
| phandle = <0x135>; | |
| }; | |
| slv-mpm { | |
| cell-id = <0x218>; | |
| label = "slv-mpm"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x3e>; | |
| linux,phandle = <0x11c>; | |
| phandle = <0x11c>; | |
| }; | |
| slv-pmic-arb { | |
| cell-id = <0x278>; | |
| label = "slv-pmic-arb"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x3b>; | |
| linux,phandle = <0x121>; | |
| phandle = <0x121>; | |
| }; | |
| slv-tlmm-north { | |
| cell-id = <0x2db>; | |
| label = "slv-tlmm-north"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xd6>; | |
| linux,phandle = <0x128>; | |
| phandle = <0x128>; | |
| }; | |
| slv-tcsr { | |
| cell-id = <0x26f>; | |
| label = "slv-tcsr"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x32>; | |
| linux,phandle = <0x118>; | |
| phandle = <0x118>; | |
| }; | |
| slv-pimem-cfg { | |
| cell-id = <0x2a9>; | |
| label = "slv-pimem-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xa7>; | |
| linux,phandle = <0x12f>; | |
| phandle = <0x12f>; | |
| }; | |
| slv-imem-cfg { | |
| cell-id = <0x273>; | |
| label = "slv-imem-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x36>; | |
| linux,phandle = <0x125>; | |
| phandle = <0x125>; | |
| }; | |
| slv-message-ram { | |
| cell-id = <0x274>; | |
| label = "slv-message-ram"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x37>; | |
| linux,phandle = <0x131>; | |
| phandle = <0x131>; | |
| }; | |
| slv-glm { | |
| cell-id = <0x2d6>; | |
| label = "slv-glm"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xd1>; | |
| linux,phandle = <0x130>; | |
| phandle = <0x130>; | |
| }; | |
| slv-bimc-cfg { | |
| cell-id = <0x275>; | |
| label = "slv-bimc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x38>; | |
| linux,phandle = <0x132>; | |
| phandle = <0x132>; | |
| }; | |
| slv-prng { | |
| cell-id = <0x26a>; | |
| label = "slv-prng"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x2c>; | |
| linux,phandle = <0x122>; | |
| phandle = <0x122>; | |
| }; | |
| slv-spdm { | |
| cell-id = <0x279>; | |
| label = "slv-spdm"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x3c>; | |
| linux,phandle = <0x120>; | |
| phandle = <0x120>; | |
| }; | |
| slv-qdss-cfg { | |
| cell-id = <0x27b>; | |
| label = "slv-qdss-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x3f>; | |
| linux,phandle = <0x114>; | |
| phandle = <0x114>; | |
| }; | |
| slv-cnoc-mnoc-cfg { | |
| cell-id = <0x280>; | |
| label = "slv-cnoc-mnoc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,connections = <0x157>; | |
| qcom,slv-rpm-id = <0x42>; | |
| linux,phandle = <0x133>; | |
| phandle = <0x133>; | |
| }; | |
| slv-snoc-cfg { | |
| cell-id = <0x282>; | |
| label = "slv-snoc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x46>; | |
| linux,phandle = <0x11a>; | |
| phandle = <0x11a>; | |
| }; | |
| slv-qm-cfg { | |
| cell-id = <0x2d9>; | |
| label = "slv-qm-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xd4>; | |
| linux,phandle = <0x115>; | |
| phandle = <0x115>; | |
| }; | |
| slv-clk-ctl { | |
| cell-id = <0x26c>; | |
| label = "slv-clk-ctl"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x2f>; | |
| linux,phandle = <0x113>; | |
| phandle = <0x113>; | |
| }; | |
| slv-mss-cfg { | |
| cell-id = <0x26d>; | |
| label = "slv-mss-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x30>; | |
| linux,phandle = <0x123>; | |
| phandle = <0x123>; | |
| }; | |
| slv-tlmm-south { | |
| cell-id = <0x2df>; | |
| label = "slv-tlmm-south"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xd9>; | |
| linux,phandle = <0x11b>; | |
| phandle = <0x11b>; | |
| }; | |
| slv-ufs-cfg { | |
| cell-id = <0x28a>; | |
| label = "slv-ufs-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x5c>; | |
| linux,phandle = <0x117>; | |
| phandle = <0x117>; | |
| }; | |
| slv-a2noc-cfg { | |
| cell-id = <0x2b0>; | |
| label = "slv-a2noc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x96>; | |
| linux,phandle = <0x127>; | |
| phandle = <0x127>; | |
| }; | |
| slv-a2noc-smmu-cfg { | |
| cell-id = <0x2b5>; | |
| label = "slv-a2noc-smmu-cfg"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x98>; | |
| linux,phandle = <0x119>; | |
| phandle = <0x119>; | |
| }; | |
| slv-gpuss-cfg { | |
| cell-id = <0x256>; | |
| label = "slv-gpuss-cfg"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xb>; | |
| linux,phandle = <0x124>; | |
| phandle = <0x124>; | |
| }; | |
| slv-ahb2phy { | |
| cell-id = <0x2ad>; | |
| label = "slv-ahb2phy"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xa3>; | |
| linux,phandle = <0x12c>; | |
| phandle = <0x12c>; | |
| }; | |
| slv-blsp-1 { | |
| cell-id = <0x265>; | |
| label = "slv-blsp-1"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x27>; | |
| linux,phandle = <0x12e>; | |
| phandle = <0x12e>; | |
| }; | |
| slv-sdcc-1 { | |
| cell-id = <0x25e>; | |
| label = "slv-sdcc-1"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x1f>; | |
| linux,phandle = <0x11f>; | |
| phandle = <0x11f>; | |
| }; | |
| slv-sdcc-2 { | |
| cell-id = <0x260>; | |
| label = "slv-sdcc-2"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x21>; | |
| linux,phandle = <0x11e>; | |
| phandle = <0x11e>; | |
| }; | |
| slv-tlmm-center { | |
| cell-id = <0x2e0>; | |
| label = "slv-tlmm-center"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0xda>; | |
| linux,phandle = <0x12b>; | |
| phandle = <0x12b>; | |
| }; | |
| slv-blsp-2 { | |
| cell-id = <0x263>; | |
| label = "slv-blsp-2"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x25>; | |
| linux,phandle = <0x12d>; | |
| phandle = <0x12d>; | |
| }; | |
| slv-pdm { | |
| cell-id = <0x267>; | |
| label = "slv-pdm"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x29>; | |
| linux,phandle = <0x12a>; | |
| phandle = <0x12a>; | |
| }; | |
| slv-cnoc-mnoc-mmss-cfg { | |
| cell-id = <0x277>; | |
| label = "slv-cnoc-mnoc-mmss-cfg"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,connections = <0x158>; | |
| qcom,slv-rpm-id = <0x3a>; | |
| linux,phandle = <0x11d>; | |
| phandle = <0x11d>; | |
| }; | |
| slv-usb-hs { | |
| cell-id = <0x266>; | |
| label = "slv-usb-hs"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x28>; | |
| linux,phandle = <0x129>; | |
| phandle = <0x129>; | |
| }; | |
| slv-usb3-0 { | |
| cell-id = <0x247>; | |
| label = "slv-usb3-0"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x16>; | |
| linux,phandle = <0x126>; | |
| phandle = <0x126>; | |
| }; | |
| slv-srvc-cnoc { | |
| cell-id = <0x286>; | |
| label = "slv-srvc-cnoc"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x134>; | |
| qcom,slv-rpm-id = <0x4c>; | |
| linux,phandle = <0x116>; | |
| phandle = <0x116>; | |
| }; | |
| slv-gnoc-bimc { | |
| cell-id = <0x2d7>; | |
| label = "slv-gnoc-bimc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x138>; | |
| qcom,connections = <0x159>; | |
| qcom,slv-rpm-id = <0xd2>; | |
| linux,phandle = <0x137>; | |
| phandle = <0x137>; | |
| }; | |
| slv-gnoc-snoc { | |
| cell-id = <0x2d8>; | |
| label = "slv-gnoc-snoc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x138>; | |
| qcom,connections = <0x15a>; | |
| qcom,slv-rpm-id = <0xd3>; | |
| linux,phandle = <0x136>; | |
| phandle = <0x136>; | |
| }; | |
| mas-gnoc-snoc { | |
| cell-id = <0x7a>; | |
| label = "mas-gnoc-snoc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,connections = <0x149 0x14e 0x14f 0x150 0x151 0x152 0x10e 0x153 0x14a>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,mas-rpm-id = <0x96>; | |
| linux,phandle = <0x15a>; | |
| phandle = <0x15a>; | |
| }; | |
| slv-camera-cfg { | |
| cell-id = <0x24d>; | |
| label = "slv-camera-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0x3>; | |
| linux,phandle = <0x13d>; | |
| phandle = <0x13d>; | |
| }; | |
| slv-camera-throttle-cfg { | |
| cell-id = <0x2c5>; | |
| label = "slv-camera-throttle-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0x9a>; | |
| linux,phandle = <0x13b>; | |
| phandle = <0x13b>; | |
| }; | |
| slv-misc-cfg { | |
| cell-id = <0x252>; | |
| label = "slv-misc-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0x8>; | |
| linux,phandle = <0x143>; | |
| phandle = <0x143>; | |
| }; | |
| slv-venus-throttle-cfg { | |
| cell-id = <0x2b8>; | |
| label = "slv-venus-throttle-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xb2>; | |
| linux,phandle = <0x139>; | |
| phandle = <0x139>; | |
| }; | |
| slv-venus-cfg { | |
| cell-id = <0x254>; | |
| label = "slv-venus-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xa>; | |
| linux,phandle = <0x13a>; | |
| phandle = <0x13a>; | |
| }; | |
| slv-mmss-clk-xpu-cfg { | |
| cell-id = <0x258>; | |
| label = "slv-mmss-clk-xpu-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xd>; | |
| linux,phandle = <0x144>; | |
| phandle = <0x144>; | |
| }; | |
| slv-mmss-clk-cfg { | |
| cell-id = <0x257>; | |
| label = "slv-mmss-clk-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xc>; | |
| linux,phandle = <0x141>; | |
| phandle = <0x141>; | |
| }; | |
| slv-mnoc-mpu-cfg { | |
| cell-id = <0x259>; | |
| label = "slv-mnoc-mpu-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xe>; | |
| linux,phandle = <0x142>; | |
| phandle = <0x142>; | |
| }; | |
| slv-display-cfg { | |
| cell-id = <0x24e>; | |
| label = "slv-display-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0x4>; | |
| linux,phandle = <0x140>; | |
| phandle = <0x140>; | |
| }; | |
| slv-csi-phy-cfg { | |
| cell-id = <0x2e6>; | |
| label = "slv-csi-phy-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xe0>; | |
| linux,phandle = <0x13e>; | |
| phandle = <0x13e>; | |
| }; | |
| slv-display-throttle-cfg { | |
| cell-id = <0x2bc>; | |
| label = "slv-display-throttle-cfg"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0x9c>; | |
| linux,phandle = <0x13f>; | |
| phandle = <0x13f>; | |
| }; | |
| slv-smmu-cfg { | |
| cell-id = <0x2d2>; | |
| label = "slv-smmu-cfg"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0xcd>; | |
| linux,phandle = <0x13c>; | |
| phandle = <0x13c>; | |
| }; | |
| slv-mnoc-bimc { | |
| cell-id = <0x272c>; | |
| label = "slv-mnoc-bimc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x2>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x148>; | |
| qcom,connections = <0x15b>; | |
| qcom,slv-rpm-id = <0x10>; | |
| qcom,enable-only-clk; | |
| clock-names = "node_clk"; | |
| clocks = <0x26 0x3c>; | |
| linux,phandle = <0x147>; | |
| phandle = <0x147>; | |
| }; | |
| slv-srvc-mnoc { | |
| cell-id = <0x25b>; | |
| label = "slv-srvc-mnoc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x145>; | |
| qcom,slv-rpm-id = <0x11>; | |
| linux,phandle = <0x146>; | |
| phandle = <0x146>; | |
| }; | |
| slv-hmss { | |
| cell-id = <0x2a1>; | |
| label = "slv-hmss"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0x14>; | |
| linux,phandle = <0x151>; | |
| phandle = <0x151>; | |
| }; | |
| slv-lpass { | |
| cell-id = <0x20a>; | |
| label = "slv-lpass"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0x15>; | |
| linux,phandle = <0x150>; | |
| phandle = <0x150>; | |
| }; | |
| slv-wlan { | |
| cell-id = <0x2d3>; | |
| label = "slv-wlan"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0xce>; | |
| linux,phandle = <0x153>; | |
| phandle = <0x153>; | |
| }; | |
| slv-cdsp { | |
| cell-id = <0x2e3>; | |
| label = "slv-cdsp"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0xdd>; | |
| linux,phandle = <0x152>; | |
| phandle = <0x152>; | |
| }; | |
| slv-ipa { | |
| cell-id = <0x2a4>; | |
| label = "slv-ipa"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,ap-owned; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0xb7>; | |
| linux,phandle = <0x14e>; | |
| phandle = <0x14e>; | |
| }; | |
| slv-snoc-bimc { | |
| cell-id = <0x2730>; | |
| label = "slv-snoc-bimc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,connections = <0x15c>; | |
| qcom,slv-rpm-id = <0x18>; | |
| linux,phandle = <0x14b>; | |
| phandle = <0x14b>; | |
| }; | |
| slv-snoc-cnoc { | |
| cell-id = <0x2734>; | |
| label = "slv-snoc-cnoc"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,connections = <0x15d>; | |
| qcom,slv-rpm-id = <0x19>; | |
| linux,phandle = <0x10e>; | |
| phandle = <0x10e>; | |
| }; | |
| slv-imem { | |
| cell-id = <0x249>; | |
| label = "slv-imem"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0x1a>; | |
| linux,phandle = <0x14a>; | |
| phandle = <0x14a>; | |
| }; | |
| slv-pimem { | |
| cell-id = <0x2c8>; | |
| label = "slv-pimem"; | |
| qcom,buswidth = <0x8>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0xa6>; | |
| linux,phandle = <0x149>; | |
| phandle = <0x149>; | |
| }; | |
| slv-qdss-stm { | |
| cell-id = <0x24c>; | |
| label = "slv-qdss-stm"; | |
| qcom,buswidth = <0x4>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0x1e>; | |
| linux,phandle = <0x14f>; | |
| phandle = <0x14f>; | |
| }; | |
| slv-srvc-snoc { | |
| cell-id = <0x24b>; | |
| label = "slv-srvc-snoc"; | |
| qcom,buswidth = <0x10>; | |
| qcom,agg-ports = <0x1>; | |
| qcom,bus-dev = <0x14c>; | |
| qcom,slv-rpm-id = <0x1d>; | |
| linux,phandle = <0x14d>; | |
| phandle = <0x14d>; | |
| }; | |
| }; | |
| devfreq_spdm_cpu { | |
| compatible = "qcom,devfreq_spdm"; | |
| qcom,msm-bus,name = "devfreq_spdm"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x1 0x200 0x0 0x0 0x1 0x200 0x0 0x0>; | |
| qcom,msm-bus,active-only; | |
| qcom,spdm-client = <0x0>; | |
| qcom,bw-upstep = <0x1c2>; | |
| qcom,bw-dwnstep = <0x2008>; | |
| qcom,max-vote = <0x2008>; | |
| qcom,up-step-multp = <0x2>; | |
| qcom,spdm-interval = <0x1e>; | |
| qcom,ports = <0x18>; | |
| qcom,alpha-up = <0x8>; | |
| qcom,alpha-down = <0xf>; | |
| qcom,bucket-size = <0x8>; | |
| qcom,pl-freqs = <0x33450 0x94ed0>; | |
| qcom,reject-rate = <0x1388 0x1388 0x1388 0x1388 0x1388 0x1388>; | |
| qcom,response-time-us = <0x1388 0x1388 0x1388 0x1388 0x1388 0x1388>; | |
| qcom,cci-response-time-us = <0x2710 0x2710 0x2710 0x2710 0x2710 0x2710>; | |
| qcom,max-cci-freq = <0xfd200>; | |
| }; | |
| devfreq_spdm_gov { | |
| compatible = "qcom,gov_spdm_hyp"; | |
| interrupt-names = "spdm-irq"; | |
| interrupts = <0x0 0xc0 0x1>; | |
| }; | |
| regulator@01fcf004 { | |
| compatible = "qcom,mem-acc-regulator"; | |
| reg = <0x1fcf004 0x4>; | |
| reg-names = "acc-sel-l1"; | |
| regulator-name = "gfx_mem_acc_corner"; | |
| regulator-min-microvolt = <0x1>; | |
| regulator-max-microvolt = <0x2>; | |
| qcom,corner-acc-map = <0x1 0x0>; | |
| qcom,acc-sel-l1-bit-pos = <0x0>; | |
| qcom,acc-sel-l1-bit-size = <0x1>; | |
| linux,phandle = <0x160>; | |
| phandle = <0x160>; | |
| }; | |
| ldo@0506e000 { | |
| compatible = "qcom,sdm660-gfx-ldo"; | |
| reg = <0x506e000 0x34>; | |
| reg-names = "ldo_addr"; | |
| regulator-name = "msm_gfx_ldo"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-max-microvolt = <0xe1d48>; | |
| linux,phandle = <0x161>; | |
| phandle = <0x161>; | |
| }; | |
| cpr4-ctrl@05061000 { | |
| compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator"; | |
| reg = <0x5061000 0x4000 0x784000 0x1000>; | |
| reg-names = "cpr_ctrl", "fuse_base"; | |
| clocks = <0x15e 0x1 0x26 0x1e>; | |
| clock-names = "core_clk", "bus_clk"; | |
| interrupts = <0x0 0x11d 0x1>; | |
| interrupt-names = "cpr"; | |
| qcom,cpr-ctrl-name = "gfx"; | |
| qcom,cpr-sensor-time = <0x3e8>; | |
| qcom,cpr-loop-time = <0x4c4b40>; | |
| qcom,cpr-idle-cycles = <0xf>; | |
| qcom,cpr-step-quot-init-min = <0xc>; | |
| qcom,cpr-step-quot-init-max = <0xe>; | |
| qcom,cpr-count-mode = <0x0>; | |
| qcom,cpr-count-repeat = <0xe>; | |
| qcom,cpr-reset-step-quot-loop-en; | |
| vdd-supply = <0x15f>; | |
| mem-acc-supply = <0x160>; | |
| system-supply = <0xc6>; | |
| qcom,voltage-step = <0x1388>; | |
| vdd-thread0-ldo-supply = <0x161>; | |
| linux,phandle = <0x359>; | |
| phandle = <0x359>; | |
| thread@0 { | |
| qcom,cpr-thread-id = <0x0>; | |
| qcom,cpr-consecutive-up = <0x0>; | |
| qcom,cpr-consecutive-down = <0x2>; | |
| qcom,cpr-up-threshold = <0x2>; | |
| qcom,cpr-down-threshold = <0x2>; | |
| regulator { | |
| regulator-name = "gfx_corner"; | |
| regulator-min-microvolt = <0x1>; | |
| regulator-max-microvolt = <0x7>; | |
| qcom,cpr-fuse-corners = <0x6>; | |
| qcom,cpr-fuse-combos = <0x8>; | |
| qcom,cpr-corners = <0x7>; | |
| qcom,cpr-corner-fmax-map = <0x1 0x2 0x3 0x4 0x5 0x6>; | |
| qcom,cpr-voltage-ceiling = <0x8ed28 0x9d788 0xb1008 0xc0df0 0xd4670 0xe1d48 0x1053b0>; | |
| qcom,cpr-voltage-floor = <0x7b0c0 0x7b0c0 0x91820 0x9f2e0 0xadd40 0xb5a40 0x1053b0>; | |
| qcom,mem-acc-voltage = <0x1 0x1 0x1 0x2 0x2 0x2 0x2>; | |
| qcom,system-voltage = <0x40 0x40 0x80 0xc0 0x100 0x140 0x180>; | |
| qcom,corner-frequencies = <0x9896800 0xfdad680 0x160dc080 0x1bb75640 0x230c2b00 0x26906fc0 0x2cb41780>; | |
| qcom,cpr-target-quotients = <0x0 0x0 0x0 0x0 0x0 0x0 0xae 0xa7 0x126 0x124 0x12f 0x139 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x107 0xf7 0x19d 0x18d 0x19f 0x19c 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x177 0x162 0x22a 0x207 0x23d 0x22a 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x19c 0x17c 0x255 0x232 0x264 0x24f 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x201 0x1dc 0x2d2 0x2a8 0x2e2 0x2ce 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x253 0x229 0x32b 0x300 0x345 0x32b 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| qcom,cpr-ro-scaling-factor = <0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6fe 0x6e0 0x7c6 0x76c 0x85c 0x7e4 0x0 0x0 0x0 0x0>; | |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
| qcom,cpr-corner-allow-ldo-mode = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| qcom,cpr-corner-allow-closed-loop = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| linux,phandle = <0xaa>; | |
| phandle = <0xaa>; | |
| }; | |
| }; | |
| }; | |
| cprh-ctrl@179c8000 { | |
| compatible = "qcom,cprh-sdm660-kbss-regulator"; | |
| reg = <0x179c8000 0x4000 0x784000 0x1000>; | |
| reg-names = "cpr_ctrl", "fuse_base"; | |
| clocks = <0xa1 0x48>; | |
| clock-names = "core_clk"; | |
| qcom,cpr-ctrl-name = "apc0"; | |
| qcom,cpr-controller-id = <0x0>; | |
| qcom,cpr-sensor-time = <0x3e8>; | |
| qcom,cpr-loop-time = <0x4c4b40>; | |
| qcom,cpr-idle-cycles = <0xf>; | |
| qcom,cpr-up-down-delay-time = <0xbb8>; | |
| qcom,cpr-step-quot-init-min = <0xc>; | |
| qcom,cpr-step-quot-init-max = <0xe>; | |
| qcom,cpr-count-mode = <0x0>; | |
| qcom,cpr-count-repeat = <0xe>; | |
| qcom,cpr-down-error-step-limit = <0x1>; | |
| qcom,cpr-up-error-step-limit = <0x1>; | |
| qcom,cpr-corner-switch-delay-time = <0x412>; | |
| qcom,cpr-voltage-settling-time = <0x6e0>; | |
| qcom,apm-threshold-voltage = <0xd4e40>; | |
| qcom,apm-crossover-voltage = <0xd4e40>; | |
| qcom,apm-hysteresis-voltage = <0x4e20>; | |
| qcom,voltage-step = <0xfa0>; | |
| qcom,voltage-base = <0x61a80>; | |
| qcom,cpr-saw-use-unit-mV; | |
| qcom,cpr-reset-step-quot-loop-en; | |
| qcom,cpr-panic-reg-addr-list = <0x179cbaa4 0x17912c18>; | |
| qcom,cpr-panic-reg-name-list = "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; | |
| qcom,cpr-enable; | |
| qcom,cpr-hw-closed-loop; | |
| linux,phandle = <0x35a>; | |
| phandle = <0x35a>; | |
| thread@0 { | |
| qcom,cpr-thread-id = <0x0>; | |
| qcom,cpr-consecutive-up = <0x0>; | |
| qcom,cpr-consecutive-down = <0x2>; | |
| qcom,cpr-up-threshold = <0x2>; | |
| qcom,cpr-down-threshold = <0x2>; | |
| regulator { | |
| regulator-name = "apc0_pwrcl_corner"; | |
| regulator-min-microvolt = <0x1>; | |
| regulator-max-microvolt = <0x8>; | |
| qcom,cpr-fuse-corners = <0x5>; | |
| qcom,cpr-fuse-combos = <0x28>; | |
| qcom,cpr-speed-bins = <0x5>; | |
| qcom,cpr-speed-bin-corners = <0x8 0x8 0x0 0x8 0x8>; | |
| qcom,cpr-corners = <0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8>; | |
| qcom,cpr-corner-fmax-map = <0x2 0x3 0x4 0x5 0x8 0x2 0x3 0x4 0x5 0x8 0x0 0x0 0x0 0x0 0x0 0x2 0x3 0x4 0x5 0x8 0x2 0x3 0x4 0x5 0x8>; | |
| qcom,cpr-voltage-ceiling = <0xb0c20 0xb0c20 0xb0c20 0xc0620 0xd3ea0 0x104be0 0x104be0 0x104be0>; | |
| qcom,cpr-voltage-floor = <0x8f8e0 0x8f8e0 0x91820 0x9f2e0 0xadd40 0xb5a40 0xbf680 0xce0e0>; | |
| qcom,corner-frequencies = <0x11e1a300 0x25c3f800 0x35c98800 0x42603000 0x538ab800 0x5b8d8000 0x68242800 0x6ddd0000 0x11e1a300 0x25c3f800 0x35c98800 0x42603000 0x538ab800 0x5b8d8000 0x68242800 0x6ddd0000 0x11e1a300 0x25c3f800 0x35c98800 0x42603000 0x538ab800 0x5b8d8000 0x60216000 0x6ddd0000 0x11e1a300 0x25c3f800 0x35c98800 0x42603000 0x538ab800 0x5b8d8000 0x68242800 0x6ddd0000>; | |
| qcom,allow-voltage-interpolation; | |
| qcom,allow-quotient-interpolation; | |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
| qcom,cpr-ro-scaling-factor = <0xe10 0xe10 0xef6 0x97e 0x9d8 0xa8c 0x6fe 0x6e0 0x7b2 0x758 0x83e 0x7da 0x9ce 0x1324 0x1112 0x12ac 0xe10 0xe10 0xef6 0x97e 0x9d8 0xa8c 0x6fe 0x6e0 0x7b2 0x758 0x83e 0x7da 0x9ce 0x1324 0x1112 0x12ac 0xe10 0xe10 0xef6 0x97e 0x9d8 0xa8c 0x6fe 0x6e0 0x7b2 0x758 0x83e 0x7da 0x9ce 0x1324 0x1112 0x12ac 0xe10 0xe10 0xef6 0x97e 0x9d8 0xa8c 0x6fe 0x6e0 0x7b2 0x758 0x83e 0x7da 0x9ce 0x1324 0x1112 0x12ac 0xe10 0xe10 0xef6 0x97e 0x9d8 0xa8c 0x6fe 0x6e0 0x7b2 0x758 0x83e 0x7da 0x9ce 0x1324 0x1112 0x12ac>; | |
| qcom,cpr-open-loop-voltage-fuse-adjustment = <0xfffff060 0xfa0 0x1b58 0x4a38 0xffffe0c0>; | |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = <0xffff8300 0xffff8ad0 0xffff8eb8 0xffffa628 0xffffadf8>; | |
| qcom,cpr-floor-to-ceiling-max-range = <0x7d00 0x7d00 0x7d00 0x9c40 0xabe0 0x9c40 0x9c40 0x9c40>; | |
| linux,phandle = <0xd1>; | |
| phandle = <0xd1>; | |
| }; | |
| }; | |
| }; | |
| cprh-ctrl@179c4000 { | |
| compatible = "qcom,cprh-sdm660-kbss-regulator"; | |
| reg = <0x179c4000 0x4000 0x784000 0x1000>; | |
| reg-names = "cpr_ctrl", "fuse_base"; | |
| clocks = <0xa1 0x48>; | |
| clock-names = "core_clk"; | |
| qcom,cpr-ctrl-name = "apc1"; | |
| qcom,cpr-controller-id = <0x1>; | |
| qcom,cpr-sensor-time = <0x3e8>; | |
| qcom,cpr-loop-time = <0x4c4b40>; | |
| qcom,cpr-idle-cycles = <0xf>; | |
| qcom,cpr-up-down-delay-time = <0xbb8>; | |
| qcom,cpr-step-quot-init-min = <0xc>; | |
| qcom,cpr-step-quot-init-max = <0xe>; | |
| qcom,cpr-count-mode = <0x0>; | |
| qcom,cpr-count-repeat = <0xe>; | |
| qcom,cpr-down-error-step-limit = <0x1>; | |
| qcom,cpr-up-error-step-limit = <0x1>; | |
| qcom,cpr-corner-switch-delay-time = <0x412>; | |
| qcom,cpr-voltage-settling-time = <0x6e0>; | |
| qcom,apm-threshold-voltage = <0xd4e40>; | |
| qcom,apm-crossover-voltage = <0xd4e40>; | |
| qcom,apm-hysteresis-voltage = <0x4e20>; | |
| qcom,voltage-step = <0xfa0>; | |
| qcom,voltage-base = <0x61a80>; | |
| qcom,cpr-saw-use-unit-mV; | |
| qcom,cpr-reset-step-quot-loop-en; | |
| qcom,cpr-panic-reg-addr-list = <0x179c7aa4 0x17812c18>; | |
| qcom,cpr-panic-reg-name-list = "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; | |
| qcom,cpr-enable; | |
| qcom,cpr-hw-closed-loop; | |
| linux,phandle = <0x35b>; | |
| phandle = <0x35b>; | |
| thread@0 { | |
| qcom,cpr-thread-id = <0x0>; | |
| qcom,cpr-consecutive-up = <0x0>; | |
| qcom,cpr-consecutive-down = <0x2>; | |
| qcom,cpr-up-threshold = <0x2>; | |
| qcom,cpr-down-threshold = <0x2>; | |
| regulator { | |
| regulator-name = "apc1_perfcl_corner"; | |
| regulator-min-microvolt = <0x1>; | |
| regulator-max-microvolt = <0x7>; | |
| qcom,cpr-fuse-corners = <0x5>; | |
| qcom,cpr-fuse-combos = <0x28>; | |
| qcom,cpr-speed-bins = <0x5>; | |
| qcom,cpr-speed-bin-corners = <0x7 0x7 0x0 0x7 0x7>; | |
| qcom,cpr-corners = <0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7>; | |
| qcom,cpr-corner-fmax-map = <0x2 0x3 0x4 0x6 0x7 0x2 0x3 0x4 0x6 0x7 0x0 0x0 0x0 0x0 0x0 0x2 0x3 0x4 0x6 0x7 0x2 0x3 0x4 0x6 0x7>; | |
| qcom,cpr-voltage-ceiling = <0xb0c20 0xb0c20 0xc0620 0xd3ea0 0xf1360 0xf1360 0x104be0>; | |
| qcom,cpr-voltage-floor = <0x8f8e0 0x91820 0x9f2e0 0xadd40 0xb5a40 0xbf680 0xce0e0>; | |
| qcom,corner-frequencies = <0x11e1a300 0x42603000 0x538ab800 0x68242800 0x74bad000 0x802c8000 0x927c0000 0x11e1a300 0x42603000 0x538ab800 0x68242800 0x74bad000 0x802c8000 0x839b6800 0x11e1a300 0x42603000 0x538ab800 0x68242800 0x6b931000 0x802c8000 0x839b6800 0x11e1a300 0x42603000 0x538ab800 0x68242800 0x74bad000 0x802c8000 0x839b6800>; | |
| qcom,allow-voltage-interpolation; | |
| qcom,allow-quotient-interpolation; | |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; | |
| qcom,cpr-ro-scaling-factor = <0xfc8 0x1086 0x0 0x8a2 0xa00 0x992 0x8b6 0x8ac 0x96a 0x8fc 0xa00 0x9a6 0x640 0xc30 0xa3c 0x8e8 0xfc8 0x1086 0x0 0x8a2 0xa00 0x992 0x8b6 0x8ac 0x96a 0x8fc 0xa00 0x9a6 0x640 0xc30 0xa3c 0x8e8 0xfc8 0x1086 0x0 0x8a2 0xa00 0x992 0x8b6 0x8ac 0x96a 0x8fc 0xa00 0x9a6 0x640 0xc30 0xa3c 0x8e8 0xfc8 0x1086 0x0 0x8a2 0xa00 0x992 0x8b6 0x8ac 0x96a 0x8fc 0xa00 0x9a6 0x640 0xc30 0xa3c 0x8e8 0xfc8 0x1086 0x0 0x8a2 0xa00 0x992 0x8b6 0x8ac 0x96a 0x8fc 0xa00 0x9a6 0x640 0xc30 0xa3c 0x8e8>; | |
| qcom,cpr-open-loop-voltage-fuse-adjustment = <0x3e80 0x6978 0x9858 0x9858 0x4e20>; | |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = <0xffffaa10 0xffffdcd8 0xffffe4a8 0xfffff830 0x2af8>; | |
| qcom,cpr-floor-to-ceiling-max-range = <0x9c40 0x9c40 0x9c40 0x9c40 0x101d0 0x101d0 0x9c40>; | |
| linux,phandle = <0xd2>; | |
| phandle = <0xd2>; | |
| }; | |
| }; | |
| }; | |
| qcom,gdsc@10f004 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_usb30"; | |
| reg = <0x10f004 0x4>; | |
| status = "ok"; | |
| linux,phandle = <0x174>; | |
| phandle = <0x174>; | |
| }; | |
| qcom,gdsc@175004 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_ufs"; | |
| reg = <0x175004 0x4>; | |
| status = "ok"; | |
| linux,phandle = <0x108>; | |
| phandle = <0x108>; | |
| }; | |
| qcom,gdsc@17d034 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_hlos1_vote_lpass_adsp"; | |
| reg = <0x17d034 0x4>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| status = "ok"; | |
| linux,phandle = <0x171>; | |
| phandle = <0x171>; | |
| }; | |
| qcom,gdsc@17d04c { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_hlos1_vote_turing_adsp"; | |
| reg = <0x17d04c 0x4>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| status = "ok"; | |
| linux,phandle = <0x172>; | |
| phandle = <0x172>; | |
| }; | |
| qcom,gdsc@17e04c { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_hlos2_vote_turing_adsp"; | |
| reg = <0x17e04c 0x4>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| status = "ok"; | |
| linux,phandle = <0x35c>; | |
| phandle = <0x35c>; | |
| }; | |
| syscon@c8ce024 { | |
| compatible = "syscon"; | |
| reg = <0xc8ce024 0x4>; | |
| linux,phandle = <0x162>; | |
| phandle = <0x162>; | |
| }; | |
| qcom,gdsc@c8ce020 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_bimc_smmu"; | |
| reg = <0xc8ce020 0x4>; | |
| hw-ctrl-addr = <0x162>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x1f4>; | |
| status = "ok"; | |
| clock-names = "bus_clk"; | |
| clocks = <0x74 0x58>; | |
| proxy-supply = <0x163>; | |
| qcom,proxy-consumer-enable; | |
| linux,phandle = <0x163>; | |
| phandle = <0x163>; | |
| }; | |
| qcom,gdsc@c8c1024 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_venus"; | |
| reg = <0xc8c1024 0x4>; | |
| status = "ok"; | |
| linux,phandle = <0xf3>; | |
| phandle = <0xf3>; | |
| }; | |
| qcom,gdsc@c8c1040 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_venus_core0"; | |
| reg = <0xc8c1040 0x4>; | |
| status = "ok"; | |
| qcom,support-hw-trigger; | |
| linux,phandle = <0x1e5>; | |
| phandle = <0x1e5>; | |
| }; | |
| qcom,gdsc@c8c34a0 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_camss_top"; | |
| reg = <0xc8c34a0 0x4>; | |
| status = "ok"; | |
| linux,phandle = <0x164>; | |
| phandle = <0x164>; | |
| }; | |
| qcom,gdsc@c8c3664 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_vfe0"; | |
| reg = <0xc8c3664 0x4>; | |
| status = "ok"; | |
| parent-supply = <0x164>; | |
| linux,phandle = <0x1c5>; | |
| phandle = <0x1c5>; | |
| }; | |
| qcom,gdsc@c8c3674 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_vfe1"; | |
| reg = <0xc8c3674 0x4>; | |
| status = "ok"; | |
| parent-supply = <0x164>; | |
| linux,phandle = <0x1c6>; | |
| phandle = <0x1c6>; | |
| }; | |
| qcom,gdsc@c8c36d4 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_cpp"; | |
| reg = <0xc8c36d4 0x4>; | |
| status = "ok"; | |
| parent-supply = <0x164>; | |
| qcom,support-hw-trigger; | |
| linux,phandle = <0x1c4>; | |
| phandle = <0x1c4>; | |
| }; | |
| qcom,gdsc@c8c2304 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_mdss"; | |
| reg = <0xc8c2304 0x4>; | |
| status = "ok"; | |
| proxy-supply = <0x165>; | |
| qcom,proxy-consumer-enable; | |
| linux,phandle = <0x165>; | |
| phandle = <0x165>; | |
| }; | |
| syscon@5066008 { | |
| compatible = "syscon"; | |
| reg = <0x5066008 0x4>; | |
| linux,phandle = <0x166>; | |
| phandle = <0x166>; | |
| }; | |
| qcom,gdsc@5066004 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_gpu_cx"; | |
| reg = <0x5066004 0x4>; | |
| hw-ctrl-addr = <0x166>; | |
| qcom,no-status-check-on-disable; | |
| qcom,gds-timeout = <0x7d0>; | |
| status = "ok"; | |
| linux,phandle = <0x16b>; | |
| phandle = <0x16b>; | |
| }; | |
| syscon@5065130 { | |
| compatible = "syscon"; | |
| reg = <0x5065130 0x4>; | |
| linux,phandle = <0x167>; | |
| phandle = <0x167>; | |
| }; | |
| syscon@5066090 { | |
| compatible = "syscon"; | |
| reg = <0x5066090 0x4>; | |
| linux,phandle = <0x168>; | |
| phandle = <0x168>; | |
| }; | |
| qcom,gdsc@5066094 { | |
| compatible = "qcom,gdsc"; | |
| regulator-name = "gdsc_gpu_gx"; | |
| reg = <0x5066094 0x4>; | |
| domain-addr = <0x167>; | |
| sw-reset = <0x168>; | |
| qcom,retain-periph; | |
| qcom,reset-aon-logic; | |
| status = "ok"; | |
| clock-names = "core_root_clk"; | |
| clocks = <0x169 0xc>; | |
| qcom,force-enable-root-clk; | |
| parent-supply = <0xaa>; | |
| linux,phandle = <0x16c>; | |
| phandle = <0x16c>; | |
| }; | |
| qcom,kgsl-hyp { | |
| compatible = "qcom,pil-tz-generic"; | |
| qcom,pas-id = <0xd>; | |
| qcom,firmware-name = "a512_zap"; | |
| linux,phandle = <0x35d>; | |
| phandle = <0x35d>; | |
| }; | |
| qcom,kgsl-busmon { | |
| label = "kgsl-busmon"; | |
| compatible = "qcom,kgsl-busmon"; | |
| linux,phandle = <0x35e>; | |
| phandle = <0x35e>; | |
| }; | |
| qcom,gpubw { | |
| compatible = "qcom,devbw"; | |
| governor = "bw_vbif"; | |
| qcom,src-dst-ports = <0x1a 0x200>; | |
| qcom,active-only; | |
| qcom,bw-tbl = <0x0 0x17d 0x23c 0x2fa 0x478 0x623 0x826 0xa25 0xb71 0xf27 0x134f 0x1429 0x172b 0x1ae1>; | |
| linux,phandle = <0x16a>; | |
| phandle = <0x16a>; | |
| }; | |
| qcom,kgsl-3d0@5000000 { | |
| label = "kgsl-3d0"; | |
| compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; | |
| status = "ok"; | |
| reg = <0x5000000 0x40000 0x780000 0x6220>; | |
| reg-names = "kgsl_3d0_reg_memory", "qfprom_memory"; | |
| interrupts = <0x0 0x12c 0x0>; | |
| interrupt-names = "kgsl_3d0_irq"; | |
| qcom,id = <0x0>; | |
| qcom,chipid = <0x5010200>; | |
| qcom,initial-pwrlevel = <0x6>; | |
| qcom,idle-timeout = <0x50>; | |
| qcom,highest-bank-bit = <0xe>; | |
| qcom,snapshot-size = <0x100000>; | |
| clocks = <0x169 0xd 0xa1 0x42 0x169 0xe 0xa1 0x40 0xa1 0x20 0x15e 0x1>; | |
| clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk", "alt_mem_iface_clk", "rbcpr_clk"; | |
| qcom,gpubw-dev = <0x16a>; | |
| qcom,bus-control; | |
| qcom,bus-width = <0x20>; | |
| qcom,msm-bus,name = "grp3d"; | |
| qcom,msm-bus,num-cases = <0xe>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x1a 0x200 0x0 0x0 0x1a 0x200 0x0 0x61a80 0x1a 0x200 0x0 0x927c0 0x1a 0x200 0x0 0xc3500 0x1a 0x200 0x0 0x124f80 0x1a 0x200 0x0 0x192580 0x1a 0x200 0x0 0x2162e0 0x1a 0x200 0x0 0x2990a0 0x1a 0x200 0x0 0x2ee000 0x1a 0x200 0x0 0x3e12a0 0x1a 0x200 0x0 0x4f1a00 0x1a 0x200 0x0 0x5294a0 0x1a 0x200 0x0 0x5ee8e0 0x1a 0x200 0x0 0x6e1b80>; | |
| regulator-names = "vddcx", "vdd"; | |
| vddcx-supply = <0x16b>; | |
| vdd-supply = <0x16c>; | |
| qcom,gpu-cx-ipeak = <0x16d 0x1>; | |
| qcom,gpu-cx-ipeak-clk = <0x29b92700>; | |
| qcom,pm-qos-active-latency = <0x206>; | |
| qcom,pm-qos-wakeup-latency = <0x206>; | |
| qcom,gpu-quirk-dp2clockgating-disable; | |
| qcom,gpu-quirk-lmloadkill-disable; | |
| qcom,enable-ca-jump; | |
| qcom,ca-busy-penalty = <0x2ee0>; | |
| qcom,ca-target-pwrlevel = <0x4>; | |
| qcom,gpu-speed-bin = <0x41a0 0x1fe00000 0x15>; | |
| linux,phandle = <0x35f>; | |
| phandle = <0x35f>; | |
| qcom,gpu-mempools { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "qcom,gpu-mempools"; | |
| qcom,mempool-max-pages = <0x8000>; | |
| qcom,gpu-mempool@0 { | |
| reg = <0x0>; | |
| qcom,mempool-page-size = <0x1000>; | |
| }; | |
| qcom,gpu-mempool@1 { | |
| reg = <0x1>; | |
| qcom,mempool-page-size = <0x10000>; | |
| qcom,mempool-allocate; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevel-bins { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "qcom,gpu-pwrlevel-bins"; | |
| qcom,gpu-pwrlevels-0 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x0>; | |
| qcom,initial-pwrlevel = <0x6>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x2cb41780>; | |
| qcom,bus-freq = <0xd>; | |
| qcom,bus-min = <0xc>; | |
| qcom,bus-max = <0xd>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = <0x29b92700>; | |
| qcom,bus-freq = <0xb>; | |
| qcom,bus-min = <0xb>; | |
| qcom,bus-max = <0xd>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = <0x26906fc0>; | |
| qcom,bus-freq = <0xb>; | |
| qcom,bus-min = <0xa>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = "#\f+"; | |
| qcom,bus-freq = <0xa>; | |
| qcom,bus-min = <0x9>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x4>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| qcom,bus-freq = <0x9>; | |
| qcom,bus-min = <0x8>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| reg = <0x5>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0x9>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| reg = <0x6>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| reg = <0x7>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@8 { | |
| reg = <0x8>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-1 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x9d>; | |
| qcom,initial-pwrlevel = <0x6>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x2cb41780>; | |
| qcom,bus-freq = <0xd>; | |
| qcom,bus-min = <0xc>; | |
| qcom,bus-max = <0xd>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = <0x29b92700>; | |
| qcom,bus-freq = <0xb>; | |
| qcom,bus-min = <0xb>; | |
| qcom,bus-max = <0xd>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = <0x26906fc0>; | |
| qcom,bus-freq = <0xb>; | |
| qcom,bus-min = <0xa>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = "#\f+"; | |
| qcom,bus-freq = <0xa>; | |
| qcom,bus-min = <0x9>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x4>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| qcom,bus-freq = <0x9>; | |
| qcom,bus-min = <0x8>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| reg = <0x5>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0x9>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| reg = <0x6>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| reg = <0x7>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@8 { | |
| reg = <0x8>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-2 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x92>; | |
| qcom,initial-pwrlevel = <0x5>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x29b92700>; | |
| qcom,bus-freq = <0xd>; | |
| qcom,bus-min = <0xc>; | |
| qcom,bus-max = <0xd>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = <0x26906fc0>; | |
| qcom,bus-freq = <0xb>; | |
| qcom,bus-min = <0xa>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = "#\f+"; | |
| qcom,bus-freq = <0xa>; | |
| qcom,bus-min = <0x9>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| qcom,bus-freq = <0x9>; | |
| qcom,bus-min = <0x8>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x4>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0x9>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| reg = <0x5>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| reg = <0x6>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@7 { | |
| reg = <0x7>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-3 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x87>; | |
| qcom,initial-pwrlevel = <0x4>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x26906fc0>; | |
| qcom,bus-freq = <0xd>; | |
| qcom,bus-min = <0xc>; | |
| qcom,bus-max = <0xd>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = "#\f+"; | |
| qcom,bus-freq = <0xa>; | |
| qcom,bus-min = <0x9>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| qcom,bus-freq = <0x9>; | |
| qcom,bus-min = <0x8>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0x9>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x4>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| reg = <0x5>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@6 { | |
| reg = <0x6>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-4 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x4e>; | |
| qcom,initial-pwrlevel = <0x1>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-5 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x5a>; | |
| qcom,initial-pwrlevel = <0x2>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x19a14780>; | |
| qcom,bus-freq = <0xb>; | |
| qcom,bus-min = <0xa>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x4>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| qcom,gpu-pwrlevels-6 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,speed-bin = <0x7a>; | |
| qcom,initial-pwrlevel = <0x3>; | |
| qcom,gpu-pwrlevel@0 { | |
| reg = <0x0>; | |
| qcom,gpu-freq = <0x22de6440>; | |
| qcom,bus-freq = <0xc>; | |
| qcom,bus-min = <0xb>; | |
| qcom,bus-max = <0xc>; | |
| }; | |
| qcom,gpu-pwrlevel@1 { | |
| reg = <0x1>; | |
| qcom,gpu-freq = <0x1bb75640>; | |
| qcom,bus-freq = <0x9>; | |
| qcom,bus-min = <0x8>; | |
| qcom,bus-max = <0xb>; | |
| }; | |
| qcom,gpu-pwrlevel@2 { | |
| reg = <0x2>; | |
| qcom,gpu-freq = <0x160dc080>; | |
| qcom,bus-freq = <0x8>; | |
| qcom,bus-min = <0x6>; | |
| qcom,bus-max = <0x9>; | |
| }; | |
| qcom,gpu-pwrlevel@3 { | |
| reg = <0x3>; | |
| qcom,gpu-freq = <0xfdad680>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x6>; | |
| }; | |
| qcom,gpu-pwrlevel@4 { | |
| reg = <0x4>; | |
| qcom,gpu-freq = <0x9896800>; | |
| qcom,bus-freq = <0x3>; | |
| qcom,bus-min = <0x3>; | |
| qcom,bus-max = <0x5>; | |
| }; | |
| qcom,gpu-pwrlevel@5 { | |
| reg = <0x5>; | |
| qcom,gpu-freq = <0x124f800>; | |
| qcom,bus-freq = <0x0>; | |
| qcom,bus-min = <0x0>; | |
| qcom,bus-max = <0x0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,kgsl-iommu { | |
| compatible = "qcom,kgsl-smmu-v2"; | |
| reg = <0x5040000 0x10000>; | |
| qcom,protect = <0x40000 0x10000>; | |
| qcom,micro-mmu-control = <0x6000>; | |
| clocks = <0xa1 0x42 0xa1 0x40 0xa1 0x20>; | |
| clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk"; | |
| qcom,secure_align_mask = <0xfff>; | |
| qcom,retention; | |
| qcom,hyp_secure_alloc; | |
| linux,phandle = <0x360>; | |
| phandle = <0x360>; | |
| gfx3d_user { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| label = "gfx3d_user"; | |
| iommus = <0x16e 0x0>; | |
| qcom,gpu-offset = <0x48000>; | |
| linux,phandle = <0x361>; | |
| phandle = <0x361>; | |
| }; | |
| gfx3d_secure { | |
| compatible = "qcom,smmu-kgsl-cb"; | |
| iommus = <0x16e 0x2>; | |
| linux,phandle = <0x362>; | |
| phandle = <0x362>; | |
| }; | |
| }; | |
| qcom,spm@178120000 { | |
| compatible = "qcom,spm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| reg = <0x17812000 0x1000>; | |
| qcom,name = "gold-l2"; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| qcom,cpu-vctl-list = <0x17 0x18 0x19 0x1a>; | |
| qcom,vctl-timeout-us = <0x1f4>; | |
| qcom,vctl-port = <0x0>; | |
| qcom,phase-port = <0x1>; | |
| qcom,saw2-avs-ctl = <0x1010031>; | |
| qcom,saw2-avs-limit = <0x4580458>; | |
| qcom,pfm-port = <0x2>; | |
| }; | |
| qcom,spm@179120000 { | |
| compatible = "qcom,spm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| reg = <0x17912000 0x1000>; | |
| qcom,name = "silver-l2"; | |
| qcom,saw2-ver-reg = <0xfd0>; | |
| qcom,cpu-vctl-list = <0x13 0x14 0x15 0x16>; | |
| qcom,vctl-timeout-us = <0x1f4>; | |
| qcom,vctl-port = <0x0>; | |
| qcom,phase-port = <0x1>; | |
| qcom,saw2-avs-ctl = <0x1010031>; | |
| qcom,saw2-avs-limit = <0x4580458>; | |
| qcom,pfm-port = <0x2>; | |
| }; | |
| qcom,lpm-levels { | |
| compatible = "qcom,lpm-levels"; | |
| qcom,use-psci; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,pm-cluster@0 { | |
| reg = <0x0>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| label = "system"; | |
| qcom,spm-device-names = "cci"; | |
| qcom,psci-mode-shift = <0x8>; | |
| qcom,psci-mode-mask = <0xf>; | |
| qcom,pm-cluster-level@0 { | |
| reg = <0x0>; | |
| label = "system-wfi"; | |
| qcom,psci-mode = <0x0>; | |
| qcom,latency-us = <0x676>; | |
| qcom,ss-power = <0xdb>; | |
| qcom,energy-overhead = <0x181be>; | |
| qcom,time-overhead = <0x8f6>; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| reg = <0x1>; | |
| label = "system-pc"; | |
| qcom,psci-mode = <0x3>; | |
| qcom,latency-us = <0x119a>; | |
| qcom,ss-power = <0x58>; | |
| qcom,energy-overhead = <0x12bef8>; | |
| qcom,time-overhead = <0x3be9>; | |
| qcom,min-child-idx = <0x3>; | |
| qcom,is-reset; | |
| qcom,notify-rpm; | |
| }; | |
| qcom,pm-cluster@0 { | |
| reg = <0x0>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| label = "pwr"; | |
| qcom,spm-device-names = "l2"; | |
| qcom,cpu = <0x13 0x14 0x15 0x16>; | |
| qcom,psci-mode-shift = <0x4>; | |
| qcom,psci-mode-mask = <0xf>; | |
| qcom,pm-cluster-level@0 { | |
| reg = <0x0>; | |
| label = "pwr-l2-wfi"; | |
| qcom,psci-mode = <0x1>; | |
| qcom,latency-us = <0x33>; | |
| qcom,ss-power = <0xfa>; | |
| qcom,energy-overhead = <0x145fc>; | |
| qcom,time-overhead = <0x59>; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| reg = <0x1>; | |
| label = "pwr-l2-dynret"; | |
| qcom,psci-mode = <0x2>; | |
| qcom,latency-us = <0x1a5>; | |
| qcom,ss-power = <0xeb>; | |
| qcom,energy-overhead = <0x35918>; | |
| qcom,time-overhead = <0x30d>; | |
| qcom,min-child-idx = <0x1>; | |
| }; | |
| qcom,pm-cluster-level@2 { | |
| reg = <0x2>; | |
| label = "pwr-l2-ret"; | |
| qcom,psci-mode = <0x3>; | |
| qcom,latency-us = <0x205>; | |
| qcom,ss-power = <0xe2>; | |
| qcom,energy-overhead = <0x4918d>; | |
| qcom,time-overhead = <0x39a>; | |
| qcom,min-child-idx = <0x2>; | |
| }; | |
| qcom,pm-cluster-level@3 { | |
| reg = <0x3>; | |
| label = "pwr-l2-pc"; | |
| qcom,psci-mode = <0x4>; | |
| qcom,latency-us = <0x846>; | |
| qcom,ss-power = <0xd2>; | |
| qcom,energy-overhead = <0xcb620>; | |
| qcom,time-overhead = <0xb66>; | |
| qcom,min-child-idx = <0x2>; | |
| qcom,is-reset; | |
| }; | |
| qcom,pm-cpu { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,psci-mode-shift = <0x0>; | |
| qcom,psci-mode-mask = <0xf>; | |
| qcom,pm-cpu-level@0 { | |
| reg = <0x0>; | |
| qcom,spm-cpu-mode = "wfi"; | |
| qcom,psci-cpu-mode = <0x1>; | |
| qcom,latency-us = <0x2a>; | |
| qcom,ss-power = <0xfa>; | |
| qcom,energy-overhead = <0x7762>; | |
| qcom,time-overhead = <0x5b>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| reg = <0x1>; | |
| qcom,psci-cpu-mode = <0x2>; | |
| qcom,spm-cpu-mode = "ret"; | |
| qcom,latency-us = <0x3f>; | |
| qcom,ss-power = <0xf5>; | |
| qcom,energy-overhead = <0xc057>; | |
| qcom,time-overhead = <0xac>; | |
| }; | |
| qcom,pm-cpu-level@2 { | |
| reg = <0x2>; | |
| qcom,spm-cpu-mode = "pc"; | |
| qcom,psci-cpu-mode = <0x3>; | |
| qcom,latency-us = <0x178>; | |
| qcom,ss-power = <0xed>; | |
| qcom,energy-overhead = <0x2c31a>; | |
| qcom,time-overhead = <0x29a>; | |
| qcom,is-reset; | |
| }; | |
| }; | |
| }; | |
| qcom,pm-cluster@1 { | |
| reg = <0x1>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| label = "perf"; | |
| qcom,spm-device-names = "l2"; | |
| qcom,cpu = <0x17 0x18 0x19 0x1a>; | |
| qcom,psci-mode-shift = <0x4>; | |
| qcom,psci-mode-mask = <0xf>; | |
| qcom,pm-cluster-level@0 { | |
| reg = <0x0>; | |
| label = "perf-l2-wfi"; | |
| qcom,psci-mode = <0x1>; | |
| qcom,latency-us = <0x33>; | |
| qcom,ss-power = <0x11b>; | |
| qcom,energy-overhead = <0x1448b>; | |
| qcom,time-overhead = <0x59>; | |
| }; | |
| qcom,pm-cluster-level@1 { | |
| reg = <0x1>; | |
| label = "perf-l2-dynret"; | |
| qcom,psci-mode = <0x2>; | |
| qcom,latency-us = <0x159>; | |
| qcom,ss-power = <0xfe>; | |
| qcom,energy-overhead = <0x306cd>; | |
| qcom,time-overhead = <0x293>; | |
| qcom,min-child-idx = <0x1>; | |
| }; | |
| qcom,pm-cluster-level@2 { | |
| reg = <0x2>; | |
| label = "perf-l2-ret"; | |
| qcom,psci-mode = <0x3>; | |
| qcom,latency-us = <0x1a3>; | |
| qcom,ss-power = <0xf4>; | |
| qcom,energy-overhead = <0x44d41>; | |
| qcom,time-overhead = <0x2e1>; | |
| qcom,min-child-idx = <0x2>; | |
| }; | |
| qcom,pm-cluster-level@3 { | |
| reg = <0x3>; | |
| label = "perf-l2-pc"; | |
| qcom,psci-mode = <0x4>; | |
| qcom,latency-us = <0x676>; | |
| qcom,ss-power = <0xdb>; | |
| qcom,energy-overhead = <0xc71d5>; | |
| qcom,time-overhead = <0x8f6>; | |
| qcom,min-child-idx = <0x2>; | |
| qcom,is-reset; | |
| }; | |
| qcom,pm-cpu { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,psci-mode-shift = <0x0>; | |
| qcom,psci-mode-mask = <0xf>; | |
| qcom,pm-cpu-level@0 { | |
| reg = <0x0>; | |
| qcom,spm-cpu-mode = "wfi"; | |
| qcom,psci-cpu-mode = <0x1>; | |
| qcom,latency-us = <0x27>; | |
| qcom,ss-power = <0x124>; | |
| qcom,energy-overhead = <0x92b6>; | |
| qcom,time-overhead = <0x44>; | |
| }; | |
| qcom,pm-cpu-level@1 { | |
| reg = <0x1>; | |
| qcom,psci-cpu-mode = <0x2>; | |
| qcom,spm-cpu-mode = "ret"; | |
| qcom,latency-us = <0x3c>; | |
| qcom,ss-power = <0x113>; | |
| qcom,energy-overhead = <0x11451>; | |
| qcom,time-overhead = <0xb5>; | |
| }; | |
| qcom,pm-cpu-level@2 { | |
| reg = <0x2>; | |
| qcom,spm-cpu-mode = "pc"; | |
| qcom,psci-cpu-mode = <0x3>; | |
| qcom,latency-us = <0x144>; | |
| qcom,ss-power = <0x107>; | |
| qcom,energy-overhead = <0x340dd>; | |
| qcom,time-overhead = <0x26d>; | |
| qcom,is-reset; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| qcom,rpm-stats@200000 { | |
| compatible = "qcom,rpm-stats"; | |
| reg = <0x200000 0x1000 0x290014 0x4 0x29001c 0x4>; | |
| reg-names = "phys_addr_base", "offset_addr", "heap_phys_addrbase"; | |
| qcom,sleep-stats-version = <0x2>; | |
| }; | |
| qcom,rpm-rail-stats@200000 { | |
| compatible = "qcom,rpm-rail-stats"; | |
| reg = <0x200000 0x100 0x29000c 0x4>; | |
| reg-names = "phys_addr_base", "offset_addr"; | |
| }; | |
| qcom,rpm-log@200000 { | |
| compatible = "qcom,rpm-log"; | |
| reg = <0x200000 0x4000 0x290018 0x4>; | |
| qcom,rpm-addr-phys = <0x200000>; | |
| qcom,offset-version = <0x4>; | |
| qcom,offset-page-buffer-addr = <0x24>; | |
| qcom,offset-log-len = <0x28>; | |
| qcom,offset-log-len-mask = <0x2c>; | |
| qcom,offset-page-indices = <0x38>; | |
| }; | |
| qcom,rpm-master-stats@778150 { | |
| compatible = "qcom,rpm-master-stats"; | |
| reg = <0x778150 0x5000>; | |
| qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; | |
| qcom,master-stats-version = <0x2>; | |
| qcom,master-offset = <0x1000>; | |
| }; | |
| memory@0x200000 { | |
| compatible = "qcom,rpm-msg-ram"; | |
| reg = <0x200000 0x1000 0x290000 0x1000>; | |
| linux,phandle = <0x16f>; | |
| phandle = <0x16f>; | |
| }; | |
| rpm-memory@0x778000 { | |
| compatible = "qcom,rpm-code-ram"; | |
| reg = <0x778000 0x5000>; | |
| linux,phandle = <0x170>; | |
| phandle = <0x170>; | |
| }; | |
| qcom,system-stats { | |
| compatible = "qcom,system-stats"; | |
| qcom,rpm-msg-ram = <0x16f>; | |
| qcom,rpm-code-ram = <0x170>; | |
| qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; | |
| }; | |
| qcom,mpm@7781b8 { | |
| compatible = "qcom,mpm-v2"; | |
| reg = <0x7781b8 0x1000 0x17911008 0x4>; | |
| reg-names = "vmpm", "ipc"; | |
| interrupts = <0x0 0xab 0x1>; | |
| clocks = <0x26 0x50>; | |
| clock-names = "xo"; | |
| qcom,num-mpm-irqs = <0x60>; | |
| qcom,ipc-bit-offset = <0x1>; | |
| qcom,gic-parent = <0x1>; | |
| qcom,gic-map = <0x2 0xd8 0x34 0x113 0x3d 0xd1 0x4f 0x17b 0x50 0x17c 0x51 0x17b 0x52 0x17c 0x57 0x166 0x5b 0x207 0xff 0x10 0xff 0x11 0xff 0x12 0xff 0x13 0xff 0x14 0xff 0x15 0xff 0x16 0xff 0x17 0xff 0x18 0xff 0x1c 0xff 0x1d 0xff 0x1e 0xff 0x20 0xff 0x21 0xff 0x22 0xff 0x23 0xff 0x24 0xff 0x27 0xff 0x28 0xff 0x29 0xff 0x2a 0xff 0x2b 0xff 0x2c 0xff 0x2d 0xff 0x2e 0xff 0x2f 0xff 0x30 0xff 0x31 0xff 0x32 0xff 0x33 0xff 0x34 0xff 0x36 0xff 0x37 0xff 0x38 0xff 0x39 0xff 0x3a 0xff 0x3b 0xff 0x3c 0xff 0x3d 0xff 0x3e 0xff 0x3f 0xff 0x40 0xff 0x41 0xff 0x42 0xff 0x43 0xff 0x44 0xff 0x45 0xff 0x46 0xff 0x49 0xff 0x4a 0xff 0x4b 0xff 0x4c 0xff 0x4d 0xff 0x4e 0xff 0x4f 0xff 0x50 0xff 0x51 0xff 0x52 0xff 0x53 0xff 0x54 0xff 0x62 0xff 0x64 0xff 0x65 0xff 0x66 0xff 0x6a 0xff 0x6b 0xff 0x6d 0xff 0x6e 0xff 0x6f 0xff 0x70 0xff 0x73 0xff 0x74 0xff 0x75 0xff 0x77 0xff 0x7a 0xff 0x7b 0xff 0x7c 0xff 0x7d 0xff 0x7f 0xff 0x80 0xff 0x81 0xff 0x82 0xff 0x85 0xff 0x86 0xff 0x87 0xff 0x88 0xff 0x8b 0xff 0x8c 0xff 0x8e 0xff 0x8f 0xff 0x90 0xff 0x91 0xff 0x92 0xff 0x94 0xff 0x95 0xff 0x96 0xff 0x97 0xff 0x98 0xff 0x9b 0xff 0x9c 0xff 0x9d 0xff 0x9e 0xff 0x9f 0xff 0xa0 0xff 0xa3 0xff 0xa4 0xff 0xa5 0xff 0xa6 0xff 0xa9 0xff 0xab 0xff 0xac 0xff 0xad 0xff 0xaf 0xff 0xb0 0xff 0xb8 0xff 0xb9 0xff 0xba 0xff 0xbc 0xff 0xbd 0xff 0xbe 0xff 0xbf 0xff 0xc0 0xff 0xc1 0xff 0xc2 0xff 0xc3 0xff 0xc4 0xff 0xc5 0xff 0xc7 0xff 0xc8 0xff 0xc9 0xff 0xca 0xff 0xcb 0xff 0xcc 0xff 0xcd 0xff 0xce 0xff 0xcf 0xff 0xd0 0xff 0xd2 0xff 0xd4 0xff 0xd5 0xff 0xd6 0xff 0xd7 0xff 0xd9 0xff 0xda 0xff 0xdb 0xff 0xdc 0xff 0xdd 0xff 0xde 0xff 0xdf 0xff 0xe0 0xff 0xe1 0xff 0xe2 0xff 0xe3 0xff 0xe4 0xff 0xe5 0xff 0xe6 0xff 0xe7 0xff 0xe8 0xff 0xe9 0xff 0xea 0xff 0xeb 0xff 0xec 0xff 0xed 0xff 0xee 0xff 0xef 0xff 0xf0 0xff 0xf1 0xff 0xf2 0xff 0xf3 0xff 0xf4 0xff 0xf5 0xff 0xf6 0xff 0xf7 0xff 0xf8 0xff 0xf9 0xff 0xfa 0xff 0xfb 0xff 0xfc 0xff 0xfd 0xff 0xfe 0xff 0xff 0xff 0x100 0xff 0x101 0xff 0x102 0xff 0x105 0xff 0x106 0xff 0x107 0xff 0x108 0xff 0x109 0xff 0x10a 0xff 0x10b 0xff 0x10d 0xff 0x10e 0xff 0x10f 0xff 0x114 0xff 0x115 0xff 0x116 0xff 0x117 0xff 0x118 0xff 0x119 0xff 0x11a 0xff 0x11b 0xff 0x11c 0xff 0x11d 0xff 0x11e 0xff 0x11f 0xff 0x120 0xff 0x121 0xff 0x123 0xff 0x124 0xff 0x125 0xff 0x126 0xff 0x127 0xff 0x128 0xff 0x129 0xff 0x12a 0xff 0x12b 0xff 0x12c 0xff 0x12d 0xff 0x12e 0xff 0x12f 0xff 0x130 0xff 0x131 0xff 0x132 0xff 0x133 0xff 0x134 0xff 0x13c 0xff 0x13d 0xff 0x13e 0xff 0x13f 0xff 0x143 0xff 0x144 0xff 0x145 0xff 0x146 0xff 0x147 0xff 0x148 0xff 0x149 0xff 0x14a 0xff 0x14b 0xff 0x14c 0xff 0x14d 0xff 0x14e 0xff 0x14f 0xff 0x150 0xff 0x151 0xff 0x152 0xff 0x153 0xff 0x154 0xff 0x155 0xff 0x156 0xff 0x159 0xff 0x15a 0xff 0x15b 0xff 0x15c 0xff 0x15e 0xff 0x15f 0xff 0x165 0xff 0x167 0xff 0x168 0xff 0x169 0xff 0x16a 0xff 0x16b 0xff 0x16c 0xff 0x16d 0xff 0x16e 0xff 0x17d 0xff 0x17e 0xff 0x181 0xff 0x182 0xff 0x183 0xff 0x184 0xff 0x185 0xff 0x186 0xff 0x187 0xff 0x188 0xff 0x189 0xff 0x194 0xff 0x195 0xff 0x196 0xff 0x197 0xff 0x198 0xff 0x199 0xff 0x19a 0xff 0x19b 0xff 0x19c 0xff 0x19d 0xff 0x19e 0xff 0x19f 0xff 0x1a0 0xff 0x1a1 0xff 0x1a2 0xff 0x1a3 0xff 0x1a7 0xff 0x1a8 0xff 0x1a9 0xff 0x1aa 0xff 0x1ab 0xff 0x1ac 0xff 0x1ad 0xff 0x1ae 0xff 0x1af 0xff 0x1b0 0xff 0x1b1 0xff 0x1b2 0xff 0x1b3 0xff 0x1b4 0xff 0x1bd 0xff 0x1be 0xff 0x1bf 0xff 0x1c0 0xff 0x1c1 0xff 0x1c2 0xff 0x1c4 0xff 0x1c5 0xff 0x1c6 0xff 0x1c7 0xff 0x1c8 0xff 0x1c9 0xff 0x1ca 0xff 0x1ce 0xff 0x1d0 0xff 0x1d1 0xff 0x1d2 0xff 0x1d4 0xff 0x1d5 0xff 0x1d7 0xff 0x1d8 0xff 0x1da 0xff 0x1db 0xff 0x1dc 0xff 0x1dd 0xff 0x1de 0xff 0x1df 0xff 0x1e0 0xff 0x1e1 0xff 0x1e2 0xff 0x1e3 0xff 0x1e4 0xff 0x1e5 0xff 0x1e6 0xff 0x1e7 0xff 0x1e8 0xff 0x1ea 0xff 0x1eb 0xff 0x1ec 0xff 0x1ee 0xff 0x1ef 0xff 0x1f0 0xff 0x1f1 0xff 0x1f2 0xff 0x1f3 0xff 0x1f4 0xff 0x1f5 0xff 0x1f7 0xff 0x1f8 0xff 0x1f9 0xff 0x1fa 0xff 0x200 0xff 0x201 0xff 0x202 0xff 0x203 0xff 0x204 0xff 0x205 0xff 0x208 0xff 0x220 0xff 0x221 0xff 0x222 0xff 0x223 0xff 0x224 0xff 0x225 0xff 0x226 0xff 0x227 0xff 0x228 0xff 0x229 0xff 0x22a 0xff 0x22c 0xff 0x22d 0xff 0x22e 0xff 0x22f 0xff 0x230 0xff 0x231 0xff 0x232 0xff 0x233 0xff 0x234 0xff 0x235 0xff 0x236 0xff 0x237 0xff 0x238 0xff 0x239 0xff 0x23a 0xff 0x23b 0xff 0x23c 0xff 0x23d 0xff 0x23e 0xff 0x23f 0xff 0x240 0xff 0x241 0xff 0x242 0xff 0x243 0xff 0x244 0xff 0x245 0xff 0x246 0xff 0x247 0xff 0x248>; | |
| qcom,gpio-parent = <0xe7>; | |
| qcom,gpio-map = <0x3 0x1 0x4 0x5 0x5 0x9 0x6 0xa 0x7 0x42 0x8 0x16 0x9 0x19 0xa 0x1c 0xb 0x3a 0xd 0x29 0xe 0x2b 0xf 0x28 0x10 0x2a 0x11 0x2e 0x12 0x32 0x13 0x2c 0x15 0x38 0x16 0x2d 0x17 0x44 0x18 0x45 0x19 0x46 0x1a 0x47 0x1b 0x48 0x1c 0x49 0x1d 0x40 0x1e 0x2 0x1f 0xd 0x20 0x6f 0x21 0x4a 0x22 0x4b 0x23 0x4c 0x24 0x52 0x25 0x11 0x26 0x4d 0x27 0x2f 0x28 0x36 0x29 0x30 0x2a 0x65 0x2b 0x31 0x2c 0x33 0x2d 0x56 0x2e 0x5a 0x2f 0x5b 0x30 0x34 0x32 0x37 0x33 0x6 0x35 0x41 0x37 0x43 0x38 0x53 0x39 0x54 0x3a 0x55 0x3b 0x57 0x3f 0x15 0x40 0x4e 0x41 0x71 0x42 0x3c 0x43 0x62 0x44 0x1e 0x46 0x1f 0x47 0x1d 0x4c 0x6b 0x53 0x6d 0x54 0x67 0x55 0x69>; | |
| }; | |
| arm,smmu-anoc2@16c0000 { | |
| compatible = "qcom,smmu-v2"; | |
| reg = <0x16c0000 0x40000>; | |
| #iommu-cells = <0x1>; | |
| qcom,register-save; | |
| qcom,skip-init; | |
| #global-interrupts = <0x2>; | |
| interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x175 0x4 0x0 0x176 0x8 0x0 0x177 0x8 0x0 0x178 0x8 0x0 0x179 0x8 0x0 0x17a 0x8 0x0 0x1ce 0x4 0x0 0x1cf 0x4 0x0 0x1d0 0x4 0x0 0x1d1 0x4 0x0 0x1d2 0x4 0x0 0x1d3 0x4 0x0 0x161 0x4 0x0 0x162 0x4 0x0 0x163 0x4 0x0 0x164 0x4 0x0 0x165 0x4 0x0 0x166 0x4 0x0 0x167 0x4 0x0 0x168 0x4 0x0 0x1ba 0x4 0x0 0x1bb 0x4 0x0 0x1bc 0x4 0x0 0x1bf 0x4 0x0 0x1d4 0x4 0x0 0x1d5 0x4 0x0 0x1d8 0x4 0x0 0x1d9 0x4 0x0 0x1da 0x4>; | |
| clocks = <0x26 0x59>; | |
| clock-names = "smmu_aggr2_noc_clk"; | |
| #clock-cells = <0x1>; | |
| attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x6070 0xf 0x6074 0x23 0x6078 0x37 0x607c 0x39 0x6080 0x3f 0x6084 0x6f 0x6088 0x74 0x608c 0x92 0x6090 0xb0 0x6094 0xf0 0x6098 0xf0 0x609c 0xf0 0x60f0 0x0 0x60f4 0x1 0x60f8 0x3 0x60fc 0x4 0x6100 0x6 0x6104 0x8 0x6108 0x9 0x610c 0xb 0x6110 0xd 0x6114 0xf 0x6118 0xf 0x611c 0xf 0x6170 0x0 0x6174 0x0 0x6178 0x0 0x617c 0x0 0x6180 0x0 0x6184 0x0 0x6188 0x0 0x618c 0x0 0x6190 0x0 0x6194 0x0 0x6198 0x0 0x619c 0x0 0x6270 0x0 0x6274 0x1 0x6278 0x2 0x627c 0x4 0x6280 0x4 0x6284 0x6 0x6288 0x6 0x628c 0xa 0x6290 0xc 0x6294 0xc 0x6298 0xc 0x629c 0xc 0x62f0 0xc 0x62f4 0x12 0x62f8 0x18 0x62fc 0x1a 0x6300 0x1d 0x6304 0x23 0x6308 0x24 0x630c 0x28 0x6310 0x2c 0x6314 0x30 0x6318 0x30 0x631c 0x30 0x6370 0x30 0x6374 0x35 0x6378 0x3a 0x637c 0x3e 0x6380 0x46 0x6384 0x50 0x6388 0x55 0x638c 0x5d 0x6390 0x67 0x6394 0x80 0x6398 0x80 0x639c 0x80 0x678c 0x12 0x6794 0x32 0x67a0 0x0 0x67a4 0xe1 0x67a8 0xf0 0x67b0 0x0 0x67b4 0xc 0x67b8 0x9c 0x67d0 0x0 0x67dc 0x4 0x67e0 0x8 0x6800 0x6 0x6900 0x3ff 0x6b48 0x330330 0x6b4c 0x81 0x6b50 0x1313 0x6b64 0x121155 0x6b68 0xcaa84920 0x6b70 0xc0c0000 0x6b74 0x8080000 0x6b78 0x8080000 0x6b80 0x20002000 0x6b84 0x20002000 0x6c00 0x5 0x6c04 0x0 0x6c08 0x5 0x6c0c 0x0 0x6c10 0x5 0x6c14 0x0 0x6c18 0x5 0x6c1c 0x0 0x6c20 0x5 0x6c24 0x0 0x6c28 0x0 0x6c2c 0x0 0x6c30 0x0 0x6c34 0x0 0x6c38 0x0 0x6c3c 0x0 0x6c40 0x0 0x6c44 0x0 0x6c48 0x0 0x6c4c 0x0 0x6c50 0x0 0x6c54 0x0 0x6c58 0x0 0x6c5c 0x0 0x6c60 0x0 0x6c64 0x0 0x6c68 0x0 0x6c6c 0x0 0x6c70 0x0 0x6c74 0x0 0x6c78 0x0 0x6c7c 0x0 0x6c80 0x0 0x6c84 0x0 0x6c88 0x0 0x6c8c 0x0 0x6c90 0x0 0x6c94 0x0 0x6c98 0x0 0x6c9c 0x0 0x6ca0 0x0 0x6ca4 0x0 0x6ca8 0x0 0x6cac 0x0 0x6cb0 0x0 0x6cb4 0x0 0x6cb8 0x0 0x6cbc 0x0 0x6cc0 0x0 0x6cc4 0x0 0x6cc8 0x0 0x6ccc 0x0 0x6cd0 0x0 0x6cd4 0x0 0x6cd8 0x0 0x6cdc 0x0 0x6ce0 0x0 0x6ce4 0x0 0x6ce8 0x0 0x6cec 0x0 0x6cf0 0x0 0x6cf4 0x0 0x6cf8 0x0 0x6cfc 0x0 0x6d00 0x3 0x6d04 0x4 0x6d08 0x4 0x6d0c 0x0 0x6d10 0x8 0x6d14 0x8 0x6d18 0x3 0x6d1c 0x2 0x6d20 0x4 0x6d24 0x0 0x6d28 0x4 0x6d2c 0x0 0x6d30 0x7 0x6d34 0x0 0x6d38 0x6 0x6d3c 0x0 0x6d40 0x0 0x6d44 0x1 0x6d48 0x4 0x6d4c 0x0 0x6d50 0x4 0x6d54 0x0 0x6d58 0x4 0x6d5c 0x0 0x6d60 0x0 0x6d64 0x0 0x6d68 0x0 0x6d6c 0x0 0x6d70 0x0 0x6d74 0x0 0x6d78 0x0 0x6d7c 0x0 0x6d80 0x0 0x6d84 0x0 0x6d88 0x0 0x6d8c 0x0 0x6d90 0x0 0x6d94 0x0 0x6d98 0x0 0x6d9c 0x0 0x6da0 0x0 0x6da4 0x0 0x6da8 0x0 0x6dac 0x0 0x6db0 0x0 0x6db4 0x0 0x6db8 0x0 0x6dbc 0x0 0x6dc0 0x0 0x6dc4 0x0 0x6dc8 0x0 0x6dcc 0x0 0x6dd0 0x0 0x6dd4 0x0 0x6dd8 0x0 0x6ddc 0x0 0x6de0 0x0 0x6de4 0x0 0x6de8 0x0 0x6dec 0x0 0x6df0 0x0 0x6df4 0x0 0x6df8 0x0 0x6dfc 0x0>; | |
| linux,phandle = <0xe8>; | |
| phandle = <0xe8>; | |
| }; | |
| arm,smmu-lpass_q6@5100000 { | |
| compatible = "qcom,smmu-v2"; | |
| reg = <0x5100000 0x40000>; | |
| #iommu-cells = <0x1>; | |
| qcom,register-save; | |
| qcom,skip-init; | |
| #global-interrupts = <0x2>; | |
| interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0xe2 0x4 0x0 0x189 0x4 0x0 0x18a 0x4 0x0 0x18b 0x4 0x0 0x18c 0x4 0x0 0x18d 0x4 0x0 0x18e 0x4 0x0 0x18f 0x4 0x0 0x190 0x4 0x0 0x191 0x4 0x0 0x192 0x4 0x0 0x193 0x4 0x0 0x89 0x4 0x0 0xe0 0x4 0x0 0xe1 0x4 0x0 0x136 0x4 0x0 0x194 0x4>; | |
| vdd-supply = <0x171>; | |
| clocks = <0xa1 0x9f>; | |
| clock-names = "lpass_q6_smmu_clk"; | |
| #clock-cells = <0x1>; | |
| attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x6070 0xe0 0x6074 0xe0 0x6078 0xe0 0x607c 0xe0 0x60f0 0xc0 0x60f4 0xc8 0x60f8 0xd0 0x60fc 0xd8 0x6170 0x0 0x6174 0x30 0x6178 0x60 0x617c 0x90 0x6270 0x0 0x6274 0x2 0x6278 0x4 0x627c 0x6 0x62f0 0x8 0x62f4 0xe 0x62f8 0x14 0x62fc 0x1a 0x6370 0x20 0x6374 0x40 0x6378 0x60 0x637c 0x80 0x6784 0x0 0x678c 0x10 0x67a0 0x0 0x67a4 0x0 0x67a8 0x20 0x67b0 0x0 0x67b4 0x8 0x67b8 0xc8 0x67d0 0x4 0x67dc 0x8 0x67e0 0x8 0x6800 0x6 0x6900 0x3ff 0x6924 0x202 0x6928 0x10a00 0x6930 0x500 0x6960 0xffffffff 0x6b64 0x121151 0x6b68 0xea800080 0x6c00 0x0 0x6c04 0x0 0x6c08 0x0 0x6c0c 0x0 0x6c10 0x1 0x6c14 0x1 0x6c18 0x1 0x6c1c 0x1 0x6c20 0x2 0x6c24 0x2 0x6c28 0x2 0x6c2c 0x2 0x6c30 0x3 0x6c34 0x3 0x6c38 0x3 0x6c3c 0x3>; | |
| linux,phandle = <0xea>; | |
| phandle = <0xea>; | |
| }; | |
| arm,smmu-mmss@cd00000 { | |
| compatible = "qcom,smmu-v2"; | |
| reg = <0xcd00000 0x40000>; | |
| #iommu-cells = <0x1>; | |
| qcom,register-save; | |
| qcom,no-smr-check; | |
| qcom,skip-init; | |
| #global-interrupts = <0x2>; | |
| interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x107 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4 0x0 0xf4 0x4 0x0 0xf5 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4 0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4 0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4 0x0 0x104 0x4 0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x110 0x4 0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>; | |
| vdd-supply = <0x163>; | |
| clocks = <0x74 0xa9 0x26 0x3c 0x74 0x57 0x74 0x58>; | |
| clock-names = "mmss_mnoc_ahb_clk", "mmssnoc_axi_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk"; | |
| #clock-cells = <0x1>; | |
| qcom,bus-master-id = <0x272b>; | |
| attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x678c 0x28 0x6794 0xe0 0x6800 0x6 0x6900 0x3ff 0x6924 0x204 0x6928 0x11002 0x6930 0x800 0x6960 0xffffffff 0x6964 0xffffffff 0x6968 0xffffffff 0x696c 0xffffffff 0x6b48 0x330330 0x6b4c 0x81 0x6b50 0x3333 0x6b54 0x3333 0x6b64 0x1a5555 0x6b68 0xbaaa892a 0x6b70 0x10100202 0x6b74 0x10100202 0x6b78 0x10100000 0x6b80 0x20042004 0x6b84 0x20042004>; | |
| linux,phandle = <0x173>; | |
| phandle = <0x173>; | |
| }; | |
| arm,smmu-kgsl@5040000 { | |
| compatible = "qcom,smmu-v2"; | |
| reg = <0x5040000 0x10000>; | |
| #iommu-cells = <0x1>; | |
| qcom,dynamic; | |
| qcom,register-save; | |
| qcom,skip-init; | |
| #global-interrupts = <0x2>; | |
| interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x149 0x4 0x0 0x14a 0x4 0x0 0x14b 0x4 0x0 0x14c 0x4 0x0 0x74 0x4 0x0 0x75 0x4 0x0 0x15d 0x4 0x0 0x15e 0x4>; | |
| qcom,deferred-regulator-disable-delay = <0x50>; | |
| vdd-supply = <0x16b>; | |
| clocks = <0xa1 0x42 0xa1 0x20 0xa1 0x40>; | |
| clock-names = "gcc_gpu_cfg_ahb_clk", "gcc_bimc_gfx_clk", "gcc_gpu_bimc_gfx_clk"; | |
| #clock-cells = <0x1>; | |
| attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x678c 0x8 0x6794 0x28 0x6800 0x6 0x6900 0x3ff 0x6924 0x204 0x6928 0x11000 0x6930 0x800 0x6960 0xffffffff 0x6b64 0x1a5551 0x6b68 0x9a82a382>; | |
| linux,phandle = <0x16e>; | |
| phandle = <0x16e>; | |
| }; | |
| arm,smmu-turing_q6@5180000 { | |
| compatible = "qcom,smmu-v2"; | |
| reg = <0x5180000 0x40000>; | |
| #iommu-cells = <0x1>; | |
| qcom,register-save; | |
| qcom,skip-init; | |
| #global-interrupts = <0x2>; | |
| interrupts = <0x0 0xe5 0x4 0x0 0xe7 0x4 0x0 0x215 0x4 0x0 0x216 0x4 0x0 0x217 0x4 0x0 0x218 0x4 0x0 0x219 0x4 0x0 0x21a 0x4 0x0 0x21b 0x4 0x0 0x21c 0x4 0x0 0x21d 0x4 0x0 0x21e 0x4 0x0 0x21f 0x4 0x0 0x220 0x4 0x0 0x221 0x4 0x0 0x222 0x4 0x0 0x223 0x4 0x0 0x224 0x4 0x0 0x225 0x4>; | |
| vdd-supply = <0x172>; | |
| clocks = <0xa1 0xb7>; | |
| clock-names = "turing_q6_smmu_clk"; | |
| #clock-cells = <0x1>; | |
| attach-impl-defs = <0x6000 0x2378 0x6060 0x1055 0x6070 0xe0 0x6074 0xe0 0x6078 0xe0 0x607c 0xe0 0x60f0 0xc0 0x60f4 0xc8 0x60f8 0xd0 0x60fc 0xd8 0x6170 0x0 0x6174 0x30 0x6178 0x60 0x617c 0x90 0x6270 0x0 0x6274 0x2 0x6278 0x4 0x627c 0x6 0x62f0 0x8 0x62f4 0xe 0x62f8 0x14 0x62fc 0x1a 0x6370 0x20 0x6374 0x40 0x6378 0x60 0x637c 0x80 0x6784 0x0 0x678c 0x10 0x67a0 0x0 0x67a4 0x0 0x67a8 0x20 0x67b0 0x0 0x67b4 0x8 0x67b8 0xc8 0x67d0 0x4 0x67dc 0x8 0x67e0 0x8 0x6800 0x6 0x6900 0x3ff 0x6924 0x202 0x6928 0x10a00 0x6930 0x500 0x6960 0xffffffff 0x6b64 0x121151 0x6b68 0xea800080 0x6c00 0x0 0x6c04 0x0 0x6c08 0x0 0x6c0c 0x0 0x6c10 0x1 0x6c14 0x1 0x6c18 0x1 0x6c1c 0x1 0x6c20 0x2 0x6c24 0x2 0x6c28 0x2 0x6c2c 0x2 0x6c30 0x3 0x6c34 0x3 0x6c38 0x3 0x6c3c 0x3>; | |
| linux,phandle = <0xeb>; | |
| phandle = <0xeb>; | |
| }; | |
| iommu_test_device { | |
| compatible = "iommu-debug-test"; | |
| iommus = <0x173 0x2a>; | |
| }; | |
| ufsice@1db0000 { | |
| compatible = "qcom,ice"; | |
| reg = <0x1db0000 0x8000>; | |
| qcom,enable-ice-clk; | |
| clock-names = "ufs_core_clk", "bus_clk", "iface_clk", "ice_core_clk"; | |
| clocks = <0xa1 0x60 0xa1 0x61 0xa1 0x5f 0xa1 0x62>; | |
| qcom,op-freq-hz = <0x0 0x0 0x0 0x11e1a300>; | |
| vdd-hba-supply = <0x108>; | |
| qcom,msm-bus,name = "ufs_ice_noc"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x1 0x28a 0x0 0x0 0x1 0x28a 0x3e8 0x0>; | |
| qcom,bus-vector-names = "MIN", "MAX"; | |
| qcom,instance-type = "ufs"; | |
| linux,phandle = <0x107>; | |
| phandle = <0x107>; | |
| }; | |
| sdcc1ice@c0c8000 { | |
| compatible = "qcom,ice"; | |
| reg = <0xc0c8000 0x8000>; | |
| qcom,enable-ice-clk; | |
| clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; | |
| clocks = <0xa1 0xa7 0xa1 0x5c 0xa1 0x5b 0xa1 0x5a>; | |
| qcom,op-freq-hz = <0x11e1a300 0x0 0x0 0x0>; | |
| qcom,msm-bus,name = "sdcc_ice_noc"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x4e 0x200 0x0 0x0 0x4e 0x200 0x3e8 0x0>; | |
| qcom,bus-vector-names = "MIN", "MAX"; | |
| qcom,instance-type = "sdcc"; | |
| linux,phandle = <0xd3>; | |
| phandle = <0xd3>; | |
| }; | |
| ssusb@a800000 { | |
| compatible = "qcom,dwc-usb3-msm"; | |
| reg = <0xa800000 0xfc100 0xc016000 0x400>; | |
| reg-names = "core_base", "ahb2phy_base"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| interrupts = <0x0 0x15b 0x0 0x0 0xf3 0x0 0x0 0xb4 0x0>; | |
| interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; | |
| USB3_GDSC-supply = <0x174>; | |
| qcom,usb-dbm = <0x175>; | |
| qcom,msm-bus,name = "usb3"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x3d 0x200 0x0 0x0 0x3d 0x200 0x3a980 0xc3500>; | |
| qcom,dwc-usb3-msm-tx-fifo-size = <0x5328>; | |
| extcon = <0x176>; | |
| qcom,pm-qos-latency = <0x29>; | |
| clocks = <0xa1 0x6b 0xa1 0x3b 0xa1 0x1f 0x26 0x5a 0xa1 0x6c 0xa1 0x6d 0xa1 0x71 0x26 0x4f>; | |
| clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "noc_aggr_clk", "utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo"; | |
| qcom,core-clk-rate = <0x7f27450>; | |
| qcom,core-clk-rate-hs = <0x3f940ab>; | |
| resets = <0xa1 0x7>; | |
| reset-names = "core_reset"; | |
| linux,phandle = <0x363>; | |
| phandle = <0x363>; | |
| dwc3@a800000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0xa800000 0xc8d0>; | |
| interrupt-parent = <0x1>; | |
| interrupts = <0x0 0x83 0x0>; | |
| usb-phy = <0x7c 0x177>; | |
| tx-fifo-resize; | |
| snps,usb3-u1u2-disable; | |
| snps,nominal-elastic-buffer; | |
| snps,disable-clk-gating; | |
| snps,has-lpm-erratum; | |
| snps,is-utmi-l1-suspend; | |
| snps,hird-threshold = [00]; | |
| }; | |
| qcom,usbbam@a904000 { | |
| compatible = "qcom,usb-bam-msm"; | |
| reg = <0xa904000 0x17000>; | |
| interrupt-parent = <0x1>; | |
| interrupts = <0x0 0x84 0x0>; | |
| qcom,bam-type = <0x0>; | |
| qcom,usb-bam-fifo-baseaddr = <0x146bb000>; | |
| qcom,usb-bam-num-pipes = <0x8>; | |
| qcom,ignore-core-reset-ack; | |
| qcom,disable-clk-gating; | |
| qcom,usb-bam-override-threshold = <0x4001>; | |
| qcom,usb-bam-max-mbps-highspeed = <0x190>; | |
| qcom,usb-bam-max-mbps-superspeed = <0xe10>; | |
| qcom,reset-bam-on-connect; | |
| qcom,pipe0 { | |
| label = "ssusb-ipa-out-0"; | |
| qcom,usb-bam-mem-type = <0x1>; | |
| qcom,dir = <0x0>; | |
| qcom,pipe-num = <0x0>; | |
| qcom,peer-bam = <0x1>; | |
| qcom,src-bam-pipe-index = <0x1>; | |
| qcom,data-fifo-size = <0x8000>; | |
| qcom,descriptor-fifo-size = <0x2000>; | |
| }; | |
| qcom,pipe1 { | |
| label = "ssusb-ipa-in-0"; | |
| qcom,usb-bam-mem-type = <0x1>; | |
| qcom,dir = <0x1>; | |
| qcom,pipe-num = <0x0>; | |
| qcom,peer-bam = <0x1>; | |
| qcom,dst-bam-pipe-index = <0x0>; | |
| qcom,data-fifo-size = <0x8000>; | |
| qcom,descriptor-fifo-size = <0x2000>; | |
| }; | |
| qcom,pipe2 { | |
| label = "ssusb-qdss-in-0"; | |
| qcom,usb-bam-mem-type = <0x2>; | |
| qcom,dir = <0x1>; | |
| qcom,pipe-num = <0x0>; | |
| qcom,peer-bam = <0x0>; | |
| qcom,peer-bam-physical-address = <0x6064000>; | |
| qcom,src-bam-pipe-index = <0x0>; | |
| qcom,dst-bam-pipe-index = <0x3>; | |
| qcom,data-fifo-offset = <0x0>; | |
| qcom,data-fifo-size = <0x1800>; | |
| qcom,descriptor-fifo-offset = <0x1800>; | |
| qcom,descriptor-fifo-size = <0x800>; | |
| }; | |
| qcom,pipe3 { | |
| label = "ssusb-dpl-ipa-in-1"; | |
| qcom,usb-bam-mem-type = <0x1>; | |
| qcom,dir = <0x1>; | |
| qcom,pipe-num = <0x1>; | |
| qcom,peer-bam = <0x1>; | |
| qcom,dst-bam-pipe-index = <0x2>; | |
| qcom,data-fifo-size = <0x8000>; | |
| qcom,descriptor-fifo-size = <0x2000>; | |
| }; | |
| }; | |
| }; | |
| qusb@c012000 { | |
| compatible = "qcom,qusb2phy"; | |
| reg = <0xc012000 0x180 0x1fcb24c 0x4 0x780240 0x4 0x188018 0x4>; | |
| reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8", "tune2_efuse_addr", "ref_clk_addr"; | |
| vdd-supply = <0x105>; | |
| vdda18-supply = <0xc9>; | |
| vdda33-supply = <0x7d>; | |
| qcom,vdd-voltage-level = <0x0 0xe1d48 0xe1d48>; | |
| qcom,tune2-efuse-bit-pos = <0x19>; | |
| qcom,tune2-efuse-num-bits = <0x4>; | |
| qcom,qusb-phy-init-seq = <0xf8 0x80 0x33 0x84 0x83 0x88 0xc5 0x8c 0x30 0x8 0x79 0xc 0x21 0x10 0x14 0x9c 0x9f 0x1c 0x0 0x18>; | |
| phy_type = "utmi"; | |
| qcom,phy-clk-scheme = "cml"; | |
| qcom,major-rev = <0x1>; | |
| clocks = <0x26 0x2e 0xa1 0x57 0xa1 0x71>; | |
| clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk"; | |
| resets = <0xa1 0x0>; | |
| reset-names = "phy_reset"; | |
| linux,phandle = <0x7c>; | |
| phandle = <0x7c>; | |
| }; | |
| ssphy@c010000 { | |
| compatible = "qcom,usb-ssphy-qmp-v2"; | |
| reg = <0xc010000 0xe18 0x1fcb244 0x4 0x1fcb248 0x4>; | |
| reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_usb3_dp_phymode"; | |
| vdd-supply = <0x105>; | |
| core-supply = <0xc9>; | |
| qcom,vdd-voltage-level = <0x0 0xe1d48 0xe1d48>; | |
| qcom,core-voltage-level = <0x0 0x1b7740 0x1b7740>; | |
| qcom,vbus-valid-override; | |
| qcom,qmp-phy-init-seq = <0xac 0x14 0x0 0x34 0x8 0x0 0x174 0x30 0x0 0x3c 0x6 0x0 0xb4 0x0 0x0 0xb8 0x8 0x0 0x70 0xf 0x0 0x19c 0x1 0x0 0x178 0x0 0x0 0xd0 0x82 0x0 0xdc 0x55 0x0 0xe0 0x55 0x0 0xe4 0x3 0x0 0x78 0xb 0x0 0x84 0x16 0x0 0x90 0x28 0x0 0x108 0x80 0x0 0x10c 0x0 0x0 0x184 0xa 0x0 0x4c 0x15 0x0 0x50 0x34 0x0 0x54 0x0 0x0 0xc8 0x0 0x0 0x18c 0x0 0x0 0xcc 0x0 0x0 0x128 0x0 0x0 0xc 0xa 0x0 0x10 0x1 0x0 0x1c 0x31 0x0 0x20 0x1 0x0 0x14 0x0 0x0 0x18 0x0 0x0 0x24 0xde 0x0 0x28 0x7 0x0 0x48 0xf 0x0 0x194 0x6 0x0 0x100 0x80 0x0 0xa8 0x1 0x0 0x430 0xb 0x0 0x830 0xb 0x0 0x444 0x0 0x0 0x844 0x0 0x0 0x43c 0x0 0x0 0x83c 0x0 0x0 0x440 0x0 0x0 0x840 0x0 0x0 0x408 0xa 0x0 0x808 0xa 0x0 0x414 0x6 0x0 0x814 0x6 0x0 0x434 0x75 0x0 0x834 0x75 0x0 0x4d4 0x2 0x0 0x8d4 0x2 0x0 0x4d8 0x4e 0x0 0x8d8 0x4e 0x0 0x4dc 0x18 0x0 0x8dc 0x18 0x0 0x4f8 0x77 0x0 0x8f8 0x77 0x0 0x4fc 0x80 0x0 0x8fc 0x80 0x0 0x4c0 0xa 0x0 0x8c0 0xa 0x0 0x504 0x3 0x0 0x904 0x3 0x0 0x50c 0x16 0x0 0x90c 0x16 0x0 0x500 0x0 0x0 0x900 0x0 0x0 0x564 0x0 0x0 0x964 0x0 0x0 0x260 0x10 0x0 0x660 0x10 0x0 0x2a4 0x12 0x0 0x6a4 0x12 0x0 0x28c 0xc6 0x0 0x68c 0xc6 0x0 0x244 0x0 0x0 0x644 0x0 0x0 0x248 0x0 0x0 0x648 0x0 0x0 0xc0c 0x9f 0x0 0xc24 0x17 0x0 0xc28 0xf 0x0 0xcc8 0x83 0x0 0xcc4 0x2 0x0 0xccc 0x9 0x0 0xcd0 0xa2 0x0 0xcd4 0x85 0x0 0xc80 0xd1 0x0 0xc84 0x1f 0x0 0xc88 0x47 0x0 0xcb8 0x75 0x0 0xcbc 0x13 0x0 0xcb0 0x86 0x0 0xca0 0x4 0x0 0xc8c 0x44 0x0 0xc70 0xe7 0x0 0xc74 0x3 0x0 0xc78 0x40 0x0 0xc7c 0x0 0x0 0xdd8 0x88 0x0 0xffffffff 0xffffffff 0x0>; | |
| qcom,qmp-phy-reg-offset = <0xd74 0xcd8 0xcdc 0xc04 0xc00 0xc08 0xa00>; | |
| clocks = <0xa1 0x6f 0xa1 0x70 0xa1 0x71 0x26 0x2e 0xa1 0x6e>; | |
| clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "ref_clk_src", "ref_clk"; | |
| resets = <0xa1 0x4 0xa1 0x5>; | |
| reset-names = "phy_reset", "phy_phy_reset"; | |
| linux,phandle = <0x177>; | |
| phandle = <0x177>; | |
| }; | |
| usb_audio_qmi_dev { | |
| compatible = "qcom,usb-audio-qmi-dev"; | |
| iommus = <0xea 0x6>; | |
| qcom,usb-audio-stream-id = <0x6>; | |
| qcom,usb-audio-intr-num = <0x2>; | |
| }; | |
| dbm@a8f8000 { | |
| compatible = "qcom,usb-dbm-1p5"; | |
| reg = <0xa8f8000 0x300>; | |
| qcom,reset-ep-after-lpm-resume; | |
| linux,phandle = <0x175>; | |
| phandle = <0x175>; | |
| }; | |
| hsusb@c200000 { | |
| compatible = "qcom,dwc-usb3-msm"; | |
| reg = <0xc200000 0xfc000 0xc016000 0x400>; | |
| reg-names = "core_base", "ahb2phy_base"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| ranges; | |
| interrupts = <0x0 0x15c 0x0 0x0 0x90 0x0>; | |
| interrupt-names = "hs_phy_irq", "pwr_event_irq"; | |
| qcom,msm-bus,name = "usb-hs"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x57 0x200 0x0 0x0 0x57 0x200 0xea60 0xc3500>; | |
| qcom,pm-qos-latency = <0x34>; | |
| clocks = <0xa1 0x68 0xa1 0x3a 0xa1 0x69 0xa1 0x6a 0x26 0x4f 0xa1 0x71>; | |
| clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; | |
| qcom,core-clk-rate = <0x3938700>; | |
| resets = <0xa1 0x6>; | |
| reset-names = "core_reset"; | |
| status = "disabled"; | |
| linux,phandle = <0x364>; | |
| phandle = <0x364>; | |
| dwc3@c200000 { | |
| compatible = "snps,dwc3"; | |
| reg = <0xc200000 0xc8d0>; | |
| interrupt-parent = <0x1>; | |
| interrupts = <0x0 0x8f 0x0>; | |
| usb-phy = <0x178 0x179>; | |
| maximum-speed = "high-speed"; | |
| snps,nominal-elastic-buffer; | |
| snps,is-utmi-l1-suspend; | |
| snps,hird-threshold = [00]; | |
| dr_mode = "host"; | |
| }; | |
| }; | |
| qusb@c014000 { | |
| compatible = "qcom,qusb2phy"; | |
| reg = <0xc014000 0x180 0x188014 0x4>; | |
| reg-names = "qusb_phy_base", "ref_clk_addr"; | |
| vdd-supply = <0x105>; | |
| vdda18-supply = <0xc9>; | |
| vdda33-supply = <0x7d>; | |
| qcom,vdd-voltage-level = <0x0 0xe1d48 0xe1d48>; | |
| qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 0x83 0x88 0xc0 0x8c 0x30 0x8 0x79 0xc 0x21 0x10 0x14 0x9c 0x9f 0x1c 0x0 0x18>; | |
| phy_type = "utmi"; | |
| qcom,phy-clk-scheme = "cml"; | |
| qcom,major-rev = <0x1>; | |
| qcom,hold-reset; | |
| clocks = <0xa1 0x71 0xa1 0x58 0x26 0x2e>; | |
| clock-names = "cfg_ahb_clk", "ref_clk", "ref_clk_src"; | |
| resets = <0xa1 0x1>; | |
| reset-names = "phy_reset"; | |
| linux,phandle = <0x178>; | |
| phandle = <0x178>; | |
| }; | |
| usb_nop_phy { | |
| compatible = "usb-nop-xceiv"; | |
| linux,phandle = <0x179>; | |
| phandle = <0x179>; | |
| }; | |
| pinctrl@03000000 { | |
| compatible = "qcom,sdm660-pinctrl"; | |
| reg = <0x3000000 0xc00000>; | |
| interrupts = <0x0 0xd0 0x0>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0xe7>; | |
| phandle = <0xe7>; | |
| msm_gpio_20 { | |
| linux,phandle = <0x28c>; | |
| phandle = <0x28c>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| msm_gpio_20_output_high { | |
| linux,phandle = <0x28d>; | |
| phandle = <0x28d>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| msm_gpio_72 { | |
| linux,phandle = <0x28e>; | |
| phandle = <0x28e>; | |
| mux { | |
| pins = "gpio72"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio72"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| uart_console_active { | |
| linux,phandle = <0xa2>; | |
| phandle = <0xa2>; | |
| mux { | |
| pins = "gpio4", "gpio5"; | |
| function = "blsp_uart2"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| led_enable { | |
| linux,phandle = <0x365>; | |
| phandle = <0x365>; | |
| mux { | |
| pins = "gpio40"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio40"; | |
| drive_strength = <0x2>; | |
| output-high; | |
| bias-disable; | |
| }; | |
| }; | |
| led_disable { | |
| linux,phandle = <0x366>; | |
| phandle = <0x366>; | |
| mux { | |
| pins = "gpio40"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio40"; | |
| drive_strength = <0x2>; | |
| output-low; | |
| bias-disable; | |
| }; | |
| }; | |
| trigout_a { | |
| linux,phandle = <0x4e>; | |
| phandle = <0x4e>; | |
| mux { | |
| pins = "gpio49"; | |
| function = "qdss_cti0_a"; | |
| }; | |
| config { | |
| pins = "gpio49"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| sdc1_clk_on { | |
| linux,phandle = <0xd6>; | |
| phandle = <0xd6>; | |
| config { | |
| pins = "sdc1_clk"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| sdc1_clk_off { | |
| linux,phandle = <0xda>; | |
| phandle = <0xda>; | |
| config { | |
| pins = "sdc1_clk"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| sdc1_cmd_on { | |
| linux,phandle = <0xd7>; | |
| phandle = <0xd7>; | |
| config { | |
| pins = "sdc1_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0xa>; | |
| }; | |
| }; | |
| sdc1_cmd_off { | |
| linux,phandle = <0xdb>; | |
| phandle = <0xdb>; | |
| config { | |
| pins = "sdc1_cmd"; | |
| num-grp-pins = <0x1>; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| sdc1_data_on { | |
| linux,phandle = <0xd8>; | |
| phandle = <0xd8>; | |
| config { | |
| pins = "sdc1_data"; | |
| bias-pull-up; | |
| drive-strength = <0xa>; | |
| }; | |
| }; | |
| sdc1_data_off { | |
| linux,phandle = <0xdc>; | |
| phandle = <0xdc>; | |
| config { | |
| pins = "sdc1_data"; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| sdc1_rclk_on { | |
| linux,phandle = <0xd9>; | |
| phandle = <0xd9>; | |
| config { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sdc1_rclk_off { | |
| linux,phandle = <0xdd>; | |
| phandle = <0xdd>; | |
| config { | |
| pins = "sdc1_rclk"; | |
| bias-pull-down; | |
| }; | |
| }; | |
| sdc2_clk_on { | |
| linux,phandle = <0xde>; | |
| phandle = <0xde>; | |
| config { | |
| pins = "sdc2_clk"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| }; | |
| }; | |
| sdc2_clk_off { | |
| linux,phandle = <0xe2>; | |
| phandle = <0xe2>; | |
| config { | |
| pins = "sdc2_clk"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| sdc2_cmd_on { | |
| linux,phandle = <0xdf>; | |
| phandle = <0xdf>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0xa>; | |
| }; | |
| }; | |
| sdc2_cmd_off { | |
| linux,phandle = <0xe3>; | |
| phandle = <0xe3>; | |
| config { | |
| pins = "sdc2_cmd"; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| sdc2_data_on { | |
| linux,phandle = <0xe0>; | |
| phandle = <0xe0>; | |
| config { | |
| pins = "sdc2_data"; | |
| bias-pull-up; | |
| drive-strength = <0xa>; | |
| }; | |
| }; | |
| sdc2_data_off { | |
| linux,phandle = <0xe4>; | |
| phandle = <0xe4>; | |
| config { | |
| pins = "sdc2_data"; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cd_on { | |
| linux,phandle = <0xe1>; | |
| phandle = <0xe1>; | |
| mux { | |
| pins = "gpio54"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio54"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| cd_off { | |
| linux,phandle = <0xe5>; | |
| phandle = <0xe5>; | |
| mux { | |
| pins = "gpio54"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio54"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_1 { | |
| i2c_1_active { | |
| linux,phandle = <0x17b>; | |
| phandle = <0x17b>; | |
| mux { | |
| pins = "gpio2", "gpio3"; | |
| function = "blsp_i2c1"; | |
| }; | |
| config { | |
| pins = "gpio2", "gpio3"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_1_sleep { | |
| linux,phandle = <0x17c>; | |
| phandle = <0x17c>; | |
| mux { | |
| pins = "gpio2", "gpio3"; | |
| function = "blsp_i2c1"; | |
| }; | |
| config { | |
| pins = "gpio2", "gpio3"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_1_bitbang { | |
| linux,phandle = <0x17d>; | |
| phandle = <0x17d>; | |
| mux { | |
| pins = "gpio2", "gpio3"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio2", "gpio3"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| i2c_2 { | |
| i2c_2_active { | |
| linux,phandle = <0x182>; | |
| phandle = <0x182>; | |
| mux { | |
| pins = "gpio6", "gpio7"; | |
| function = "blsp_i2c2"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_2_sleep { | |
| linux,phandle = <0x183>; | |
| phandle = <0x183>; | |
| mux { | |
| pins = "gpio6", "gpio7"; | |
| function = "blsp_i2c2"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_2_bitbang { | |
| linux,phandle = <0x184>; | |
| phandle = <0x184>; | |
| mux { | |
| pins = "gpio6", "gpio7"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio6", "gpio7"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| i2c_3 { | |
| i2c_3_active { | |
| linux,phandle = <0x185>; | |
| phandle = <0x185>; | |
| mux { | |
| pins = "gpio10", "gpio11"; | |
| function = "blsp_i2c3"; | |
| }; | |
| config { | |
| pins = "gpio10", "gpio11"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_3_sleep { | |
| linux,phandle = <0x186>; | |
| phandle = <0x186>; | |
| mux { | |
| pins = "gpio10", "gpio11"; | |
| function = "blsp_i2c3"; | |
| }; | |
| config { | |
| pins = "gpio10", "gpio11"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_3_bitbang { | |
| linux,phandle = <0x187>; | |
| phandle = <0x187>; | |
| mux { | |
| pins = "gpio10", "gpio11"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio10", "gpio11"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| i2c_4 { | |
| i2c_4_active { | |
| linux,phandle = <0x188>; | |
| phandle = <0x188>; | |
| mux { | |
| pins = "gpio14", "gpio15"; | |
| function = "blsp_i2c4"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_4_sleep { | |
| linux,phandle = <0x189>; | |
| phandle = <0x189>; | |
| mux { | |
| pins = "gpio14", "gpio15"; | |
| function = "blsp_i2c4"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_4_bitbang { | |
| linux,phandle = <0x18a>; | |
| phandle = <0x18a>; | |
| mux { | |
| pins = "gpio14", "gpio15"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio14", "gpio15"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| i2c_5 { | |
| i2c_5_active { | |
| linux,phandle = <0x18c>; | |
| phandle = <0x18c>; | |
| mux { | |
| pins = "gpio18", "gpio19"; | |
| function = "blsp_i2c5"; | |
| }; | |
| config { | |
| pins = "gpio18", "gpio19"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_5_sleep { | |
| linux,phandle = <0x18d>; | |
| phandle = <0x18d>; | |
| mux { | |
| pins = "gpio18", "gpio19"; | |
| function = "blsp_i2c5"; | |
| }; | |
| config { | |
| pins = "gpio18", "gpio19"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_5_bitbang { | |
| linux,phandle = <0x18e>; | |
| phandle = <0x18e>; | |
| mux { | |
| pins = "gpio18", "gpio19"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio18", "gpio19"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| i2c_6 { | |
| i2c_6_active { | |
| linux,phandle = <0x18f>; | |
| phandle = <0x18f>; | |
| mux { | |
| pins = "gpio22", "gpio23"; | |
| function = "blsp_i2c6"; | |
| }; | |
| config { | |
| pins = "gpio22", "gpio23"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_6_sleep { | |
| linux,phandle = <0x190>; | |
| phandle = <0x190>; | |
| mux { | |
| pins = "gpio22", "gpio23"; | |
| function = "blsp_i2c6"; | |
| }; | |
| config { | |
| pins = "gpio22", "gpio23"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_6_bitbang { | |
| linux,phandle = <0x191>; | |
| phandle = <0x191>; | |
| mux { | |
| pins = "gpio22", "gpio23"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio22", "gpio23"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| nfc { | |
| nfc_int_active { | |
| linux,phandle = <0x193>; | |
| phandle = <0x193>; | |
| mux { | |
| pins = "gpio28"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio28"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_int_suspend { | |
| linux,phandle = <0x195>; | |
| phandle = <0x195>; | |
| mux { | |
| pins = "gpio28"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio28"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_enable_active { | |
| linux,phandle = <0x194>; | |
| phandle = <0x194>; | |
| mux { | |
| pins = "gpio29", "gpio30", "gpio31"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio29", "gpio30", "gpio31"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| nfc_enable_suspend { | |
| linux,phandle = <0x196>; | |
| phandle = <0x196>; | |
| mux { | |
| pins = "gpio29", "gpio30", "gpio31"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio29", "gpio30", "gpio31"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| i2c_7 { | |
| i2c_7_active { | |
| linux,phandle = <0x198>; | |
| phandle = <0x198>; | |
| mux { | |
| pins = "gpio26", "gpio27"; | |
| function = "blsp_i2c7"; | |
| }; | |
| config { | |
| pins = "gpio26", "gpio27"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_7_sleep { | |
| linux,phandle = <0x199>; | |
| phandle = <0x199>; | |
| mux { | |
| pins = "gpio26", "gpio27"; | |
| function = "blsp_i2c7"; | |
| }; | |
| config { | |
| pins = "gpio26", "gpio27"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_7_bitbang { | |
| linux,phandle = <0x19a>; | |
| phandle = <0x19a>; | |
| mux { | |
| pins = "gpio26", "gpio27"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio26", "gpio27"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| i2c_8 { | |
| i2c_8_active { | |
| linux,phandle = <0x19b>; | |
| phandle = <0x19b>; | |
| mux { | |
| pins = "gpio30", "gpio31"; | |
| function = "blsp_i2c8_a"; | |
| }; | |
| config { | |
| pins = "gpio30", "gpio31"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| i2c_8_sleep { | |
| linux,phandle = <0x19c>; | |
| phandle = <0x19c>; | |
| mux { | |
| pins = "gpio30", "gpio31"; | |
| function = "blsp_i2c8_a"; | |
| }; | |
| config { | |
| pins = "gpio30", "gpio31"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| i2c_8_bitbang { | |
| linux,phandle = <0x19d>; | |
| phandle = <0x19d>; | |
| mux { | |
| pins = "gpio30", "gpio31"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio30", "gpio31"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| spi_1 { | |
| spi_1_active { | |
| linux,phandle = <0x19e>; | |
| phandle = <0x19e>; | |
| mux { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| function = "blsp_spi1"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_1_sleep { | |
| linux,phandle = <0x19f>; | |
| phandle = <0x19f>; | |
| mux { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| function = "blsp_spi1"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_2 { | |
| spi_2_active { | |
| linux,phandle = <0x1a0>; | |
| phandle = <0x1a0>; | |
| mux { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| function = "blsp_spi2"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_2_sleep { | |
| linux,phandle = <0x1a1>; | |
| phandle = <0x1a1>; | |
| mux { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| function = "blsp_spi2"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_3 { | |
| spi_3_active { | |
| linux,phandle = <0x1a2>; | |
| phandle = <0x1a2>; | |
| mux { | |
| pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
| function = "blsp_spi3"; | |
| }; | |
| config { | |
| pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_3_sleep { | |
| linux,phandle = <0x1a3>; | |
| phandle = <0x1a3>; | |
| mux { | |
| pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
| function = "blsp_spi3"; | |
| }; | |
| config { | |
| pins = "gpio8", "gpio9", "gpio10", "gpio11"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_4 { | |
| spi_4_active { | |
| linux,phandle = <0x1a4>; | |
| phandle = <0x1a4>; | |
| mux { | |
| pins = "gpio12", "gpio13", "gpio14", "gpio15"; | |
| function = "blsp_spi4"; | |
| }; | |
| config { | |
| pins = "gpio12", "gpio13", "gpio14", "gpio15"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_4_sleep { | |
| linux,phandle = <0x1a5>; | |
| phandle = <0x1a5>; | |
| mux { | |
| pins = "gpio12", "gpio13", "gpio14", "gpio15"; | |
| function = "blsp_spi4"; | |
| }; | |
| config { | |
| pins = "gpio12", "gpio13", "gpio14", "gpio15"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_5 { | |
| spi_5_active { | |
| linux,phandle = <0x1a6>; | |
| phandle = <0x1a6>; | |
| mux { | |
| pins = "gpio16", "gpio17", "gpio18", "gpio19"; | |
| function = "blsp_spi5"; | |
| }; | |
| config { | |
| pins = "gpio16", "gpio17", "gpio18", "gpio19"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_5_sleep { | |
| linux,phandle = <0x1a7>; | |
| phandle = <0x1a7>; | |
| mux { | |
| pins = "gpio16", "gpio17", "gpio18", "gpio19"; | |
| function = "blsp_spi5"; | |
| }; | |
| config { | |
| pins = "gpio16", "gpio17", "gpio18", "gpio19"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_6 { | |
| spi_6_active { | |
| linux,phandle = <0x1a8>; | |
| phandle = <0x1a8>; | |
| mux { | |
| pins = "gpio49", "gpio52", "gpio22", "gpio23"; | |
| function = "blsp_spi6"; | |
| }; | |
| config { | |
| pins = "gpio49", "gpio52", "gpio22", "gpio23"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_6_sleep { | |
| linux,phandle = <0x1a9>; | |
| phandle = <0x1a9>; | |
| mux { | |
| pins = "gpio49", "gpio52", "gpio22", "gpio23"; | |
| function = "blsp_spi6"; | |
| }; | |
| config { | |
| pins = "gpio49", "gpio52", "gpio22", "gpio23"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_7 { | |
| spi_7_active { | |
| linux,phandle = <0x1aa>; | |
| phandle = <0x1aa>; | |
| mux { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| function = "blsp_spi7"; | |
| }; | |
| config { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_7_sleep { | |
| linux,phandle = <0x1ab>; | |
| phandle = <0x1ab>; | |
| mux { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| function = "blsp_spi7"; | |
| }; | |
| config { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spi_8 { | |
| spi_8_active { | |
| linux,phandle = <0x1ac>; | |
| phandle = <0x1ac>; | |
| mux { | |
| pins = "gpio28", "gpio29", "gpio30", "gpio31"; | |
| function = "blsp_spi8_a"; | |
| }; | |
| config { | |
| pins = "gpio28", "gpio29", "gpio30", "gpio31"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| spi_8_sleep { | |
| linux,phandle = <0x1ad>; | |
| phandle = <0x1ad>; | |
| mux { | |
| pins = "gpio28", "gpio29", "gpio30", "gpio31"; | |
| function = "blsp_spi8_a"; | |
| }; | |
| config { | |
| pins = "gpio28", "gpio29", "gpio30", "gpio31"; | |
| drive-strength = <0x6>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| ant-check-pin { | |
| ant_check_default { | |
| linux,phandle = <0x28f>; | |
| phandle = <0x28f>; | |
| mux { | |
| pins = "gpio74"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio74"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| input-enable; | |
| input-debounce = <0x1388>; | |
| }; | |
| }; | |
| }; | |
| wcd_usbc_analog_en1 { | |
| wcd_usbc_ana_en1_idle { | |
| linux,phandle = <0x253>; | |
| phandle = <0x253>; | |
| mux { | |
| pins = "gpio80"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio80"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| wcd_usbc_ana_en1_active { | |
| linux,phandle = <0x252>; | |
| phandle = <0x252>; | |
| mux { | |
| pins = "gpio80"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio80"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| wcd_usbc_analog_en2n { | |
| wcd_usbc_ana_en2n_idle { | |
| linux,phandle = <0x255>; | |
| phandle = <0x255>; | |
| mux { | |
| pins = "gpio75"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio75"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| wcd_usbc_ana_en2n_active { | |
| linux,phandle = <0x254>; | |
| phandle = <0x254>; | |
| mux { | |
| pins = "gpio75"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio75"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| sdw_clk_pin { | |
| sdw_clk_sleep { | |
| linux,phandle = <0x367>; | |
| phandle = <0x367>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "sndwire_clk"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x2>; | |
| bias-bus-hold; | |
| }; | |
| }; | |
| sdw_clk_active { | |
| linux,phandle = <0x368>; | |
| phandle = <0x368>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "sndwire_clk"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x2>; | |
| bias-bus-hold; | |
| }; | |
| }; | |
| }; | |
| sdw_clk_data { | |
| sdw_data_sleep { | |
| linux,phandle = <0x369>; | |
| phandle = <0x369>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "sndwire_data"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| drive-strength = <0x4>; | |
| bias-bus-hold; | |
| }; | |
| }; | |
| sdw_data_active { | |
| linux,phandle = <0x36a>; | |
| phandle = <0x36a>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "sndwire_data"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| drive-strength = <0x4>; | |
| bias-bus-hold; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sck { | |
| pri_mi2s_sck_sleep { | |
| linux,phandle = <0x23b>; | |
| phandle = <0x23b>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_sck_active { | |
| linux,phandle = <0x237>; | |
| phandle = <0x237>; | |
| mux { | |
| pins = "gpio12"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio12"; | |
| drive-strength = <0x8>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_ws { | |
| pri_mi2s_ws_sleep { | |
| linux,phandle = <0x23c>; | |
| phandle = <0x23c>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_ws_active { | |
| linux,phandle = <0x238>; | |
| phandle = <0x238>; | |
| mux { | |
| pins = "gpio13"; | |
| function = "pri_mi2s_ws"; | |
| }; | |
| config { | |
| pins = "gpio13"; | |
| drive-strength = <0x8>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sd0 { | |
| pri_mi2s_sd0_sleep { | |
| linux,phandle = <0x23d>; | |
| phandle = <0x23d>; | |
| mux { | |
| pins = "gpio14"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_sd0_active { | |
| linux,phandle = <0x239>; | |
| phandle = <0x239>; | |
| mux { | |
| pins = "gpio14"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio14"; | |
| drive-strength = <0x8>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| pri_mi2s_sd1 { | |
| pri_mi2s_sd1_sleep { | |
| linux,phandle = <0x23e>; | |
| phandle = <0x23e>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| pri_mi2s_sd1_active { | |
| linux,phandle = <0x23a>; | |
| phandle = <0x23a>; | |
| mux { | |
| pins = "gpio15"; | |
| function = "pri_mi2s"; | |
| }; | |
| config { | |
| pins = "gpio15"; | |
| drive-strength = <0x8>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| spkr_1_sd_n { | |
| spkr_1_sd_n_sleep { | |
| linux,phandle = <0xb0>; | |
| phandle = <0xb0>; | |
| mux { | |
| pins = "gpio26"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| spkr_1_sd_n_active { | |
| linux,phandle = <0xaf>; | |
| phandle = <0xaf>; | |
| mux { | |
| pins = "gpio26"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio26"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| spkr_2_sd_n { | |
| spkr_2_sd_n_sleep { | |
| linux,phandle = <0xb2>; | |
| phandle = <0xb2>; | |
| mux { | |
| pins = "gpio27"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| spkr_2_sd_n_active { | |
| linux,phandle = <0xb1>; | |
| phandle = <0xb1>; | |
| mux { | |
| pins = "gpio27"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio27"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| wcd_gnd_mic_swap { | |
| wcd_gnd_mic_swap_idle { | |
| linux,phandle = <0x24d>; | |
| phandle = <0x24d>; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| output-low; | |
| }; | |
| }; | |
| wcd_gnd_mic_swap_active { | |
| linux,phandle = <0x24c>; | |
| phandle = <0x24c>; | |
| mux { | |
| pins = "gpio63"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio63"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| msm_hph_en0 { | |
| hph_en0_sleep { | |
| linux,phandle = <0xb4>; | |
| phandle = <0xb4>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| output-low; | |
| }; | |
| }; | |
| hph_en0_active { | |
| linux,phandle = <0xb3>; | |
| phandle = <0xb3>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| msm_hph_en1 { | |
| hph_en1_sleep { | |
| linux,phandle = <0xb6>; | |
| phandle = <0xb6>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| output-low; | |
| }; | |
| }; | |
| hph_en1_active { | |
| linux,phandle = <0xb5>; | |
| phandle = <0xb5>; | |
| mux { | |
| pins = "gpio25"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio25"; | |
| output-high; | |
| }; | |
| }; | |
| }; | |
| cci0_active { | |
| linux,phandle = <0x1c7>; | |
| phandle = <0x1c7>; | |
| mux { | |
| pins = "gpio36", "gpio37"; | |
| function = "cci_i2c"; | |
| }; | |
| config { | |
| pins = "gpio36", "gpio37"; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cci0_suspend { | |
| linux,phandle = <0x1c9>; | |
| phandle = <0x1c9>; | |
| mux { | |
| pins = "gpio36", "gpio37"; | |
| function = "cci_i2c"; | |
| }; | |
| config { | |
| pins = "gpio36", "gpio37"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cci1_active { | |
| linux,phandle = <0x1c8>; | |
| phandle = <0x1c8>; | |
| mux { | |
| pins = "gpio38", "gpio39"; | |
| function = "cci_i2c"; | |
| }; | |
| config { | |
| pins = "gpio38", "gpio39"; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cci1_suspend { | |
| linux,phandle = <0x1ca>; | |
| phandle = <0x1ca>; | |
| mux { | |
| pins = "gpio38", "gpio39"; | |
| function = "cci_i2c"; | |
| }; | |
| config { | |
| pins = "gpio38", "gpio39"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_actuator_vaf_active0 { | |
| linux,phandle = <0x36b>; | |
| phandle = <0x36b>; | |
| mux { | |
| pins = "gpio45"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio45"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_actuator_vaf_suspend0 { | |
| linux,phandle = <0x36c>; | |
| phandle = <0x36c>; | |
| mux { | |
| pins = "gpio45"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio45"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_actuator_vaf_active { | |
| linux,phandle = <0x1cb>; | |
| phandle = <0x1cb>; | |
| mux { | |
| pins = "gpio50"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio50"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_actuator_vaf_suspend { | |
| linux,phandle = <0x1cc>; | |
| phandle = <0x1cc>; | |
| mux { | |
| pins = "gpio50"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio50"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_tof_active { | |
| linux,phandle = <0x36d>; | |
| phandle = <0x36d>; | |
| mux { | |
| pins = "gpio50", "gpio42", "gpio45"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio50", "gpio42", "gpio45"; | |
| bias-pull-up; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_tof_suspend { | |
| linux,phandle = <0x36e>; | |
| phandle = <0x36e>; | |
| mux { | |
| pins = "gpio50", "gpio42", "gpio45"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio50", "gpio42", "gpio45"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_mclk0_active { | |
| linux,phandle = <0x1cf>; | |
| phandle = <0x1cf>; | |
| mux { | |
| pins = "gpio32"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio32"; | |
| bias-disable; | |
| drive-strength = <0x4>; | |
| }; | |
| }; | |
| cam_sensor_mclk0_suspend { | |
| linux,phandle = <0x1d1>; | |
| phandle = <0x1d1>; | |
| mux { | |
| pins = "gpio32"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio32"; | |
| bias-pull-down; | |
| drive-strength = <0x4>; | |
| }; | |
| }; | |
| cam_sensor_rear_active { | |
| linux,phandle = <0x36f>; | |
| phandle = <0x36f>; | |
| mux { | |
| pins = "gpio46", "gpio44"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio46", "gpio44"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_rear_suspend { | |
| linux,phandle = <0x370>; | |
| phandle = <0x370>; | |
| mux { | |
| pins = "gpio46", "gpio44"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio46", "gpio44"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_mclk1_active { | |
| linux,phandle = <0x1d9>; | |
| phandle = <0x1d9>; | |
| mux { | |
| pins = "gpio33"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio33"; | |
| bias-disable; | |
| drive-strength = <0x4>; | |
| }; | |
| }; | |
| cam_sensor_mclk1_suspend { | |
| linux,phandle = <0x1db>; | |
| phandle = <0x1db>; | |
| mux { | |
| pins = "gpio33"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio33"; | |
| bias-pull-down; | |
| drive-strength = <0x4>; | |
| }; | |
| }; | |
| cam_sensor_rear2_active { | |
| linux,phandle = <0x1d0>; | |
| phandle = <0x1d0>; | |
| mux { | |
| pins = "gpio48", "gpio51"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio48", "gpio51"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_rear2_suspend { | |
| linux,phandle = <0x1d2>; | |
| phandle = <0x1d2>; | |
| mux { | |
| pins = "gpio48", "gpio51"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio48", "gpio51"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_mclk2_active { | |
| linux,phandle = <0x371>; | |
| phandle = <0x371>; | |
| mux { | |
| pins = "gpio34"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio34"; | |
| bias-disable; | |
| drive-strength = <0x4>; | |
| }; | |
| }; | |
| cam_sensor_mclk2_suspend { | |
| linux,phandle = <0x372>; | |
| phandle = <0x372>; | |
| mux { | |
| pins = "gpio34"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio34"; | |
| bias-pull-down; | |
| drive-strength = <0x4>; | |
| }; | |
| }; | |
| cam_sensor_front_active { | |
| linux,phandle = <0x1da>; | |
| phandle = <0x1da>; | |
| mux { | |
| pins = "gpio47", "gpio44"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio47", "gpio44"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_front_suspend { | |
| linux,phandle = <0x1dc>; | |
| phandle = <0x1dc>; | |
| mux { | |
| pins = "gpio47"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio47"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_mclk3_active { | |
| linux,phandle = <0x1d5>; | |
| phandle = <0x1d5>; | |
| mux { | |
| pins = "gpio35"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio35"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_mclk3_suspend { | |
| linux,phandle = <0x1d7>; | |
| phandle = <0x1d7>; | |
| mux { | |
| pins = "gpio35"; | |
| function = "cam_mclk"; | |
| }; | |
| config { | |
| pins = "gpio35"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_front_iris_active { | |
| linux,phandle = <0x1d6>; | |
| phandle = <0x1d6>; | |
| mux { | |
| pins = "gpio52"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio52"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| cam_sensor_front_iris_suspend { | |
| linux,phandle = <0x1d8>; | |
| phandle = <0x1d8>; | |
| mux { | |
| pins = "gpio52"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio52"; | |
| bias-disable; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| blsp1_uart1_active { | |
| linux,phandle = <0x1b0>; | |
| phandle = <0x1b0>; | |
| mux { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| function = "blsp_uart1"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp1_uart1_sleep { | |
| linux,phandle = <0x1af>; | |
| phandle = <0x1af>; | |
| mux { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp1_uart2_active { | |
| linux,phandle = <0x1b3>; | |
| phandle = <0x1b3>; | |
| mux { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| function = "blsp_uart2 "; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp1_uart2_sleep { | |
| linux,phandle = <0x1b2>; | |
| phandle = <0x1b2>; | |
| mux { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio4", "gpio5", "gpio6", "gpio7"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp2_uart1 { | |
| linux,phandle = <0x373>; | |
| phandle = <0x373>; | |
| blsp2_uart1_tx_active { | |
| linux,phandle = <0x1b8>; | |
| phandle = <0x1b8>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "blsp_uart5"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp2_uart1_tx_sleep { | |
| linux,phandle = <0x1b5>; | |
| phandle = <0x1b5>; | |
| mux { | |
| pins = "gpio16"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio16"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| blsp2_uart1_rxcts_active { | |
| linux,phandle = <0x1b9>; | |
| phandle = <0x1b9>; | |
| mux { | |
| pins = "gpio17", "gpio18"; | |
| function = "blsp_uart5"; | |
| }; | |
| config { | |
| pins = "gpio17", "gpio18"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp2_uart1_rxcts_sleep { | |
| linux,phandle = <0x1b6>; | |
| phandle = <0x1b6>; | |
| mux { | |
| pins = "gpio17", "gpio18"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio17", "gpio18"; | |
| drive-strength = <0x2>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| blsp2_uart1_rfr_active { | |
| linux,phandle = <0x1ba>; | |
| phandle = <0x1ba>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "blsp_uart5"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp2_uart1_rfr_sleep { | |
| linux,phandle = <0x1b7>; | |
| phandle = <0x1b7>; | |
| mux { | |
| pins = "gpio19"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio19"; | |
| drive-strength = <0x2>; | |
| bias-no-pull; | |
| }; | |
| }; | |
| }; | |
| blsp2_uart2_active { | |
| linux,phandle = <0x1bd>; | |
| phandle = <0x1bd>; | |
| mux { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| function = "blsp_uart6_a"; | |
| }; | |
| config { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| blsp2_uart2_sleep { | |
| linux,phandle = <0x1bc>; | |
| phandle = <0x1bc>; | |
| mux { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio24", "gpio25", "gpio26", "gpio27"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| tlmm_gpio_key { | |
| gpio_key_active { | |
| linux,phandle = <0x262>; | |
| phandle = <0x262>; | |
| mux { | |
| pins = "gpio64", "gpio113"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio64", "gpio113"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| gpio_key_suspend { | |
| linux,phandle = <0x263>; | |
| phandle = <0x263>; | |
| mux { | |
| pins = "gpio64", "gpio113"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio64", "gpio113"; | |
| drive-strength = <0x2>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| pmx_mdss { | |
| linux,phandle = <0x374>; | |
| phandle = <0x374>; | |
| mdss_dsi_active { | |
| linux,phandle = <0x278>; | |
| phandle = <0x278>; | |
| mux { | |
| pins = "gpio53"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio53"; | |
| drive-strength = <0x8>; | |
| bias-disable = <0x0>; | |
| }; | |
| }; | |
| mdss_dsi_suspend { | |
| linux,phandle = <0x27a>; | |
| phandle = <0x27a>; | |
| mux { | |
| pins = "gpio53"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio53"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| pmx_mdss_te { | |
| mdss_te_active { | |
| linux,phandle = <0x279>; | |
| phandle = <0x279>; | |
| mux { | |
| pins = "gpio59"; | |
| function = "mdp_vsync"; | |
| }; | |
| config { | |
| pins = "gpio59"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| mdss_te_suspend { | |
| linux,phandle = <0x27b>; | |
| phandle = <0x27b>; | |
| mux { | |
| pins = "gpio59"; | |
| function = "mdp_vsync"; | |
| }; | |
| config { | |
| pins = "gpio59"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| }; | |
| mdss_dp_aux_active { | |
| linux,phandle = <0x280>; | |
| phandle = <0x280>; | |
| mux { | |
| pins = "gpio55", "gpio56"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio55", "gpio56"; | |
| bias-disable = <0x0>; | |
| drive-strength = <0x8>; | |
| }; | |
| }; | |
| mdss_dp_aux_suspend { | |
| linux,phandle = <0x282>; | |
| phandle = <0x282>; | |
| mux { | |
| pins = "gpio55", "gpio56"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio55", "gpio56"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| mdss_dp_usbplug_cc_active { | |
| linux,phandle = <0x281>; | |
| phandle = <0x281>; | |
| mux { | |
| pins = "gpio58"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio58"; | |
| bias-disable; | |
| drive-strength = <0x10>; | |
| }; | |
| }; | |
| mdss_dp_usbplug_cc_suspend { | |
| linux,phandle = <0x283>; | |
| phandle = <0x283>; | |
| mux { | |
| pins = "gpio58"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio58"; | |
| bias-pull-down; | |
| drive-strength = <0x2>; | |
| }; | |
| }; | |
| ts_mux { | |
| ts_active { | |
| linux,phandle = <0x17f>; | |
| phandle = <0x17f>; | |
| mux { | |
| pins = "gpio66", "gpio67"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio66", "gpio67"; | |
| drive-strength = <0x10>; | |
| bias-pull-up; | |
| }; | |
| }; | |
| ts_reset_suspend { | |
| linux,phandle = <0x181>; | |
| phandle = <0x181>; | |
| mux { | |
| pins = "gpio66"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio66"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| ts_int_suspend { | |
| linux,phandle = <0x180>; | |
| phandle = <0x180>; | |
| mux { | |
| pins = "gpio67"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio67"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c@c175000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc175000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x5f 0x0>; | |
| dmas = <0x17a 0x4 0x40 0x20000020 0x20 0x17a 0x5 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x56>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x24>; | |
| qcom,i2c-dat = <0xe7 0x2 0x0>; | |
| qcom,i2c-clk = <0xe7 0x3 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x17b>; | |
| pinctrl-1 = <0x17c>; | |
| pinctrl-2 = <0x17d>; | |
| status = "ok"; | |
| linux,phandle = <0x375>; | |
| phandle = <0x375>; | |
| novatek@62 { | |
| compatible = "novatek,NVT-ts"; | |
| reg = <0x62>; | |
| interrupt-parent = <0xe7>; | |
| interrupts = <0x43 0x2008>; | |
| vcc_i2c-supply = <0x17e>; | |
| pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; | |
| pinctrl-0 = <0x17f>; | |
| pinctrl-1 = <0x180 0x181>; | |
| novatek,reset-gpio = <0xe7 0x42 0x0>; | |
| novatek,irq-gpio = <0xe7 0x43 0x2001>; | |
| novatek,mp-support-dt; | |
| novatek-mp-criteria-5911@0 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "novatek-mp-criteria-5911"; | |
| IC_X_CFG_SIZE = <0x12>; | |
| IC_Y_CFG_SIZE = <0x24>; | |
| IC_KEY_CFG_SIZE = <0x4>; | |
| X_Channel = <0x12>; | |
| Y_Channel = <0x24>; | |
| AIN_X = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11>; | |
| AIN_Y = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; | |
| AIN_KEY = <0x0 0x1 0x2 0xff>; | |
| PS_Config_Lmt_Short_Rawdata_P = <0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x36b0 0x4e20 0x4e20 0x4e20>; | |
| PS_Config_Lmt_Short_Rawdata_N = <0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2d1e 0x2d1e 0x2d1e>; | |
| PS_Config_Lmt_Short_Diff_P = <0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c>; | |
| PS_Config_Lmt_Short_Diff_N = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| PS_Config_Lmt_Short_Base_P = <0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0>; | |
| PS_Config_Lmt_Short_Base_N = <0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 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| PS_Config_Lmt_Open_Rawdata_P = <0x76b 0xb21 0xb90 0xb92 0xb97 0xb8f 0xb94 0xafd 0xffff 0xffff 0xb16 0xbbb 0xbae 0xbb7 0xbc3 0xbd1 0xb59 0x778 0xaf0 0xb8d 0xb87 0xb8a 0xb8c 0xb83 0xb8a 0xb78 0xb28 0xb47 0xb9d 0xbb0 0xba8 0xbb0 0xbbc 0xbc8 0xbce 0xb11 0xba5 0xba0 0xb9a 0xb9b 0xb9e 0xb96 0xb9a 0xb8a 0xb7c 0xb90 0xb9d 0xbb0 0xba9 0xbad 0xbbb 0xbc6 0xbcc 0xbd4 0xb9b 0xb9b 0xb9e 0xb9f 0xb9f 0xb96 0xb9a 0xb88 0xb7a 0xb8f 0xb9e 0xbb3 0xbae 0xbb2 0xbc1 0xbce 0xbd3 0xbd8 0xbb1 0xb9a 0xb96 0xb96 0xb95 0xb8f 0xb92 0xb81 0xb74 0xb96 0xba4 0xbb1 0xbb0 0xbb3 0xbbf 0xbcc 0xbd3 0xbd6 0xbb0 0xb99 0xb9a 0xb99 0xb96 0xb90 0xb92 0xb7f 0xb73 0xb9b 0xba8 0xbb5 0xbb3 0xbba 0xbc5 0xbce 0xbd7 0xbd8 0xba9 0xba8 0xba4 0xba2 0xba0 0xb9a 0xb9d 0xb88 0xb81 0xb9d 0xbac 0xbb6 0xbb6 0xbbb 0xbc6 0xbcf 0xbd7 0xbd4 0xbac 0xbb2 0xbac 0xba9 0xbb0 0xba7 0xba9 0xb95 0xb90 0xba5 0xbb3 0xbb3 0xbad 0xbbf 0xbca 0xbd1 0xbda 0xbd4 0xbb6 0xbac 0xba9 0xba4 0xba4 0xb9e 0xba2 0xb8c 0xb87 0xba5 0xbb5 0xbba 0xbb2 0xbc1 0xbce 0xbd3 0xbd8 0xbd1 0xbc0 0xba9 0xba9 0xba4 0xba5 0xb9d 0xb9e 0xb8b 0xb84 0xbb1 0xbbe 0xbc1 0xbbb 0xbc9 0xbd4 0xbda 0xbdf 0xbd8 0xbba 0xba3 0xba2 0xb9d 0xb97 0xb91 0xb97 0xb88 0xb7f 0xbb3 0xbbb 0xbc1 0xbbf 0xbc8 0xbcf 0xbd8 0xbdd 0xbd4 0xbb6 0xba5 0xba7 0xba0 0xb9f 0xb99 0xb9b 0xb8b 0xb84 0xba4 0xbab 0xbb2 0xbb0 0xbbe 0xbc4 0xbc9 0xbce 0xbc4 0xbab 0xbab 0xbad 0xba5 0xba5 0xb9e 0xb9f 0xb90 0xb8a 0xbb1 0xbb9 0xbbf 0xbbc 0xbca 0xbd1 0xbd6 0xbd6 0xbca 0xbb0 0xba8 0xba9 0xba0 0xba2 0xb99 0xb97 0xb8f 0xb84 0xbb9 0xbc1 0xbc8 0xbc5 0xbd1 0xbd6 0xbda 0xbda 0xbce 0xbb1 0xba3 0xbab 0xba3 0xba2 0xb9b 0xb97 0xb92 0xb88 0xbb1 0xbb7 0xbc3 0xbbe 0xbca 0xbce 0xbcf 0xbcc 0xbc4 0xbad 0xb9e 0xba5 0xb9e 0xb9b 0xb92 0xb97 0xb8f 0xb81 0xbab 0xbb2 0xbbb 0xbba 0xbc8 0xbca 0xbcf 0xbcc 0xbbf 0xbad 0xb97 0xb9f 0xb95 0xb95 0xb8c 0xb91 0xb90 0xb78 0xba7 0xbac 0xbb3 0xbb5 0xbbf 0xbc0 0xbc6 0xbc4 0xbb9 0xba5 0xb94 0xb9b 0xb92 0xb8f 0xb86 0xb8b 0xb88 0xb75 0xb9e 0xba5 0xbab 0xbac 0xbb6 0xbb6 0xbbb 0xbb6 0xbae 0xb9d 0xb90 0xb94 0xb8c 0xb8b 0xb83 0xb88 0xb84 0xb6f 0xba2 0xba9 0xbb2 0xbb1 0xbbb 0xbbe 0xbc1 0xbba 0xbb0 0xb91 0xb95 0xb9d 0xb95 0xb92 0xb8a 0xb8f 0xb8b 0xb7c 0xb95 0xb9a 0xba5 0xba3 0xbad 0xbad 0xbb5 0xbab 0xba4 0xb8d 0xb7d 0xb82 0xb7a 0xb78 0xb71 0xb78 0xb74 0xb6a 0xb9e 0xba3 0xbae 0xbad 0xbb6 0xbb6 0xbbc 0xbb7 0xbae 0xb91 0xb83 0xb8b 0xb82 0xb81 0xb7a 0xb82 0xb7d 0xb71 0xb8a 0xb8d 0xb9f 0xb9b 0xba5 0xba4 0xba9 0xba4 0xb9a 0xb7d 0xb7a 0xb7d 0xb75 0xb74 0xb6c 0xb75 0xb71 0xb63 0xb8b 0xb8f 0xb9d 0xb9a 0xba4 0xba4 0xba5 0xb9f 0xb94 0xb84 0xb6c 0xb70 0xb66 0xb63 0xb5e 0xb67 0xb65 0xb57 0xb8d 0xb95 0xba2 0xb9f 0xba5 0xba5 0xba8 0xba0 0xb96 0xa7c 0xa6c 0xa72 0xa6d 0xa69 0xa62 0xa69 0xa64 0xa5e 0xa7e 0xa7f 0xa91 0xa8e 0xa97 0xa9b 0xa98 0xa94 0xa93 0xa73 0xa6e 0xa71 0xa6c 0xa6b 0xa63 0xa6c 0xa68 0xa60 0xa73 0xa77 0xa84 0xa81 0xa8d 0xa8f 0xa8e 0xa8a 0xa89 0xa71 0xa63 0xa67 0xa62 0xa5f 0xa57 0xa5f 0xa5d 0xa55 0xa78 0xa7a 0xa8a 0xa89 0xa91 0xa94 0xa93 0xa91 0xa8e 0xa75 0xa62 0xa65 0xa5f 0xa5d 0xa59 0xa5f 0xa5b 0xa54 0xa78 0xa7a 0xa89 0xa88 0xa8f 0xa93 0xa91 0xa8f 0xa8c 0xa65 0xa5f 0xa62 0xa5b 0xa55 0xa50 0xa5b 0xa56 0xa4d 0xa62 0xa64 0xa71 0xa6e 0xa75 0xa77 0xa7a 0xa78 0xa76 0xa64 0xa55 0xa57 0xa51 0xa4f 0xa49 0xa52 0xa4b 0xa44 0xa69 0xa6c 0xa77 0xa73 0xa7b 0xa7e 0xa7e 0xa7f 0xa7c 0xa60 0xa52 0xa52 0xa4b 0xa4b 0xa46 0xa4f 0xa48 0xa42 0xa60 0xa64 0xa6e 0xa6c 0xa73 0xa75 0xa75 0xa76 0xa71 0xa57 0xa42 0xa42 0xa3a 0xa39 0xa35 0xa3f 0xa35 0xa33 0xa5f 0xa63 0xa6d 0xa6b 0xa73 0xa75 0xa77 0xa77 0xa72 0xa54 0xa38 0xa36 0xa30 0xa30 0xa2c 0xa36 0xa2c 0xa27 0xa4b 0xa4f 0xa57 0xa55 0xa5d 0xa5f 0xa5e 0xa60 0xa5e 0xa42 0xa36 0xa36 0xa30 0xa30 0xa2b 0xa36 0xa2a 0xa25 0xa43 0xa49 0xa50 0xa4f 0xa59 0xa5a 0xa5d 0xa5f 0xa63 0x94b 0xa26 0xa25 0xa20 0xa1e 0xa19 0xa2a 0xa19 0xa13 0xa2c 0xa35 0xa47 0xa39 0xa41 0xa41 0xa46 0xa47 0x96a 0x618 0x9b5 0xa2e 0xa28 0xa2c 0xa28 0xa35 0xa26 0xa1e 0xa21 0xa2b 0xa3e 0xa30 0xa36 0xa36 0xa39 0x9c3 0x618 0x32c8 0x32c8 0x32c8>; | |
| PS_Config_Lmt_Open_Rawdata_N = <0x444 0x666 0x6a5 0x6a7 0x6aa 0x6a4 0x6a7 0x650 0xffff0001 0xffff0001 0x65f 0x6be 0x6b7 0x6bc 0x6c2 0x6ca 0x686 0x44b 0x649 0x6a4 0x6a0 0x6a1 0x6a3 0x69e 0x6a1 0x697 0x669 0x67c 0x6ac 0x6b7 0x6b3 0x6b7 0x6bf 0x6c5 0x6c9 0x65c 0x6b2 0x6af 0x6ab 0x6ac 0x6ad 0x6a9 0x6ab 0x6a1 0x699 0x6a5 0x6ac 0x6b7 0x6b4 0x6b6 0x6be 0x6c5 0x6c7 0x6cd 0x6ac 0x6ac 0x6ad 0x6ae 0x6ae 0x6a9 0x6ab 0x6a1 0x699 0x6a4 0x6ad 0x6ba 0x6b7 0x6b9 0x6c2 0x6c9 0x6cc 0x6cf 0x6b8 0x6ab 0x6a9 0x6a9 0x6a8 0x6a4 0x6a7 0x69c 0x695 0x6a9 0x6b1 0x6b8 0x6b7 0x6ba 0x6c0 0x6c7 0x6cc 0x6cd 0x6b7 0x6aa 0x6ab 0x6aa 0x6a9 0x6a5 0x6a7 0x69c 0x694 0x6ac 0x6b3 0x6ba 0x6ba 0x6bd 0x6c4 0x6c9 0x6ce 0x6cf 0x6b4 0x6b3 0x6b1 0x6af 0x6af 0x6ab 0x6ac 0x6a1 0x69c 0x6ac 0x6b5 0x6bb 0x6bb 0x6be 0x6c5 0x6ca 0x6ce 0x6cd 0x6b5 0x6b9 0x6b5 0x6b4 0x6b7 0x6b2 0x6b4 0x6a8 0x6a5 0x6b2 0x6ba 0x6ba 0x6b6 0x6c0 0x6c7 0x6ca 0x6cf 0x6cd 0x6bb 0x6b5 0x6b4 0x6b1 0x6b1 0x6ad 0x6af 0x6a3 0x6a0 0x6b2 0x6ba 0x6bd 0x6b9 0x6c2 0x6c9 0x6cc 0x6cf 0x6ca 0x6c1 0x6b4 0x6b4 0x6b1 0x6b2 0x6ac 0x6ad 0x6a2 0x69f 0x6b8 0x6bf 0x6c2 0x6be 0x6c6 0x6cd 0x6cf 0x6d2 0x6cf 0x6bd 0x6b0 0x6af 0x6ac 0x6aa 0x6a6 0x6aa 0x6a1 0x69c 0x6ba 0x6be 0x6c2 0x6c0 0x6c5 0x6ca 0x6cf 0x6d2 0x6cd 0x6bb 0x6b2 0x6b2 0x6af 0x6ae 0x6aa 0x6ac 0x6a2 0x69f 0x6b1 0x6b4 0x6b9 0x6b7 0x6bf 0x6c3 0x6c6 0x6c9 0x6c3 0x6b4 0x6b4 0x6b6 0x6b2 0x6b2 0x6ad 0x6ae 0x6a5 0x6a1 0x6b8 0x6bc 0x6c0 0x6bf 0x6c7 0x6ca 0x6cd 0x6cd 0x6c7 0x6b7 0x6b3 0x6b4 0x6af 0x6af 0x6aa 0x6aa 0x6a4 0x69f 0x6bc 0x6c2 0x6c5 0x6c4 0x6ca 0x6cd 0x6cf 0x6cf 0x6c9 0x6b8 0x6b0 0x6b4 0x6b0 0x6af 0x6ac 0x6aa 0x6a7 0x6a1 0x6b8 0x6bc 0x6c2 0x6bf 0x6c7 0x6c9 0x6ca 0x6c7 0x6c3 0x6b6 0x6ad 0x6b2 0x6ad 0x6ac 0x6a7 0x6aa 0x6a4 0x69c 0x6b4 0x6b9 0x6be 0x6bd 0x6c5 0x6c7 0x6ca 0x6c7 0x6c0 0x6b6 0x6aa 0x6ae 0x6a8 0x6a8 0x6a3 0x6a6 0x6a5 0x697 0x6b2 0x6b5 0x6ba 0x6ba 0x6c0 0x6c1 0x6c5 0x6c3 0x6bc 0x6b2 0x6a7 0x6ac 0x6a7 0x6a4 0x69f 0x6a2 0x6a1 0x696 0x6ad 0x6b2 0x6b4 0x6b5 0x6bb 0x6bb 0x6be 0x6bb 0x6b7 0x6ac 0x6a5 0x6a7 0x6a3 0x6a2 0x69e 0x6a1 0x69f 0x692 0x6af 0x6b4 0x6b9 0x6b8 0x6be 0x6bf 0x6c2 0x6bd 0x6b7 0x6a6 0x6a8 0x6ac 0x6a8 0x6a7 0x6a1 0x6a4 0x6a2 0x699 0x6a8 0x6ab 0x6b2 0x6b0 0x6b6 0x6b6 0x6ba 0x6b4 0x6b1 0x6a4 0x69a 0x69d 0x699 0x697 0x694 0x697 0x695 0x68f 0x6ad 0x6b0 0x6b7 0x6b6 0x6bb 0x6bb 0x6bf 0x6bc 0x6b7 0x6a6 0x69e 0x6a2 0x69d 0x69c 0x699 0x69d 0x69a 0x694 0x6a1 0x6a4 0x6ae 0x6ac 0x6b2 0x6b1 0x6b4 0x6b1 0x6ab 0x69a 0x699 0x69a 0x696 0x695 0x691 0x696 0x694 0x68c 0x6a2 0x6a4 0x6ac 0x6ab 0x6b1 0x6b1 0x6b2 0x6ae 0x6a7 0x69f 0x691 0x693 0x68d 0x68c 0x689 0x68e 0x68c 0x684 0x6a4 0x6a8 0x6af 0x6ae 0x6b2 0x6b2 0x6b3 0x6af 0x6a9 0x607 0x5fd 0x601 0x5fe 0x5fc 0x5f7 0x5fc 0x5f9 0x5f5 0x607 0x608 0x612 0x611 0x616 0x618 0x617 0x615 0x614 0x602 0x5ff 0x600 0x5fd 0x5fd 0x5f8 0x5fd 0x5fb 0x5f7 0x602 0x604 0x60b 0x60a 0x610 0x612 0x611 0x60f 0x60e 0x600 0x5f8 0x5fa 0x5f7 0x5f6 0x5f2 0x5f6 0x5f4 0x5f0 0x605 0x605 0x60f 0x60e 0x612 0x615 0x614 0x612 0x611 0x602 0x5f7 0x5fa 0x5f6 0x5f4 0x5f2 0x5f6 0x5f4 0x5ef 0x605 0x605 0x60e 0x60d 0x612 0x614 0x612 0x612 0x60f 0x5fa 0x5f6 0x5f7 0x5f4 0x5f0 0x5ed 0x5f4 0x5f1 0x5ec 0x5f7 0x5f9 0x600 0x5ff 0x602 0x604 0x605 0x605 0x603 0x5f9 0x5f0 0x5f2 0x5ee 0x5ec 0x5ea 0x5ef 0x5ea 0x5e7 0x5fc 0x5fd 0x604 0x602 0x606 0x607 0x607 0x608 0x607 0x5f7 0x5ef 0x5ef 0x5ea 0x5ea 0x5e7 0x5ec 0x5e9 0x5e5 0x5f7 0x5f9 0x5ff 0x5fd 0x602 0x602 0x602 0x603 0x600 0x5f2 0x5e5 0x5e5 0x5e1 0x5e0 0x5de 0x5e4 0x5de 0x5dc 0x5f6 0x5f8 0x5fe 0x5fd 0x602 0x602 0x604 0x604 0x601 0x5ef 0x5df 0x5df 0x5db 0x5db 0x5d9 0x5df 0x5d9 0x5d6 0x5ea 0x5ec 0x5f2 0x5f0 0x5f4 0x5f6 0x5f5 0x5f7 0x5f5 0x5e5 0x5df 0x5df 0x5db 0x5db 0x5d8 0x5df 0x5d7 0x5d4 0x5e6 0x5ea 0x5ed 0x5ec 0x5f2 0x5f3 0x5f4 0x5f6 0x5f8 0x558 0x5d5 0x5d4 0x5d1 0x5d1 0x5ce 0x5d7 0x5ce 0x5ca 0x5d9 0x5de 0x5e8 0x5e0 0x5e4 0x5e4 0x5e7 0x5e8 0x569 0x381 0x594 0x5d9 0x5d7 0x5d9 0x5d7 0x5de 0x5d5 0x5d1 0x5d2 0x5d8 0x5e3 0x5db 0x5df 0x5df 0x5e0 0x59c 0x381 0x1964 0x1964 0x1964>; | |
| PS_Config_Lmt_FW_Rawdata_P = <0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0xffff 0xffff 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x7d0 0x7d0 0x7d0>; | |
| PS_Config_Lmt_FW_Rawdata_N = <0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0xffff0001 0xffff0001 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x190 0x190 0x190>; | |
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| PS_Config_Diff_Test_Frame = <0x32>; | |
| }; | |
| novatek-mp-criteria-5913@0 { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| compatible = "novatek-mp-criteria-5913"; | |
| IC_X_CFG_SIZE = <0x12>; | |
| IC_Y_CFG_SIZE = <0x24>; | |
| IC_KEY_CFG_SIZE = <0x0>; | |
| X_Channel = <0x12>; | |
| Y_Channel = <0x24>; | |
| AIN_X = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11>; | |
| AIN_Y = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>; | |
| AIN_KEY = <0x0 0x1 0x2 0xff>; | |
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| PS_Config_Lmt_Short_Rawdata_N = <0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2af8 0x2d1e 0x2d1e 0x2d1e>; | |
| PS_Config_Lmt_Short_Diff_P = <0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c 0x189c>; | |
| PS_Config_Lmt_Short_Diff_N = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| PS_Config_Lmt_Short_Base_P = <0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0 0x7d0>; | |
| PS_Config_Lmt_Short_Base_N = <0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 0xfffff830 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| PS_Config_Lmt_Open_Rawdata_P = <0xffff 0xd51 0xd4a 0xd4a 0xd4f 0xd41 0xd44 0xd0e 0xffff 0xffff 0xd4b 0xd89 0xd8b 0xd96 0xd96 0xd8b 0xd8f 0xffff 0xc1a 0xc40 0xc41 0xc3e 0xc41 0xc37 0xc3a 0xc31 0xb86 0xbb1 0xc60 0xc6b 0xc6c 0xc75 0xc76 0xc74 0xc71 0xc42 0xcaf 0xc90 0xc90 0xc8e 0xc90 0xc85 0xc88 0xc7d 0xc7d 0xcb3 0xcaf 0xcbb 0xcbc 0xcc6 0xcc8 0xcc3 0xcc3 0xcd4 0xc65 0xc46 0xc47 0xc44 0xc45 0xc3a 0xc3d 0xc31 0xc33 0xc69 0xc65 0xc71 0xc72 0xc7a 0xc7e 0xc7b 0xc7b 0xc8c 0xcb6 0xc95 0xc97 0xc93 0xc93 0xc88 0xc8c 0xc7f 0xc81 0xcb9 0xcb3 0xcc0 0xcc0 0xcc9 0xccc 0xcc9 0xccb 0xcdd 0xc6b 0xc4a 0xc4b 0xc46 0xc46 0xc3c 0xc40 0xc33 0xc35 0xc64 0xc5f 0xc6c 0xc6d 0xc75 0xc79 0xc79 0xc7a 0xc8f 0xcb5 0xc93 0xc94 0xc90 0xc90 0xc86 0xc88 0xc7b 0xc7f 0xcb1 0xca9 0xcb9 0xcb9 0xcc2 0xcc6 0xcc6 0xcc3 0xcd8 0xc6c 0xc49 0xc4b 0xc46 0xc47 0xc3d 0xc40 0xc33 0xc38 0xc61 0xc5b 0xc69 0xc68 0xc70 0xc74 0xc76 0xc74 0xc8b 0xcb7 0xc94 0xc97 0xc92 0xc93 0xc87 0xc8c 0xc7d 0xc82 0xcad 0xca5 0xcb5 0xcb3 0xcbc 0xcbf 0xcc3 0xcc0 0xcda 0xc61 0xc40 0xc42 0xc3c 0xc3d 0xc33 0xc38 0xc2b 0xc2d 0xc5b 0xc54 0xc63 0xc60 0xc68 0xc6b 0xc71 0xc6e 0xc88 0xcae 0xc8b 0xc8f 0xc88 0xc88 0xc7f 0xc83 0xc76 0xc79 0xcac 0xca4 0xcaf 0xcaf 0xcb7 0xcba 0xcc0 0xcbe 0xcd8 0xc5f 0xc3a 0xc40 0xc39 0xc39 0xc2f 0xc34 0xc28 0xc2b 0xc54 0xc4a 0xc54 0xc53 0xc5b 0xc5e 0xc64 0xc63 0xc7d 0xca1 0xc7f 0xc83 0xc7d 0xc7e 0xc74 0xc78 0xc6c 0xc6e 0xc9c 0xc90 0xc99 0xc98 0xca1 0xca4 0xcac 0xcac 0xcc7 0xc53 0xc31 0xc35 0xc2f 0xc30 0xc26 0xc2a 0xc22 0xc20 0xc49 0xc40 0xc47 0xc46 0xc4f 0xc52 0xc5a 0xc5b 0xc76 0xc94 0xc71 0xc78 0xc71 0xc72 0xc68 0xc6c 0xc67 0xc63 0xc93 0xc88 0xc90 0xc8f 0xc98 0xc99 0xca2 0xca1 0xcbe 0xc40 0xc1f 0xc24 0xc1e 0xc1f 0xc16 0xc1d 0xc15 0xc11 0xc3a 0xc34 0xc39 0xc37 0xc40 0xc44 0xc4b 0xc4b 0xc67 0xc87 0xc65 0xc6b 0xc64 0xc67 0xc5c 0xc63 0xc61 0xc58 0xc87 0xc81 0xc83 0xc82 0xc8b 0xc8c 0xc95 0xc95 0xcb3 0xc31 0xc11 0xc16 0xc10 0xc10 0xc06 0xc0e 0xc08 0xc03 0xc2b 0xc20 0xc28 0xc24 0xc2c 0xc2f 0xc38 0xc38 0xc54 0xc6e 0xc4d 0xc52 0xc4a 0xc4d 0xc44 0xc4a 0xc44 0xc3e 0xc75 0xc6b 0xc72 0xc6d 0xc76 0xc79 0xc82 0xc83 0xc9f 0xc1b 0xbf8 0xbff 0xbf8 0xbf9 0xbf0 0xbf8 0xbf2 0xbef 0xc1d 0xc12 0xc1a 0xc15 0xc1d 0xc20 0xc27 0xc28 0xc45 0xc5b 0xc39 0xc3e 0xc38 0xc3a 0xc31 0xc39 0xc31 0xc33 0xc60 0xc56 0xc5c 0xc58 0xc60 0xc63 0xc6b 0xc6c 0xc8a 0xc06 0xbe3 0xbe9 0xbe3 0xbe5 0xbdd 0xbe7 0xbdd 0xbdd 0xc03 0xbf8 0xc01 0xbfc 0xc03 0xc06 0xc0d 0xc0e 0xc2c 0xc44 0xc23 0xc27 0xc22 0xc23 0xc1b 0xc23 0xc1b 0xc1a 0xc4d 0xc41 0xc4a 0xc45 0xc4d 0xc4f 0xc54 0xc57 0xc75 0xbee 0xbcc 0xbd0 0xbc9 0xbcc 0xbc4 0xbcd 0xbc5 0xbc4 0xbeb 0xbe1 0xbeb 0xbe5 0xbec 0xbee 0xbf4 0xbf6 0xc13 0xb68 0xb47 0xb4d 0xb49 0xb47 0xb40 0xb49 0xb41 0xb45 0xb71 0xb63 0xb6c 0xb65 0xb6d 0xb70 0xb75 0xb77 0xb94 0xb1a 0xaf9 0xafd 0xaf8 0xaf9 0xaf2 0xafb 0xaf3 0xaf7 0xb12 0xb08 0xb11 0xb0a 0xb11 0xb13 0xb1a 0xb1c 0xb39 0xb54 0xb31 0xb36 0xb30 0xb31 0xb2b 0xb34 0xb2d 0xb2f 0xb53 0xb4e 0xb54 0xb4d 0xb54 0xb57 0xb5c 0xb60 0xb7f 0xb01 0xade 0xae3 0xadd 0xade 0xad8 0xae1 0xadb 0xadb 0xaeb 0xaea 0xaf2 0xaec 0xaf3 0xaf4 0xafc 0xafd 0xb1c 0xb38 0xb19 0xb1c 0xb17 0xb17 0xb11 0xb1b 0xb12 0xb15 0xb28 0xb26 0xb30 0xb28 0xb2f 0xb31 0xb38 0xb3a 0xb57 0xadf 0xac0 0xac4 0xabf 0xabf 0xaba 0xac3 0xaba 0xabc 0xacd 0xacb 0xad6 0xace 0xad4 0xad6 0xade 0xadf 0xaf9 0xb17 0xaf7 0xafb 0xaf4 0xaf4 0xaef 0xaf8 0xaee 0xaf3 0xb0a 0xb08 0xb13 0xb0c 0xb11 0xb15 0xb1b 0xb1c 0xb38 0xac1 0xaa0 0xaa4 0xa9e 0xa9e 0xa98 0xaa2 0xa98 0xa9c 0xaae 0xaab 0xab8 0xaaf 0xab6 0xab8 0xabf 0xac0 0xada 0xaf5 0xad6 0xad9 0xad4 0xad4 0xacd 0xada 0xacd 0xad2 0xae7 0xae5 0xaf2 0xae8 0xaf0 0xaf2 0xaf8 0xaf9 0xb15 0x934 0xa7a 0xa7d 0xa79 0xa79 0xa73 0xa82 0xa73 0xa77 0xa88 0xa84 0xa95 0xa88 0xa8f 0xa91 0xa98 0xa98 0x947 0x91b 0xaad 0xab1 0xaab 0xaad 0xaa6 0xab6 0xaa5 0xaaa 0xac5 0xac1 0xad4 0xac4 0xacc 0xacd 0xad4 0xad6 0x93a 0x871 0xa02 0xa6a 0xa70 0xa71 0xa63 0xa73 0xa64 0xa69 0xa7d 0xa7a 0xa8b 0xa7d 0xa8b 0xa8c 0xa88 0xa23 0x88b 0x32c8 0x32c8 0x32c8>; | |
| PS_Config_Lmt_Open_Rawdata_N = <0xffff0001 0x72b 0x728 0x728 0x72b 0x723 0x724 0x708 0xffff0001 0xffff0001 0x729 0x74a 0x74b 0x751 0x751 0x74b 0x74d 0xffff0001 0x684 0x698 0x699 0x698 0x699 0x694 0x696 0x691 0x634 0x64b 0x6aa 0x6b0 0x6b0 0x6b5 0x6b6 0x6b4 0x6b3 0x69a 0x6d5 0x6c4 0x6c4 0x6c2 0x6c4 0x6be 0x6c0 0x6b9 0x6b9 0x6d7 0x6d5 0x6db 0x6dc 0x6e1 0x6e2 0x6df 0x6df 0x6e8 0x6ad 0x69c 0x69d 0x69b 0x69b 0x696 0x697 0x691 0x691 0x6af 0x6ad 0x6b3 0x6b4 0x6b8 0x6ba 0x6b9 0x6b9 0x6c2 0x6d8 0x6c7 0x6c7 0x6c5 0x6c5 0x6c0 0x6c2 0x6bb 0x6bb 0x6da 0x6d7 0x6de 0x6de 0x6e3 0x6e4 0x6e3 0x6e3 0x6ed 0x6b0 0x69e 0x69f 0x69c 0x69c 0x696 0x698 0x691 0x693 0x6ac 0x6a9 0x6b0 0x6b1 0x6b5 0x6b7 0x6b7 0x6b8 0x6c3 0x6d7 0x6c5 0x6c6 0x6c4 0x6c4 0x6be 0x6c0 0x6b9 0x6bb 0x6d5 0x6d1 0x6da 0x6da 0x6de 0x6e1 0x6e1 0x6df 0x6ea 0x6b0 0x69d 0x69f 0x69c 0x69d 0x697 0x698 0x691 0x694 0x6ab 0x6a7 0x6af 0x6ae 0x6b2 0x6b4 0x6b6 0x6b4 0x6c1 0x6d9 0x6c6 0x6c7 0x6c5 0x6c5 0x6bf 0x6c2 0x6b9 0x6bc 0x6d3 0x6cf 0x6d7 0x6d7 0x6dc 0x6dd 0x6df 0x6de 0x6ec 0x6ab 0x698 0x69a 0x696 0x697 0x691 0x694 0x68d 0x68f 0x6a7 0x6a4 0x6ab 0x6aa 0x6ae 0x6b0 0x6b3 0x6b2 0x6c0 0x6d4 0x6c1 0x6c3 0x6c0 0x6c0 0x6bb 0x6bd 0x6b6 0x6b7 0x6d3 0x6ce 0x6d5 0x6d5 0x6d9 0x6da 0x6de 0x6dc 0x6ea 0x6a9 0x696 0x698 0x695 0x695 0x68f 0x692 0x68c 0x68d 0x6a4 0x69e 0x6a4 0x6a3 0x6a7 0x6a9 0x6ac 0x6ab 0x6b9 0x6cd 0x6bb 0x6bd 0x6b9 0x6ba 0x6b4 0x6b7 0x6b0 0x6b2 0x6ca 0x6c4 0x6c9 0x6c8 0x6cd 0x6ce 0x6d3 0x6d3 0x6e1 0x6a3 0x691 0x693 0x68f 0x690 0x68a 0x68d 0x688 0x688 0x69d 0x698 0x69d 0x69c 0x6a1 0x6a2 0x6a6 0x6a7 0x6b6 0x6c6 0x6b3 0x6b7 0x6b3 0x6b4 0x6ae 0x6b0 0x6ad 0x6ab 0x6c5 0x6c0 0x6c4 0x6c3 0x6c8 0x6c9 0x6ce 0x6cd 0x6dc 0x698 0x687 0x68a 0x686 0x687 0x682 0x686 0x681 0x67f 0x696 0x692 0x695 0x694 0x698 0x69b 0x69f 0x69f 0x6ad 0x6bf 0x6ad 0x6b0 0x6ac 0x6ad 0x6a8 0x6ab 0x6ab 0x6a6 0x6bf 0x6bb 0x6bd 0x6bc 0x6c1 0x6c2 0x6c7 0x6c7 0x6d7 0x691 0x67f 0x682 0x67f 0x67f 0x67a 0x67e 0x67a 0x678 0x68d 0x688 0x68c 0x68a 0x68e 0x68f 0x694 0x694 0x6a4 0x6b2 0x69f 0x6a2 0x69e 0x69f 0x69b 0x69e 0x69b 0x698 0x6b5 0x6b0 0x6b4 0x6b1 0x6b6 0x6b7 0x6bc 0x6bd 0x6cc 0x685 0x672 0x675 0x672 0x673 0x66e 0x672 0x66e 0x66d 0x686 0x680 0x684 0x681 0x686 0x688 0x68b 0x68c 0x69b 0x6a7 0x695 0x698 0x694 0x696 0x691 0x695 0x691 0x691 0x6aa 0x6a4 0x6a8 0x6a6 0x6aa 0x6ab 0x6b0 0x6b0 0x6c0 0x67a 0x667 0x66a 0x667 0x667 0x663 0x669 0x663 0x663 0x678 0x672 0x677 0x674 0x678 0x67a 0x67d 0x67e 0x68e 0x69b 0x689 0x68b 0x688 0x689 0x685 0x689 0x685 0x684 0x69f 0x699 0x69e 0x69b 0x69f 0x6a1 0x6a4 0x6a5 0x6b5 0x66c 0x65a 0x65c 0x659 0x65a 0x656 0x65b 0x657 0x656 0x66b 0x665 0x66b 0x667 0x66c 0x66c 0x670 0x671 0x681 0x624 0x613 0x616 0x613 0x613 0x60f 0x613 0x60f 0x611 0x629 0x621 0x626 0x623 0x627 0x628 0x62b 0x62d 0x63c 0x5fa 0x5e9 0x5eb 0x5e8 0x5e9 0x5e5 0x5e9 0x5e5 0x5e7 0x5f6 0x5f0 0x5f5 0x5f2 0x5f5 0x5f7 0x5fa 0x5fc 0x60b 0x61a 0x607 0x60a 0x606 0x607 0x603 0x608 0x605 0x605 0x619 0x616 0x61a 0x616 0x61a 0x61b 0x61e 0x620 0x631 0x5ed 0x5da 0x5dd 0x5d9 0x5da 0x5d7 0x5db 0x5d9 0x5d9 0x5e1 0x5e0 0x5e5 0x5e2 0x5e5 0x5e6 0x5ea 0x5eb 0x5fc 0x60a 0x5fa 0x5fc 0x5f9 0x5f9 0x5f5 0x5fb 0x5f6 0x5f7 0x602 0x601 0x606 0x602 0x605 0x607 0x60a 0x60c 0x61b 0x5db 0x5ca 0x5cc 0x5c9 0x5c9 0x5c6 0x5cb 0x5c6 0x5c8 0x5d1 0x5d0 0x5d6 0x5d2 0x5d4 0x5d6 0x5da 0x5db 0x5e9 0x5f9 0x5e7 0x5e9 0x5e6 0x5e6 0x5e3 0x5e8 0x5e2 0x5e5 0x5f2 0x5f0 0x5f7 0x5f3 0x5f5 0x5f7 0x5fb 0x5fc 0x60a 0x5cb 0x5b8 0x5bb 0x5b8 0x5b8 0x5b4 0x5ba 0x5b4 0x5b6 0x5c0 0x5bf 0x5c6 0x5c1 0x5c4 0x5c6 0x5c9 0x5ca 0x5d8 0x5e7 0x5d6 0x5d7 0x5d4 0x5d4 0x5d1 0x5d8 0x5d1 0x5d4 0x5df 0x5de 0x5e5 0x5e0 0x5e4 0x5e5 0x5e8 0x5e9 0x5f7 0x4f4 0x5a4 0x5a6 0x5a3 0x5a3 0x5a1 0x5a8 0x5a1 0x5a3 0x5ac 0x5aa 0x5b3 0x5ac 0x5af 0x5b1 0x5b4 0x5b4 0x4ff 0x4e7 0x5bf 0x5c2 0x5bf 0x5bf 0x5bc 0x5c4 0x5bb 0x5be 0x5cd 0x5cb 0x5d4 0x5cc 0x5d0 0x5d1 0x5d4 0x5d6 0x4f8 0x48b 0x564 0x59c 0x59f 0x59f 0x598 0x5a1 0x598 0x59b 0x5a6 0x5a4 0x5ad 0x5a6 0x5ad 0x5ae 0x5ac 0x575 0x499 0x1964 0x1964 0x1964>; | |
| PS_Config_Lmt_FW_Rawdata_P = <0xffff 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0xffff 0xffff 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0xffff 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x6d6 0x7d0 0x7d0 0x7d0>; | |
| PS_Config_Lmt_FW_Rawdata_N = <0xffff0001 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0xffff0001 0xffff0001 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0xffff0001 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x28a 0x190 0x190 0x190>; | |
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| PS_Config_Lmt_FW_CC_Q_N = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| PS_Config_Lmt_FW_Diff_P = <0xffff 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0xffff 0xffff 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0xffff 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32 0x32>; | |
| PS_Config_Lmt_FW_Diff_N = <0xffff0001 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffff0001 0xffff0001 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffff0001 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce 0xffffffce>; | |
| PS_Config_Diff_Test_Frame = <0x32>; | |
| }; | |
| }; | |
| synaptics_tcm@20 { | |
| compatible = "synaptics,tcm-i2c"; | |
| reg = <0x20>; | |
| interrupt-parent = <0xe7>; | |
| interrupts = <0x43 0x2008>; | |
| vdd-supply = <0x17e>; | |
| pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; | |
| pinctrl-0 = <0x17f>; | |
| pinctrl-1 = <0x180>; | |
| synaptics,bus-reg-name = "vdd"; | |
| synaptics,irq-gpio = <0xe7 0x43 0x2008>; | |
| synaptics,irq-on-state = <0x0>; | |
| synaptics,reset-gpio = <0xe7 0x42 0x0>; | |
| synaptics,reset-on-state = <0x0>; | |
| synaptics,reset-active-ms = <0x14>; | |
| synaptics,reset-delay-ms = <0xc8>; | |
| synaptics,power-delay-ms = <0xc8>; | |
| synaptics,ubl-i2c-addr = <0x20>; | |
| }; | |
| }; | |
| i2c@c176000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc176000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x60 0x0>; | |
| dmas = <0x17a 0x6 0x40 0x20000020 0x20 0x17a 0x7 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x56>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x26>; | |
| qcom,i2c-dat = <0xe7 0x6 0x0>; | |
| qcom,i2c-clk = <0xe7 0x7 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x182>; | |
| pinctrl-1 = <0x183>; | |
| pinctrl-2 = <0x184>; | |
| status = "disabled"; | |
| linux,phandle = <0x376>; | |
| phandle = <0x376>; | |
| }; | |
| i2c@c177000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc177000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x61 0x0>; | |
| dmas = <0x17a 0x8 0x40 0x20000020 0x20 0x17a 0x9 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x56>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x28>; | |
| qcom,i2c-dat = <0xe7 0xa 0x0>; | |
| qcom,i2c-clk = <0xe7 0xb 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x185>; | |
| pinctrl-1 = <0x186>; | |
| pinctrl-2 = <0x187>; | |
| status = "disabled"; | |
| linux,phandle = <0x377>; | |
| phandle = <0x377>; | |
| }; | |
| i2c@c178000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc178000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x62 0x0>; | |
| dmas = <0x17a 0xa 0x40 0x20000020 0x20 0x17a 0xb 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x56>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x2a>; | |
| qcom,i2c-dat = <0xe7 0xe 0x0>; | |
| qcom,i2c-clk = <0xe7 0xf 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x188>; | |
| pinctrl-1 = <0x189>; | |
| pinctrl-2 = <0x18a>; | |
| status = "disabled"; | |
| linux,phandle = <0x378>; | |
| phandle = <0x378>; | |
| }; | |
| i2c@c1b5000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc1b5000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x65 0x0>; | |
| dmas = <0x18b 0x4 0x40 0x20000020 0x20 0x18b 0x5 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x54>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x2f>; | |
| qcom,i2c-dat = <0xe7 0x12 0x0>; | |
| qcom,i2c-clk = <0xe7 0x13 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x18c>; | |
| pinctrl-1 = <0x18d>; | |
| pinctrl-2 = <0x18e>; | |
| status = "disabled"; | |
| linux,phandle = <0x379>; | |
| phandle = <0x379>; | |
| }; | |
| i2c@c1b6000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc1b6000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x66 0x0>; | |
| dmas = <0x18b 0x6 0x40 0x20000020 0x20 0x18b 0x7 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x54>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x31>; | |
| qcom,i2c-dat = <0xe7 0x16 0x0>; | |
| qcom,i2c-clk = <0xe7 0x17 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x18f>; | |
| pinctrl-1 = <0x190>; | |
| pinctrl-2 = <0x191>; | |
| status = "okay"; | |
| linux,phandle = <0x37a>; | |
| phandle = <0x37a>; | |
| nq@28 { | |
| compatible = "qcom,nq-nci"; | |
| reg = <0x28>; | |
| qcom,nq-irq = <0xe7 0x1c 0x0>; | |
| qcom,nq-ven = <0xe7 0x1d 0x0>; | |
| qcom,nq-firm = <0xe7 0x1e 0x0>; | |
| qcom,nq-clkreq = <0x192 0x4 0x0>; | |
| qcom,nq-esepwr = <0xe7 0x1f 0x0>; | |
| interrupt-parent = <0xe7>; | |
| qcom,clk-src = "BBCLK3"; | |
| interrupts = <0x1c 0x0>; | |
| interrupt-names = "nfc_irq"; | |
| pinctrl-names = "nfc_active", "nfc_suspend"; | |
| pinctrl-0 = <0x193 0x194>; | |
| pinctrl-1 = <0x195 0x196>; | |
| clocks = <0x26 0x38>; | |
| clock-names = "ref_clk"; | |
| }; | |
| tas2557@4c { | |
| compatible = "ti,tas2557"; | |
| reg = <0x4c>; | |
| #ti,load = <0x0>; | |
| #ti,channel = <0x0>; | |
| i2c-pull-up; | |
| vdd-supply = <0x197>; | |
| vcc_i2c-supply = <0x197>; | |
| ti,cdc-reset-gpio = <0xe7 0x4d 0x0>; | |
| ti,irq-gpio = <0xe7 0x49 0x0>; | |
| ti,i2s-bits = <0x10>; | |
| status = "ok"; | |
| }; | |
| max98927@3a { | |
| compatible = "maxim,max98927L"; | |
| status = "okay"; | |
| reg = <0x3a>; | |
| mono_stereo_mode = <0x0>; | |
| interleave_mode = <0x0>; | |
| maxim,98927-reset-gpio = <0xe7 0x4d 0x0>; | |
| }; | |
| tfa98xx@34 { | |
| compatible = "nxp,tfa98xx"; | |
| reg = <0x34>; | |
| i2c-pull-up; | |
| vdd-supply = <0x197>; | |
| vcc_i2c-supply = <0x197>; | |
| reset-gpio = <0xe7 0x4d 0x0>; | |
| irq-gpio = <0xe7 0x49 0x0>; | |
| status = "ok"; | |
| }; | |
| }; | |
| i2c@c1b7000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc1b7000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x67 0x0>; | |
| dmas = <0x18b 0x8 0x40 0x20000020 0x20 0x18b 0x9 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x54>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x33>; | |
| qcom,i2c-dat = <0xe7 0x1a 0x0>; | |
| qcom,i2c-clk = <0xe7 0x1b 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x198>; | |
| pinctrl-1 = <0x199>; | |
| pinctrl-2 = <0x19a>; | |
| status = "disabled"; | |
| linux,phandle = <0x37b>; | |
| phandle = <0x37b>; | |
| }; | |
| i2c@c1b8000 { | |
| compatible = "qcom,i2c-msm-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg = <0xc1b8000 0x600>; | |
| reg-names = "qup_phys_addr"; | |
| interrupt-names = "qup_irq"; | |
| interrupts = <0x0 0x68 0x0>; | |
| dmas = <0x18b 0xa 0x40 0x20000020 0x20 0x18b 0xb 0x20 0x20000020 0x20>; | |
| dma-names = "tx", "rx"; | |
| qcom,master-id = <0x54>; | |
| qcom,clk-freq-out = <0x61a80>; | |
| qcom,clk-freq-in = <0x124f800>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x35>; | |
| qcom,i2c-dat = <0xe7 0x1e 0x0>; | |
| qcom,i2c-clk = <0xe7 0x1f 0x0>; | |
| pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang"; | |
| pinctrl-0 = <0x19b>; | |
| pinctrl-1 = <0x19c>; | |
| pinctrl-2 = <0x19d>; | |
| status = "disabled"; | |
| linux,phandle = <0x37c>; | |
| phandle = <0x37c>; | |
| }; | |
| spi@c175000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc175000 0x600 0xc144000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x5f 0x0 0x0 0xee 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0x4>; | |
| qcom,bam-producer-pipe-index = <0x5>; | |
| qcom,master-id = <0x56>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x19e>; | |
| pinctrl-1 = <0x19f>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x25>; | |
| status = "disabled"; | |
| linux,phandle = <0x37d>; | |
| phandle = <0x37d>; | |
| }; | |
| spi@c176000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc176000 0x600 0xc144000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x60 0x0 0x0 0xee 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0x6>; | |
| qcom,bam-producer-pipe-index = <0x7>; | |
| qcom,master-id = <0x56>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1a0>; | |
| pinctrl-1 = <0x1a1>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x27>; | |
| status = "disabled"; | |
| linux,phandle = <0x37e>; | |
| phandle = <0x37e>; | |
| }; | |
| spi@c177000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc177000 0x600 0xc144000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x61 0x0 0x0 0xee 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0x8>; | |
| qcom,bam-producer-pipe-index = <0x9>; | |
| qcom,master-id = <0x56>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1a2>; | |
| pinctrl-1 = <0x1a3>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x29>; | |
| status = "disabled"; | |
| linux,phandle = <0x37f>; | |
| phandle = <0x37f>; | |
| }; | |
| spi@c178000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc178000 0x600 0xc144000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x62 0x0 0x0 0xee 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0xa>; | |
| qcom,bam-producer-pipe-index = <0xb>; | |
| qcom,master-id = <0x56>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1a4>; | |
| pinctrl-1 = <0x1a5>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x23 0xa1 0x2b>; | |
| status = "disabled"; | |
| linux,phandle = <0x380>; | |
| phandle = <0x380>; | |
| }; | |
| spi@c1b5000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc1b5000 0x600 0xc184000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x65 0x0 0x0 0xef 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0x4>; | |
| qcom,bam-producer-pipe-index = <0x5>; | |
| qcom,master-id = <0x54>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1a6>; | |
| pinctrl-1 = <0x1a7>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x30>; | |
| status = "disabled"; | |
| linux,phandle = <0x381>; | |
| phandle = <0x381>; | |
| }; | |
| spi@c1b6000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc1b6000 0x600 0xc184000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x66 0x0 0x0 0xef 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0x6>; | |
| qcom,bam-producer-pipe-index = <0x7>; | |
| qcom,master-id = <0x54>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1a8>; | |
| pinctrl-1 = <0x1a9>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x32>; | |
| status = "disabled"; | |
| linux,phandle = <0x382>; | |
| phandle = <0x382>; | |
| }; | |
| spi@c1b7000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc1b7000 0x600 0xc184000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x67 0x0 0x0 0xef 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0x8>; | |
| qcom,bam-producer-pipe-index = <0x9>; | |
| qcom,master-id = <0x54>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1aa>; | |
| pinctrl-1 = <0x1ab>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x34>; | |
| status = "okay"; | |
| linux,phandle = <0x383>; | |
| phandle = <0x383>; | |
| device@1 { | |
| compatible = "qcom,spi-msm-codec-slave"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| reg = <0x1>; | |
| spi-max-frequency = <0xf4240>; | |
| spi-cpol; | |
| }; | |
| }; | |
| spi@c1b8000 { | |
| compatible = "qcom,spi-qup-v2"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "spi_physical", "spi_bam_physical"; | |
| reg = <0xc1b8000 0x600 0xc184000 0x1f000>; | |
| interrupt-names = "spi_irq", "spi_bam_irq"; | |
| interrupts = <0x0 0x68 0x0 0x0 0xef 0x0>; | |
| spi-max-frequency = <0x2faf080>; | |
| qcom,use-bam; | |
| qcom,ver-reg-exists; | |
| qcom,bam-consumer-pipe-index = <0xa>; | |
| qcom,bam-producer-pipe-index = <0xb>; | |
| qcom,master-id = <0x54>; | |
| qcom,use-pinctrl; | |
| pinctrl-names = "spi_default", "spi_sleep"; | |
| pinctrl-0 = <0x1ac>; | |
| pinctrl-1 = <0x1ad>; | |
| clock-names = "iface_clk", "core_clk"; | |
| clocks = <0xa1 0x2e 0xa1 0x36>; | |
| status = "disabled"; | |
| linux,phandle = <0x384>; | |
| phandle = <0x384>; | |
| }; | |
| uart@c16f000 { | |
| compatible = "qcom,msm-hsuart-v14"; | |
| reg = <0xc16f000 0x200 0xc144000 0x1f000>; | |
| reg-names = "core_mem", "bam_mem"; | |
| interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
| #address-cells = <0x0>; | |
| interrupt-parent = <0x1ae>; | |
| interrupts = <0x0 0x1 0x2>; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0xffffffff>; | |
| interrupt-map = <0x0 0x1 0x0 0x0 0x6b 0x0 0x1 0x1 0x0 0x0 0xee 0x0 0x2 0xe7 0x1 0x0>; | |
| qcom,inject-rx-on-wakeup; | |
| qcom,rx-char-to-inject = <0xfd>; | |
| qcom,bam-tx-ep-pipe-index = <0x0>; | |
| qcom,bam-rx-ep-pipe-index = <0x1>; | |
| qcom,master-id = <0x56>; | |
| clock-names = "core_clk", "iface_clk"; | |
| clocks = <0xa1 0x2c 0xa1 0x23>; | |
| pinctrl-names = "sleep", "default"; | |
| pinctrl-0 = <0x1af>; | |
| pinctrl-1 = <0x1b0>; | |
| qcom,msm-bus,name = "buart1"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
| status = "disabled"; | |
| linux,phandle = <0x1ae>; | |
| phandle = <0x1ae>; | |
| }; | |
| uart@c170000 { | |
| compatible = "qcom,msm-hsuart-v14"; | |
| reg = <0xc170000 0x200 0xc144000 0x1f000>; | |
| reg-names = "core_mem", "bam_mem"; | |
| interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
| #address-cells = <0x0>; | |
| interrupt-parent = <0x1b1>; | |
| interrupts = <0x0 0x1 0x2>; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0xffffffff>; | |
| interrupt-map = <0x0 0x1 0x0 0x0 0x6c 0x0 0x1 0x1 0x0 0x0 0xee 0x0 0x2 0xe7 0x5 0x0>; | |
| qcom,inject-rx-on-wakeup; | |
| qcom,rx-char-to-inject = <0xfd>; | |
| qcom,bam-tx-ep-pipe-index = <0x2>; | |
| qcom,bam-rx-ep-pipe-index = <0x3>; | |
| qcom,master-id = <0x56>; | |
| clock-names = "core_clk", "iface_clk"; | |
| clocks = <0xa1 0x2d 0xa1 0x23>; | |
| pinctrl-names = "sleep", "default"; | |
| pinctrl-0 = <0x1b2>; | |
| pinctrl-1 = <0x1b3>; | |
| qcom,msm-bus,name = "buart2"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x56 0x200 0x0 0x0 0x56 0x200 0x1f4 0x320>; | |
| status = "disabled"; | |
| linux,phandle = <0x1b1>; | |
| phandle = <0x1b1>; | |
| }; | |
| uart@c1af000 { | |
| compatible = "qcom,msm-hsuart-v14"; | |
| reg = <0xc1af000 0x200 0xc184000 0x1f000>; | |
| reg-names = "core_mem", "bam_mem"; | |
| interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
| #address-cells = <0x0>; | |
| interrupt-parent = <0x1b4>; | |
| interrupts = <0x0 0x1 0x2>; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0xffffffff>; | |
| interrupt-map = <0x0 0x1 0x0 0x0 0x71 0x0 0x1 0x1 0x0 0x0 0xef 0x0 0x2 0xe7 0x11 0x0>; | |
| qcom,inject-rx-on-wakeup; | |
| qcom,rx-char-to-inject = <0xfd>; | |
| qcom,bam-tx-ep-pipe-index = <0x0>; | |
| qcom,bam-rx-ep-pipe-index = <0x1>; | |
| qcom,master-id = <0x54>; | |
| clock-names = "core_clk", "iface_clk"; | |
| clocks = <0xa1 0x37 0xa1 0x2e>; | |
| pinctrl-names = "sleep", "default"; | |
| pinctrl-0 = <0x1b5 0x1b6 0x1b7>; | |
| pinctrl-1 = <0x1b8 0x1b9 0x1ba>; | |
| qcom,msm-bus,name = "buart3"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x54 0x200 0x0 0x0 0x54 0x200 0x1f4 0x320>; | |
| status = "ok"; | |
| linux,phandle = <0x1b4>; | |
| phandle = <0x1b4>; | |
| }; | |
| uart@c1b0000 { | |
| compatible = "qcom,msm-hsuart-v14"; | |
| reg = <0xc1b0000 0x200 0xc184000 0x1f000>; | |
| reg-names = "core_mem", "bam_mem"; | |
| interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; | |
| #address-cells = <0x0>; | |
| interrupt-parent = <0x1bb>; | |
| interrupts = <0x0 0x1 0x2>; | |
| #interrupt-cells = <0x1>; | |
| interrupt-map-mask = <0xffffffff>; | |
| interrupt-map = <0x0 0x1 0x0 0x0 0x72 0x0 0x1 0x1 0x0 0x0 0xef 0x0 0x2 0xe7 0x19 0x0>; | |
| qcom,inject-rx-on-wakeup; | |
| qcom,rx-char-to-inject = <0xfd>; | |
| qcom,bam-tx-ep-pipe-index = <0x2>; | |
| qcom,bam-rx-ep-pipe-index = <0x3>; | |
| qcom,master-id = <0x54>; | |
| clock-names = "core_clk", "iface_clk"; | |
| clocks = <0xa1 0x38 0xa1 0x2e>; | |
| pinctrl-names = "sleep", "default"; | |
| pinctrl-0 = <0x1bc>; | |
| pinctrl-1 = <0x1bd>; | |
| qcom,msm-bus,name = "buart4"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x54 0x200 0x0 0x0 0x54 0x200 0x1f4 0x320>; | |
| status = "disabled"; | |
| linux,phandle = <0x1bb>; | |
| phandle = <0x1bb>; | |
| }; | |
| qcom,smp2pgpio-rdbg-2-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "rdbg"; | |
| qcom,remote-pid = <0x2>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1be>; | |
| phandle = <0x1be>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_2_in { | |
| compatible = "qcom,smp2pgpio_client_rdbg_2_in"; | |
| gpios = <0x1be 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-rdbg-2-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "rdbg"; | |
| qcom,remote-pid = <0x2>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1bf>; | |
| phandle = <0x1bf>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_2_out { | |
| compatible = "qcom,smp2pgpio_client_rdbg_2_out"; | |
| gpios = <0x1bf 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-rdbg-1-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "rdbg"; | |
| qcom,remote-pid = <0x1>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1c0>; | |
| phandle = <0x1c0>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_1_in { | |
| compatible = "qcom,smp2pgpio_client_rdbg_1_in"; | |
| gpios = <0x1c0 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-rdbg-1-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "rdbg"; | |
| qcom,remote-pid = <0x1>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1c1>; | |
| phandle = <0x1c1>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_1_out { | |
| compatible = "qcom,smp2pgpio_client_rdbg_1_out"; | |
| gpios = <0x1c1 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-rdbg-5-in { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "rdbg"; | |
| qcom,remote-pid = <0x5>; | |
| qcom,is-inbound; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1c2>; | |
| phandle = <0x1c2>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_5_in { | |
| compatible = "qcom,smp2pgpio_client_rdbg_5_in"; | |
| gpios = <0x1c2 0x0 0x0>; | |
| }; | |
| qcom,smp2pgpio-rdbg-5-out { | |
| compatible = "qcom,smp2pgpio"; | |
| qcom,entry-name = "rdbg"; | |
| qcom,remote-pid = <0x5>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x2>; | |
| linux,phandle = <0x1c3>; | |
| phandle = <0x1c3>; | |
| }; | |
| qcom,smp2pgpio_client_rdbg_5_out { | |
| compatible = "qcom,smp2pgpio_client_rdbg_5_out"; | |
| gpios = <0x1c3 0x0 0x0>; | |
| }; | |
| qcom,msm-cam@ca00000 { | |
| compatible = "qcom,msm-cam"; | |
| reg = <0xca00000 0x4000>; | |
| reg-names = "msm-cam"; | |
| status = "ok"; | |
| bus-vectors = "suspend", "svs", "nominal", "turbo"; | |
| qcom,bus-votes = <0x0 0x8f0d180 0x1312d000 0x1312d000>; | |
| qcom,gpu-limit = <0x29b92700>; | |
| }; | |
| qcom,csiphy@c824000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; | |
| reg = <0xc824000 0x1000 0xca00120 0x4>; | |
| reg-names = "csiphy", "csiphy_clk_mux"; | |
| interrupts = <0x0 0x4e 0x0>; | |
| interrupt-names = "csiphy"; | |
| gdscr-supply = <0x164>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "gdscr", "bimc_smmu"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0xc 0x74 0x65 0x74 0x5c 0x74 0xd 0x74 0x66 0x74 0x7e 0x74 0x13 0x74 0x79 0x74 0x90>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", "csiphy_ahb2crif"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0x0 0x0 0x100db355 0x0 0x0 0x10089d40 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,csiphy@c825000 { | |
| cell-index = <0x1>; | |
| compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; | |
| reg = <0xc825000 0x1000 0xca00124 0x4>; | |
| reg-names = "csiphy", "csiphy_clk_mux"; | |
| interrupts = <0x0 0x4f 0x0>; | |
| interrupt-names = "csiphy"; | |
| gdscr-supply = <0x164>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "gdscr", "bimc_smmu"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0xe 0x74 0x6a 0x74 0x5d 0x74 0xf 0x74 0x6b 0x74 0x7e 0x74 0x13 0x74 0x7a 0x74 0x90>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", "csiphy_ahb2crif"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0x0 0x0 0x100db355 0x0 0x0 0xbebc200 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,csiphy@c826000 { | |
| cell-index = <0x2>; | |
| compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; | |
| reg = <0xc826000 0x1000 0xca00128 0x4>; | |
| reg-names = "csiphy", "csiphy_clk_mux"; | |
| interrupts = <0x0 0x50 0x0>; | |
| interrupt-names = "csiphy"; | |
| gdscr-supply = <0x164>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "gdscr", "bimc_smmu"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x10 0x74 0x6f 0x74 0x5e 0x74 0x11 0x74 0x70 0x74 0x7e 0x74 0x13 0x74 0x7b 0x74 0x90>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", "csiphy_ahb2crif"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0x0 0x0 0x100db355 0x0 0x0 0x10089d40 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,csid@ca30000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,csid-v5.0", "qcom,csid"; | |
| reg = <0xca30000 0x400>; | |
| reg-names = "csid"; | |
| interrupts = <0x0 0x128 0x0>; | |
| interrupt-names = "csid"; | |
| qcom,csi-vdd-voltage = <0x124f80>; | |
| qcom,mipi-csi-vdd-supply = <0x109>; | |
| gdscr-supply = <0x164>; | |
| vdd_sec-supply = <0x105>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
| qcom,cam-vreg-min-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x0 0x0 0x0>; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x7e 0x74 0xc 0x74 0x13 0x74 0x65 0x74 0x64 0x74 0x68 0x74 0x67 0x74 0x5c>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0xbebc200 0x0 0x0 0x0 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,csid@ca30400 { | |
| cell-index = <0x1>; | |
| compatible = "qcom,csid-v5.0", "qcom,csid"; | |
| reg = <0xca30400 0x400>; | |
| reg-names = "csid"; | |
| interrupts = <0x0 0x129 0x0>; | |
| interrupt-names = "csid"; | |
| qcom,csi-vdd-voltage = <0x124f80>; | |
| qcom,mipi-csi-vdd-supply = <0x109>; | |
| gdscr-supply = <0x164>; | |
| vdd_sec-supply = <0x105>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
| qcom,cam-vreg-min-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x0 0x0 0x0>; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x7e 0x74 0xe 0x74 0x13 0x74 0x6a 0x74 0x69 0x74 0x6d 0x74 0x6c 0x74 0x5d>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0xbebc200 0x0 0x0 0x0 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,csid@ca30800 { | |
| cell-index = <0x2>; | |
| compatible = "qcom,csid-v5.0", "qcom,csid"; | |
| reg = <0xca30800 0x400>; | |
| reg-names = "csid"; | |
| interrupts = <0x0 0x12a 0x0>; | |
| interrupt-names = "csid"; | |
| qcom,csi-vdd-voltage = <0x124f80>; | |
| qcom,mipi-csi-vdd-supply = <0x109>; | |
| gdscr-supply = <0x164>; | |
| vdd_sec-supply = <0x105>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
| qcom,cam-vreg-min-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x0 0x0 0x0>; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x7e 0x74 0x10 0x74 0x13 0x74 0x6f 0x74 0x6e 0x74 0x72 0x74 0x71 0x74 0x5e>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0xbebc200 0x0 0x0 0x0 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,csid@ca30c00 { | |
| cell-index = <0x3>; | |
| compatible = "qcom,csid-v5.0", "qcom,csid"; | |
| reg = <0xca30c00 0x400>; | |
| reg-names = "csid"; | |
| interrupts = <0x0 0x12b 0x0>; | |
| interrupt-names = "csid"; | |
| qcom,csi-vdd-voltage = <0x124f80>; | |
| qcom,mipi-csi-vdd-supply = <0x109>; | |
| gdscr-supply = <0x164>; | |
| vdd_sec-supply = <0x105>; | |
| bimc_smmu-supply = <0x163>; | |
| qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; | |
| qcom,cam-vreg-min-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0xe1d48 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x0 0x0 0x0>; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x7e 0x74 0x12 0x74 0x13 0x74 0x74 0x74 0x73 0x74 0x76 0x74 0x75 0x74 0x5f>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x127a3980 0xbebc200 0x0 0x0 0x0 0x0 0x0>; | |
| status = "ok"; | |
| }; | |
| qcom,cam_smmu { | |
| compatible = "qcom,msm-cam-smmu"; | |
| status = "ok"; | |
| msm_cam_smmu_cb1 { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| iommus = <0x173 0xc00 0x173 0xc01 0x173 0xc02 0x173 0xc03>; | |
| label = "vfe"; | |
| qcom,scratch-buf-support; | |
| }; | |
| msm_cam_smmu_cb2 { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| iommus = <0x173 0xa00>; | |
| label = "cpp"; | |
| }; | |
| msm_cam_smmu_cb4 { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| iommus = <0x173 0x800>; | |
| label = "jpeg_enc0"; | |
| }; | |
| msm_cam_smmu_cb5 { | |
| compatible = "qcom,msm-cam-smmu-cb"; | |
| iommus = <0x173 0x801>; | |
| label = "jpeg_dma"; | |
| }; | |
| }; | |
| qcom,cpp@ca04000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,cpp"; | |
| reg = <0xca04000 0x100 0xca80000 0x3000 0xca18000 0x3000 0xc8c36d4 0x4>; | |
| reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; | |
| interrupts = <0x0 0x126 0x0>; | |
| interrupt-names = "cpp"; | |
| smmu-vdd-supply = <0x163>; | |
| camss-vdd-supply = <0x164>; | |
| vdd-supply = <0x1c4>; | |
| qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x59 0x74 0x87 0x74 0xb 0x74 0x62 0x74 0x60 0x74 0x61 0x74 0x86 0x74 0x58 0x74 0x63>; | |
| clock-names = "mmssnoc_axi_clk", "mnoc_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk", "cpp_src_clk", "cpp_core_clk", "camss_cpp_ahb_clk", "camss_cpp_axi_clk", "micro_iface_clk", "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0xbebc200 0xbebc200 0x0 0x0 0x0 0x0 0x0>; | |
| qcom,min-clock-rate = <0xbebc200>; | |
| qcom,bus-master = <0x1>; | |
| qcom,vbif-qos-setting = <0x550 0x55555555 0x554 0x55555555 0x558 0x55555555 0x55c 0x55555555 0x560 0x55555555 0x564 0x55555555 0x568 0x55555555 0x56c 0x55555555 0x570 0x55555555 0x574 0x55555555 0x578 0x55555555 0x57c 0x55555555 0x580 0x55555555 0x584 0x55555555 0x588 0x55555555 0x58c 0x55555555>; | |
| status = "ok"; | |
| qcom,msm-bus,name = "msm_camera_cpp"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x6a 0x200 0x0 0x0 0x6a 0x200 0x0 0x0>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,cpp-cx-ipeak = <0x16d 0x2>; | |
| resets = <0x74 0x0>; | |
| reset-names = "micro_iface_reset"; | |
| qcom,src-clock-rates = <0x7270e00 0xf424000 0x16e36000 0x1c9c3800 0x202fbf00 0x22551000>; | |
| qcom,micro-reset; | |
| qcom,cpp-fw-payload-info { | |
| qcom,stripe-base = <0x316>; | |
| qcom,plane-base = <0x2cb>; | |
| qcom,stripe-size = <0x3f>; | |
| qcom,plane-size = <0x19>; | |
| qcom,fe-ptr-off = <0xb>; | |
| qcom,we-ptr-off = <0x17>; | |
| qcom,ref-fe-ptr-off = <0x11>; | |
| qcom,ref-we-ptr-off = <0x24>; | |
| qcom,we-meta-ptr-off = <0x2a>; | |
| qcom,fe-mmu-pf-ptr-off = <0x7>; | |
| qcom,ref-fe-mmu-pf-ptr-off = <0xa>; | |
| qcom,we-mmu-pf-ptr-off = <0xd>; | |
| qcom,dup-we-mmu-pf-ptr-off = <0x12>; | |
| qcom,ref-we-mmu-pf-ptr-off = <0x17>; | |
| qcom,set-group-buffer-len = <0x87>; | |
| qcom,dup-frame-indicator-off = <0x46>; | |
| }; | |
| }; | |
| qcom,ispif@ca31000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,ispif-v3.0", "qcom,ispif"; | |
| reg = <0xca31000 0xc00 0xca00020 0x4>; | |
| reg-names = "ispif", "csi_clk_mux"; | |
| interrupts = <0x0 0x135 0x0>; | |
| interrupt-names = "ispif"; | |
| qcom,num-isps = <0x2>; | |
| camss-vdd-supply = <0x164>; | |
| vfe0-vdd-supply = <0x1c5>; | |
| vfe1-vdd-supply = <0x1c6>; | |
| qcom,vdd-names = "camss-vdd", "vfe0-vdd", "vfe1-vdd"; | |
| qcom,clock-cntl-support; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x59 0x74 0x87 0x74 0x7e 0x74 0xc 0x74 0xe 0x74 0x10 0x74 0x12 0x74 0x68 0x74 0x6d 0x74 0x72 0x74 0x76 0x74 0x67 0x74 0x6c 0x74 0x71 0x74 0x75 0x74 0x65 0x74 0x6a 0x74 0x6f 0x74 0x74 0x74 0xbb 0x74 0x89 0x74 0x77 0x74 0xbc 0x74 0x8c 0x74 0x78>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb_clk", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi0_src_clk", "csi1_src_clk", "csi2_src_clk", "csi3_src_clk", "csi0_rdi_clk", "csi1_rdi_clk", "csi2_rdi_clk", "csi3_rdi_clk", "csi0_pix_clk", "csi1_pix_clk", "csi2_pix_clk", "csi3_pix_clk", "camss_csi0_clk", "camss_csi1_clk", "camss_csi2_clk", "camss_csi3_clk", "vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk", "vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| qcom,clock-control = "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "INIT_RATE", "INIT_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE", "NO_SET_RATE"; | |
| status = "ok"; | |
| }; | |
| qcom,vfe0@ca10000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,vfe48"; | |
| reg = <0xca10000 0x4000 0xca40000 0x3000>; | |
| reg-names = "vfe", "vfe_vbif"; | |
| interrupts = <0x0 0x13a 0x0>; | |
| interrupt-names = "vfe"; | |
| vdd-supply = <0x1c5>; | |
| camss-vdd-supply = <0x164>; | |
| smmu-vdd-supply = <0x163>; | |
| qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; | |
| clocks = <0x74 0xac 0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0xbb 0x74 0x89 0x74 0x8a 0x74 0x88 0x74 0x8e 0x74 0x8f 0x74 0x77>; | |
| clock-names = "mmss_throttle_camss_axi_clk", "mmssnoc_axi", "mnoc_ahb_clk", "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", "camss_vfe_vbif_axi_clk", "camss_csi_vfe_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x18148d00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x22551000 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| status = "ok"; | |
| qos-entries = <0x8>; | |
| qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420>; | |
| qos-settings = <0xaaa5aaa5 0xaaa5aaa5 0xaaa5aaa5 0xaa55aaa5 0xaa55aa55 0xaa55aa55 0xaa55aa55 0x5aa55>; | |
| vbif-entries = <0x3>; | |
| vbif-regs = <0x124 0xac 0xd0>; | |
| vbif-settings = <0x3 0x40 0x1010>; | |
| ds-entries = <0x11>; | |
| ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464>; | |
| ds-settings = <0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0x110>; | |
| qcom,msm-bus,name = "msm_camera_vfe"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x5f5e100 0x5f5e100>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,vfe-cx-ipeak = <0x16d 0x2>; | |
| linux,phandle = <0x385>; | |
| phandle = <0x385>; | |
| }; | |
| qcom,vfe1@ca14000 { | |
| cell-index = <0x1>; | |
| compatible = "qcom,vfe48"; | |
| reg = <0xca14000 0x4000 0xca40000 0x3000>; | |
| reg-names = "vfe", "vfe_vbif"; | |
| interrupts = <0x0 0x13b 0x0>; | |
| interrupt-names = "vfe"; | |
| vdd-supply = <0x1c6>; | |
| camss-vdd-supply = <0x164>; | |
| smmu-vdd-supply = <0x163>; | |
| qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; | |
| clocks = <0x74 0xac 0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0xbc 0x74 0x8c 0x74 0x8d 0x74 0x8b 0x74 0x8e 0x74 0x8f 0x74 0x78>; | |
| clock-names = "mmss_throttle_camss_axi_clk", "mmssnoc_axi", "mnoc_ahb_clk", "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", "camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src", "camss_vfe_clk", "camss_vfe_stream_clk", "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", "camss_vfe_vbif_axi_clk", "camss_csi_vfe_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x18148d00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x22551000 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| status = "ok"; | |
| qos-entries = <0x8>; | |
| qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420>; | |
| qos-settings = <0xaaa5aaa5 0xaaa5aaa5 0xaaa5aaa5 0xaa55aaa5 0xaa55aa55 0xaa55aa55 0xaa55aa55 0x5aa55>; | |
| vbif-entries = <0x3>; | |
| vbif-regs = <0x124 0xac 0xd0>; | |
| vbif-settings = <0x3 0x40 0x1010>; | |
| ds-entries = <0x11>; | |
| ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c 0x450 0x454 0x458 0x45c 0x460 0x464>; | |
| ds-settings = <0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0xcccc1111 0x110>; | |
| qcom,msm-bus,name = "msm_camera_vfe"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x1d 0x200 0x0 0x0 0x1d 0x200 0x5f5e100 0x5f5e100>; | |
| qcom,msm-bus-vector-dyn-vote; | |
| qcom,vfe-cx-ipeak = <0x16d 0x2>; | |
| linux,phandle = <0x386>; | |
| phandle = <0x386>; | |
| }; | |
| qcom,vfe { | |
| compatible = "qcom,vfe"; | |
| num_child = <0x2>; | |
| }; | |
| qcom,cci@ca0c000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,cci"; | |
| reg = <0xca0c000 0x4000>; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| reg-names = "cci"; | |
| interrupts = <0x0 0x127 0x0>; | |
| interrupt-names = "cci"; | |
| status = "ok"; | |
| mmagic-supply = <0x163>; | |
| gdscr-supply = <0x164>; | |
| qcom,cam-vreg-name = "mmagic", "gdscr"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0xa 0x74 0x5a 0x74 0x5b>; | |
| clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x124f800 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x23c3460 0x0 0x0>; | |
| pinctrl-names = "cci_default", "cci_suspend"; | |
| pinctrl-0 = <0x1c7 0x1c8>; | |
| pinctrl-1 = <0x1c9 0x1ca>; | |
| gpios = <0xe7 0x24 0x0 0xe7 0x25 0x0 0xe7 0x26 0x0 0xe7 0x27 0x0>; | |
| qcom,gpio-tbl-num = <0x0 0x1 0x2 0x3>; | |
| qcom,gpio-tbl-flags = <0x1 0x1 0x1 0x1>; | |
| qcom,gpio-tbl-label = "CCI_I2C_DATA0", "CCI_I2C_CLK0", "CCI_I2C_DATA1", "CCI_I2C_CLK1"; | |
| linux,phandle = <0x387>; | |
| phandle = <0x387>; | |
| qcom,i2c_standard_mode { | |
| status = "ok"; | |
| qcom,hw-thigh = <0xc9>; | |
| qcom,hw-tlow = <0xae>; | |
| qcom,hw-tsu-sto = <0xcc>; | |
| qcom,hw-tsu-sta = <0xe7>; | |
| qcom,hw-thd-dat = <0x16>; | |
| qcom,hw-thd-sta = <0xa2>; | |
| qcom,hw-tbuf = <0xe3>; | |
| qcom,hw-scl-stretch-en = <0x0>; | |
| qcom,hw-trdhld = <0x6>; | |
| qcom,hw-tsp = <0x3>; | |
| qcom,cci-clk-src = <0x23c3460>; | |
| linux,phandle = <0x388>; | |
| phandle = <0x388>; | |
| }; | |
| qcom,i2c_fast_mode { | |
| status = "ok"; | |
| qcom,hw-thigh = <0x26>; | |
| qcom,hw-tlow = <0x38>; | |
| qcom,hw-tsu-sto = <0x28>; | |
| qcom,hw-tsu-sta = <0x28>; | |
| qcom,hw-thd-dat = <0x16>; | |
| qcom,hw-thd-sta = <0x23>; | |
| qcom,hw-tbuf = <0x3e>; | |
| qcom,hw-scl-stretch-en = <0x0>; | |
| qcom,hw-trdhld = <0x6>; | |
| qcom,hw-tsp = <0x3>; | |
| qcom,cci-clk-src = <0x23c3460>; | |
| linux,phandle = <0x389>; | |
| phandle = <0x389>; | |
| }; | |
| qcom,i2c_custom_mode { | |
| status = "ok"; | |
| qcom,hw-thigh = <0x26>; | |
| qcom,hw-tlow = <0x38>; | |
| qcom,hw-tsu-sto = <0x28>; | |
| qcom,hw-tsu-sta = <0x28>; | |
| qcom,hw-thd-dat = <0x16>; | |
| qcom,hw-thd-sta = <0x23>; | |
| qcom,hw-tbuf = <0x3e>; | |
| qcom,hw-scl-stretch-en = <0x1>; | |
| qcom,hw-trdhld = <0x6>; | |
| qcom,hw-tsp = <0x3>; | |
| qcom,cci-clk-src = <0x23c3460>; | |
| linux,phandle = <0x38a>; | |
| phandle = <0x38a>; | |
| }; | |
| qcom,i2c_fast_plus_mode { | |
| status = "ok"; | |
| qcom,hw-thigh = <0x10>; | |
| qcom,hw-tlow = <0x16>; | |
| qcom,hw-tsu-sto = <0x11>; | |
| qcom,hw-tsu-sta = <0x12>; | |
| qcom,hw-thd-dat = <0x10>; | |
| qcom,hw-thd-sta = <0xf>; | |
| qcom,hw-tbuf = <0x18>; | |
| qcom,hw-scl-stretch-en = <0x0>; | |
| qcom,hw-trdhld = <0x3>; | |
| qcom,hw-tsp = <0x3>; | |
| qcom,cci-clk-src = <0x23c3460>; | |
| linux,phandle = <0x38b>; | |
| phandle = <0x38b>; | |
| }; | |
| qcom,actuator@1 { | |
| cell-index = <0x1>; | |
| reg = <0x1>; | |
| compatible = "qcom,actuator"; | |
| qcom,cci-master = <0x1>; | |
| gpios = <0xe7 0x32 0x0>; | |
| qcom,gpio-vaf = <0x0>; | |
| qcom,gpio-req-tbl-num = <0x0>; | |
| qcom,gpio-req-tbl-flags = <0x0>; | |
| qcom,gpio-req-tbl-label = "CAM_VAF"; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1cb>; | |
| pinctrl-1 = <0x1cc>; | |
| linux,phandle = <0x1e2>; | |
| phandle = <0x1e2>; | |
| }; | |
| qcom,eeprom@0 { | |
| cell-index = <0x0>; | |
| reg = <0x0>; | |
| compatible = "qcom,eeprom"; | |
| qcom,eeprom-name = "lavender_ov02a10_ofilm_i"; | |
| qcom,i2c-freq-mode = <0x1>; | |
| qcom,slave-addr = <0xa8>; | |
| qcom,num-blocks = <0x1>; | |
| qcom,page0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,mem0 = <0x1bf6 0x0 0x2 0x0 0x1 0x0>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1cf 0x1d0>; | |
| pinctrl-1 = <0x1d1 0x1d2>; | |
| gpios = <0xe7 0x20 0x0 0xe7 0x30 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
| qcom,cam-power-seq-type = "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio"; | |
| qcom,cam-power-seq-val = "sensor_gpio_reset", "cam_vana", "cam_vdig", "cam_vio", "sensor_cam_mclk", "sensor_gpio_reset"; | |
| qcom,cam-power-seq-cfg-val = <0x0 0x1 0x1 0x1 0x16e3600 0x1>; | |
| qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x1 0x1 0xa>; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x0>; | |
| status = "ok"; | |
| clocks = <0x74 0x1c 0x74 0x82>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| linux,phandle = <0x1de>; | |
| phandle = <0x1de>; | |
| }; | |
| qcom,eeprom@1 { | |
| cell-index = <0x1>; | |
| reg = <0x1>; | |
| compatible = "qcom,eeprom"; | |
| qcom,i2c-freq-mode = <0x1>; | |
| qcom,slave-addr = <0xa2>; | |
| qcom,num-blocks = <0x1>; | |
| qcom,page0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,mem0 = <0x1bf6 0x0 0x2 0x0 0x1 0x0>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1d3>; | |
| cam_vdig-supply = <0x1d4>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1d5 0x1d6>; | |
| pinctrl-1 = <0x1d7 0x1d8>; | |
| gpios = <0xe7 0x23 0x0 0xe7 0x34 0x0 0xe7 0x32 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-vaf = <0x2>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1 0x2>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAM_VAF"; | |
| qcom,cam-power-seq-type = "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_gpio", "sensor_clk", "sensor_gpio"; | |
| qcom,cam-power-seq-val = "sensor_gpio_reset", "cam_vana", "cam_vdig", "cam_vio", "sensor_gpio_vaf", "sensor_cam_mclk", "sensor_gpio_reset"; | |
| qcom,cam-power-seq-cfg-val = <0x0 0x1 0x1 0x1 0x1 0x16e3600 0x1>; | |
| qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x1 0x1 0x1 0xa>; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x1>; | |
| status = "ok"; | |
| clocks = <0x74 0x1f 0x74 0x85>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| linux,phandle = <0x1e3>; | |
| phandle = <0x1e3>; | |
| }; | |
| qcom,eeprom@2 { | |
| cell-index = <0x2>; | |
| reg = <0x2>; | |
| compatible = "qcom,eeprom"; | |
| qcom,i2c-freq-mode = <0x1>; | |
| qcom,slave-addr = <0xa0>; | |
| qcom,num-blocks = <0x1>; | |
| qcom,page0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,mem0 = <0x18f6 0x0 0x2 0x0 0x1 0x0>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1d9 0x1da>; | |
| pinctrl-1 = <0x1db 0x1dc>; | |
| gpios = <0xe7 0x21 0x0 0xe7 0x2f 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1"; | |
| qcom,cam-power-seq-type = "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio"; | |
| qcom,cam-power-seq-val = "sensor_gpio_reset", "cam_vana", "cam_vdig", "cam_vio", "sensor_cam_mclk", "sensor_gpio_reset"; | |
| qcom,cam-power-seq-cfg-val = <0x0 0x1 0x1 0x1 0x16e3600 0x1>; | |
| qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x1 0x1 0xa>; | |
| qcom,sensor-position = <0x1>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x1>; | |
| status = "ok"; | |
| clocks = <0x74 0x1d 0x74 0x83>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| linux,phandle = <0x1e4>; | |
| phandle = <0x1e4>; | |
| }; | |
| qcom,eeprom@3 { | |
| cell-index = <0x3>; | |
| reg = <0x3>; | |
| compatible = "qcom,eeprom"; | |
| qcom,eeprom-name = "lavender_s5k5e8_ofilm_i"; | |
| qcom,i2c-freq-mode = <0x1>; | |
| qcom,slave-addr = <0x30>; | |
| qcom,num-blocks = <0x1b>; | |
| qcom,page0 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page1 = <0x1 0xa02 0x2 0x4 0x1 0x1>; | |
| qcom,poll1 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem1 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page2 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll2 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem2 = <0x10 0xa34 0x2 0x0 0x1 0x0>; | |
| qcom,page3 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll3 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem3 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page4 = <0x1 0xa02 0x2 0x5 0x1 0x1>; | |
| qcom,poll4 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem4 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page5 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll5 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem5 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page6 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll6 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem6 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page7 = <0x1 0xa02 0x2 0x6 0x1 0x1>; | |
| qcom,poll7 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem7 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page8 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll8 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem8 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page9 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll9 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem9 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page10 = <0x1 0xa02 0x2 0x7 0x1 0x1>; | |
| qcom,poll10 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem10 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page11 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll11 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem11 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page12 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll12 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem12 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page13 = <0x1 0xa02 0x2 0x8 0x1 0x1>; | |
| qcom,poll13 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem13 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page14 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll14 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem14 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page15 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll15 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem15 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page16 = <0x1 0xa02 0x2 0x9 0x1 0x1>; | |
| qcom,poll16 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem16 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page17 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll17 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem17 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page18 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll18 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem18 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page19 = <0x1 0xa02 0x2 0xa 0x1 0x1>; | |
| qcom,poll19 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem19 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page20 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll20 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem20 = <0x18 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page21 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll21 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem21 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page22 = <0x1 0xa02 0x2 0xe 0x1 0x1>; | |
| qcom,poll22 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem22 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page23 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll23 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem23 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page24 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll24 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem24 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page25 = <0x1 0xa02 0x2 0xf 0x1 0x1>; | |
| qcom,poll25 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem25 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page26 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll26 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem26 = <0xf 0xa04 0x2 0x0 0x1 0x0>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1cf 0x1d0>; | |
| pinctrl-1 = <0x1d1 0x1d2>; | |
| gpios = <0xe7 0x20 0x0 0xe7 0x30 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
| qcom,cam-power-seq-type = "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio"; | |
| qcom,cam-power-seq-val = "sensor_gpio_reset", "cam_vana", "cam_vdig", "cam_vio", "sensor_cam_mclk", "sensor_gpio_reset"; | |
| qcom,cam-power-seq-cfg-val = <0x0 0x1 0x1 0x1 0x16e3600 0x1>; | |
| qcom,cam-power-seq-delay = <0x1 0x5 0x5 0x5 0x1 0xa>; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x0>; | |
| status = "ok"; | |
| clocks = <0x74 0x1c 0x74 0x82>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| linux,phandle = <0x1df>; | |
| phandle = <0x1df>; | |
| }; | |
| qcom,eeprom@4 { | |
| cell-index = <0x4>; | |
| reg = <0x4>; | |
| compatible = "qcom,eeprom"; | |
| qcom,eeprom-name = "lavender_ov02a10_sunny_ii"; | |
| qcom,i2c-freq-mode = <0x1>; | |
| qcom,slave-addr = <0xa2>; | |
| qcom,num-blocks = <0x1>; | |
| qcom,page0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,mem0 = <0x1bf6 0x0 0x2 0x0 0x1 0x0>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1cf 0x1d0>; | |
| pinctrl-1 = <0x1d1 0x1d2>; | |
| gpios = <0xe7 0x20 0x0 0xe7 0x30 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
| qcom,cam-power-seq-type = "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio"; | |
| qcom,cam-power-seq-val = "sensor_gpio_reset", "cam_vana", "cam_vdig", "cam_vio", "sensor_cam_mclk", "sensor_gpio_reset"; | |
| qcom,cam-power-seq-cfg-val = <0x0 0x1 0x1 0x1 0x16e3600 0x1>; | |
| qcom,cam-power-seq-delay = <0x1 0x1 0x1 0x1 0x1 0xa>; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x0>; | |
| status = "ok"; | |
| clocks = <0x74 0x1c 0x74 0x82>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| linux,phandle = <0x1e0>; | |
| phandle = <0x1e0>; | |
| }; | |
| qcom,eeprom@5 { | |
| cell-index = <0x5>; | |
| reg = <0x5>; | |
| compatible = "qcom,eeprom"; | |
| qcom,eeprom-name = "lavender_s5k5e8_sunny_ii"; | |
| qcom,i2c-freq-mode = <0x1>; | |
| qcom,slave-addr = <0x30>; | |
| qcom,num-blocks = <0x1b>; | |
| qcom,page0 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll0 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem0 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page1 = <0x1 0xa02 0x2 0x4 0x1 0x1>; | |
| qcom,poll1 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem1 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page2 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll2 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem2 = <0x10 0xa34 0x2 0x0 0x1 0x0>; | |
| qcom,page3 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll3 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem3 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page4 = <0x1 0xa02 0x2 0x5 0x1 0x1>; | |
| qcom,poll4 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem4 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page5 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll5 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem5 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page6 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll6 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem6 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page7 = <0x1 0xa02 0x2 0x6 0x1 0x1>; | |
| qcom,poll7 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem7 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page8 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll8 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem8 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page9 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll9 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem9 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page10 = <0x1 0xa02 0x2 0x7 0x1 0x1>; | |
| qcom,poll10 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem10 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page11 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll11 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem11 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page12 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll12 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem12 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page13 = <0x1 0xa02 0x2 0x8 0x1 0x1>; | |
| qcom,poll13 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem13 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page14 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll14 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem14 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page15 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll15 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem15 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page16 = <0x1 0xa02 0x2 0x9 0x1 0x1>; | |
| qcom,poll16 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem16 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page17 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll17 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem17 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page18 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll18 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem18 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page19 = <0x1 0xa02 0x2 0xa 0x1 0x1>; | |
| qcom,poll19 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem19 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page20 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll20 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem20 = <0x18 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page21 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll21 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem21 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page22 = <0x1 0xa02 0x2 0xe 0x1 0x1>; | |
| qcom,poll22 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem22 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page23 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll23 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem23 = <0x40 0xa04 0x2 0x0 0x1 0x0>; | |
| qcom,page24 = <0x1 0xa00 0x2 0x4 0x1 0x1>; | |
| qcom,poll24 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem24 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page25 = <0x1 0xa02 0x2 0xf 0x1 0x1>; | |
| qcom,poll25 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem25 = <0x0 0x0 0x2 0x0 0x1 0x0>; | |
| qcom,page26 = <0x1 0xa00 0x2 0x1 0x1 0x5>; | |
| qcom,poll26 = <0x0 0x0 0x2 0x0 0x1 0x1>; | |
| qcom,mem26 = <0xf 0xa04 0x2 0x0 0x1 0x0>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1cf 0x1d0>; | |
| pinctrl-1 = <0x1d1 0x1d2>; | |
| gpios = <0xe7 0x20 0x0 0xe7 0x30 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
| qcom,cam-power-seq-type = "sensor_gpio", "sensor_vreg", "sensor_vreg", "sensor_vreg", "sensor_clk", "sensor_gpio"; | |
| qcom,cam-power-seq-val = "sensor_gpio_reset", "cam_vana", "cam_vdig", "cam_vio", "sensor_cam_mclk", "sensor_gpio_reset"; | |
| qcom,cam-power-seq-cfg-val = <0x0 0x1 0x1 0x1 0x16e3600 0x1>; | |
| qcom,cam-power-seq-delay = <0x1 0x5 0x5 0x5 0x1 0xa>; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x0>; | |
| status = "ok"; | |
| clocks = <0x74 0x1c 0x74 0x82>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| linux,phandle = <0x1e1>; | |
| phandle = <0x1e1>; | |
| }; | |
| qcom,camera@0 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,camera"; | |
| reg = <0x0>; | |
| qcom,csiphy-sd-index = <0x0>; | |
| qcom,csid-sd-index = <0x0>; | |
| qcom,mount-angle = <0x5a>; | |
| qcom,led-flash-src = <0x1dd>; | |
| qcom,eeprom-src = <0x1de 0x1df 0x1e0 0x1e1>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1cf 0x1d0>; | |
| pinctrl-1 = <0x1d1 0x1d2>; | |
| gpios = <0xe7 0x20 0x0 0xe7 0x30 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0"; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x0>; | |
| status = "ok"; | |
| clocks = <0x74 0x1c 0x74 0x82>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| }; | |
| qcom,camera@1 { | |
| cell-index = <0x1>; | |
| compatible = "qcom,camera"; | |
| reg = <0x1>; | |
| qcom,csiphy-sd-index = <0x1>; | |
| qcom,csid-sd-index = <0x1>; | |
| qcom,mount-angle = <0x5a>; | |
| qcom,led-flash-src = <0x1dd>; | |
| qcom,actuator-src = <0x1e2>; | |
| qcom,eeprom-src = <0x1e3>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1d3>; | |
| cam_vdig-supply = <0x1d4>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1d5 0x1d6>; | |
| pinctrl-1 = <0x1d7 0x1d8>; | |
| gpios = <0xe7 0x23 0x0 0xe7 0x34 0x0 0xe7 0x32 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-vaf = <0x2>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1 0x2>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK3", "CAM_RESET3", "CAM_VAF"; | |
| qcom,sensor-position = <0x0>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x1>; | |
| status = "ok"; | |
| clocks = <0x74 0x1f 0x74 0x85>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| }; | |
| qcom,camera@2 { | |
| cell-index = <0x2>; | |
| compatible = "qcom,camera"; | |
| reg = <0x2>; | |
| qcom,csiphy-sd-index = <0x2>; | |
| qcom,csid-sd-index = <0x2>; | |
| qcom,mount-angle = <0x10e>; | |
| qcom,eeprom-src = <0x1e4>; | |
| cam_vio-supply = <0x17e>; | |
| cam_vana-supply = <0x1cd>; | |
| cam_vdig-supply = <0x1ce>; | |
| qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; | |
| qcom,cam-vreg-min-voltage = <0x1b2920 0x0 0x0>; | |
| qcom,cam-vreg-max-voltage = <0x1dc130 0x0 0x0>; | |
| qcom,cam-vreg-op-mode = <0x19a28 0x0 0x0>; | |
| qcom,gpio-no-mux = <0x0>; | |
| pinctrl-names = "cam_default", "cam_suspend"; | |
| pinctrl-0 = <0x1d9 0x1da>; | |
| pinctrl-1 = <0x1db 0x1dc>; | |
| gpios = <0xe7 0x21 0x0 0xe7 0x2f 0x0 0xe7 0x2d 0x0>; | |
| qcom,gpio-reset = <0x1>; | |
| qcom,gpio-standby = <0x2>; | |
| qcom,gpio-req-tbl-num = <0x0 0x1 0x2>; | |
| qcom,gpio-req-tbl-flags = <0x1 0x0 0x0>; | |
| qcom,gpio-req-tbl-label = "CAMIF_MCLK1", "CAM_RESET1", "CAM_STANDBY1"; | |
| qcom,sensor-position = <0x1>; | |
| qcom,sensor-mode = <0x0>; | |
| qcom,cci-master = <0x1>; | |
| status = "ok"; | |
| clocks = <0x74 0x1d 0x74 0x83>; | |
| clock-names = "cam_src_clk", "cam_clk"; | |
| qcom,clock-rates = <0x16e3600 0x0>; | |
| }; | |
| }; | |
| qcom,jpeg@ca1c000 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,jpeg"; | |
| reg = <0xca1c000 0x4000 0xca60000 0x3000>; | |
| reg-names = "jpeg_hw", "jpeg_vbif"; | |
| interrupts = <0x0 0x13c 0x0>; | |
| interrupt-names = "jpeg"; | |
| smmu-vdd-supply = <0x163>; | |
| camss-vdd-supply = <0x164>; | |
| qcom,vdd-names = "smmu-vdd", "camss-vdd"; | |
| clock-names = "mmssnoc_axi", "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", "core_clk", "mmss_camss_jpeg_ahb_clk", "mmss_camss_jpeg_axi_clk"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x0 0x74 0x80 0x74 0x81>; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0>; | |
| qcom,vbif-reg-settings = <0x4 0x1>; | |
| qcom,prefetch-reg-settings = <0x30c 0x1111 0x318 0x31 0x324 0x31 0x330 0x31 0x33c 0x0>; | |
| qcom,msm-bus,name = "msm_camera_jpeg0"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x0 0x0 0x3e 0x200 0x124f80 0x124f80>; | |
| status = "ok"; | |
| }; | |
| qcom,jpeg@caa0000 { | |
| cell-index = <0x3>; | |
| compatible = "qcom,jpegdma"; | |
| reg = <0xcaa0000 0x4000 0xca60000 0x3000>; | |
| reg-names = "jpeg_hw", "jpeg_vbif"; | |
| interrupts = <0x0 0x130 0x0>; | |
| interrupt-names = "jpeg"; | |
| smmu-vdd-supply = <0x163>; | |
| camss-vdd-supply = <0x164>; | |
| qcom,vdd-names = "smmu-vdd", "camss-vdd"; | |
| clock-names = "mmssnoc_axi", "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", "mmss_camss_ahb_clk", "mmss_camss_top_ahb_clk", "core_clk", "mmss_camss_jpeg_ahb_clk", "mmss_camss_jpeg_axi_clk"; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0x59 0x74 0x87 0x74 0x1 0x74 0x80 0x74 0x81>; | |
| qcom,clock-rates = <0x0 0x0 0x0 0x0 0x0 0x0 0x1c9c3800 0x0 0x0>; | |
| qcom,vbif-reg-settings = <0x4 0x1>; | |
| qcom,prefetch-reg-settings = <0x18c 0x11 0x1a0 0x31 0x1b0 0x31>; | |
| qcom,msm-bus,name = "msm_camera_jpeg_dma"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x3e 0x200 0x0 0x0 0x3e 0x200 0x124f80 0x124f80>; | |
| qcom,max-ds-factor = <0x80>; | |
| status = "ok"; | |
| }; | |
| qcom,vidc@cc00000 { | |
| compatible = "qcom,msm-vidc"; | |
| status = "ok"; | |
| reg = <0xcc00000 0x100000>; | |
| interrupts = <0x0 0x11f 0x4>; | |
| qcom,hfi = "venus"; | |
| qcom,hfi-version = "3xx"; | |
| qcom,firmware-name = "venus"; | |
| qcom,never-unload-fw; | |
| qcom,sw-power-collapse; | |
| qcom,max-secure-instances = <0x5>; | |
| qcom,reg-presets = <0x80010 0x1f001f 0x80018 0x156 0x8001c 0x156>; | |
| qcom,max-hw-load = <0xfd200>; | |
| qcom,allowed-clock-rates = <0x1ee62800 0x1a524800 0x18148d00 0x1312d000 0x100da650 0x7f27450>; | |
| qcom,dcvs-tbl = <0xdb240 0xbf400 0xef100 0x3f00000c 0xc7380 0xb34c0 0xca800 0xc000000 0xdb240 0xdb240 0xef100 0x4000004>; | |
| qcom,dcvs-limit = <0x7e90 0x1e 0x7e90 0x18>; | |
| smmu-vdd-supply = <0x163>; | |
| venus-supply = <0xf3>; | |
| venus-core0-supply = <0x1e5>; | |
| clock-names = "gcc_mmss_sys_noc_axi_clk", "mmssnoc_axi_clk", "mmss_throttle_video_axi_clk", "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", "mmss_video_core_clk", "mmss_video_ahb_clk", "mmss_video_axi_clk", "mmss_video_core0_clk"; | |
| clocks = <0xa1 0x4c 0x26 0x3c 0x74 0xb2 0x74 0xa9 0x74 0x57 0x74 0x58 0x74 0xb6 0x74 0xb4 0x74 0xb5 0x74 0xb7>; | |
| qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 0x3 0x0 0x2 0x3>; | |
| qcom,cx-ipeak-data = <0x16d 0x4>; | |
| qcom,clock-freq-threshold = <0x1ee62800>; | |
| linux,phandle = <0x38c>; | |
| phandle = <0x38c>; | |
| bus_cnoc { | |
| compatible = "qcom,msm-vidc,bus"; | |
| label = "cnoc"; | |
| qcom,bus-master = <0x1>; | |
| qcom,bus-slave = <0x254>; | |
| qcom,bus-governor = "performance"; | |
| qcom,bus-range-kbps = <0x1 0x1>; | |
| }; | |
| venus_bus_ddr { | |
| compatible = "qcom,msm-vidc,bus"; | |
| label = "venus-ddr"; | |
| qcom,bus-master = <0x3f>; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-governor = "venus-ddr-gov"; | |
| qcom,bus-range-kbps = <0x3e8 0x241648>; | |
| }; | |
| arm9_bus_ddr { | |
| compatible = "qcom,msm-vidc,bus"; | |
| label = "venus-arm9-ddr"; | |
| qcom,bus-master = <0x3f>; | |
| qcom,bus-slave = <0x200>; | |
| qcom,bus-governor = "performance"; | |
| qcom,bus-range-kbps = <0x1 0x1>; | |
| }; | |
| qcom,clock-freq-tbl { | |
| qcom,profile-enc { | |
| qcom,codec-mask = <0x55555555>; | |
| qcom,cycles-per-mb = <0x3a3>; | |
| qcom,low-power-mode-factor = <0x8206>; | |
| }; | |
| qcom,profile-dec { | |
| qcom,codec-mask = <0xf3ffffff>; | |
| qcom,cycles-per-mb = <0x163>; | |
| }; | |
| qcom,profile-hevcdec { | |
| qcom,codec-mask = <0xc000000>; | |
| qcom,cycles-per-mb = <0x190>; | |
| }; | |
| }; | |
| venus-ddr-gov { | |
| compatible = "qcom,msm-vidc,governor,table"; | |
| status = "ok"; | |
| qcom,bus-freq-table { | |
| qcom,profile-enc { | |
| qcom,codec-mask = <0x55555555>; | |
| qcom,load-busfreq-tbl = <0xef100 0xfee20 0xd2f00 0xd88d8 0x77880 0xa2990 0x69780 0x8d1d0 0x3bc40 0x54790 0x34bc0 0x47888 0x1a5e0 0x24dd8 0x0 0x0>; | |
| }; | |
| qcom,profile-dec { | |
| qcom,codec-mask = <0xffffffff>; | |
| qcom,load-busfreq-tbl = <0xef100 0x241648 0xd2f00 0x1e2e90 0x77880 0x1149c8 0x69780 0xf2ad0 0x3bc40 0x8d9a0 0x34bc0 0x7a508 0x1a5e0 0x3e418 0x0 0x0>; | |
| }; | |
| qcom,profile-dec-ubwc { | |
| qcom,codec-mask = <0xffffffff>; | |
| qcom,ubwc-mode; | |
| qcom,load-busfreq-tbl = <0xef100 0x1cdea0 0xd2f00 0x17b650 0x77880 0xda818 0x69780 0xbeac8 0x3bc40 0x704e0 0x34bc0 0x497c8 0x1a5e0 0x31510 0x0 0x0>; | |
| }; | |
| qcom,profile-dec-ubwc-10bit { | |
| qcom,codec-mask = <0xffffffff>; | |
| qcom,ubwc-10bit; | |
| qcom,load-busfreq-tbl = <0xef100 0x255400 0xd2f00 0x202c00 0x77880 0x126c00 0x69780 0x102800 0x3bc40 0x96800 0x34bc0 0x82800 0x1a5e0 0x42400 0x0 0x0>; | |
| }; | |
| }; | |
| }; | |
| non_secure_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| label = "venus_ns"; | |
| iommus = <0x173 0x400 0x173 0x401 0x173 0x40a 0x173 0x407 0x173 0x40e 0x173 0x40f 0x173 0x408 0x173 0x409 0x173 0x40b 0x173 0x40c 0x173 0x40d 0x173 0x410 0x173 0x421 0x173 0x428 0x173 0x429 0x173 0x42b 0x173 0x42c 0x173 0x42d 0x173 0x411 0x173 0x431>; | |
| buffer-types = <0xfff>; | |
| virtual-addr-pool = <0x79000000 0x60000000>; | |
| }; | |
| firmware_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| qcom,fw-context-bank; | |
| iommus = <0x173 0x580 0x173 0x586>; | |
| }; | |
| secure_bitstream_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| label = "venus_sec_bitstream"; | |
| iommus = <0x173 0x500 0x173 0x502 0x173 0x509 0x173 0x50a 0x173 0x50b 0x173 0x50e 0x173 0x526 0x173 0x529 0x173 0x52b>; | |
| buffer-types = <0x241>; | |
| virtual-addr-pool = <0x51000000 0x28000000>; | |
| qcom,secure-context-bank; | |
| }; | |
| secure_pixel_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| label = "venus_sec_pixel"; | |
| iommus = <0x173 0x504 0x173 0x50c 0x173 0x510 0x173 0x52c>; | |
| buffer-types = <0x106>; | |
| virtual-addr-pool = <0x29000000 0x28000000>; | |
| qcom,secure-context-bank; | |
| linux,phandle = <0x38d>; | |
| phandle = <0x38d>; | |
| }; | |
| secure_non_pixel_cb { | |
| compatible = "qcom,msm-vidc,context-bank"; | |
| label = "venus_sec_non_pixel"; | |
| iommus = <0x173 0x505 0x173 0x507 0x173 0x508 0x173 0x50d 0x173 0x50f 0x173 0x525 0x173 0x528 0x173 0x52d 0x173 0x540>; | |
| buffer-types = <0x480>; | |
| virtual-addr-pool = <0x1000000 0x28000000>; | |
| qcom,secure-context-bank; | |
| linux,phandle = <0x38e>; | |
| phandle = <0x38e>; | |
| }; | |
| }; | |
| qcom,msm-pcm { | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,msm-pcm-dsp-id = <0x0>; | |
| linux,phandle = <0x1ec>; | |
| phandle = <0x1ec>; | |
| }; | |
| qcom,msm-pcm-routing { | |
| compatible = "qcom,msm-pcm-routing"; | |
| linux,phandle = <0x1f6>; | |
| phandle = <0x1f6>; | |
| }; | |
| qcom,msm-compr-dsp { | |
| compatible = "qcom,msm-compr-dsp"; | |
| linux,phandle = <0x1f8>; | |
| phandle = <0x1f8>; | |
| }; | |
| qcom,msm-ultra-low-latency { | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,msm-pcm-dsp-id = <0x2>; | |
| qcom,msm-pcm-low-latency; | |
| qcom,latency-level = "ultra"; | |
| linux,phandle = <0x1ee>; | |
| phandle = <0x1ee>; | |
| }; | |
| qcom,msm-pcm-low-latency { | |
| compatible = "qcom,msm-pcm-dsp"; | |
| qcom,msm-pcm-dsp-id = <0x1>; | |
| qcom,msm-pcm-low-latency; | |
| qcom,latency-level = "regular"; | |
| linux,phandle = <0x1ed>; | |
| phandle = <0x1ed>; | |
| }; | |
| qcom,msm-pcm-dsp-noirq { | |
| compatible = "qcom,msm-pcm-dsp-noirq"; | |
| qcom,msm-pcm-low-latency; | |
| qcom,latency-level = "ultra"; | |
| linux,phandle = <0x1f9>; | |
| phandle = <0x1f9>; | |
| }; | |
| qcom,msm-cpe-lsm { | |
| compatible = "qcom,msm-cpe-lsm"; | |
| linux,phandle = <0x1f7>; | |
| phandle = <0x1f7>; | |
| }; | |
| qcom,msm-cpe-lsm@3 { | |
| compatible = "qcom,msm-cpe-lsm"; | |
| qcom,msm-cpe-lsm-id = <0x3>; | |
| linux,phandle = <0x1fa>; | |
| phandle = <0x1fa>; | |
| }; | |
| qcom,wcd-dsp-mgr { | |
| compatible = "qcom,wcd-dsp-mgr"; | |
| qcom,wdsp-components = <0x1e6 0x0 0x1e7 0x1 0x1e8 0x2>; | |
| qcom,img-filename = "cpe_9340"; | |
| status = "disabled"; | |
| linux,phandle = <0x38f>; | |
| phandle = <0x38f>; | |
| }; | |
| qcom,wcd-dsp-glink { | |
| compatible = "qcom,wcd-dsp-glink"; | |
| status = "disabled"; | |
| linux,phandle = <0x390>; | |
| phandle = <0x390>; | |
| }; | |
| qcom,msm-compress-dsp { | |
| compatible = "qcom,msm-compress-dsp"; | |
| linux,phandle = <0x1f2>; | |
| phandle = <0x1f2>; | |
| }; | |
| qcom,msm-voip-dsp { | |
| compatible = "qcom,msm-voip-dsp"; | |
| linux,phandle = <0x1ef>; | |
| phandle = <0x1ef>; | |
| }; | |
| qcom,msm-pcm-voice { | |
| compatible = "qcom,msm-pcm-voice"; | |
| qcom,destroy-cvd; | |
| linux,phandle = <0x1f0>; | |
| phandle = <0x1f0>; | |
| }; | |
| qcom,msm-stub-codec { | |
| compatible = "qcom,msm-stub-codec"; | |
| linux,phandle = <0x227>; | |
| phandle = <0x227>; | |
| }; | |
| qcom,msm-dai-fe { | |
| compatible = "qcom,msm-dai-fe"; | |
| }; | |
| qcom,msm-pcm-afe { | |
| compatible = "qcom,msm-pcm-afe"; | |
| linux,phandle = <0x1f4>; | |
| phandle = <0x1f4>; | |
| }; | |
| qcom,msm-dai-q6-dp { | |
| compatible = "qcom,msm-dai-q6-hdmi"; | |
| qcom,msm-dai-q6-dev-id = <0x6020>; | |
| linux,phandle = <0x1fb>; | |
| phandle = <0x1fb>; | |
| }; | |
| qcom,msm-pcm-loopback { | |
| compatible = "qcom,msm-pcm-loopback"; | |
| linux,phandle = <0x1f1>; | |
| phandle = <0x1f1>; | |
| }; | |
| qcom,msm-dai-mi2s { | |
| compatible = "qcom,msm-dai-mi2s"; | |
| qcom,msm-dai-q6-mi2s-prim { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x0>; | |
| qcom,msm-mi2s-rx-lines = <0x1>; | |
| qcom,msm-mi2s-tx-lines = <0x2>; | |
| linux,phandle = <0x1fc>; | |
| phandle = <0x1fc>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-sec { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x1>; | |
| qcom,msm-mi2s-rx-lines = <0x1>; | |
| qcom,msm-mi2s-tx-lines = <0x0>; | |
| linux,phandle = <0x1fd>; | |
| phandle = <0x1fd>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quat { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x3>; | |
| qcom,msm-mi2s-rx-lines = <0x1>; | |
| qcom,msm-mi2s-tx-lines = <0x2>; | |
| linux,phandle = <0x1ff>; | |
| phandle = <0x1ff>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-tert { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x2>; | |
| qcom,msm-mi2s-rx-lines = <0x0>; | |
| qcom,msm-mi2s-tx-lines = <0x3>; | |
| linux,phandle = <0x1fe>; | |
| phandle = <0x1fe>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-quin { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x5>; | |
| qcom,msm-mi2s-rx-lines = <0x1>; | |
| qcom,msm-mi2s-tx-lines = <0x2>; | |
| linux,phandle = <0x391>; | |
| phandle = <0x391>; | |
| }; | |
| qcom,msm-dai-q6-mi2s-senary { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x6>; | |
| qcom,msm-mi2s-rx-lines = <0x0>; | |
| qcom,msm-mi2s-tx-lines = <0x3>; | |
| linux,phandle = <0x392>; | |
| phandle = <0x392>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s0 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x7>; | |
| qcom,msm-mi2s-rx-lines = <0x3>; | |
| qcom,msm-mi2s-tx-lines = <0x0>; | |
| linux,phandle = <0x23f>; | |
| phandle = <0x23f>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s1 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x8>; | |
| qcom,msm-mi2s-rx-lines = <0x3>; | |
| qcom,msm-mi2s-tx-lines = <0x0>; | |
| linux,phandle = <0x240>; | |
| phandle = <0x240>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s2 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0x9>; | |
| qcom,msm-mi2s-rx-lines = <0x0>; | |
| qcom,msm-mi2s-tx-lines = <0x3>; | |
| linux,phandle = <0x241>; | |
| phandle = <0x241>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s3 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0xa>; | |
| qcom,msm-mi2s-rx-lines = <0x0>; | |
| qcom,msm-mi2s-tx-lines = <0x3>; | |
| linux,phandle = <0x242>; | |
| phandle = <0x242>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s4 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0xb>; | |
| qcom,msm-mi2s-rx-lines = <0x3>; | |
| qcom,msm-mi2s-tx-lines = <0x0>; | |
| linux,phandle = <0x243>; | |
| phandle = <0x243>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s5 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0xc>; | |
| qcom,msm-mi2s-rx-lines = <0x0>; | |
| qcom,msm-mi2s-tx-lines = <0x3>; | |
| linux,phandle = <0x244>; | |
| phandle = <0x244>; | |
| }; | |
| qcom,msm-dai-q6-int-mi2s6 { | |
| compatible = "qcom,msm-dai-q6-mi2s"; | |
| qcom,msm-dai-q6-mi2s-dev-id = <0xd>; | |
| qcom,msm-mi2s-rx-lines = <0x0>; | |
| qcom,msm-mi2s-tx-lines = <0x3>; | |
| linux,phandle = <0x393>; | |
| phandle = <0x393>; | |
| }; | |
| }; | |
| qcom,msm-lsm-client { | |
| compatible = "qcom,msm-lsm-client"; | |
| linux,phandle = <0x1f5>; | |
| phandle = <0x1f5>; | |
| }; | |
| qcom,msm-dai-q6 { | |
| compatible = "qcom,msm-dai-q6"; | |
| qcom,msm-dai-q6-sb-0-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4000>; | |
| linux,phandle = <0x204>; | |
| phandle = <0x204>; | |
| }; | |
| qcom,msm-dai-q6-sb-0-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4001>; | |
| linux,phandle = <0x205>; | |
| phandle = <0x205>; | |
| }; | |
| qcom,msm-dai-q6-sb-1-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4002>; | |
| linux,phandle = <0x206>; | |
| phandle = <0x206>; | |
| }; | |
| qcom,msm-dai-q6-sb-1-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4003>; | |
| linux,phandle = <0x207>; | |
| phandle = <0x207>; | |
| }; | |
| qcom,msm-dai-q6-sb-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4004>; | |
| linux,phandle = <0x208>; | |
| phandle = <0x208>; | |
| }; | |
| qcom,msm-dai-q6-sb-2-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4005>; | |
| linux,phandle = <0x209>; | |
| phandle = <0x209>; | |
| }; | |
| qcom,msm-dai-q6-sb-3-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4006>; | |
| linux,phandle = <0x20a>; | |
| phandle = <0x20a>; | |
| }; | |
| qcom,msm-dai-q6-sb-3-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4007>; | |
| linux,phandle = <0x20b>; | |
| phandle = <0x20b>; | |
| }; | |
| qcom,msm-dai-q6-sb-4-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4008>; | |
| linux,phandle = <0x20c>; | |
| phandle = <0x20c>; | |
| }; | |
| qcom,msm-dai-q6-sb-4-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4009>; | |
| linux,phandle = <0x20d>; | |
| phandle = <0x20d>; | |
| }; | |
| qcom,msm-dai-q6-sb-5-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400b>; | |
| linux,phandle = <0x20e>; | |
| phandle = <0x20e>; | |
| }; | |
| qcom,msm-dai-q6-sb-5-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400a>; | |
| linux,phandle = <0x217>; | |
| phandle = <0x217>; | |
| }; | |
| qcom,msm-dai-q6-sb-6-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400c>; | |
| linux,phandle = <0x218>; | |
| phandle = <0x218>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400f>; | |
| linux,phandle = <0x21a>; | |
| phandle = <0x21a>; | |
| }; | |
| qcom,msm-dai-q6-sb-7-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x400e>; | |
| linux,phandle = <0x219>; | |
| phandle = <0x219>; | |
| }; | |
| qcom,msm-dai-q6-sb-8-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4011>; | |
| linux,phandle = <0x21b>; | |
| phandle = <0x21b>; | |
| }; | |
| qcom,msm-dai-q6-sb-8-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x4010>; | |
| linux,phandle = <0x21c>; | |
| phandle = <0x21c>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3000>; | |
| linux,phandle = <0x394>; | |
| phandle = <0x394>; | |
| }; | |
| qcom,msm-dai-q6-bt-sco-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3001>; | |
| linux,phandle = <0x395>; | |
| phandle = <0x395>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3004>; | |
| linux,phandle = <0x396>; | |
| phandle = <0x396>; | |
| }; | |
| qcom,msm-dai-q6-int-fm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x3005>; | |
| linux,phandle = <0x397>; | |
| phandle = <0x397>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xe0>; | |
| linux,phandle = <0x20f>; | |
| phandle = <0x20f>; | |
| }; | |
| qcom,msm-dai-q6-be-afe-pcm-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xe1>; | |
| linux,phandle = <0x210>; | |
| phandle = <0x210>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xf1>; | |
| linux,phandle = <0x211>; | |
| phandle = <0x211>; | |
| }; | |
| qcom,msm-dai-q6-afe-proxy-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0xf0>; | |
| linux,phandle = <0x212>; | |
| phandle = <0x212>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8003>; | |
| linux,phandle = <0x213>; | |
| phandle = <0x213>; | |
| }; | |
| qcom,msm-dai-q6-incall-record-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8004>; | |
| linux,phandle = <0x214>; | |
| phandle = <0x214>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8005>; | |
| linux,phandle = <0x215>; | |
| phandle = <0x215>; | |
| }; | |
| qcom,msm-dai-q6-incall-music-2-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x8002>; | |
| linux,phandle = <0x216>; | |
| phandle = <0x216>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-rx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x7000>; | |
| linux,phandle = <0x21d>; | |
| phandle = <0x21d>; | |
| }; | |
| qcom,msm-dai-q6-usb-audio-tx { | |
| compatible = "qcom,msm-dai-q6-dev"; | |
| qcom,msm-dai-q6-dev-id = <0x7001>; | |
| linux,phandle = <0x21e>; | |
| phandle = <0x21e>; | |
| }; | |
| }; | |
| qcom,msm-pcm-hostless { | |
| compatible = "qcom,msm-pcm-hostless"; | |
| linux,phandle = <0x1f3>; | |
| phandle = <0x1f3>; | |
| audio_test_mod { | |
| compatible = "qcom,audio-test-mod"; | |
| }; | |
| }; | |
| qcom,msm-pri-auxpcm { | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-auxpcm-interface = "primary"; | |
| qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
| linux,phandle = <0x200>; | |
| phandle = <0x200>; | |
| }; | |
| qcom,msm-sec-auxpcm { | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-auxpcm-interface = "secondary"; | |
| qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
| linux,phandle = <0x201>; | |
| phandle = <0x201>; | |
| }; | |
| qcom,msm-tert-auxpcm { | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-auxpcm-interface = "tertiary"; | |
| qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
| linux,phandle = <0x202>; | |
| phandle = <0x202>; | |
| }; | |
| qcom,msm-quat-auxpcm { | |
| compatible = "qcom,msm-auxpcm-dev"; | |
| qcom,msm-cpudai-auxpcm-mode = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-sync = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-frame = <0x5 0x4>; | |
| qcom,msm-cpudai-auxpcm-quant = <0x2 0x2>; | |
| qcom,msm-cpudai-auxpcm-num-slots = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-slot-mapping = <0x1 0x1>; | |
| qcom,msm-cpudai-auxpcm-data = <0x0 0x0>; | |
| qcom,msm-cpudai-auxpcm-pcm-clk-rate = <0x1f4000 0x1f4000>; | |
| qcom,msm-auxpcm-interface = "quaternary"; | |
| qcom,msm-cpudai-afe-clk-ver = <0x2>; | |
| linux,phandle = <0x203>; | |
| phandle = <0x203>; | |
| }; | |
| qcom,msm-audio-ion { | |
| compatible = "qcom,msm-audio-ion"; | |
| qcom,smmu-version = <0x2>; | |
| qcom,smmu-enabled; | |
| iommus = <0xea 0x1>; | |
| }; | |
| qcom,msm-adsp-loader { | |
| compatible = "qcom,adsp-loader"; | |
| qcom,adsp-state = <0x0>; | |
| }; | |
| qcom,msm-dai-tdm-pri-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9100>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-pri-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9000>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x21f>; | |
| phandle = <0x21f>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-pri-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9101>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-pri-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9001>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x220>; | |
| phandle = <0x220>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-sec-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9110>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-sec-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9010>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x221>; | |
| phandle = <0x221>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-sec-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9111>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-sec-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9011>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x222>; | |
| phandle = <0x222>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-tert-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9120>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-tert-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9020>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x223>; | |
| phandle = <0x223>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-tert-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9121>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-tert-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9021>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x224>; | |
| phandle = <0x224>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-quat-rx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9130>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9030>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-quat-rx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9030>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x225>; | |
| phandle = <0x225>; | |
| }; | |
| }; | |
| qcom,msm-dai-tdm-quat-tx { | |
| compatible = "qcom,msm-dai-tdm"; | |
| qcom,msm-cpudai-tdm-group-id = <0x9131>; | |
| qcom,msm-cpudai-tdm-group-num-ports = <0x1>; | |
| qcom,msm-cpudai-tdm-group-port-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-clk-rate = <0x177000>; | |
| qcom,msm-cpudai-tdm-clk-internal = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-mode = <0x1>; | |
| qcom,msm-cpudai-tdm-sync-src = <0x1>; | |
| qcom,msm-cpudai-tdm-data-out = <0x0>; | |
| qcom,msm-cpudai-tdm-invert-sync = <0x1>; | |
| qcom,msm-cpudai-tdm-data-delay = <0x1>; | |
| qcom,msm-dai-q6-tdm-quat-tx-0 { | |
| compatible = "qcom,msm-dai-q6-tdm"; | |
| qcom,msm-cpudai-tdm-dev-id = <0x9031>; | |
| qcom,msm-cpudai-tdm-data-align = <0x0>; | |
| linux,phandle = <0x226>; | |
| phandle = <0x226>; | |
| }; | |
| }; | |
| qcom,avtimer@150f700c { | |
| compatible = "qcom,avtimer"; | |
| reg = <0x150f700c 0x4 0x150f7010 0x4>; | |
| reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; | |
| qcom,clk-div = <0x1b>; | |
| }; | |
| sound-9335 { | |
| compatible = "qcom,sdm660-asoc-snd-tasha"; | |
| qcom,model = "sdm660-tasha-snd-card"; | |
| qcom,wcn-btfm; | |
| qcom,mi2s-audio-intf; | |
| qcom,auxpcm-audio-intf; | |
| qcom,ext-disp-audio-rx; | |
| qcom,msm-mi2s-master = <0x1 0x1 0x1 0x1>; | |
| qcom,audio-routing = "AIF4 VI", "MCLK", "RX_BIAS", "MCLK", "MADINPUT", "MCLK", "AMIC2", "MIC BIAS2", "MIC BIAS2", "Headset Mic", "AMIC3", "MIC BIAS2", "MIC BIAS2", "ANCRight Headset Mic", "AMIC4", "MIC BIAS2", "MIC BIAS2", "ANCLeft Headset Mic", "AMIC5", "MIC BIAS3", "MIC BIAS3", "Handset Mic", "AMIC6", "MIC BIAS4", "MIC BIAS4", "Analog Mic6", "DMIC0", "MIC BIAS1", "MIC BIAS1", "Digital Mic0", "DMIC1", "MIC BIAS1", "MIC BIAS1", "Digital Mic1", "DMIC2", "MIC BIAS3", "MIC BIAS3", "Digital Mic2", "DMIC3", "MIC BIAS3", "MIC BIAS3", "Digital Mic3", "DMIC4", "MIC BIAS4", "MIC BIAS4", "Digital Mic4", "DMIC5", "MIC BIAS4", "MIC BIAS4", "Digital Mic5", "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT"; | |
| qcom,msm-mbhc-hphl-swh = <0x1>; | |
| qcom,msm-mbhc-gnd-swh = <0x1>; | |
| qcom,us-euro-gpios = <0x1e9>; | |
| qcom,hph-en0-gpio = <0x1ea>; | |
| qcom,hph-en1-gpio = <0x1eb>; | |
| qcom,msm-mclk-freq = <0x927c00>; | |
| asoc-platform = <0x1ec 0x1ed 0x1ee 0x1ef 0x1f0 0x1f1 0x1f2 0x1f3 0x1f4 0x1f5 0x1f6 0x1f7 0x1f8 0x1f9 0x1fa>; | |
| asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq", "msm-cpe-lsm.3"; | |
| asoc-cpu = <0x1fb 0x1fc 0x1fd 0x1fe 0x1ff 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20a 0x20b 0x20c 0x20d 0x20e 0x20f 0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21a 0x21b 0x21c 0x21d 0x21e 0x21f 0x220 0x221 0x222 0x223 0x224 0x225 0x226>; | |
| asoc-cpu-names = "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; | |
| asoc-codec = <0x227 0x228>; | |
| asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; | |
| qcom,wsa-max-devs = <0x2>; | |
| qcom,wsa-devs = <0x229 0x22a 0x22b 0x22c>; | |
| qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; | |
| status = "disabled"; | |
| linux,phandle = <0x398>; | |
| phandle = <0x398>; | |
| }; | |
| sound-tavil { | |
| compatible = "qcom,sdm660-asoc-snd-tavil"; | |
| qcom,model = "sdm660-tavil-snd-card"; | |
| qcom,wcn-btfm; | |
| qcom,mi2s-audio-intf; | |
| qcom,auxpcm-audio-intf; | |
| qcom,ext-disp-audio-rx; | |
| qcom,msm-mi2s-master = <0x1 0x1 0x1 0x1>; | |
| qcom,audio-routing = "AIF4 VI", "MCLK", "RX_BIAS", "MCLK", "MADINPUT", "MCLK", "AMIC2", "MIC BIAS2", "MIC BIAS2", "Headset Mic", "AMIC3", "MIC BIAS2", "MIC BIAS2", "ANCRight Headset Mic", "AMIC4", "MIC BIAS2", "MIC BIAS2", "ANCLeft Headset Mic", "AMIC5", "MIC BIAS3", "MIC BIAS3", "Handset Mic", "DMIC0", "MIC BIAS1", "MIC BIAS1", "Digital Mic0", "DMIC1", "MIC BIAS1", "MIC BIAS1", "Digital Mic1", "DMIC2", "MIC BIAS3", "MIC BIAS3", "Digital Mic2", "DMIC3", "MIC BIAS3", "MIC BIAS3", "Digital Mic3", "DMIC4", "MIC BIAS4", "MIC BIAS4", "Digital Mic4", "DMIC5", "MIC BIAS4", "MIC BIAS4", "Digital Mic5", "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT"; | |
| qcom,msm-mbhc-hphl-swh = <0x1>; | |
| qcom,msm-mbhc-gnd-swh = <0x1>; | |
| qcom,us-euro-gpios = <0x22d>; | |
| qcom,hph-en0-gpio = <0x22e>; | |
| qcom,hph-en1-gpio = <0x22f>; | |
| qcom,msm-mclk-freq = <0x927c00>; | |
| asoc-platform = <0x1ec 0x1ed 0x1ee 0x1ef 0x1f0 0x1f1 0x1f2 0x1f3 0x1f4 0x1f5 0x1f6 0x1f7 0x1f8 0x1f9>; | |
| asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm", "msm-compr-dsp", "msm-pcm-dsp-noirq"; | |
| asoc-cpu = <0x1fb 0x1fc 0x1fd 0x1fe 0x1ff 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20a 0x20b 0x20c 0x20d 0x20e 0x20f 0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21a 0x21b 0x21c 0x21d 0x21e 0x21f 0x220 0x221 0x222 0x223 0x224 0x225 0x226>; | |
| asoc-cpu-names = "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; | |
| asoc-codec = <0x227 0x228>; | |
| asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; | |
| qcom,wsa-max-devs = <0x2>; | |
| qcom,wsa-devs = <0x230 0x231 0x232 0x233>; | |
| qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; | |
| status = "disabled"; | |
| qcom,msm-mbhc-moist-cfg = <0x0 0x0 0x3>; | |
| linux,phandle = <0x399>; | |
| phandle = <0x399>; | |
| }; | |
| sound { | |
| status = "okay"; | |
| compatible = "qcom,sdm660-asoc-snd"; | |
| qcom,model = "sdm660-snd-card"; | |
| qcom,wcn-btfm; | |
| qcom,mi2s-audio-intf; | |
| qcom,auxpcm-audio-intf; | |
| qcom,ext-disp-audio-rx; | |
| qcom,msm-mi2s-master = <0x1 0x1 0x1 0x1>; | |
| qcom,msm-mclk-freq = <0x927c00>; | |
| qcom,msm-mbhc-hphl-swh = <0x1>; | |
| qcom,msm-mbhc-gnd-swh = <0x1>; | |
| qcom,msm-micbias1-ext-cap; | |
| qcom,msm-hs-micbias-type = "external"; | |
| qcom,cdc-pdm-gpios = <0x234>; | |
| qcom,cdc-comp-gpios = <0x235>; | |
| qcom,cdc-dmic-gpios = <0x236>; | |
| pinctrl-names = "pri_i2s_active", "pri_i2s_sleep"; | |
| pinctrl-0 = <0x237 0x238 0x239 0x23a>; | |
| pinctrl-1 = <0x23b 0x23c 0x23d 0x23e>; | |
| qcom,audio-routing = "RX_BIAS", "INT_MCLK0", "SPK_RX_BIAS", "INT_MCLK0", "INT_LDO_H", "INT_MCLK0", "RX_I2S_CLK", "INT_MCLK0", "TX_I2S_CLK", "INT_MCLK0", "MIC BIAS External", "Handset Mic", "MIC BIAS External2", "Headset Mic", "MIC BIAS External", "Secondary Mic", "AMIC1", "MIC BIAS External", "AMIC2", "MIC BIAS External2", "AMIC3", "MIC BIAS External", "DMIC1", "MIC BIAS External", "MIC BIAS External", "Digital Mic1", "DMIC2", "MIC BIAS External", "MIC BIAS External", "Digital Mic2", "DMIC3", "MIC BIAS External", "MIC BIAS External", "Digital Mic3", "DMIC4", "MIC BIAS External", "MIC BIAS External", "Digital Mic4", "SpkrLeft IN", "SPK1 OUT", "SpkrRight IN", "SPK2 OUT", "PDM_IN_RX1", "PDM_OUT_RX1", "PDM_IN_RX2", "PDM_OUT_RX2", "PDM_IN_RX3", "PDM_OUT_RX3", "ADC1_IN", "ADC1_OUT", "ADC2_IN", "ADC2_OUT", "ADC3_IN", "ADC3_OUT"; | |
| asoc-platform = <0x1ec 0x1ed 0x1ee 0x1ef 0x1f0 0x1f1 0x1f2 0x1f3 0x1f4 0x1f5 0x1f6 0x1f8 0x1f9>; | |
| asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2", "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback", "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe", "msm-lsm-client", "msm-pcm-routing", "msm-compr-dsp", "msm-pcm-dsp-noirq"; | |
| asoc-cpu = <0x1fb 0x1fc 0x1fd 0x1fe 0x1ff 0x23f 0x240 0x241 0x242 0x243 0x244 0x200 0x201 0x202 0x203 0x20f 0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x219 0x21a 0x21b 0x21c 0x21d 0x21e 0x21f 0x220 0x221 0x222 0x223 0x224 0x225 0x226>; | |
| asoc-cpu-names = "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.7", "msm-dai-q6-mi2s.8", "msm-dai-q6-mi2s.9", "msm-dai-q6-mi2s.10", "msm-dai-q6-mi2s.11", "msm-dai-q6-mi2s.12", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913"; | |
| asoc-codec = <0x227 0x245 0x246 0x247 0x228>; | |
| asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec", "analog-codec", "msm_sdw_codec", "msm-ext-disp-audio-codec-rx"; | |
| qcom,wsa-max-devs = <0x2>; | |
| qcom,wsa-devs = <0x248 0x249 0x24a 0x24b>; | |
| qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; | |
| qcom,wsa-disable; | |
| linux,phandle = <0x39a>; | |
| phandle = <0x39a>; | |
| }; | |
| msm_cdc_pinctrl@75 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x24c>; | |
| pinctrl-1 = <0x24d>; | |
| linux,phandle = <0x1e9>; | |
| phandle = <0x1e9>; | |
| }; | |
| wcd9xxx-irq { | |
| compatible = "qcom,wcd9xxx-irq"; | |
| interrupt-controller; | |
| #interrupt-cells = <0x1>; | |
| interrupts = <0x0 0xb1 0x0>; | |
| interrupt-names = "wcd_irq"; | |
| status = "disabled"; | |
| linux,phandle = <0xab>; | |
| phandle = <0xab>; | |
| }; | |
| audio_ext_clk { | |
| compatible = "qcom,audio-ref-clk"; | |
| qcom,audio-ref-clk-gpio = <0x192 0x3 0x0>; | |
| clock-names = "osr_clk"; | |
| clocks = <0x26 0x26>; | |
| qcom,node_has_rpm_clock; | |
| #clock-cells = <0x1>; | |
| qcom,codec-mclk-clk-freq = <0xac4400>; | |
| qcom,mclk-clk-reg = <0x15020018 0x0>; | |
| pinctrl-names = "sleep", "active"; | |
| pinctrl-0 = <0x24e>; | |
| pinctrl-1 = <0x24f>; | |
| status = "disabled"; | |
| linux,phandle = <0xad>; | |
| phandle = <0xad>; | |
| }; | |
| audio_ext_clk_lnbb { | |
| compatible = "qcom,audio-ref-clk"; | |
| clock-names = "osr_clk"; | |
| clocks = <0x26 0x32>; | |
| qcom,node_has_rpm_clock; | |
| #clock-cells = <0x1>; | |
| linux,phandle = <0xb9>; | |
| phandle = <0xb9>; | |
| }; | |
| msm_cdc_pinctrl@64 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x250>; | |
| pinctrl-1 = <0x251>; | |
| qcom,lpi-gpios; | |
| status = "disabled"; | |
| linux,phandle = <0xac>; | |
| phandle = <0xac>; | |
| }; | |
| msm_cdc_pinctrl_usbc_audio_en1 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x252>; | |
| pinctrl-1 = <0x253>; | |
| linux,phandle = <0x39b>; | |
| phandle = <0x39b>; | |
| }; | |
| msm_cdc_pinctrl_usbc_audio_en2 { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x254>; | |
| pinctrl-1 = <0x255>; | |
| linux,phandle = <0x39c>; | |
| phandle = <0x39c>; | |
| }; | |
| lpi_pinctrl@15070000 { | |
| compatible = "qcom,lpi-pinctrl"; | |
| reg = <0x15070000 0x0>; | |
| qcom,num-gpios = <0x20>; | |
| gpio-controller; | |
| #gpio-cells = <0x2>; | |
| linux,phandle = <0x39d>; | |
| phandle = <0x39d>; | |
| lpi_mclk0_active { | |
| linux,phandle = <0x24f>; | |
| phandle = <0x24f>; | |
| mux { | |
| pins = "gpio18"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x8>; | |
| bias-disable; | |
| }; | |
| }; | |
| lpi_mclk0_sleep { | |
| linux,phandle = <0x24e>; | |
| phandle = <0x24e>; | |
| mux { | |
| pins = "gpio18"; | |
| function = "func2"; | |
| }; | |
| config { | |
| pins = "gpio18"; | |
| drive-strength = <0x2>; | |
| bias-pull-down; | |
| }; | |
| }; | |
| cdc_pdm_gpios_active { | |
| linux,phandle = <0x256>; | |
| phandle = <0x256>; | |
| mux { | |
| pins = "gpio18", "gpio19", "gpio21", "gpio23", "gpio25"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio18", "gpio19", "gpio21", "gpio23", "gpio25"; | |
| drive-strength = <0x8>; | |
| output-high; | |
| }; | |
| }; | |
| cdc_pdm_gpios_sleep { | |
| linux,phandle = <0x258>; | |
| phandle = <0x258>; | |
| mux { | |
| pins = "gpio18", "gpio19", "gpio21", "gpio23", "gpio25"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio18", "gpio19", "gpio21", "gpio23", "gpio25"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| cdc_pdm_2_gpios_active { | |
| linux,phandle = <0x257>; | |
| phandle = <0x257>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x8>; | |
| }; | |
| }; | |
| cdc_pdm_2_gpios_sleep { | |
| linux,phandle = <0x259>; | |
| phandle = <0x259>; | |
| mux { | |
| pins = "gpio20"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio20"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| cdc_pdm_comp_gpios_active { | |
| linux,phandle = <0x25a>; | |
| phandle = <0x25a>; | |
| mux { | |
| pins = "gpio22", "gpio24"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio22", "gpio24"; | |
| drive-strength = <0x8>; | |
| }; | |
| }; | |
| cdc_pdm_comp_gpios_sleep { | |
| linux,phandle = <0x25b>; | |
| phandle = <0x25b>; | |
| mux { | |
| pins = "gpio22", "gpio24"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio22", "gpio24"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| }; | |
| }; | |
| lpi_cdc_reset_active { | |
| linux,phandle = <0x250>; | |
| phandle = <0x250>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x10>; | |
| output-high; | |
| }; | |
| }; | |
| lpi_cdc_reset_sleep { | |
| linux,phandle = <0x251>; | |
| phandle = <0x251>; | |
| mux { | |
| pins = "gpio24"; | |
| function = "gpio"; | |
| }; | |
| config { | |
| pins = "gpio24"; | |
| drive-strength = <0x10>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| dmic12_gpios_active { | |
| linux,phandle = <0x25c>; | |
| phandle = <0x25c>; | |
| mux { | |
| pins = "gpio26", "gpio28"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio26", "gpio28"; | |
| drive-strength = <0x8>; | |
| output-high; | |
| }; | |
| }; | |
| dmic12_gpios_sleep { | |
| linux,phandle = <0x25e>; | |
| phandle = <0x25e>; | |
| mux { | |
| pins = "gpio26", "gpio28"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio26", "gpio28"; | |
| drive-strength = <0x2>; | |
| bias-disable; | |
| output-low; | |
| }; | |
| }; | |
| dmic34_gpios_active { | |
| linux,phandle = <0x25d>; | |
| phandle = <0x25d>; | |
| mux { | |
| pins = "gpio27", "gpio29"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio27", "gpio29"; | |
| drive-strength = <0x8>; | |
| input-enable; | |
| }; | |
| }; | |
| dmic34_gpios_sleep { | |
| linux,phandle = <0x25f>; | |
| phandle = <0x25f>; | |
| mux { | |
| pins = "gpio27", "gpio29"; | |
| function = "func1"; | |
| }; | |
| config { | |
| pins = "gpio27", "gpio29"; | |
| drive-strength = <0x2>; | |
| pull-down; | |
| input-enable; | |
| }; | |
| }; | |
| }; | |
| cdc_pdm_pinctrl { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x256 0x257>; | |
| pinctrl-1 = <0x258 0x259>; | |
| qcom,lpi-gpios; | |
| linux,phandle = <0x234>; | |
| phandle = <0x234>; | |
| }; | |
| cdc_comp_pinctrl { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x25a>; | |
| pinctrl-1 = <0x25b>; | |
| qcom,lpi-gpios; | |
| linux,phandle = <0x235>; | |
| phandle = <0x235>; | |
| }; | |
| cdc_dmic_pinctrl { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| pinctrl-names = "aud_active", "aud_sleep"; | |
| pinctrl-0 = <0x25c 0x25d>; | |
| pinctrl-1 = <0x25e 0x25f>; | |
| qcom,lpi-gpios; | |
| linux,phandle = <0x236>; | |
| phandle = <0x236>; | |
| }; | |
| sdw_clk_data_pinctrl { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| linux,phandle = <0x39e>; | |
| phandle = <0x39e>; | |
| }; | |
| wsa_spkr_en1_pinctrl { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| linux,phandle = <0x260>; | |
| phandle = <0x260>; | |
| }; | |
| wsa_spkr_en2_pinctrl { | |
| compatible = "qcom,msm-cdc-pinctrl"; | |
| linux,phandle = <0x261>; | |
| phandle = <0x261>; | |
| }; | |
| msm-sdw-codec@152c1000 { | |
| status = "okay"; | |
| compatible = "qcom,msm-sdw-codec"; | |
| reg = <0x152c1000 0x0>; | |
| interrupts = <0x0 0xa1 0x0>; | |
| interrupt-names = "swr_master_irq"; | |
| linux,phandle = <0x247>; | |
| phandle = <0x247>; | |
| swr_master { | |
| compatible = "qcom,swr-wcd"; | |
| #address-cells = <0x2>; | |
| #size-cells = <0x0>; | |
| wsa881x_en@20170211 { | |
| compatible = "qcom,wsa881x"; | |
| status = "disabled"; | |
| reg = <0x0 0x20170211>; | |
| qcom,spkr-sd-n-node = <0x260>; | |
| linux,phandle = <0x248>; | |
| phandle = <0x248>; | |
| }; | |
| wsa881x_en@20170212 { | |
| compatible = "qcom,wsa881x"; | |
| status = "disabled"; | |
| reg = <0x0 0x20170212>; | |
| qcom,spkr-sd-n-node = <0x261>; | |
| linux,phandle = <0x249>; | |
| phandle = <0x249>; | |
| }; | |
| wsa881x_en@21170213 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x21170213>; | |
| status = "disabled"; | |
| qcom,spkr-sd-n-node = <0x260>; | |
| linux,phandle = <0x24a>; | |
| phandle = <0x24a>; | |
| }; | |
| wsa881x_en@21170214 { | |
| compatible = "qcom,wsa881x"; | |
| reg = <0x0 0x21170214>; | |
| status = "disabled"; | |
| qcom,spkr-sd-n-node = <0x261>; | |
| linux,phandle = <0x24b>; | |
| phandle = <0x24b>; | |
| }; | |
| }; | |
| }; | |
| gpio_keys { | |
| status = "okay"; | |
| compatible = "gpio-keys"; | |
| input-name = "gpio-keys"; | |
| pinctrl-names = "tlmm_gpio_key_active", "tlmm_gpio_key_suspend"; | |
| pinctrl-0 = <0x262>; | |
| pinctrl-1 = <0x263>; | |
| camera_focus { | |
| label = "camera_focus"; | |
| gpios = <0xe7 0x40 0x1>; | |
| linux,input-type = <0x1>; | |
| linux,code = <0x210>; | |
| debounce-interval = <0xf>; | |
| }; | |
| camera_snapshot { | |
| label = "camera_snapshot"; | |
| gpios = <0xe7 0x71 0x1>; | |
| linux,input-type = <0x1>; | |
| linux,code = <0x2fe>; | |
| debounce-interval = <0xf>; | |
| }; | |
| vol_up { | |
| label = "volume_up"; | |
| gpios = <0x264 0x7 0x1>; | |
| linux,input-type = <0x1>; | |
| linux,code = <0x73>; | |
| gpio-key,wakeup; | |
| debounce-interval = <0xf>; | |
| }; | |
| }; | |
| qcom,mdss_mdp@c900000 { | |
| compatible = "qcom,mdss_mdp"; | |
| status = "ok"; | |
| reg = <0xc900000 0x90000 0xc9b0000 0x1040>; | |
| reg-names = "mdp_phys", "vbif_phys"; | |
| interrupts = <0x0 0x53 0x0>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x1>; | |
| vdd-supply = <0x165>; | |
| qcom,msm-bus,name = "mdss_mdp"; | |
| qcom,msm-bus,num-cases = <0x3>; | |
| qcom,msm-bus,num-paths = <0x2>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x17 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800 0x17 0x200 0x0 0x61a800>; | |
| qcom,mdss-ab-factor = <0x1 0x1>; | |
| qcom,mdss-ib-factor = <0x1 0x1>; | |
| qcom,mdss-clk-factor = <0x69 0x64>; | |
| qcom,max-mixer-width = <0xa00>; | |
| qcom,max-pipe-width = <0xa00>; | |
| qcom,max-dest-scaler-input-width = <0x800>; | |
| qcom,max-dest-scaler-output-width = <0xa00>; | |
| qcom,mdss-vbif-qos-rt-setting = <0x1 0x2 0x2 0x2>; | |
| qcom,mdss-vbif-qos-nrt-setting = <0x1 0x1 0x1 0x1>; | |
| qcom,vbif-settings = <0xac 0x8040 0xd0 0x2828>; | |
| qcom,mdss-cx-ipeak = <0x16d 0x3>; | |
| qcom,mdss-has-panic-ctrl; | |
| qcom,mdss-per-pipe-panic-luts = <0xf 0xffff 0xfffc 0xff00>; | |
| qcom,mdss-mdp-reg-offset = <0x1000>; | |
| qcom,max-bandwidth-low-kbps = <0x64b540>; | |
| qcom,max-bandwidth-high-kbps = <0x64b540>; | |
| qcom,max-bandwidth-per-pipe-kbps = <0x2f4d60>; | |
| qcom,max-clk-rate = <0x18964020>; | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| qcom,mdss-default-ot-wr-limit = <0x20>; | |
| qcom,mdss-dram-channels = <0x2>; | |
| qcom,max-bw-settings = <0x1 0x64b540 0x2 0x44aa20>; | |
| qcom,mdss-pipe-vig-off = <0x5000 0x7000>; | |
| qcom,mdss-pipe-dma-off = <0x25000 0x27000 0x29000>; | |
| qcom,mdss-pipe-cursor-off = <0x35000>; | |
| qcom,mdss-pipe-vig-xin-id = <0x0 0x4>; | |
| qcom,mdss-pipe-dma-xin-id = <0x1 0x5 0x9>; | |
| qcom,mdss-pipe-cursor-xin-id = <0x2>; | |
| qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0x0 0x0 0x2b4 0x0 0x0>; | |
| qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 0x8 0xc 0x2b4 0x8 0xc 0x2c4 0x8 0xc>; | |
| qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 0x10 0xf>; | |
| qcom,mdss-ctl-off = <0x2000 0x2200 0x2400 0x2600 0x2800>; | |
| qcom,mdss-mixer-intf-off = <0x45000 0x46000 0x47000 0x4a000>; | |
| qcom,mdss-dspp-off = <0x55000 0x57000>; | |
| qcom,mdss-wb-off = <0x66000>; | |
| qcom,mdss-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; | |
| qcom,mdss-pingpong-off = <0x71000 0x71800 0x72000 0x72800>; | |
| qcom,mdss-slave-pingpong-off = <0x73000>; | |
| qcom,mdss-ppb-ctl-off = <0x330 0x338 0x370 0x374>; | |
| qcom,mdss-ppb-cfg-off = <0x334 0x33c>; | |
| qcom,mdss-has-pingpong-split; | |
| qcom,mdss-has-separate-rotator; | |
| qcom,mdss-ad-off = <0x79000 0x79800>; | |
| qcom,mdss-cdm-off = <0x7a200>; | |
| qcom,mdss-dsc-off = <0x81000 0x81400>; | |
| qcom,mdss-wfd-mode = "intf"; | |
| qcom,mdss-has-source-split; | |
| qcom,mdss-highest-bank-bit = <0x1>; | |
| qcom,mdss-has-decimation; | |
| qcom,mdss-idle-power-collapse-enabled; | |
| clocks = <0x74 0xa9 0x74 0x92 0x74 0x93 0x74 0xaf 0x74 0x20 0x74 0xa2 0x74 0xa6 0x74 0x20>; | |
| clock-names = "mnoc_clk", "iface_clk", "bus_clk", "throttle_bus_clk", "core_clk_src", "core_clk", "vsync_clk", "lut_clk"; | |
| qcom,mdp-settings = <0x1190 0x0 0x12ac 0xc0000ccc 0x12b4 0xc0000ccc 0x12bc 0xcccccc 0x12c4 0xcccc 0x13a8 0xcccc0c0 0x13b0 0xccccc0c0 0x13b8 0xcccc0000 0x13d0 0xcc0000 0x506c 0x0 0x706c 0x0 0x906c 0x0 0xb06c 0x0 0x1506c 0x0 0x1706c 0x0 0x1906c 0x0 0x1b06c 0x0 0x2506c 0x0 0x2706c 0x0>; | |
| qcom,regs-dump-mdp = <0x1000 0x1458 0x2000 0x2094 0x2200 0x2294 0x2400 0x2494 0x2600 0x2694 0x2800 0x2894 0x5000 0x5154 0x5a00 0x5b00 0x7000 0x7154 0x7a00 0x7b00 0x25000 0x25184 0x27000 0x27184 0x29000 0x29184 0x35000 0x35150 0x45000 0x452bc 0x46000 0x462bc 0x47000 0x472bc 0x4a000 0x4a2bc 0x55000 0x5522c 0x57000 0x5722c 0x66000 0x662c0 0x6b000 0x6b268 0x6b800 0x6ba68 0x6c000 0x6c268 0x71000 0x710d4 0x71800 0x718d4 0x73000 0x730d4 0x81000 0x81140 0x81400 0x81540>; | |
| qcom,regs-dump-names-mdp = "MDP", "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", "DMA0_SSPP", "DMA1_SSPP", "DMA2_SSPP", "CURSOR0_SSPP", "LAYER_0", "LAYER_1", "LAYER_2", "LAYER_5", "DSPP_0", "DSPP_1", "WB_2", "INTF_0", "INTF_1", "INTF_2", "PP_0", "PP_1", "PP_4", "DSC_0", "DSC_1"; | |
| qcom,mdss-prefill-outstanding-buffer-bytes = <0x0>; | |
| qcom,mdss-prefill-y-buffer-bytes = <0x0>; | |
| qcom,mdss-prefill-scaler-buffer-lines-bilinear = <0x2>; | |
| qcom,mdss-prefill-scaler-buffer-lines-caf = <0x4>; | |
| qcom,mdss-prefill-post-scaler-buffer-pixels = <0xa00>; | |
| qcom,mdss-prefill-pingpong-buffer-pixels = <0x1400>; | |
| qcom,mdss-pref-prim-intf = "dsi"; | |
| linux,phandle = <0x275>; | |
| phandle = <0x275>; | |
| qcom,mdss-reg-bus { | |
| qcom,msm-bus,name = "mdss_reg"; | |
| qcom,msm-bus,num-cases = <0x4>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,vectors-KBps = <0x1 0x24e 0x0 0x0 0x1 0x24e 0x0 0x12c00 0x1 0x24e 0x0 0x27100 0x1 0x24e 0x0 0x4e200>; | |
| }; | |
| qcom,mdss-pp-offsets { | |
| qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; | |
| qcom,mdss-sspp-vig-pcc-off = <0x1b00>; | |
| qcom,mdss-sspp-rgb-pcc-off = <0x380>; | |
| qcom,mdss-sspp-dma-pcc-off = <0x380>; | |
| qcom,mdss-lm-pgc-off = <0x3c0>; | |
| qcom,mdss-dspp-gamut-off = <0x1600>; | |
| qcom,mdss-dspp-pcc-off = <0x1700>; | |
| qcom,mdss-dspp-pgc-off = <0x17c0>; | |
| }; | |
| qcom,mdss-scaler-offsets { | |
| qcom,mdss-vig-scaler-off = <0xa00>; | |
| qcom,mdss-vig-scaler-lut-off = <0xb00>; | |
| qcom,mdss-has-dest-scaler; | |
| qcom,mdss-dest-block-off = <0x61000>; | |
| qcom,mdss-dest-scaler-off = <0x800 0x1000>; | |
| qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>; | |
| }; | |
| qcom,smmu_mdp_unsec_cb { | |
| compatible = "qcom,smmu_mdp_unsec"; | |
| iommus = <0x173 0x0>; | |
| gdsc-mmagic-mdss-supply = <0x163>; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58>; | |
| clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; | |
| linux,phandle = <0x39f>; | |
| phandle = <0x39f>; | |
| }; | |
| qcom,smmu_mdp_sec_cb { | |
| compatible = "qcom,smmu_mdp_sec"; | |
| iommus = <0x173 0x1>; | |
| gdsc-mmagic-mdss-supply = <0x163>; | |
| clocks = <0x26 0x3c 0x74 0xa9 0x74 0x57 0x74 0x58>; | |
| clock-names = "mmss_noc_axi_clk", "mmss_noc_ahb_clk", "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk"; | |
| linux,phandle = <0x3a0>; | |
| phandle = <0x3a0>; | |
| }; | |
| qcom,mdss_fb_primary { | |
| cell-index = <0x0>; | |
| compatible = "qcom,mdss-fb"; | |
| linux,phandle = <0x276>; | |
| phandle = <0x276>; | |
| qcom,cont-splash-memory { | |
| linux,contiguous-region = <0x265>; | |
| }; | |
| }; | |
| qcom,mdss_fb_wfd { | |
| cell-index = <0x1>; | |
| compatible = "qcom,mdss-fb"; | |
| linux,phandle = <0x27c>; | |
| phandle = <0x27c>; | |
| }; | |
| qcom,mdss_fb_dp { | |
| cell-index = <0x2>; | |
| compatible = "qcom,mdss-fb"; | |
| qcom,mdss-intf = <0x266>; | |
| linux,phandle = <0x27e>; | |
| phandle = <0x27e>; | |
| }; | |
| qcom,mdss_dsi_sim_video { | |
| qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x280>; | |
| qcom,mdss-dsi-panel-height = <0x1e0>; | |
| qcom,mdss-dsi-h-front-porch = <0x8>; | |
| qcom,mdss-dsi-h-back-porch = <0x8>; | |
| qcom,mdss-dsi-h-pulse-width = <0x8>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x6>; | |
| qcom,mdss-dsi-v-front-porch = <0x6>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-off-command = [22 01 00 00 00 00 02 00 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0x0 0x0 0x0>; | |
| qcom,mdss-dsi-t-clk-post = <0x4>; | |
| qcom,mdss-dsi-t-clk-pre = <0x1b>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x0 0x0 0x0 0x1 0x0>; | |
| qcom,panel-ack-disabled; | |
| linux,phandle = <0x3a1>; | |
| phandle = <0x3a1>; | |
| }; | |
| qcom,mdss_dsi_dual_sim_video { | |
| qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x500>; | |
| qcom,mdss-dsi-panel-height = <0x5a0>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x2c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x4>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-panel-broadcast-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
| qcom,mdss-dsi-t-clk-post = <0x3>; | |
| qcom,mdss-dsi-t-clk-pre = <0x27>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0xc8 0x1 0x14>; | |
| qcom,panel-ack-disabled; | |
| linux,phandle = <0x3a2>; | |
| phandle = <0x3a2>; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_video_truly { | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x7>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0x3ff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe2362400 0x666a2838 0x2a030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x14 0x1 0x32>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,config-select = <0x267>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x23180708 0x40304a0>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x35>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-bitclk; | |
| qcom,mdss-dsi-dynamic-bitclk_freq = <0x2f942f40 0x2fc75ca0 0x2ffa8a00 0x302db760 0x3060e4c0>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3a3>; | |
| phandle = <0x3a3>; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| linux,phandle = <0x267>; | |
| phandle = <0x267>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_truly_wqxga_cmd { | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x7>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
| qcom,adjust-timer-wakeup-ms = <0x1>; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 05 40 15 01 00 00 00 00 02 06 19 15 01 00 00 00 00 02 07 1e 15 01 00 00 00 00 02 0b 73 15 01 00 00 00 00 02 0c 73 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f ae 15 01 00 00 00 00 02 11 b8 15 01 00 00 00 00 02 13 00 15 01 00 00 00 00 02 58 80 15 01 00 00 00 00 02 59 01 15 01 00 00 00 00 02 5a 00 15 01 00 00 00 00 02 5b 01 15 01 00 00 00 00 02 5c 80 15 01 00 00 00 00 02 5d 81 15 01 00 00 00 00 02 5e 00 15 01 00 00 00 00 02 5f 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 68 03 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 1c 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 01 15 01 00 00 00 00 02 04 0f 15 01 00 00 00 00 02 05 10 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 89 15 01 00 00 00 00 02 09 8a 15 01 00 00 00 00 02 0a 13 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 15 15 01 00 00 00 00 02 0d 15 15 01 00 00 00 00 02 0e 17 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 1c 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 0f 15 01 00 00 00 00 02 15 10 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 89 15 01 00 00 00 00 02 19 8a 15 01 00 00 00 00 02 1a 13 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 15 15 01 00 00 00 00 02 1d 15 15 01 00 00 00 00 02 1e 17 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 40 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 dc 21 15 01 00 00 00 00 02 dd 22 15 01 00 00 00 00 02 de 07 15 01 00 00 00 00 02 df 07 15 01 00 00 00 00 02 e3 6d 15 01 00 00 00 00 02 e1 07 15 01 00 00 00 00 02 e2 07 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 7f 15 15 01 00 00 00 00 02 75 15 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 93 0a 15 01 00 00 00 00 02 94 0a 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9d b0 15 01 00 00 00 00 02 9f 63 15 01 00 00 00 00 02 98 10 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 04 3b 03 0a 0a 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 fb 01 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,config-select = <0x269>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x23180708 0x40304a0>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3a4>; | |
| phandle = <0x3a4>; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| linux,phandle = <0x269>; | |
| phandle = <0x269>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt36850_truly_wqhd_cmd { | |
| qcom,mdss-dsi-panel-name = "Dual nt36850 cmd mode dsi truly panel without DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x8c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x14>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x14>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 19 15 01 00 00 00 00 02 01 03 15 01 00 00 00 00 02 02 04 15 01 00 00 00 00 02 03 1b 15 01 00 00 00 00 02 04 1d 15 01 00 00 00 00 02 05 01 15 01 00 00 00 00 02 06 0c 15 01 00 00 00 00 02 07 0f 15 01 00 00 00 00 02 08 1f 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 13 15 01 00 00 00 00 02 0c 16 15 01 00 00 00 00 02 0d 14 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 00 15 01 00 00 00 00 02 10 19 15 01 00 00 00 00 02 11 03 15 01 00 00 00 00 02 12 04 15 01 00 00 00 00 02 13 1b 15 01 00 00 00 00 02 14 1d 15 01 00 00 00 00 02 15 01 15 01 00 00 00 00 02 16 0c 15 01 00 00 00 00 02 17 0f 15 01 00 00 00 00 02 18 1f 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 13 15 01 00 00 00 00 02 1c 16 15 01 00 00 00 00 02 1d 14 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 10 15 01 00 00 00 00 02 23 28 15 01 00 00 00 00 02 24 28 15 01 00 00 00 00 02 25 5d 15 01 00 00 00 00 02 26 28 15 01 00 00 00 00 02 27 28 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 15 15 01 00 00 00 00 02 2b 00 15 01 00 00 00 00 02 2d 00 15 01 00 00 00 00 02 2f 02 15 01 00 00 00 00 02 30 02 15 01 00 00 00 00 02 31 00 15 01 00 00 00 00 02 32 23 15 01 00 00 00 00 02 33 01 15 01 00 00 00 00 02 34 03 15 01 00 00 00 00 02 35 49 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 1d 15 01 00 00 00 00 02 38 08 15 01 00 00 00 00 02 39 03 15 01 00 00 00 00 02 3a 49 15 01 00 00 00 00 02 42 01 15 01 00 00 00 00 02 43 8c 15 01 00 00 00 00 02 44 a3 15 01 00 00 00 00 02 48 8c 15 01 00 00 00 00 02 49 a3 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5f 4d 15 01 00 00 00 00 02 63 00 15 01 00 00 00 00 02 67 04 15 01 00 00 00 00 02 6e 10 15 01 00 00 00 00 02 72 02 15 01 00 00 00 00 02 73 00 15 01 00 00 00 00 02 74 04 15 01 00 00 00 00 02 75 1b 15 01 00 00 00 00 02 76 05 15 01 00 00 00 00 02 77 01 15 01 00 00 00 00 02 78 00 15 01 00 00 00 00 02 79 00 15 01 00 00 00 00 02 7a 00 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c da 15 01 00 00 00 00 02 7d 10 15 01 00 00 00 00 02 7e 04 15 01 00 00 00 00 02 7f 1b 15 01 00 00 00 00 02 80 00 15 01 00 00 00 00 02 81 05 15 01 00 00 00 00 02 82 01 15 01 00 00 00 00 02 83 00 15 01 00 00 00 00 02 84 05 15 01 00 00 00 00 02 85 05 15 01 00 00 00 00 02 86 1b 15 01 00 00 00 00 02 87 1b 15 01 00 00 00 00 02 88 1b 15 01 00 00 00 00 02 89 1b 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 8b f0 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8f 63 15 01 00 00 00 00 02 90 51 15 01 00 00 00 00 02 91 40 15 01 00 00 00 00 02 92 51 15 01 00 00 00 00 02 93 08 15 01 00 00 00 00 02 94 08 15 01 00 00 00 00 02 95 51 15 01 00 00 00 00 02 96 51 15 01 00 00 00 00 02 97 00 15 01 00 00 00 00 02 98 00 15 01 00 00 00 00 02 99 33 15 01 00 00 00 00 02 9b ff 15 01 00 00 00 00 02 9c 01 15 01 00 00 00 00 02 9d 30 15 01 00 00 00 00 02 a5 10 15 01 00 00 00 00 02 a6 01 15 01 00 00 00 00 02 a9 21 15 01 00 00 00 00 02 b3 2a 15 01 00 00 00 00 02 b4 da 15 01 00 00 00 00 02 ba 83 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 c5 aa 15 01 00 00 00 00 02 c6 09 15 01 00 00 00 00 02 c7 00 15 01 00 00 00 00 02 c9 c0 15 01 00 00 00 00 02 ca 04 15 01 00 00 00 00 02 d5 3f 15 01 00 00 00 00 02 d6 10 15 01 00 00 00 00 02 d7 3f 15 01 00 00 00 00 02 d8 10 15 01 00 00 00 00 02 d9 ee 15 01 00 00 00 00 02 da 49 15 01 00 00 00 00 02 db 94 15 01 00 00 00 00 02 e9 33 15 01 00 00 00 00 02 eb 28 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ee 00 15 01 00 00 00 00 02 ef 06 15 01 00 00 00 00 02 f0 01 15 01 00 00 00 00 02 f1 01 15 01 00 00 00 00 02 f2 0d 15 01 00 00 00 00 02 f3 48 15 01 00 00 00 00 02 f6 00 15 01 00 00 00 00 02 f7 00 15 01 00 00 00 00 02 f8 00 15 01 00 00 00 00 02 f9 00 15 01 00 00 00 00 02 ff 26 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 ab 15 01 00 00 00 00 02 01 00 15 01 00 00 00 00 02 02 80 15 01 00 00 00 00 02 03 08 15 01 00 00 00 00 02 04 01 15 01 00 00 00 00 02 05 32 15 01 00 00 00 00 02 06 4c 15 01 00 00 00 00 02 07 26 15 01 00 00 00 00 02 08 09 15 01 00 00 00 00 02 09 02 15 01 00 00 00 00 02 0a 32 15 01 00 00 00 00 02 0b 55 15 01 00 00 00 00 02 0c 14 15 01 00 00 00 00 02 0d 28 15 01 00 00 00 00 02 0e 40 15 01 00 00 00 00 02 0f 80 15 01 00 00 00 00 02 10 00 15 01 00 00 00 00 02 11 22 15 01 00 00 00 00 02 12 0a 15 01 00 00 00 00 02 13 20 15 01 00 00 00 00 02 14 06 15 01 00 00 00 00 02 15 00 15 01 00 00 00 00 02 16 40 15 01 00 00 00 00 02 19 43 15 01 00 00 00 00 02 1a 03 15 01 00 00 00 00 02 1b 25 15 01 00 00 00 00 02 1c 11 15 01 00 00 00 00 02 1d 00 15 01 00 00 00 00 02 1e 80 15 01 00 00 00 00 02 1f 00 15 01 00 00 00 00 02 20 03 15 01 00 00 00 00 02 21 03 15 01 00 00 00 00 02 22 25 15 01 00 00 00 00 02 23 25 15 01 00 00 00 00 02 24 00 15 01 00 00 00 00 02 25 a7 15 01 00 00 00 00 02 26 80 15 01 00 00 00 00 02 27 a5 15 01 00 00 00 00 02 28 06 15 01 00 00 00 00 02 29 85 15 01 00 00 00 00 02 2a 30 15 01 00 00 00 00 02 2b 97 15 01 00 00 00 00 02 2f 25 15 01 00 00 00 00 02 30 26 15 01 00 00 00 00 02 31 41 15 01 00 00 00 00 02 32 04 15 01 00 00 00 00 02 33 04 15 01 00 00 00 00 02 34 2b 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 37 c8 15 01 00 00 00 00 02 38 26 15 01 00 00 00 00 02 39 25 15 01 00 00 00 00 02 3a 26 15 01 00 00 00 00 02 3f eb 15 01 00 00 00 00 02 41 21 15 01 00 00 00 00 02 42 03 15 01 00 00 00 00 02 43 00 15 01 00 00 00 00 02 44 11 15 01 00 00 00 00 02 45 00 15 01 00 00 00 00 02 46 00 15 01 00 00 00 00 02 47 00 15 01 00 00 00 00 02 48 03 15 01 00 00 00 00 02 49 03 15 01 00 00 00 00 02 4a 00 15 01 00 00 00 00 02 4b 00 15 01 00 00 00 00 02 4c 01 15 01 00 00 00 00 02 4d 4e 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 4c 15 01 00 00 00 00 02 50 0d 15 01 00 00 00 00 02 51 0e 15 01 00 00 00 00 02 52 20 15 01 00 00 00 00 02 53 97 15 01 00 00 00 00 02 54 4b 15 01 00 00 00 00 02 55 4c 15 01 00 00 00 00 02 56 20 15 01 00 00 00 00 02 58 04 15 01 00 00 00 00 02 59 04 15 01 00 00 00 00 02 5a 09 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5d c8 15 01 00 00 00 00 02 5e 4c 15 01 00 00 00 00 02 5f 4b 15 01 00 00 00 00 02 60 00 15 01 00 00 00 00 02 80 2b 15 01 00 00 00 00 02 81 43 15 01 00 00 00 00 02 82 03 15 01 00 00 00 00 02 83 25 15 01 00 00 00 00 02 84 11 15 01 00 00 00 00 02 85 00 15 01 00 00 00 00 02 86 80 15 01 00 00 00 00 02 87 00 15 01 00 00 00 00 02 88 00 15 01 00 00 00 00 02 89 03 15 01 00 00 00 00 02 8a 22 15 01 00 00 00 00 02 8b 25 15 01 00 00 00 00 02 8c 00 15 01 00 00 00 00 02 8d a4 15 01 00 00 00 00 02 8e 00 15 01 00 00 00 00 02 8f a2 15 01 00 00 00 00 02 90 06 15 01 00 00 00 00 02 91 63 15 01 00 00 00 00 02 92 30 15 01 00 00 00 00 02 93 97 15 01 00 00 00 00 02 94 25 15 01 00 00 00 00 02 95 26 15 01 00 00 00 00 02 96 41 15 01 00 00 00 00 02 97 04 15 01 00 00 00 00 02 98 04 15 01 00 00 00 00 02 99 f0 15 01 00 00 00 00 02 9a 00 15 01 00 00 00 00 02 9b 00 15 01 00 00 00 00 02 9c c8 15 01 00 00 00 00 02 9d 50 15 01 00 00 00 00 02 9e 26 15 01 00 00 00 00 02 9f 25 15 01 00 00 00 00 02 a0 26 15 01 00 00 00 00 02 a2 00 15 01 00 00 00 00 02 a3 33 15 01 00 00 00 00 02 a5 40 15 01 00 00 00 00 02 a6 40 15 01 00 00 00 00 02 ac 91 15 01 00 00 00 00 02 ad 66 15 01 00 00 00 00 02 ae 66 15 01 00 00 00 00 02 b1 40 15 01 00 00 00 00 02 b2 40 15 01 00 00 00 00 02 b4 40 15 01 00 00 00 00 02 b5 40 15 01 00 00 00 00 02 b7 40 15 01 00 00 00 00 02 b8 40 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bb 00 15 01 00 00 00 00 02 c2 01 15 01 00 00 00 00 02 c3 01 15 01 00 00 00 00 02 c4 01 15 01 00 00 00 00 02 c5 01 15 01 00 00 00 00 02 c6 01 15 01 00 00 00 00 02 c8 00 15 01 00 00 00 00 02 c9 00 15 01 00 00 00 00 02 ca 00 15 01 00 00 00 00 02 cd 00 15 01 00 00 00 00 02 ce 00 15 01 00 00 00 00 02 d6 04 15 01 00 00 00 00 02 d7 00 15 01 00 00 00 00 02 d8 0d 15 01 00 00 00 00 02 d9 00 15 01 00 00 00 00 02 da 00 15 01 00 00 00 00 02 db 00 15 01 00 00 00 00 02 dc 00 15 01 00 00 00 00 02 dd 00 15 01 00 00 00 00 02 de 00 15 01 00 00 00 00 02 df 01 15 01 00 00 00 00 02 e0 00 15 01 00 00 00 00 02 e1 00 15 01 00 00 00 00 02 e2 19 15 01 00 00 00 00 02 e3 04 15 01 00 00 00 00 02 e4 00 15 01 00 00 00 00 02 e5 04 15 01 00 00 00 00 02 e6 00 15 01 00 00 00 00 02 e7 12 15 01 00 00 00 00 02 e8 00 15 01 00 00 00 00 02 e9 50 15 01 00 00 00 00 02 ea 10 15 01 00 00 00 00 02 eb 02 15 01 00 00 00 00 02 ff 27 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 28 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 60 0a 15 01 00 00 00 00 02 63 32 15 01 00 00 00 00 02 64 01 15 01 00 00 00 00 02 68 da 15 01 00 00 00 00 02 69 00 15 01 00 00 00 00 02 ff 29 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 60 0a 15 01 00 00 00 00 02 63 32 15 01 00 00 00 00 02 64 01 15 01 00 00 00 00 02 68 da 15 01 00 00 00 00 02 69 00 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 35 40 15 01 00 00 00 00 02 36 40 15 01 00 00 00 00 02 37 00 15 01 00 00 00 00 02 89 c6 15 01 00 00 00 00 02 ff f0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ea 40 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 44 03 e8 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 01 05 01 00 00 0a 00 02 20 00 15 01 00 00 00 00 02 bb 10 05 01 00 00 78 00 02 11 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,cmd-sync-wait-broadcast; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-panel-timings = <0xda342400 0x64682838 0x2a030400>; | |
| qcom,mdss-dsi-t-clk-pre = <0x31>; | |
| qcom,mdss-dsi-t-clk-post = <0xe>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241c0809 0x50304a0>; | |
| linux,phandle = <0x3a5>; | |
| phandle = <0x3a5>; | |
| }; | |
| qcom,mdss_dsi_sharp_wqxga_video { | |
| qcom,mdss-dsi-panel-name = "Dual SHARP video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x320>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x4c>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0xb>; | |
| qcom,mdss-dsi-v-front-porch = <0x2>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 05 01 00 00 02 00 02 29 00]; | |
| qcom,mdss-dsi-pre-off-command = [05 01 00 00 02 00 02 28 00 05 01 00 00 a0 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,cmd-sync-wait-broadcast; | |
| qcom,mdss-dsi-panel-timings = <0xe2362400 0x666a2838 0x2a030400>; | |
| qcom,mdss-dsi-t-clk-post = <0x2>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2a>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-bl-pmic-pwm-frequency = <0x32>; | |
| qcom,mdss-dsi-bl-pmic-bank-select = <0x2>; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x2 0x0 0x5 0x1 0x78>; | |
| qcom,mdss-pan-physical-width-dimension = <0x53>; | |
| qcom,mdss-pan-physical-height-dimension = <0x85>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x35>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,mdss-dsi-panel-status-check-mode = "bta_check"; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,esd-check-enabled; | |
| qcom,config-select = <0x26a>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x23200609 0x50304a0 0x23200609 0x50304a0 0x23200609 0x50304a0 0x23200609 0x50304a0 0x232e0608 0x50304a0>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3a6>; | |
| phandle = <0x3a6>; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| linux,phandle = <0x26a>; | |
| phandle = <0x26a>; | |
| }; | |
| config1 { | |
| qcom,split-mode = "pingpong-split"; | |
| linux,phandle = <0x3a7>; | |
| phandle = <0x3a7>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_dsc_video_truly { | |
| qcom,mdss-dsi-panel-name = "nt35597 video mode dsi truly panel with DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x8>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x2 0xfb011501 0x0 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x2 0x5401501 0x0 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x2 0xc731501 0x0 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x2 0x13001501 0x0 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x2 0x5b011501 0x0 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x2 0x5f011501 0x0 0x2721115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x2 0xfb011501 0x0 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x2 0x3011501 0x0 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x2 0x7101501 0x0 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x2 0xb131501 0x0 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x2 0xf171501 0x0 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x2 0x13011501 0x0 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x2 0x17101501 0x0 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x2 0x1b131501 0x0 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x2 0x1f171501 0x0 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x2 0x23401501 0x0 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x2 0x27401501 0x0 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x2 0xde071501 0x0 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x2 0xe2071501 0x0 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x2 0x4c111501 0x0 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x2 0x50101501 0x0 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x2 0x56001501 0x0 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x2 0x5b431501 0x0 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x2 0x63221501 0x0 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x2 0x72021501 0x0 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x2 0x7d601501 0x0 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x2 0xb4001501 0x0 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x2 0x80001501 0x0 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x2 0x8a001501 0x0 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x2 0x98101501 0x0 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x0 0x2c00339 0x1000000 0x43b03 0xa0a1501 0x0 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x3150100 0x2 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0x110404 0x70c0404 0x3030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xb>; | |
| qcom,mdss-dsi-t-clk-pre = <0x23>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,compression-mode = "dsc"; | |
| qcom,config-select = <0x26b>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x201d0507 0x30304a0 0x201d0507 0x30304a0 0x201d0507 0x30304a0 0x201d0507 0x30304a0 0x20120506 0x31304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x35>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3a8>; | |
| phandle = <0x3a8>; | |
| config0 { | |
| qcom,mdss-dsc-encoders = <0x1>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
| qcom,mdss-dsc-bit-per-component = <0x8>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| linux,phandle = <0x3a9>; | |
| phandle = <0x3a9>; | |
| }; | |
| config1 { | |
| qcom,lm-split = <0x2d0 0x2d0>; | |
| qcom,mdss-dsc-encoders = <0x1>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
| qcom,mdss-dsc-bit-per-component = <0x8>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| linux,phandle = <0x3aa>; | |
| phandle = <0x3aa>; | |
| }; | |
| config2 { | |
| qcom,lm-split = <0x2d0 0x2d0>; | |
| qcom,mdss-dsc-encoders = <0x2>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
| qcom,mdss-dsc-bit-per-component = <0x8>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| linux,phandle = <0x26b>; | |
| phandle = <0x26b>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_dsc_cmd_truly { | |
| qcom,mdss-dsi-panel-name = "nt35597 cmd mode dsi truly panel with DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x5a0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x8>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x20150100 0x2 0xfb011501 0x0 0x2000115 0x1000000 0x20155 0x15010000 0x202 0x45150100 0x2 0x5401501 0x0 0x2061915 0x1000000 0x2071e 0x15010000 0x20b 0x73150100 0x2 0xc731501 0x0 0x20eb015 0x1000000 0x20fae 0x15010000 0x211 0xb8150100 0x2 0x13001501 0x0 0x2588015 0x1000000 0x25901 0x15010000 0x25a 0x150100 0x2 0x5b011501 0x0 0x25c8015 0x1000000 0x25d81 0x15010000 0x25e 0x150100 0x2 0x5f011501 0x0 0x2721115 0x1000000 0x26803 0x15010000 0x2ff 0x24150100 0x2 0xfb011501 0x0 0x2001c15 0x1000000 0x2010b 0x15010000 0x202 0xc150100 0x2 0x3011501 0x0 0x2040f15 0x1000000 0x20510 0x15010000 0x206 0x10150100 0x2 0x7101501 0x0 0x2088915 0x1000000 0x2098a 0x15010000 0x20a 0x13150100 0x2 0xb131501 0x0 0x20c1515 0x1000000 0x20d15 0x15010000 0x20e 0x17150100 0x2 0xf171501 0x0 0x2101c15 0x1000000 0x2110b 0x15010000 0x212 0xc150100 0x2 0x13011501 0x0 0x2140f15 0x1000000 0x21510 0x15010000 0x216 0x10150100 0x2 0x17101501 0x0 0x2188915 0x1000000 0x2198a 0x15010000 0x21a 0x13150100 0x2 0x1b131501 0x0 0x21c1515 0x1000000 0x21d15 0x15010000 0x21e 0x17150100 0x2 0x1f171501 0x0 0x2204015 0x1000000 0x22101 0x15010000 0x222 0x150100 0x2 0x23401501 0x0 0x2244015 0x1000000 0x2256d 0x15010000 0x226 0x40150100 0x2 0x27401501 0x0 0x2e00015 0x1000000 0x2dc21 0x15010000 0x2dd 0x22150100 0x2 0xde071501 0x0 0x2df0715 0x1000000 0x2e36d 0x15010000 0x2e1 0x7150100 0x2 0xe2071501 0x0 0x229d815 0x1000000 0x22a2a 0x15010000 0x24b 0x3150100 0x2 0x4c111501 0x0 0x24d1015 0x1000000 0x24e01 0x15010000 0x24f 0x1150100 0x2 0x50101501 0x0 0x2510015 0x1000000 0x25280 0x15010000 0x253 0x150100 0x2 0x56001501 0x0 0x2540715 0x1000000 0x25807 0x15010000 0x255 0x25150100 0x2 0x5b431501 0x0 0x25c0015 0x1000000 0x25f73 0x15010000 0x260 0x73150100 0x2 0x63221501 0x0 0x2640015 0x1000000 0x26708 0x15010000 0x268 0x4150100 0x2 0x72021501 0x0 0x27a8015 0x1000000 0x27b91 0x15010000 0x27c 0xd8150100 0x2 0x7d601501 0x0 0x27f1515 0x1000000 0x27515 0x15010000 0x2b3 0xc0150100 0x2 0xb4001501 0x0 0x2b50015 0x1000000 0x27800 0x15010000 0x279 0x150100 0x2 0x80001501 0x0 0x2830015 0x1000000 0x2930a 0x15010000 0x294 0xa150100 0x2 0x8a001501 0x0 0x29bff15 0x1000000 0x29db0 0x15010000 0x29f 0x63150100 0x2 0x98101501 0x0 0x2ec0015 0x1000000 0x2ff10 0x39010000 0x11c1 0x9200010 0x2000268 0x1bb000a 0x66704c5 0x39010000 0x3c2 0x10f01501 0x0 0x2c00315 0x1000000 0x43b03 0xa0a1501 0x0 0x2350015 0x1000000 0x2e501 0x15010000 0x2bb 0x10150100 0x2 0xfb010501 0x7800 0x2110005 0x1000078 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xb>; | |
| qcom,mdss-dsi-t-clk-pre = <0x23>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,adjust-timer-wakeup-ms = <0x1>; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,ulps-enabled; | |
| qcom,compression-mode = "dsc"; | |
| qcom,config-select = <0x26c>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x201d0507 0x30304a0 0x201d0507 0x30304a0 0x201d0507 0x30304a0 0x201d0507 0x30304a0 0x20120506 0x31304a0>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3ab>; | |
| phandle = <0x3ab>; | |
| config0 { | |
| qcom,mdss-dsc-encoders = <0x1>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
| qcom,mdss-dsc-bit-per-component = <0x8>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| linux,phandle = <0x3ac>; | |
| phandle = <0x3ac>; | |
| }; | |
| config1 { | |
| qcom,lm-split = <0x2d0 0x2d0>; | |
| qcom,mdss-dsc-encoders = <0x1>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
| qcom,mdss-dsc-bit-per-component = <0x8>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| linux,phandle = <0x3ad>; | |
| phandle = <0x3ad>; | |
| }; | |
| config2 { | |
| qcom,lm-split = <0x2d0 0x2d0>; | |
| qcom,mdss-dsc-encoders = <0x2>; | |
| qcom,mdss-dsc-slice-height = <0x10>; | |
| qcom,mdss-dsc-slice-width = <0x2d0>; | |
| qcom,mdss-dsc-slice-per-pkt = <0x2>; | |
| qcom,mdss-dsc-bit-per-component = <0x8>; | |
| qcom,mdss-dsc-bit-per-pixel = <0x8>; | |
| qcom,mdss-dsc-block-prediction-enable; | |
| linux,phandle = <0x26c>; | |
| phandle = <0x26c>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_video { | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi panel without DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x7>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0x3ff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-panel-hdr-enabled; | |
| qcom,mdss-dsi-panel-hdr-color-primaries = <0x38a4 0x3c8c 0x7d00 0x4268 0x3c8c 0x7530 0x1f40 0xbb8>; | |
| qcom,mdss-dsi-panel-peak-brightness = <0x401640>; | |
| qcom,mdss-dsi-panel-blackness-level = <0xc9e>; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ba 03 15 01 00 00 00 00 02 e5 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 bb 03 15 01 00 00 00 00 02 b0 03 39 01 00 00 00 00 06 3b 03 08 08 64 9a 15 01 00 00 00 00 02 ff e0 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 6b 3d 15 01 00 00 00 00 02 6c 3d 15 01 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3d 15 01 00 00 00 00 02 6f 3d 15 01 00 00 00 00 02 35 02 15 01 00 00 00 00 02 36 72 15 01 00 00 00 00 02 37 10 15 01 00 00 00 00 02 08 c0 15 01 00 00 00 00 02 ff 10 05 01 00 00 78 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe2362400 0x666a2838 0x2a030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x35>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,config-select = <0x26d>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x23180708 0x40304a0>; | |
| linux,phandle = <0x3ae>; | |
| phandle = <0x3ae>; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| linux,phandle = <0x26d>; | |
| phandle = <0x26d>; | |
| }; | |
| config1 { | |
| qcom,split-mode = "pingpong-split"; | |
| linux,phandle = <0x3af>; | |
| phandle = <0x3af>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35597_wqxga_cmd { | |
| qcom,mdss-dsi-panel-name = "Dual nt35597 cmd mode dsi panel without DSC"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x2d0>; | |
| qcom,mdss-dsi-panel-height = <0xa00>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x20>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x7>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xcd322200 0x60642634 0x29030400>; | |
| qcom,adjust-timer-wakeup-ms = <0x1>; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-pan-physical-width-dimension = <0x4a>; | |
| qcom,mdss-pan-physical-height-dimension = <0x83>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x100002ff 0x10150100 0x100002 0xfb011501 0x1000 0x2ba0315 0x1000010 0x2e501 0x15010000 0x10000235 0x150100 0x100002 0xbb101501 0x1000 0x2b00315 0x1000010 0x2ffe0 0x15010000 0x100002fb 0x1150100 0x100002 0x6b3d1501 0x1000 0x26c3d15 0x1000010 0x26d3d 0x15010000 0x1000026e 0x3d150100 0x100002 0x6f3d1501 0x1000 0x2350215 0x1000010 0x23672 0x15010000 0x10000237 0x10150100 0x100002 0x8c01501 0x1000 0x2ff2415 0x1000010 0x2fb01 0x15010000 0x100002c6 0x6150100 0x100002 0xff100501 0xa000 0x2110005 0x10000a0 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00 05 01 00 00 3c 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,config-select = <0x26e>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x231e0708 0x50304a0 0x23180708 0x40304a0>; | |
| linux,phandle = <0x3b0>; | |
| phandle = <0x3b0>; | |
| config0 { | |
| qcom,split-mode = "dualctl-split"; | |
| linux,phandle = <0x26e>; | |
| phandle = <0x26e>; | |
| }; | |
| config1 { | |
| qcom,split-mode = "pingpong-split"; | |
| linux,phandle = <0x3b1>; | |
| phandle = <0x3b1>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_nt35695b_truly_fhd_video { | |
| qcom,mdss-dsi-panel-name = "nt35695b truly fhd video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0xc>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x2>; | |
| qcom,mdss-dsi-v-front-porch = <0xc>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2f>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 03 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241e0809 0x50304a0 0x241e0809 0x50304a0 0x241e0809 0x50304a0 0x241e0809 0x50304a0 0x241a0809 0x50304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3b2>; | |
| phandle = <0x3b2>; | |
| }; | |
| qcom,mdss_dsi_nt35695b_truly_fhd_cmd { | |
| qcom,mdss-dsi-panel-name = "nt35695b truly fhd command mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0xc>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x2>; | |
| qcom,mdss-dsi-v-front-porch = <0xc>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2f>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 55 15 01 00 00 00 00 02 02 45 15 01 00 00 00 00 02 03 55 15 01 00 00 00 00 02 05 50 15 01 00 00 00 00 02 06 a8 15 01 00 00 00 00 02 07 ad 15 01 00 00 00 00 02 08 0c 15 01 00 00 00 00 02 0b aa 15 01 00 00 00 00 02 0c aa 15 01 00 00 00 00 02 0e b0 15 01 00 00 00 00 02 0f b3 15 01 00 00 00 00 02 11 28 15 01 00 00 00 00 02 12 10 15 01 00 00 00 00 02 13 01 15 01 00 00 00 00 02 14 4a 15 01 00 00 00 00 02 15 12 15 01 00 00 00 00 02 16 12 15 01 00 00 00 00 02 30 01 15 01 00 00 00 00 02 72 11 15 01 00 00 00 00 02 58 82 15 01 00 00 00 00 02 59 00 15 01 00 00 00 00 02 5a 02 15 01 00 00 00 00 02 5b 00 15 01 00 00 00 00 02 5c 82 15 01 00 00 00 00 02 5d 80 15 01 00 00 00 00 02 5e 02 15 01 00 00 00 00 02 5f 00 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 00 01 15 01 00 00 00 00 02 01 0b 15 01 00 00 00 00 02 02 0c 15 01 00 00 00 00 02 03 89 15 01 00 00 00 00 02 04 8a 15 01 00 00 00 00 02 05 0f 15 01 00 00 00 00 02 06 10 15 01 00 00 00 00 02 07 10 15 01 00 00 00 00 02 08 1c 15 01 00 00 00 00 02 09 00 15 01 00 00 00 00 02 0a 00 15 01 00 00 00 00 02 0b 00 15 01 00 00 00 00 02 0c 00 15 01 00 00 00 00 02 0d 13 15 01 00 00 00 00 02 0e 15 15 01 00 00 00 00 02 0f 17 15 01 00 00 00 00 02 10 01 15 01 00 00 00 00 02 11 0b 15 01 00 00 00 00 02 12 0c 15 01 00 00 00 00 02 13 89 15 01 00 00 00 00 02 14 8a 15 01 00 00 00 00 02 15 0f 15 01 00 00 00 00 02 16 10 15 01 00 00 00 00 02 17 10 15 01 00 00 00 00 02 18 1c 15 01 00 00 00 00 02 19 00 15 01 00 00 00 00 02 1a 00 15 01 00 00 00 00 02 1b 00 15 01 00 00 00 00 02 1c 00 15 01 00 00 00 00 02 1d 13 15 01 00 00 00 00 02 1e 15 15 01 00 00 00 00 02 1f 17 15 01 00 00 00 00 02 20 00 15 01 00 00 00 00 02 21 01 15 01 00 00 00 00 02 22 00 15 01 00 00 00 00 02 23 40 15 01 00 00 00 00 02 24 40 15 01 00 00 00 00 02 25 6d 15 01 00 00 00 00 02 26 40 15 01 00 00 00 00 02 27 40 15 01 00 00 00 00 02 29 d8 15 01 00 00 00 00 02 2a 2a 15 01 00 00 00 00 02 4b 03 15 01 00 00 00 00 02 4c 11 15 01 00 00 00 00 02 4d 10 15 01 00 00 00 00 02 4e 01 15 01 00 00 00 00 02 4f 01 15 01 00 00 00 00 02 50 10 15 01 00 00 00 00 02 51 00 15 01 00 00 00 00 02 52 80 15 01 00 00 00 00 02 53 00 15 01 00 00 00 00 02 54 07 15 01 00 00 00 00 02 55 25 15 01 00 00 00 00 02 56 00 15 01 00 00 00 00 02 58 07 15 01 00 00 00 00 02 5b 43 15 01 00 00 00 00 02 5c 00 15 01 00 00 00 00 02 5f 73 15 01 00 00 00 00 02 60 73 15 01 00 00 00 00 02 63 22 15 01 00 00 00 00 02 64 00 15 01 00 00 00 00 02 67 08 15 01 00 00 00 00 02 68 04 15 01 00 00 00 00 02 7a 80 15 01 00 00 00 00 02 7b 91 15 01 00 00 00 00 02 7c d8 15 01 00 00 00 00 02 7d 60 15 01 00 00 00 00 02 93 06 15 01 00 00 00 00 02 94 06 15 01 00 00 00 00 02 8a 00 15 01 00 00 00 00 02 9b 0f 15 01 00 00 00 00 02 b3 c0 15 01 00 00 00 00 02 b4 00 15 01 00 00 00 00 02 b5 00 15 01 00 00 00 00 02 b6 21 15 01 00 00 00 00 02 b7 22 15 01 00 00 00 00 02 b8 07 15 01 00 00 00 00 02 b9 07 15 01 00 00 00 00 02 ba 22 15 01 00 00 00 00 02 bd 20 15 01 00 00 00 00 02 be 07 15 01 00 00 00 00 02 bf 07 15 01 00 00 00 00 02 c1 6d 15 01 00 00 00 00 02 c4 24 15 01 00 00 00 00 02 e3 00 15 01 00 00 00 00 02 ec 00 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 bb 10 15 01 00 00 00 00 02 35 02 05 01 00 00 78 00 02 11 00 05 01 00 00 78 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241e0809 0x50304a0 0x241e0809 0x50304a0 0x241e0809 0x50304a0 0x241e0809 0x50304a0 0x241a0809 0x50304a0>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3b3>; | |
| phandle = <0x3b3>; | |
| }; | |
| qcom,mdss_dsi_truly_1080p_cmd { | |
| qcom,mdss-dsi-panel-name = "truly 1080p cmd mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x10>; | |
| qcom,mdss-dsi-v-front-porch = <0x4>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| qcom,mdss-dsi-t-clk-post = <0x2>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 d6 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 23 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 07 b3 04 00 00 00 00 00 29 01 00 00 00 00 03 b6 3a d3 29 01 00 00 00 00 03 c0 00 00 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01 22 22 00 01 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06 00 00 00 00 00 04 00 00 00 0c 06 29 01 00 00 00 00 29 c6 78 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 00 78 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0 23 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00 a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,ulps-enabled; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231a0809 0x50304a0>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x1c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| linux,phandle = <0x3b4>; | |
| phandle = <0x3b4>; | |
| }; | |
| qcom,mdss_dsi_truly_1080p_video { | |
| qcom,mdss-dsi-panel-name = "truly 1080p video mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-h-back-porch = <0x40>; | |
| qcom,mdss-dsi-h-pulse-width = <0x10>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x10>; | |
| qcom,mdss-dsi-v-front-porch = <0x4>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| qcom,mdss-dsi-t-clk-post = <0x2>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 78 00 02 11 00 23 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 07 b3 14 00 00 00 00 00 29 01 00 00 00 00 03 b6 3a d3 29 01 00 00 00 00 03 c0 00 00 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01 22 22 00 01 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06 00 00 00 00 00 04 00 00 00 0c 06 29 01 00 00 00 00 29 c6 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 00 01 00 69 00 69 00 69 00 00 00 00 00 69 00 69 00 69 10 19 07 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0 23 01 00 00 00 00 02 cc 0b 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00 a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00 00 fc 00 00 00 00 00 fc 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231e0809 0x50304a0 0x231a0809 0x50304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x1c>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| linux,phandle = <0x3b5>; | |
| phandle = <0x3b5>; | |
| }; | |
| qcom,mdss_dsi_rm67195_amoled_fhd_cmd { | |
| qcom,mdss-dsi-panel-name = "rm67195 amoled fhd cmd mode dsi panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x780>; | |
| qcom,mdss-dsi-h-front-porch = <0x78>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0xc>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0xc>; | |
| qcom,mdss-dsi-v-front-porch = <0x8>; | |
| qcom,mdss-dsi-v-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2fe 0xd150100 0x2 0xbc01501 0x0 0x2420015 0x1000000 0x21808 0x15010000 0x208 0x41150100 0x2 0x46021501 0x0 0x21e0415 0x1000002 0x21e00 0x15010000 0x2fe 0xa150100 0x2 0x24171501 0x0 0x2040715 0x1000000 0x21a0c 0x15010000 0x200020f 0x44150100 0x2 0xfe0b1501 0x0 0x2284015 0x1000002 0x2294f 0x15010000 0x2fe 0x4150100 0x2 0xad81501 0x0 0x20ce615 0x1000000 0x24e20 0x15010000 0x24f 0x1b150100 0x2 0x502f1501 0x200 0x2510815 0x1000000 0x2fe09 0x15010000 0x200 0x8150100 0x2 0x1081501 0x0 0x2020015 0x1000000 0x20300 0x15010000 0x204 0x10150100 0x2 0x5001501 0x0 0x2060815 0x1000000 0x20708 0x15010000 0x208 0x150100 0x2 0x12241501 0x0 0x2134915 0x1000000 0x21492 0x15010000 0x215 0x49150100 0x2 0x16921501 0x0 0x2172415 0x1000000 0x21824 0x15010000 0x219 0x49150100 0x2 0x1a921501 0x0 0x21b4915 0x1000000 0x21c92 0x15010000 0x21d 0x24150100 0x2 0x1e241501 0x0 0x21f4915 0x1000000 0x22092 0x15010000 0x221 0x49150100 0x2 0x22921501 0x0 0x2232415 0x1000000 0x29b07 0x15010000 0x200029c 0xa5150100 0x2 0xfe001501 0x0 0x2c20815 0x1000002 0x23500 0x39010000 0x344 0x3e80501 0x8200 0x2110005 0x1000014 0x22900>; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 82 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x2f>; | |
| qcom,mdss-dsi-wr-mem-start = <0x2c>; | |
| qcom,mdss-dsi-wr-mem-continue = <0x3c>; | |
| qcom,mdss-dsi-te-pin-select = <0x1>; | |
| qcom,mdss-dsi-te-dcs-command = <0x1>; | |
| qcom,mdss-dsi-te-check-enable; | |
| qcom,mdss-dsi-te-using-te-pin; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xff>; | |
| qcom,mdss-pan-physical-width-dimension = <0x46>; | |
| qcom,mdss-pan-physical-height-dimension = <0x7d>; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x14 0x0 0x14 0x1 0x14>; | |
| qcom,mdss-dsi-panel-orientation = "180"; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241a0809 0x50304a0>; | |
| qcom,panel-supply-entries = <0x26f>; | |
| linux,phandle = <0x3b6>; | |
| phandle = <0x3b6>; | |
| }; | |
| qcom,mdss_dsi_lgd_incell_sw49106_fhd_video { | |
| qcom,mdss-dsi-panel-name = "lgd incell sw49106 fhd video"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsi-h-front-porch = <0x8>; | |
| qcom,mdss-dsi-h-back-porch = <0x8>; | |
| qcom,mdss-dsi-h-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x5c>; | |
| qcom,mdss-dsi-v-front-porch = <0xaa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x1>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xf83c2800 0x6e722e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x30>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [05 01 00 00 0b 00 02 35 00 15 01 00 00 00 00 02 36 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 24 15 01 00 00 00 00 02 55 80 39 01 00 00 00 00 02 b0 ac 39 01 00 00 00 00 06 b1 46 00 80 14 85 39 01 00 00 00 00 08 b3 05 08 14 00 1c 00 02 39 01 00 00 00 00 10 b4 83 08 00 04 04 04 04 00 00 00 00 00 00 00 00 39 01 00 00 00 00 13 b5 03 1e 0b 02 29 00 00 00 00 04 00 24 00 10 10 10 10 00 39 01 00 00 00 00 0a b6 00 72 39 13 08 67 00 60 46 39 01 00 00 00 00 05 b7 00 50 37 04 39 01 00 00 00 00 0c b8 70 38 14 ed 08 04 00 01 0a a0 00 39 01 00 00 00 00 06 c0 8a 8f 18 c1 12 39 01 00 00 00 00 07 c1 01 00 30 c2 c7 0f 39 01 00 00 00 00 03 c2 2a 00 39 01 00 00 00 00 07 c3 05 0e 0e 50 88 09 39 01 00 00 00 00 04 c4 a2 e8 f4 39 01 00 00 00 00 05 c5 c2 2a 4e 08 39 01 00 00 00 00 03 c6 15 01 39 01 00 00 00 00 07 ca 00 00 03 84 55 f5 39 01 00 00 00 00 03 cb 3f a0 39 01 00 00 00 00 09 cc f0 03 10 55 11 fc 34 34 39 01 00 00 00 00 07 cd 11 50 50 90 00 f3 39 01 00 00 00 00 07 ce a0 28 28 34 00 ab 39 01 00 00 00 00 10 d0 10 1b 22 2a 35 42 4a 53 4d 44 34 23 10 03 81 39 01 00 00 00 00 10 d1 09 15 1c 25 31 3f 47 52 4f 45 34 22 0e 01 83 39 01 00 00 00 00 10 d2 10 1b 22 29 34 41 49 52 4e 44 34 23 10 03 81 39 01 00 00 00 00 10 d3 09 15 1c 24 30 3e 46 51 50 45 34 22 0e 01 83 39 01 00 00 00 00 10 d4 10 1b 22 2a 35 42 4a 53 4d 44 34 23 10 03 81 39 01 00 00 00 00 10 d5 09 15 1c 25 31 3f 47 52 4f 45 34 22 0e 01 83 39 01 00 00 00 00 0d e5 24 23 11 10 00 0a 08 06 04 11 0e 23 39 01 00 00 00 00 0d e6 24 23 11 10 01 0b 09 07 05 11 0e 23 39 01 00 00 00 00 07 e7 15 16 17 18 19 1a 39 01 00 00 00 00 07 e8 1b 1c 1d 1e 1f 20 39 01 00 00 00 00 05 ed 00 01 53 0c 39 01 00 00 00 00 03 f0 b2 00 39 01 00 00 00 00 05 f2 01 00 17 00 39 01 00 00 64 00 07 f3 00 50 90 c9 00 01 05 01 00 00 78 00 02 11 00 05 01 00 00 05 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 64 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xc8 0x0 0xc8 0x1 0xc8>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241b0809 0x50304a0>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3b7>; | |
| phandle = <0x3b7>; | |
| }; | |
| qcom,mdss_dsi_hx8399_truly_fhd_video { | |
| qcom,mdss-dsi-panel-name = "hx8399c video mode dsi truly panel"; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-dsi-h-front-porch = <0x2a>; | |
| qcom,mdss-dsi-h-back-porch = <0x2a>; | |
| qcom,mdss-dsi-h-pulse-width = <0xa>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0xf>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x3>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-pan-physical-width-dimension = <0x41>; | |
| qcom,mdss-pan-physical-height-dimension = <0x81>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-color-order = "rgb_swap_rgb"; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 b9 ff 83 99 39 01 00 00 00 00 02 d2 88 39 01 00 00 00 00 0c b1 02 04 72 92 01 32 aa 11 11 52 57 39 01 00 00 00 00 10 b2 00 80 80 cc 05 07 5a 11 10 10 00 1e 70 03 d4 39 01 00 00 00 00 2d b4 00 ff 59 59 01 ab 00 00 09 00 03 05 00 28 03 0b 0d 21 03 02 00 0c a3 80 59 59 02 ab 00 00 09 00 03 05 00 28 03 0b 0d 02 00 0c a3 01 39 01 00 00 05 00 22 d3 00 0c 03 03 00 00 10 10 00 00 03 00 03 00 08 78 08 78 00 00 00 00 00 24 02 05 05 03 00 00 00 05 40 39 01 00 00 05 00 21 d5 20 20 19 19 18 18 02 03 00 01 24 24 18 18 18 18 24 24 00 00 00 00 00 00 00 00 2f 2f 30 30 31 31 39 01 00 00 05 00 21 d6 24 24 18 18 19 19 01 00 03 02 24 24 18 18 18 18 20 20 40 40 40 40 40 40 40 40 2f 2f 30 30 31 31 39 01 00 00 00 00 02 bd 00 39 01 00 00 00 00 11 d8 aa aa aa aa aa aa aa aa aa ba aa aa aa ba aa aa 39 01 00 00 00 00 02 bd 01 39 01 00 00 00 00 11 d8 00 00 00 00 00 00 00 00 82 ea aa aa 82 ea aa aa 39 01 00 00 00 00 02 bd 02 39 01 00 00 00 00 09 d8 ff ff c0 3f ff ff c0 3f 39 01 00 00 00 00 02 bd 00 39 01 00 00 05 00 37 e0 01 21 31 2d 66 6f 7b 75 7a 81 86 89 8c 90 95 97 9a a1 a2 aa 9e ad b0 5b 57 63 7a 01 21 31 2d 66 6f 7b 75 7a 81 86 89 8c 90 95 97 9a a1 a2 aa 9e ad b0 5b 57 63 7a 39 01 00 00 00 00 03 b6 7e 7e 39 01 00 00 00 00 02 cc 08 05 01 00 00 96 00 02 11 00 05 01 00 00 32 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00 05 01 00 00 96 00 02 10 00]; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; | |
| qcom,mdss-dsi-lane-map = "lane_map_0123"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-t-clk-post = <0xe>; | |
| qcom,mdss-dsi-t-clk-pre = <0x31>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-lp11-init; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0xa 0x0 0xa 0x1 0xa>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241f0809 0x50304a0 0x241c0809 0x50304a0>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x10a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; | |
| qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; | |
| qcom,mdss-dsi-panel-status-read-length = <0x4>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,mdss-dsi-pan-enable-dynamic-fps; | |
| qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; | |
| linux,phandle = <0x3b8>; | |
| phandle = <0x3b8>; | |
| }; | |
| qcom,mdss_dsi_nt36672_tianma_fhd_video { | |
| qcom,mdss-dsi-panel-name = "tianma nt36672 fhd video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-pan-physical-height-dimension = <0x88>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-h-back-porch = <0x38>; | |
| qcom,mdss-dsi-h-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x21>; | |
| qcom,mdss-dsi-v-front-porch = <0x4>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x32>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 30 10 15 01 00 00 00 00 02 31 50 15 01 00 00 00 00 02 32 2f 15 01 00 00 00 00 02 ff 10 05 01 00 00 46 00 02 11 00 15 01 00 00 00 00 02 51 ff 39 01 00 00 00 00 03 68 03 04 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 05 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command; | |
| qcom,mdss-dsi-ce-off-command; | |
| qcom,mdss-dsi-srgb-on-command; | |
| qcom,mdss-dsi-srgb-off-command; | |
| qcom,mdss-dsi-cabc-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 07 20 15 00 00 00 00 00 02 08 05 15 00 00 00 00 00 02 09 00 15 00 00 00 00 00 02 10 95 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 ff 15 00 00 00 00 00 02 32 ff 15 00 00 00 00 00 02 33 ff 15 00 00 00 00 00 02 34 ff 15 01 00 00 00 00 02 35 ff 15 00 00 00 00 00 02 36 ff 15 00 00 00 00 00 02 37 ff 15 00 00 00 00 00 02 38 ff 15 00 00 00 00 00 02 39 ff 15 00 00 00 00 00 02 3a ff 15 00 00 00 00 00 02 3b f9 15 00 00 00 00 00 02 3d d9 15 00 00 00 00 00 02 3f b9 15 00 00 00 00 00 02 40 ab 15 00 00 00 00 00 02 41 98 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 01]; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0xf>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x251f090a 0x60304a0 0x251f090a 0x60304a0 0x251f090a 0x60304a0 0x251f090a 0x60304a0 0x251e080a 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3b9>; | |
| phandle = <0x3b9>; | |
| }; | |
| qcom,mdss_dsi_nt36672_jdi_fhd_video { | |
| qcom,mdss-dsi-panel-name = "jdi nt36672 fhd video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x870>; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-pan-physical-height-dimension = <0x88>; | |
| qcom,mdss-dsi-h-front-porch = <0x60>; | |
| qcom,mdss-dsi-h-back-porch = <0x38>; | |
| qcom,mdss-dsi-h-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x21>; | |
| qcom,mdss-dsi-v-front-porch = <0x4>; | |
| qcom,mdss-dsi-v-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xe6382600 0x686e2a3c 0x44030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xd>; | |
| qcom,mdss-dsi-t-clk-pre = <0x32>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 30 10 15 01 00 00 00 00 02 31 50 15 01 00 00 00 00 02 32 2f 15 01 00 00 00 00 02 ff 10 05 01 00 00 46 00 02 11 00 15 01 00 00 00 00 02 51 ff 39 01 00 00 00 00 03 68 03 04 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 05 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 05 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command; | |
| qcom,mdss-dsi-ce-off-command; | |
| qcom,mdss-dsi-srgb-on-command; | |
| qcom,mdss-dsi-srgb-off-command; | |
| qcom,mdss-dsi-cabc-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 07 20 15 00 00 00 00 00 02 08 05 15 00 00 00 00 00 02 09 00 15 00 00 00 00 00 02 10 95 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 ff 15 00 00 00 00 00 02 32 ff 15 00 00 00 00 00 02 33 ff 15 00 00 00 00 00 02 34 ff 15 01 00 00 00 00 02 35 ff 15 00 00 00 00 00 02 36 ff 15 00 00 00 00 00 02 37 ff 15 00 00 00 00 00 02 38 ff 15 00 00 00 00 00 02 39 ff 15 00 00 00 00 00 02 3a ff 15 00 00 00 00 00 02 3b f9 15 00 00 00 00 00 02 3d d9 15 00 00 00 00 00 02 3f b9 15 00 00 00 00 00 02 40 ab 15 00 00 00 00 00 02 41 98 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 01]; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0xf>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x251f090a 0x60304a0 0x251f090a 0x60304a0 0x251f090a 0x60304a0 0x251f090a 0x60304a0 0x251e080a 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3ba>; | |
| phandle = <0x3ba>; | |
| }; | |
| qcom,mdss_dsi_nt36672a_tianma_fhdplus_video { | |
| qcom,mdss-dsi-panel-name = "tianma nt36672a fhdplus video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-pan-physical-width-dimension = <0x43>; | |
| qcom,mdss-pan-physical-height-dimension = <0x91>; | |
| qcom,mdss-dsi-h-front-porch = <0x5a>; | |
| qcom,mdss-dsi-h-back-porch = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x8>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x3>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xfe3c2a00 0x70742e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xe>; | |
| qcom,mdss-dsi-t-clk-pre = <0x37>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 25 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 18 96 15 01 00 00 00 00 02 05 04 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 78 01 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 82 13 15 01 00 00 00 00 02 84 31 15 01 00 00 00 00 02 88 13 15 01 00 00 00 00 02 8a 31 15 01 00 00 00 00 02 8e e4 15 01 00 00 00 00 02 8f 01 15 01 00 00 00 00 02 90 80 15 01 00 00 00 00 02 ff 26 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 a9 12 15 01 00 00 00 00 02 aa 10 15 01 00 00 00 00 02 ae 8a 15 01 00 00 00 00 02 ff 10 15 01 00 00 50 00 02 11 00 15 01 00 00 00 00 02 b0 01 15 01 00 00 00 00 02 35 00 39 01 00 00 00 00 03 68 03 04 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 15 01 00 00 00 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 14 00 02 28 00 15 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command; | |
| qcom,mdss-dsi-ce-off-command; | |
| qcom,mdss-dsi-srgb-on-command = [15 01 00 00 00 00 02 ff 22 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 36 15 00 00 00 00 00 02 01 35 15 00 00 00 00 00 02 02 34 15 00 00 00 00 00 02 03 33 15 00 00 00 00 00 02 04 31 15 00 00 00 00 00 02 05 31 15 00 00 00 00 00 02 06 30 15 00 00 00 00 00 02 07 2f 15 00 00 00 00 00 02 08 2e 15 00 00 00 00 00 02 09 2d 15 00 00 00 00 00 02 0a 2c 15 00 00 00 00 00 02 0b 2b 15 00 00 00 00 00 02 0c 29 15 00 00 00 00 00 02 0d 26 15 00 00 00 00 00 02 0e 23 15 00 00 00 00 00 02 0f 20 15 00 00 00 00 00 02 10 1d 15 00 00 00 00 00 02 11 50 15 00 00 00 00 00 02 12 60 15 01 00 00 00 00 02 13 70 15 00 00 00 00 00 02 14 58 15 00 00 00 00 00 02 15 68 15 00 00 00 00 00 02 16 78 15 00 00 00 00 00 02 17 77 15 00 00 00 00 00 02 18 40 15 00 00 00 00 00 02 19 40 15 00 00 00 00 00 02 1a 40 15 00 00 00 00 00 02 1b 40 15 00 00 00 00 00 02 1c 40 15 00 00 00 00 00 02 1d 40 15 00 00 00 00 00 02 1e 40 15 00 00 00 00 00 02 1f 40 15 00 00 00 00 00 02 20 40 15 00 00 00 00 00 02 21 45 15 00 00 00 00 00 02 22 49 15 00 00 00 00 00 02 23 4c 15 00 00 00 00 00 02 24 4b 15 00 00 00 00 00 02 25 48 15 00 00 00 00 00 02 26 44 15 00 00 00 00 00 02 27 41 15 01 00 00 00 00 02 28 40 15 00 00 00 00 00 02 2d 00 15 00 00 00 00 00 02 2f 37 15 00 00 00 00 00 02 30 37 15 00 00 00 00 00 02 31 37 15 00 00 00 00 00 02 32 37 15 00 00 00 00 00 02 33 37 15 00 00 00 00 00 02 34 37 15 00 00 00 00 00 02 35 37 15 00 00 00 00 00 02 36 37 15 00 00 00 00 00 02 37 37 15 00 00 00 00 00 02 38 38 15 00 00 00 00 00 02 39 38 15 00 00 00 00 00 02 3a 38 15 00 00 00 00 00 02 3b 37 15 00 00 00 00 00 02 3d 37 15 00 00 00 00 00 02 3f 37 15 00 00 00 00 00 02 40 36 15 00 00 00 00 00 02 41 34 15 00 00 00 00 00 02 42 40 15 00 00 00 00 00 02 43 40 15 01 00 00 00 00 02 44 40 15 00 00 00 00 00 02 45 40 15 00 00 00 00 00 02 46 40 15 00 00 00 00 00 02 47 40 15 00 00 00 00 00 02 48 40 15 00 00 00 00 00 02 49 40 15 00 00 00 00 00 02 4a 40 15 00 00 00 00 00 02 4b 3f 15 00 00 00 00 00 02 4c 3e 15 00 00 00 00 00 02 4d 3d 15 00 00 00 00 00 02 4e 3c 15 00 00 00 00 00 02 4f 3c 15 00 00 00 00 00 02 50 3b 15 00 00 00 00 00 02 51 3a 15 00 00 00 00 00 02 52 39 15 00 00 00 00 00 02 53 01 15 00 00 00 00 00 02 54 00 15 00 00 00 00 00 02 55 fe 15 00 00 00 00 00 02 56 77 15 00 00 00 00 00 02 58 3f 15 00 00 00 00 00 02 59 3e 15 01 00 00 00 00 02 5a 3e 15 00 00 00 00 00 02 5b 3d 15 00 00 00 00 00 02 5c 3d 15 00 00 00 00 00 02 5d 3d 15 00 00 00 00 00 02 5e 3d 15 00 00 00 00 00 02 5f 3c 15 00 00 00 00 00 02 60 bc 15 00 00 00 00 00 02 61 3c 15 00 00 00 00 00 02 62 3c 15 00 00 00 00 00 02 63 3c 15 00 00 00 00 00 02 64 3c 15 00 00 00 00 00 02 65 3c 15 00 00 00 00 00 02 66 bd 15 00 00 00 00 00 02 67 bd 15 00 00 00 00 00 02 68 3d 15 00 00 00 00 00 02 69 bd 15 00 00 00 00 00 02 6a 3c 15 00 00 00 00 00 02 6b 3c 15 00 00 00 00 00 02 6c 3d 15 00 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3c 15 00 00 00 00 00 02 6f 3d 15 00 00 00 00 00 02 70 00 15 00 00 00 00 00 02 71 c0 15 00 00 00 00 00 02 72 03 15 00 00 00 00 00 02 73 00 15 00 00 00 00 00 02 74 06 15 00 00 00 00 00 02 75 0c 15 00 00 00 00 00 02 76 03 15 00 00 00 00 00 02 77 09 15 00 00 00 00 00 02 78 0f 15 00 00 00 00 00 02 79 68 15 00 00 00 00 00 02 7a 88 15 00 00 00 00 00 02 7c 80 15 00 00 00 00 00 02 7d 80 15 00 00 00 00 00 02 7e 80 15 00 00 00 00 00 02 7f 80 15 00 00 00 00 00 02 80 c2 15 00 00 00 00 00 02 81 02 15 00 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 00 15 00 00 00 00 00 02 85 85 15 00 00 00 00 00 02 86 80 15 00 00 00 00 00 02 87 80 15 00 00 00 00 00 02 88 40 15 00 00 00 00 00 02 89 74 15 00 00 00 00 00 02 8a 77 15 00 00 00 00 00 02 8b 7a 15 00 00 00 00 00 02 8c 7e 15 00 00 00 00 00 02 8d 7f 15 00 00 00 00 00 02 8e 7e 15 00 00 00 00 00 02 8f 79 15 00 00 00 00 00 02 90 73 15 00 00 00 00 00 02 91 65 15 00 00 00 00 00 02 92 6d 15 00 00 00 00 00 02 93 74 15 00 00 00 00 00 02 94 7d 15 00 00 00 00 00 02 95 80 15 00 00 00 00 00 02 96 80 15 00 00 00 00 00 02 97 81 15 00 00 00 00 00 02 98 82 15 01 00 00 00 00 02 99 82 15 00 00 00 00 00 02 9a 82 15 00 00 00 00 00 02 9b 81 15 00 00 00 00 00 02 9c 81 15 00 00 00 00 00 02 9d 80 15 00 00 00 00 00 02 9e 7f 15 00 00 00 00 00 02 9f 7b 15 00 00 00 00 00 02 a0 78 15 00 00 00 00 00 02 a2 80 15 00 00 00 00 00 02 a6 80 15 00 00 00 00 00 02 a7 80 15 00 00 00 00 00 02 a9 80 15 00 00 00 00 00 02 aa 80 15 00 00 00 00 00 02 ab 80 15 00 00 00 00 00 02 ac 80 15 00 00 00 00 00 02 ad 80 15 00 00 00 00 00 02 ae 80 15 00 00 00 00 00 02 af 80 15 00 00 00 00 00 02 b7 76 15 00 00 00 00 00 02 b8 76 15 00 00 00 00 00 02 b9 05 15 01 00 00 00 00 02 ba 0d 15 00 00 00 00 00 02 bb 14 15 00 00 00 00 00 02 bc 0f 15 00 00 00 00 00 02 bd 18 15 00 00 00 00 00 02 be 1f 15 00 00 00 00 00 02 bf 05 15 00 00 00 00 00 02 c0 0d 15 00 00 00 00 00 02 c1 14 15 00 00 00 00 00 02 c2 03 15 00 00 00 00 00 02 c3 07 15 00 00 00 00 00 02 c4 0a 15 00 00 00 00 00 02 c5 a0 15 00 00 00 00 00 02 c6 55 15 00 00 00 00 00 02 c7 ff 15 00 00 00 00 00 02 c8 39 15 00 00 00 00 00 02 c9 44 15 00 00 00 00 00 02 ca 12 15 00 00 00 00 00 02 cd 80 15 00 00 00 00 00 02 db 80 15 00 00 00 00 00 02 dc 80 15 00 00 00 00 00 02 dd 80 15 01 00 00 00 00 02 e0 80 15 00 00 00 00 00 02 e1 80 15 00 00 00 00 00 02 e2 80 15 00 00 00 00 00 02 e3 80 15 00 00 00 00 00 02 e4 80 15 00 00 00 00 00 02 e5 40 15 00 00 00 00 00 02 e6 40 15 00 00 00 00 00 02 e7 40 15 00 00 00 00 00 02 e8 40 15 00 00 00 00 00 02 e9 40 15 00 00 00 00 00 02 ea 40 15 00 00 00 00 00 02 eb 40 15 00 00 00 00 00 02 ec 40 15 00 00 00 00 00 02 ed 40 15 00 00 00 00 00 02 ee 40 15 00 00 00 00 00 02 ef 40 15 00 00 00 00 00 02 f0 40 15 00 00 00 00 00 02 f1 40 15 00 00 00 00 00 02 f2 40 15 00 00 00 00 00 02 f3 40 15 01 00 00 00 00 02 f4 40 15 00 00 00 00 00 02 f5 40 15 00 00 00 00 00 02 f6 40 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 55 80]; | |
| qcom,mdss-dsi-srgb-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-cabc-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 05 2d 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 8a 15 01 00 00 00 00 02 15 6a 15 00 00 00 00 00 02 16 0b 15 00 00 00 00 00 02 29 80 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 ff 15 00 00 00 00 00 02 32 ff 15 00 00 00 00 00 02 33 ff 15 00 00 00 00 00 02 34 ff 15 00 00 00 00 00 02 35 ff 15 00 00 00 00 00 02 36 ff 15 01 00 00 00 00 02 37 ff 15 01 00 00 00 00 02 38 ff 15 01 00 00 00 00 02 39 ff 15 00 00 00 00 00 02 3a ff 15 00 00 00 00 00 02 3b fa 15 00 00 00 00 00 02 3d f5 15 00 00 00 00 00 02 3f f0 15 00 00 00 00 00 02 40 e8 15 00 00 00 00 00 02 41 e3 15 00 00 00 00 00 02 ff 10 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 55 01]; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0xf>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x26200a0b 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3bb>; | |
| phandle = <0x3bb>; | |
| }; | |
| qcom,mdss_dsi_nt36672a_shenchao_fhdplus_video { | |
| qcom,mdss-dsi-panel-name = "shenchao nt36672a fhdplus video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-pan-physical-width-dimension = <0x43>; | |
| qcom,mdss-pan-physical-height-dimension = <0x91>; | |
| qcom,mdss-dsi-h-front-porch = <0x5a>; | |
| qcom,mdss-dsi-h-back-porch = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x8>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x3>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xfe3c2a00 0x70742e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xe>; | |
| qcom,mdss-dsi-t-clk-pre = <0x37>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x25150100 0x2 0xfb011501 0x0 0x2189615 0x1000000 0x20504 0x15010000 0x2ff 0x27150100 0x2 0xfb011501 0x0 0x2d91015 0x1000000 0x2ff24 0x15010000 0x2fb 0x1150100 0x2 0x82131501 0x0 0x2843115 0x1000000 0x28813 0x15010000 0x28a 0x31150100 0x2 0x8ee41501 0x0 0x28f0115 0x1000000 0x29080 0x15010000 0x29d 0xb0150100 0x2 0xff261501 0x0 0x2fb0115 0x1000000 0x2a912 0x15010000 0x2aa 0x10150100 0x2 0xae8a1501 0x0 0x21cfa15 0x1000000 0x2ff10 0x15010000 0x2b0 0x1050100 0x460002 0x11001501 0x0 0x251ff39 0x1000000 0x36803 0x4150100 0x2 0x532c1501 0x0 0x2550005 0x1000000 0x22900>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 14 00 02 28 00 15 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command; | |
| qcom,mdss-dsi-ce-off-command; | |
| qcom,mdss-dsi-srgb-on-command = [15 01 00 00 00 00 02 ff 22 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 00 36 15 00 00 00 00 00 02 01 35 15 00 00 00 00 00 02 02 34 15 00 00 00 00 00 02 03 33 15 00 00 00 00 00 02 04 31 15 00 00 00 00 00 02 05 31 15 00 00 00 00 00 02 06 30 15 00 00 00 00 00 02 07 2f 15 00 00 00 00 00 02 08 2e 15 00 00 00 00 00 02 09 2d 15 00 00 00 00 00 02 0a 2c 15 00 00 00 00 00 02 0b 2b 15 00 00 00 00 00 02 0c 29 15 00 00 00 00 00 02 0d 26 15 00 00 00 00 00 02 0e 23 15 00 00 00 00 00 02 0f 20 15 00 00 00 00 00 02 10 1d 15 00 00 00 00 00 02 11 50 15 00 00 00 00 00 02 12 60 15 01 00 00 00 00 02 13 70 15 00 00 00 00 00 02 14 58 15 00 00 00 00 00 02 15 68 15 00 00 00 00 00 02 16 78 15 00 00 00 00 00 02 17 77 15 00 00 00 00 00 02 18 40 15 00 00 00 00 00 02 19 40 15 00 00 00 00 00 02 1a 40 15 00 00 00 00 00 02 1b 40 15 00 00 00 00 00 02 1c 40 15 00 00 00 00 00 02 1d 40 15 00 00 00 00 00 02 1e 40 15 00 00 00 00 00 02 1f 40 15 00 00 00 00 00 02 20 40 15 00 00 00 00 00 02 21 45 15 00 00 00 00 00 02 22 49 15 00 00 00 00 00 02 23 4c 15 00 00 00 00 00 02 24 4b 15 00 00 00 00 00 02 25 48 15 00 00 00 00 00 02 26 44 15 00 00 00 00 00 02 27 41 15 01 00 00 00 00 02 28 40 15 00 00 00 00 00 02 2d 00 15 00 00 00 00 00 02 2f 37 15 00 00 00 00 00 02 30 37 15 00 00 00 00 00 02 31 37 15 00 00 00 00 00 02 32 37 15 00 00 00 00 00 02 33 37 15 00 00 00 00 00 02 34 37 15 00 00 00 00 00 02 35 37 15 00 00 00 00 00 02 36 37 15 00 00 00 00 00 02 37 37 15 00 00 00 00 00 02 38 38 15 00 00 00 00 00 02 39 38 15 00 00 00 00 00 02 3a 38 15 00 00 00 00 00 02 3b 37 15 00 00 00 00 00 02 3d 37 15 00 00 00 00 00 02 3f 37 15 00 00 00 00 00 02 40 36 15 00 00 00 00 00 02 41 34 15 00 00 00 00 00 02 42 40 15 00 00 00 00 00 02 43 40 15 01 00 00 00 00 02 44 40 15 00 00 00 00 00 02 45 40 15 00 00 00 00 00 02 46 40 15 00 00 00 00 00 02 47 40 15 00 00 00 00 00 02 48 40 15 00 00 00 00 00 02 49 40 15 00 00 00 00 00 02 4a 40 15 00 00 00 00 00 02 4b 3f 15 00 00 00 00 00 02 4c 3e 15 00 00 00 00 00 02 4d 3d 15 00 00 00 00 00 02 4e 3c 15 00 00 00 00 00 02 4f 3c 15 00 00 00 00 00 02 50 3b 15 00 00 00 00 00 02 51 3a 15 00 00 00 00 00 02 52 39 15 00 00 00 00 00 02 53 01 15 00 00 00 00 00 02 54 00 15 00 00 00 00 00 02 55 fe 15 00 00 00 00 00 02 56 77 15 00 00 00 00 00 02 58 3f 15 00 00 00 00 00 02 59 3e 15 01 00 00 00 00 02 5a 3e 15 00 00 00 00 00 02 5b 3d 15 00 00 00 00 00 02 5c 3d 15 00 00 00 00 00 02 5d 3d 15 00 00 00 00 00 02 5e 3d 15 00 00 00 00 00 02 5f 3c 15 00 00 00 00 00 02 60 bc 15 00 00 00 00 00 02 61 3c 15 00 00 00 00 00 02 62 3c 15 00 00 00 00 00 02 63 3c 15 00 00 00 00 00 02 64 3c 15 00 00 00 00 00 02 65 3c 15 00 00 00 00 00 02 66 bd 15 00 00 00 00 00 02 67 bd 15 00 00 00 00 00 02 68 3d 15 00 00 00 00 00 02 69 bd 15 00 00 00 00 00 02 6a 3c 15 00 00 00 00 00 02 6b 3c 15 00 00 00 00 00 02 6c 3d 15 00 00 00 00 00 02 6d 3d 15 01 00 00 00 00 02 6e 3c 15 00 00 00 00 00 02 6f 3d 15 00 00 00 00 00 02 70 00 15 00 00 00 00 00 02 71 c0 15 00 00 00 00 00 02 72 03 15 00 00 00 00 00 02 73 00 15 00 00 00 00 00 02 74 06 15 00 00 00 00 00 02 75 0c 15 00 00 00 00 00 02 76 03 15 00 00 00 00 00 02 77 09 15 00 00 00 00 00 02 78 0f 15 00 00 00 00 00 02 79 68 15 00 00 00 00 00 02 7a 88 15 00 00 00 00 00 02 7c 80 15 00 00 00 00 00 02 7d 80 15 00 00 00 00 00 02 7e 80 15 00 00 00 00 00 02 7f 80 15 00 00 00 00 00 02 80 c2 15 00 00 00 00 00 02 81 02 15 00 00 00 00 00 02 83 01 15 01 00 00 00 00 02 84 00 15 00 00 00 00 00 02 85 85 15 00 00 00 00 00 02 86 80 15 00 00 00 00 00 02 87 80 15 00 00 00 00 00 02 88 40 15 00 00 00 00 00 02 89 74 15 00 00 00 00 00 02 8a 77 15 00 00 00 00 00 02 8b 7a 15 00 00 00 00 00 02 8c 7e 15 00 00 00 00 00 02 8d 7f 15 00 00 00 00 00 02 8e 7e 15 00 00 00 00 00 02 8f 79 15 00 00 00 00 00 02 90 73 15 00 00 00 00 00 02 91 65 15 00 00 00 00 00 02 92 6d 15 00 00 00 00 00 02 93 74 15 00 00 00 00 00 02 94 7d 15 00 00 00 00 00 02 95 80 15 00 00 00 00 00 02 96 80 15 00 00 00 00 00 02 97 81 15 00 00 00 00 00 02 98 82 15 01 00 00 00 00 02 99 82 15 00 00 00 00 00 02 9a 82 15 00 00 00 00 00 02 9b 81 15 00 00 00 00 00 02 9c 81 15 00 00 00 00 00 02 9d 80 15 00 00 00 00 00 02 9e 7f 15 00 00 00 00 00 02 9f 7b 15 00 00 00 00 00 02 a0 78 15 00 00 00 00 00 02 a2 80 15 00 00 00 00 00 02 a6 80 15 00 00 00 00 00 02 a7 80 15 00 00 00 00 00 02 a9 80 15 00 00 00 00 00 02 aa 80 15 00 00 00 00 00 02 ab 80 15 00 00 00 00 00 02 ac 80 15 00 00 00 00 00 02 ad 80 15 00 00 00 00 00 02 ae 80 15 00 00 00 00 00 02 af 80 15 00 00 00 00 00 02 b7 76 15 00 00 00 00 00 02 b8 76 15 00 00 00 00 00 02 b9 05 15 01 00 00 00 00 02 ba 0d 15 00 00 00 00 00 02 bb 14 15 00 00 00 00 00 02 bc 0f 15 00 00 00 00 00 02 bd 18 15 00 00 00 00 00 02 be 1f 15 00 00 00 00 00 02 bf 05 15 00 00 00 00 00 02 c0 0d 15 00 00 00 00 00 02 c1 14 15 00 00 00 00 00 02 c2 03 15 00 00 00 00 00 02 c3 07 15 00 00 00 00 00 02 c4 0a 15 00 00 00 00 00 02 c5 a0 15 00 00 00 00 00 02 c6 55 15 00 00 00 00 00 02 c7 ff 15 00 00 00 00 00 02 c8 39 15 00 00 00 00 00 02 c9 44 15 00 00 00 00 00 02 ca 12 15 00 00 00 00 00 02 cd 80 15 00 00 00 00 00 02 db 80 15 00 00 00 00 00 02 dc 80 15 00 00 00 00 00 02 dd 80 15 01 00 00 00 00 02 e0 80 15 00 00 00 00 00 02 e1 80 15 00 00 00 00 00 02 e2 80 15 00 00 00 00 00 02 e3 80 15 00 00 00 00 00 02 e4 80 15 00 00 00 00 00 02 e5 40 15 00 00 00 00 00 02 e6 40 15 00 00 00 00 00 02 e7 40 15 00 00 00 00 00 02 e8 40 15 00 00 00 00 00 02 e9 40 15 00 00 00 00 00 02 ea 40 15 00 00 00 00 00 02 eb 40 15 00 00 00 00 00 02 ec 40 15 00 00 00 00 00 02 ed 40 15 00 00 00 00 00 02 ee 40 15 00 00 00 00 00 02 ef 40 15 00 00 00 00 00 02 f0 40 15 00 00 00 00 00 02 f1 40 15 00 00 00 00 00 02 f2 40 15 00 00 00 00 00 02 f3 40 15 01 00 00 00 00 02 f4 40 15 00 00 00 00 00 02 f5 40 15 00 00 00 00 00 02 f6 40 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 55 80]; | |
| qcom,mdss-dsi-srgb-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-cabc-on-command = [15 01 00 00 00 00 02 ff 23 15 00 00 00 00 00 02 fb 01 15 00 00 00 00 00 02 01 84 15 00 00 00 00 00 02 04 00 15 00 00 00 00 00 02 05 00 15 00 00 00 00 00 02 06 00 15 00 00 00 00 00 02 08 04 15 00 00 00 00 00 02 11 01 15 00 00 00 00 00 02 12 8a 15 01 00 00 00 00 02 15 6a 15 00 00 00 00 00 02 16 0b 15 00 00 00 00 00 02 29 80 15 00 00 00 00 00 02 30 ff 15 00 00 00 00 00 02 31 ff 15 00 00 00 00 00 02 32 ff 15 00 00 00 00 00 02 33 ff 15 00 00 00 00 00 02 34 ff 15 00 00 00 00 00 02 35 ff 15 00 00 00 00 00 02 36 ff 15 01 00 00 00 00 02 37 ff 15 01 00 00 00 00 02 38 ff 15 01 00 00 00 00 02 39 ff 15 00 00 00 00 00 02 3a ff 15 00 00 00 00 00 02 3b fa 15 00 00 00 00 00 02 3d f5 15 00 00 00 00 00 02 3f f0 15 00 00 00 00 00 02 40 e8 15 00 00 00 00 00 02 41 e3 15 00 00 00 00 00 02 ff 10 15 00 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 55 01]; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0xf>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x26200a0b 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x3bc>; | |
| phandle = <0x3bc>; | |
| }; | |
| qcom,mdss_dsi_td4320_boe_fhdplus_video { | |
| qcom,mdss-dsi-panel-name = "boe td4320 fhdplus video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x924>; | |
| qcom,mdss-pan-physical-width-dimension = <0x43>; | |
| qcom,mdss-pan-physical-height-dimension = <0x91>; | |
| qcom,mdss-dsi-h-front-porch = <0x56>; | |
| qcom,mdss-dsi-h-back-porch = <0x64>; | |
| qcom,mdss-dsi-h-pulse-width = <0x2>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x3c>; | |
| qcom,mdss-dsi-v-front-porch = <0x4>; | |
| qcom,mdss-dsi-v-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xfe3c2a00 0x70742e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xe>; | |
| qcom,mdss-dsi-t-clk-pre = <0x37>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 b0 00 29 01 00 00 00 00 02 d6 00 29 01 00 00 00 00 08 b8 2d 53 01 be 00 00 00 29 01 00 00 00 00 08 b9 73 51 03 e6 00 02 03 29 01 00 00 00 00 08 ba cd 55 03 e6 00 00 00 29 01 00 00 00 00 22 ce 5d 40 60 7f 9b b9 ce db e7 ef f2 f4 f5 f7 f9 fb fd ff 0b 00 04 04 42 00 69 5a 40 40 00 00 04 fa 00 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 24 15 01 00 00 00 00 02 55 00 39 01 00 00 60 00 02 11 00 39 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 14 00 02 28 00 15 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command; | |
| qcom,mdss-dsi-ce-off-command; | |
| qcom,mdss-dsi-srgb-on-command = <0x29010000 0x2b0 0x4290100 0x2 0xd6002901 0x0 0x42ca1dfc 0xfcfc1d0e 0xebf21ee3 0xe5d9e4de 0xd0c91fe4 0x10fefad8 0xff0000ff 0x23ff00 0xff0034fd 0x45ff0000 0xff003ae8 0xff00ffff 0xffe7ff 0xff00fffc 0x37e2ffff 0xff00fffb 0x4bff0029 0x1000000 0x2b003>; | |
| qcom,mdss-dsi-srgb-off-command = [29 01 00 00 00 00 02 b0 04 29 01 00 00 00 00 02 ca 1c 29 01 00 00 00 00 02 b0 03]; | |
| qcom,mdss-dsi-cabc-on-command = [15 01 00 00 00 00 02 55 81]; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0x1e>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x1c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x26200a0b 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| qcom,panel-supply-entries = <0x268>; | |
| linux,phandle = <0x277>; | |
| phandle = <0x277>; | |
| }; | |
| qcom,mdss_dsi_nt36672a_e7t_tianma_fhdplus_video { | |
| qcom,mdss-dsi-panel-name = "tianma nt36672a fhdplus video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x8e8>; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-pan-physical-height-dimension = <0x8f>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x1c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x8>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x3>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xfe3c2a00 0x70742e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xf>; | |
| qcom,mdss-dsi-t-clk-pre = <0x37>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 25 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 18 96 15 01 00 00 00 00 02 05 04 15 01 00 00 00 00 02 ff 20 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 78 01 15 01 00 00 00 00 02 ff 24 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 82 13 15 01 00 00 00 00 02 84 31 15 01 00 00 00 00 02 88 13 15 01 00 00 00 00 02 8a 31 15 01 00 00 00 00 02 8e e4 15 01 00 00 00 00 02 8f 01 15 01 00 00 00 00 02 90 80 15 01 00 00 00 00 02 ff 26 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 a9 12 15 01 00 00 00 00 02 aa 10 15 01 00 00 00 00 02 ae 8a 15 01 00 00 00 00 02 ff 10 15 01 00 00 50 00 02 11 00 15 01 00 00 00 00 02 b0 01 15 01 00 00 00 00 02 35 00 15 01 00 00 00 00 02 51 ff 15 01 00 00 00 00 02 53 2c 15 01 00 00 00 00 02 55 00 15 01 00 00 00 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 14 00 02 28 00 15 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command = <0x15010000 0x2ff 0x22150000 0x2 0xfb011500 0x0 0x2004015 0x0 0x20140 0x15000000 0x202 0x40150000 0x2 0x3401500 0x0 0x2044015 0x0 0x20540 0x15000000 0x206 0x40150000 0x2 0x7401500 0x0 0x2084015 0x0 0x20940 0x15000000 0x20a 0x40150000 0x2 0xb401500 0x0 0x20c4015 0x0 0x20d40 0x15000000 0x20e 0x40150000 0x2 0xf401500 0x0 0x2104015 0x0 0x21150 0x15000000 0x212 0x60150000 0x2 0x13701501 0x0 0x2145815 0x0 0x21568 0x15000000 0x216 0x78150000 0x2 0x17771500 0x0 0x2183e15 0x0 0x21936 0x15000000 0x21a 0x30150000 0x2 0x1b281500 0x0 0x21c2515 0x0 0x21d23 0x15000000 0x21e 0x26150000 0x2 0x1f2a1500 0x0 0x2203015 0x0 0x22136 0x15000000 0x222 0x3c150000 0x2 0x23401500 0x0 0x2244015 0x0 0x22540 0x15000000 0x226 0x40150000 0x2 0x27401501 0x0 0x2284015 0x0 0x22d00 0x15000000 0x22f 0x40150000 0x2 0x30401500 0x0 0x2314015 0x0 0x23240 0x15000000 0x233 0x40150000 0x2 0x34401500 0x0 0x2354015 0x0 0x23640 0x15000000 0x237 0x40150000 0x2 0x38401500 0x0 0x2394015 0x0 0x23a40 0x15000000 0x23b 0x40150000 0x2 0x3d401500 0x0 0x23f4015 0x1000000 0x24040 0x15000000 0x241 0x40150000 0x2 0x42401500 0x0 0x2434015 0x0 0x24440 0x15000000 0x245 0x40150000 0x2 0x46401500 0x0 0x2474015 0x0 0x24840 0x15000000 0x249 0x40150000 0x2 0x4a401500 0x0 0x24b4015 0x0 0x24c40 0x15000000 0x24d 0x40150000 0x2 0x4e401500 0x0 0x24f4015 0x0 0x25040 0x15000000 0x251 0x40150100 0x2 0x52401500 0x0 0x2530115 0x0 0x25401 0x15000000 0x255 0xff150000 0x2 0x56761500 0x0 0x258c815 0x0 0x259ca 0x15000000 0x25a 0x48150000 0x2 0x5b481500 0x0 0x25c4815 0x0 0x25d48 0x15000000 0x25e 0x48150000 0x2 0x5f481500 0x0 0x2604815 0x0 0x26148 0x15000000 0x262 0x48150000 0x2 0x63481500 0x0 0x2644815 0x1000000 0x26548 0x15000000 0x266 0x48150000 0x2 0x67481500 0x0 0x2684815 0x0 0x26948 0x15000000 0x26a 0x48150000 0x2 0x6b481500 0x0 0x26c4815 0x0 0x26d48 0x15000000 0x26e 0x48150000 0x2 0x6fc81500 0x0 0x2700315 0x0 0x27100 0x15000000 0x272 0x80150000 0x2 0x73001500 0x0 0x2740615 0x0 0x2750c 0x15000000 0x276 0x3150000 0x2 0x77091501 0x0 0x2780f15 0x0 0x27968 0x15000000 0x27a 0x8b150000 0x2 0x7c801500 0x0 0x27d8015 0x0 0x27e80 0x15000000 0x27f 0x150000 0x2 0x80001500 0x0 0x2810015 0x0 0x28301 0x15000000 0x284 0x150000 0x2 0x85801500 0x0 0x2868015 0x0 0x28780 0x15000000 0x288 0x40150000 0x2 0x89831500 0x0 0x28a8615 0x0 0x28b80 0x15010000 0x28c 0x80150000 0x2 0x8d801500 0x0 0x28e8015 0x0 0x28f80 0x15000000 0x290 0x80150000 0x2 0x91801500 0x0 0x2928015 0x0 0x29380 0x15000000 0x294 0x80150000 0x2 0x95801500 0x0 0x2968015 0x0 0x29780 0x15000000 0x298 0x80150000 0x2 0x99801500 0x0 0x29a8015 0x0 0x29b80 0x15000000 0x29c 0x80150000 0x2 0x9d801500 0x0 0x29e8015 0x0 0x29f80 0x15010000 0x2a0 0x80150000 0x2 0xa2801500 0x0 0x2a68015 0x0 0x2a780 0x15000000 0x2a9 0x80150000 0x2 0xaa801500 0x0 0x2ab8015 0x0 0x2ac80 0x15000000 0x2ad 0x80150000 0x2 0xae801500 0x0 0x2af8015 0x0 0x2b776 0x15000000 0x2b8 0x76150000 0x2 0xb9011500 0x0 0x2ba0d15 0x0 0x2bb14 0x15000000 0x2bc 0xf150000 0x2 0xbd181500 0x0 0x2be1f15 0x1000000 0x2bf02 0x15000000 0x2c0 0xd150000 0x2 0xc1141500 0x0 0x2c20315 0x0 0x2c307 0x15000000 0x2c4 0xa150000 0x2 0xc5a01500 0x0 0x2c65515 0x0 0x2c73a 0x15000000 0x2c8 0x1150000 0x2 0xc9021500 0x0 0x2ca1215 0x0 0x2cd80 0x15000000 0x2db 0x80150000 0x2 0xdc801500 0x0 0x2dd8015 0x0 0x2e080 0x15010000 0x2e1 0x80150000 0x2 0xe2801500 0x0 0x2e38015 0x0 0x2e480 0x15000000 0x2e5 0x40150000 0x2 0xe6401500 0x0 0x2e74015 0x0 0x2e840 0x15000000 0x2e9 0x40150000 0x2 0xea401500 0x0 0x2eb4015 0x0 0x2ec40 0x15000000 0x2ed 0x40150000 0x2 0xee401500 0x0 0x2ef4015 0x1000000 0x2f040 0x15000000 0x2f1 0x40150000 0x2 0xf2401500 0x0 0x2f34015 0x0 0x2f440 0x15000000 0x2f5 0x40150000 0x2 0xf6401501 0x0 0x2ff1015 0x1000000 0x25580>; | |
| qcom,mdss-dsi-ce-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-srgb-on-command = <0x15010000 0x2ff 0x22150000 0x2 0xfb011500 0x0 0x2003515 0x0 0x20135 0x15000000 0x202 0x35150000 0x2 0x3351500 0x0 0x2043415 0x0 0x20534 0x15000000 0x206 0x34150000 0x2 0x7341500 0x0 0x2083315 0x0 0x20933 0x15000000 0x20a 0x33150000 0x2 0xb331500 0x0 0x20c3315 0x0 0x20d33 0x15000000 0x20e 0x33150000 0x2 0xf331500 0x0 0x2103215 0x0 0x21150 0x15000000 0x212 0x60150000 0x2 0x13701500 0x0 0x2145815 0x0 0x21568 0x15010000 0x216 0x78150000 0x2 0x17771500 0x0 0x2184015 0x0 0x21940 0x15000000 0x21a 0x40150000 0x2 0x1b401500 0x0 0x21c4015 0x0 0x21d40 0x15000000 0x21e 0x40150000 0x2 0x1f401500 0x0 0x2204015 0x0 0x22145 0x15000000 0x222 0x49150000 0x2 0x234c1500 0x0 0x2244b15 0x0 0x22548 0x15000000 0x226 0x44150000 0x2 0x27411500 0x0 0x2284015 0x1000000 0x22d00 0x15000000 0x22f 0x37150000 0x2 0x30361500 0x0 0x2313615 0x0 0x23236 0x15000000 0x233 0x38150000 0x2 0x34381500 0x0 0x2353615 0x0 0x23637 0x15000000 0x237 0x36150000 0x2 0x38371500 0x0 0x2393415 0x0 0x23a34 0x15000000 0x23b 0x32150000 0x2 0x3d321500 0x0 0x23f3015 0x0 0x2402f 0x15000000 0x241 0x2c150000 0x2 0x42361500 0x0 0x2433615 0x0 0x24436 0x15000000 0x245 0x36150000 0x2 0x46351501 0x0 0x2473515 0x0 0x24835 0x15000000 0x249 0x35150000 0x2 0x4a351500 0x0 0x24b3515 0x0 0x24c35 0x15000000 0x24d 0x34150000 0x2 0x4e331500 0x0 0x24f3315 0x0 0x25032 0x15000000 0x251 0x31150000 0x2 0x52301500 0x0 0x2530115 0x0 0x25400 0x15000000 0x255 0xfe150000 0x2 0x56771500 0x0 0x2584115 0x0 0x25942 0x15000000 0x25a 0x43150100 0x2 0x5b441500 0x0 0x25c4415 0x0 0x25d45 0x15000000 0x25e 0x45150000 0x2 0x5f441500 0x0 0x260c315 0x0 0x26144 0x15000000 0x262 0x46150000 0x2 0x63471500 0x0 0x2644715 0x0 0x26548 0x15000000 0x266 0x4a150000 0x2 0x674c1500 0x0 0x2685015 0x0 0x2694d 0x15000000 0x26a 0x49150000 0x2 0x6b471500 0x0 0x26c4715 0x1000000 0x26d47 0x15000000 0x26e 0x45150000 0x2 0x6f441500 0x0 0x2700015 0x0 0x27100 0x15000000 0x272 0x1150000 0x2 0x73001500 0x0 0x2740615 0x0 0x2750c 0x15000000 0x276 0x3150000 0x2 0x77091500 0x0 0x2780f15 0x0 0x27968 0x15000000 0x27a 0x88150000 0x2 0x7c801500 0x0 0x27d8015 0x0 0x27e80 0x15000000 0x27f 0x80150100 0x2 0x80061500 0x0 0x2810015 0x0 0x28301 0x15000000 0x284 0x4150000 0x2 0x855d1500 0x0 0x2865915 0x0 0x28763 0x15000000 0x288 0x40150000 0x2 0x89801500 0x0 0x28a8015 0x0 0x28b80 0x15000000 0x28c 0x80150000 0x2 0x8d801500 0x0 0x28e8015 0x0 0x28f80 0x15000000 0x290 0x80150000 0x2 0x91801500 0x0 0x2928015 0x1000000 0x29380 0x15000000 0x294 0x80150000 0x2 0x95801500 0x0 0x2968015 0x0 0x29780 0x15000000 0x298 0x80150000 0x2 0x99801500 0x0 0x29a8015 0x0 0x29b80 0x15000000 0x29c 0x80150000 0x2 0x9d801500 0x0 0x29e8015 0x0 0x29f80 0x15000000 0x2a0 0x80150000 0x2 0xa27c1500 0x0 0x2a68015 0x0 0x2a780 0x15000000 0x2a9 0x80150100 0x2 0xaa801500 0x0 0x2ab8015 0x0 0x2ac80 0x15000000 0x2ad 0x80150000 0x2 0xae801500 0x0 0x2af6f15 0x0 0x2b776 0x15000000 0x2b8 0x76150000 0x2 0xb9051500 0x0 0x2ba0d15 0x0 0x2bb14 0x15000000 0x2bc 0xf150000 0x2 0xbd181500 0x0 0x2be1f15 0x0 0x2bf05 0x15000000 0x2c0 0xd150000 0x2 0xc1141500 0x0 0x2c20315 0x0 0x2c307 0x15000000 0x2c4 0xa150100 0x2 0xc5a01500 0x0 0x2c65515 0x0 0x2c7ff 0x15000000 0x2c8 0x39150000 0x2 0xc9441500 0x0 0x2ca1215 0x0 0x2cd80 0x15000000 0x2db 0x70150000 0x2 0xdc801500 0x0 0x2dd8015 0x0 0x2e07a 0x15000000 0x2e1 0x7f150000 0x2 0xe2801500 0x0 0x2e38015 0x0 0x2e480 0x15000000 0x2e5 0x40150000 0x2 0xe6401500 0x0 0x2e74015 0x1000000 0x2e840 0x15000000 0x2e9 0x40150000 0x2 0xea401500 0x0 0x2eb4015 0x0 0x2ec40 0x15000000 0x2ed 0x40150000 0x2 0xee401500 0x0 0x2ef4015 0x0 0x2f040 0x15000000 0x2f1 0x40150000 0x2 0xf2401500 0x0 0x2f34015 0x0 0x2f440 0x15000000 0x2f5 0x40150000 0x2 0xf6401501 0x0 0x2ff1015 0x1000000 0x25580>; | |
| qcom,mdss-dsi-srgb-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-cabc-on-command = <0x15010000 0x2ff 0x23150100 0x2 0xfb011501 0x0 0x2018415 0x1000000 0x20408 0x15010000 0x205 0x2d150100 0x2 0x6001501 0x0 0x2110115 0x1000000 0x21280 0x15010000 0x215 0x6d150100 0x2 0x160b1501 0x0 0x2290a15 0x1000000 0x230ff 0x15010000 0x231 0xff150100 0x2 0x32ff1501 0x0 0x233ff15 0x1000000 0x234ff 0x15010000 0x235 0xff150100 0x2 0x36ff1501 0x0 0x237ff15 0x1000000 0x238fc 0x15010000 0x239 0xf8150100 0x2 0x3af41501 0x0 0x23bf115 0x1000000 0x23dee 0x15010000 0x23f 0xeb150100 0x2 0x40e81501 0x0 0x241e515 0x1000000 0x2ff10 0x15010000 0x2fb 0x1150100 0x2 0x51ff1501 0x0 0x2532c15 0x1000000 0x25501>; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0xf>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x26200a0b 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| linux,phandle = <0x3bd>; | |
| phandle = <0x3bd>; | |
| }; | |
| qcom,mdss_dsi_nt36672a_e7t_shenchao_fhdplus_video { | |
| qcom,mdss-dsi-panel-name = "shenchao nt36672a fhdplus video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x8e8>; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-pan-physical-height-dimension = <0x8f>; | |
| qcom,mdss-dsi-h-front-porch = <0x64>; | |
| qcom,mdss-dsi-h-back-porch = <0x78>; | |
| qcom,mdss-dsi-h-pulse-width = <0x1c>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0x8>; | |
| qcom,mdss-dsi-v-front-porch = <0xa>; | |
| qcom,mdss-dsi-v-pulse-width = <0x3>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xfe3c2a00 0x70742e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xf>; | |
| qcom,mdss-dsi-t-clk-pre = <0x37>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = <0x15010000 0x2ff 0x25150100 0x2 0xfb011501 0x0 0x2189615 0x1000000 0x20504 0x15010000 0x2ff 0x10150100 0x500002 0x11001501 0x0 0x2b00115 0x1000000 0x23500 0x15010000 0x251 0xff150100 0x2 0x532c1501 0x0 0x2550015 0x1000000 0x22900>; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 14 00 02 28 00 15 01 00 00 78 00 02 10 00]; | |
| qcom,mdss-dsi-ce-on-command = <0x15010000 0x2ff 0x22150000 0x2 0xfb011500 0x0 0x2004015 0x0 0x20140 0x15000000 0x202 0x40150000 0x2 0x3401500 0x0 0x2044015 0x0 0x20540 0x15000000 0x206 0x40150000 0x2 0x7401500 0x0 0x2084015 0x0 0x20940 0x15000000 0x20a 0x40150000 0x2 0xb401500 0x0 0x20c4015 0x0 0x20d40 0x15000000 0x20e 0x40150000 0x2 0xf401500 0x0 0x2104015 0x0 0x21150 0x15000000 0x212 0x60150000 0x2 0x13701501 0x0 0x2145815 0x0 0x21568 0x15000000 0x216 0x78150000 0x2 0x17771500 0x0 0x2184015 0x0 0x2194a 0x15000000 0x21a 0x52150000 0x2 0x1b561500 0x0 0x21c5315 0x0 0x21d4d 0x15000000 0x21e 0x47150000 0x2 0x1f401500 0x0 0x2204015 0x0 0x22140 0x15000000 0x222 0x40150000 0x2 0x23401500 0x0 0x2244015 0x0 0x22540 0x15000000 0x226 0x40150000 0x2 0x27401501 0x0 0x2284015 0x0 0x22d00 0x15000000 0x22f 0x40150000 0x2 0x30401500 0x0 0x2314015 0x0 0x23240 0x15000000 0x233 0x40150000 0x2 0x34401500 0x0 0x2354015 0x0 0x23640 0x15000000 0x237 0x40150000 0x2 0x38401500 0x0 0x2394015 0x0 0x23a40 0x15000000 0x23b 0x40150000 0x2 0x3d401500 0x0 0x23f4015 0x1000000 0x24040 0x15000000 0x241 0x40150000 0x2 0x42401500 0x0 0x2434015 0x0 0x24440 0x15000000 0x245 0x40150000 0x2 0x46401500 0x0 0x2474015 0x0 0x24840 0x15000000 0x249 0x40150000 0x2 0x4a401500 0x0 0x24b4015 0x0 0x24c40 0x15000000 0x24d 0x40150000 0x2 0x4e401500 0x0 0x24f4015 0x0 0x25040 0x15000000 0x251 0x40150100 0x2 0x52401500 0x0 0x2530115 0x0 0x25401 0x15000000 0x255 0xff150000 0x2 0x56771500 0x0 0x258d415 0x0 0x259d2 0x15000000 0x25a 0x50150000 0x2 0x5b501500 0x0 0x25c5015 0x0 0x25d50 0x15000000 0x25e 0x50150000 0x2 0x5f501500 0x0 0x2605015 0x0 0x26150 0x15000000 0x262 0x50150000 0x2 0x63501500 0x0 0x2645015 0x1000000 0x26550 0x15000000 0x266 0x50150000 0x2 0x67501500 0x0 0x2685015 0x0 0x26950 0x15000000 0x26a 0x50150000 0x2 0x6b501500 0x0 0x26c5015 0x0 0x26d50 0x15000000 0x26e 0x50150000 0x2 0x6fd01500 0x0 0x2700315 0x0 0x27100 0x15000000 0x272 0x80150000 0x2 0x73001500 0x0 0x2740615 0x0 0x2750c 0x15000000 0x276 0x3150000 0x2 0x77091501 0x0 0x2780f15 0x0 0x27968 0x15000000 0x27a 0x8b150000 0x2 0x7c801500 0x0 0x27d8015 0x0 0x27e80 0x15000000 0x27f 0x150000 0x2 0x80001500 0x0 0x2810015 0x0 0x28301 0x15000000 0x284 0x150000 0x2 0x85801500 0x0 0x2868015 0x0 0x28780 0x15000000 0x288 0x40150000 0x2 0x89831500 0x0 0x28a8615 0x0 0x28b80 0x15010000 0x28c 0x80150000 0x2 0x8d801500 0x0 0x28e8015 0x0 0x28f80 0x15000000 0x290 0x80150000 0x2 0x91801500 0x0 0x2928015 0x0 0x29380 0x15000000 0x294 0x80150000 0x2 0x95801500 0x0 0x2968015 0x0 0x29780 0x15000000 0x298 0x80150000 0x2 0x99801500 0x0 0x29a8015 0x0 0x29b80 0x15000000 0x29c 0x80150000 0x2 0x9d801500 0x0 0x29e8015 0x0 0x29f80 0x15010000 0x2a0 0x80150000 0x2 0xa2801500 0x0 0x2a68015 0x0 0x2a780 0x15000000 0x2a9 0x80150000 0x2 0xaa801500 0x0 0x2ab8015 0x0 0x2ac80 0x15000000 0x2ad 0x80150000 0x2 0xae801500 0x0 0x2af8015 0x0 0x2b776 0x15000000 0x2b8 0x76150000 0x2 0xb9011500 0x0 0x2ba0d15 0x0 0x2bb14 0x15000000 0x2bc 0xf150000 0x2 0xbd181500 0x0 0x2be1f15 0x1000000 0x2bf02 0x15000000 0x2c0 0xd150000 0x2 0xc1141500 0x0 0x2c20315 0x0 0x2c307 0x15000000 0x2c4 0xa150000 0x2 0xc5a01500 0x0 0x2c65515 0x0 0x2c73a 0x15000000 0x2c8 0x1150000 0x2 0xc9021500 0x0 0x2ca1215 0x0 0x2cd80 0x15000000 0x2db 0x80150000 0x2 0xdc801500 0x0 0x2dd8015 0x0 0x2e080 0x15010000 0x2e1 0x80150000 0x2 0xe2801500 0x0 0x2e38015 0x0 0x2e480 0x15000000 0x2e5 0x40150000 0x2 0xe6401500 0x0 0x2e74015 0x0 0x2e840 0x15000000 0x2e9 0x40150000 0x2 0xea401500 0x0 0x2eb4015 0x0 0x2ec40 0x15000000 0x2ed 0x40150000 0x2 0xee401500 0x0 0x2ef4015 0x1000000 0x2f040 0x15000000 0x2f1 0x40150000 0x2 0xf2401500 0x0 0x2f34015 0x0 0x2f440 0x15000000 0x2f5 0x40150000 0x2 0xf6401501 0x0 0x2ff1015 0x1000000 0x25580>; | |
| qcom,mdss-dsi-ce-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-srgb-on-command = <0x15010000 0x2ff 0x22150000 0x2 0xfb011500 0x0 0x2004015 0x0 0x20140 0x15000000 0x202 0x40150000 0x2 0x3401500 0x0 0x2044015 0x0 0x20540 0x15000000 0x206 0x40150000 0x2 0x7401500 0x0 0x2084015 0x0 0x2093f 0x15010000 0x20a 0x3d150000 0x2 0xb3b1500 0x0 0x20c3b15 0x0 0x20d39 0x15000000 0x20e 0x38150000 0x2 0xf381500 0x0 0x2103715 0x0 0x21150 0x15000000 0x212 0x60150000 0x2 0x13701500 0x0 0x2145815 0x0 0x21568 0x15000000 0x216 0x78150100 0x2 0x17771500 0x0 0x2184015 0x0 0x21940 0x15000000 0x21a 0x40150000 0x2 0x1b401500 0x0 0x21c4015 0x0 0x21d40 0x15000000 0x21e 0x40150000 0x2 0x1f401500 0x0 0x2204015 0x1000000 0x22145 0x15000000 0x222 0x49150000 0x2 0x234c1500 0x0 0x2244b15 0x0 0x22548 0x15000000 0x226 0x44150000 0x2 0x27411500 0x0 0x2284015 0x0 0x22d00 0x15000000 0x22f 0x40150000 0x2 0x30401500 0x0 0x2314015 0x1000000 0x23240 0x15000000 0x233 0x40150000 0x2 0x34401500 0x0 0x2354015 0x0 0x23640 0x15000000 0x237 0x40150000 0x2 0x383f1500 0x0 0x2393d15 0x0 0x23a3c 0x15000000 0x23b 0x3a150000 0x2 0x3d371500 0x0 0x23f3415 0x0 0x24031 0x15000000 0x241 0x2d150100 0x2 0x42401500 0x0 0x2433e15 0x0 0x2443b 0x15000000 0x245 0x38150000 0x2 0x46351500 0x0 0x2473515 0x0 0x24834 0x15000000 0x249 0x34150000 0x2 0x4a331500 0x0 0x24b3315 0x0 0x24c32 0x15000000 0x24d 0x31150000 0x2 0x4e301501 0x0 0x24f2e15 0x0 0x2502c 0x15000000 0x251 0x2a150000 0x2 0x52281500 0x0 0x2530115 0x0 0x25400 0x15000000 0x255 0xfe150000 0x2 0x56771500 0x0 0x2585015 0x0 0x25951 0x15010000 0x25a 0x50150000 0x2 0x5b501500 0x0 0x25c5015 0x0 0x25d50 0x15000000 0x25e 0x4e150000 0x2 0x5f4b1500 0x0 0x2604915 0x0 0x2614b 0x15000000 0x262 0x4e150000 0x2 0x63501501 0x0 0x2645015 0x0 0x26550 0x15000000 0x266 0x4e150000 0x2 0x674d1500 0x0 0x268ca15 0x0 0x2694d 0x15000000 0x26a 0x4e150000 0x2 0x6b501500 0x0 0x26c5015 0x0 0x26d50 0x15000000 0x26e 0x50150100 0x2 0x6f511500 0x0 0x2700015 0x0 0x27101 0x15000000 0x272 0x150000 0x2 0x73001500 0x0 0x2740615 0x0 0x2750c 0x15000000 0x276 0x3150000 0x2 0x77091500 0x0 0x2780f15 0x0 0x27968 0x15000000 0x27a 0x88150100 0x2 0x7c801500 0x0 0x27d8015 0x0 0x27e80 0x15000000 0x27f 0x150000 0x2 0x80001500 0x0 0x2810015 0x0 0x28301 0x15000000 0x284 0x3150000 0x2 0x85651500 0x0 0x2868f15 0x0 0x28779 0x15010000 0x288 0x40150000 0x2 0x89801500 0x0 0x28a8015 0x0 0x28b80 0x15000000 0x28c 0x80150000 0x2 0x8d801500 0x0 0x28e8015 0x0 0x28f80 0x15000000 0x290 0x80150000 0x2 0x91801500 0x0 0x2928015 0x0 0x29380 0x15010000 0x294 0x80150000 0x2 0x95801500 0x0 0x2968015 0x0 0x29780 0x15000000 0x298 0x80150000 0x2 0x99801500 0x0 0x29a8015 0x0 0x29b80 0x15000000 0x29c 0x80150000 0x2 0x9d801500 0x0 0x29e8015 0x0 0x29f80 0x15010000 0x2a0 0x80150000 0x2 0xa2801500 0x0 0x2a68015 0x0 0x2a780 0x15000000 0x2a9 0x80150000 0x2 0xaa801500 0x0 0x2ab8015 0x0 0x2ac80 0x15000000 0x2ad 0x80150000 0x2 0xae801500 0x0 0x2af8015 0x1000000 0x2b776 0x15000000 0x2b8 0x76150000 0x2 0xb9051500 0x0 0x2ba0d15 0x0 0x2bb14 0x15000000 0x2bc 0xf150000 0x2 0xbd181500 0x0 0x2be1f15 0x0 0x2bf05 0x15000000 0x2c0 0xd150000 0x2 0xc1141500 0x0 0x2c20315 0x1000000 0x2c307 0x15000000 0x2c4 0xa150000 0x2 0xc5a01500 0x0 0x2c65515 0x0 0x2c7ff 0x15000000 0x2c8 0x39150000 0x2 0xc9441500 0x0 0x2ca1215 0x0 0x2cd80 0x15000000 0x2db 0x81150000 0x2 0xdc801500 0x0 0x2dd8015 0x1000000 0x2e080 0x15000000 0x2e1 0x80150000 0x2 0xe2801500 0x0 0x2e38015 0x0 0x2e480 0x15000000 0x2e5 0x40150000 0x2 0xe6401500 0x0 0x2e74015 0x0 0x2e840 0x15000000 0x2e9 0x40150000 0x2 0xea401500 0x0 0x2eb4015 0x0 0x2ec40 0x15000000 0x2ed 0x40150100 0x2 0xee401500 0x0 0x2ef4015 0x0 0x2f040 0x15000000 0x2f1 0x40150000 0x2 0xf2401500 0x0 0x2f34015 0x0 0x2f440 0x15000000 0x2f5 0x40150000 0x2 0xf6401501 0x0 0x2ff1015 0x1000000 0x25580>; | |
| qcom,mdss-dsi-srgb-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-cabc-on-command = <0x15010000 0x2ff 0x23150100 0x2 0xfb011501 0x0 0x2018415 0x1000000 0x20408 0x15010000 0x205 0x2d150100 0x2 0x6001501 0x0 0x2110115 0x1000000 0x21280 0x15010000 0x215 0x6d150100 0x2 0x160b1501 0x0 0x2290a15 0x1000000 0x230ff 0x15010000 0x231 0xff150100 0x2 0x32ff1501 0x0 0x233ff15 0x1000000 0x234ff 0x15010000 0x235 0xff150100 0x2 0x36ff1501 0x0 0x237ff15 0x1000000 0x238fc 0x15010000 0x239 0xf8150100 0x2 0x3af41501 0x0 0x23bf115 0x1000000 0x23dee 0x15010000 0x23f 0xeb150100 0x2 0x40e81501 0x0 0x241e515 0x1000000 0x2ff10 0x15010000 0x2fb 0x1150100 0x2 0x51ff1501 0x0 0x2532c15 0x1000000 0x25501>; | |
| qcom,mdss-dsi-cabc-off-command = [15 01 00 00 00 00 02 ff 10 15 01 00 00 00 00 02 fb 01 15 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x1 0x0 0x5 0x1 0xf>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x26200a0b 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| linux,phandle = <0x3be>; | |
| phandle = <0x3be>; | |
| }; | |
| qcom,mdss_dsi_ft8719_e7t_boe_fhdplus_video { | |
| qcom,mdss-dsi-panel-name = "boe ft8719 fhdplus video mode dsi panel"; | |
| qcom,mdss-dsi-panel-controller = <0x270>; | |
| qcom,mdss-dsi-panel-type = "dsi_video_mode"; | |
| qcom,mdss-dsi-panel-framerate = <0x3c>; | |
| qcom,mdss-dsi-virtual-channel-id = <0x0>; | |
| qcom,mdss-dsi-stream = <0x0>; | |
| qcom,mdss-dsi-panel-width = <0x438>; | |
| qcom,mdss-dsi-panel-height = <0x8e8>; | |
| qcom,mdss-pan-physical-width-dimension = <0x44>; | |
| qcom,mdss-pan-physical-height-dimension = <0x8f>; | |
| qcom,mdss-dsi-h-front-porch = <0x7c>; | |
| qcom,mdss-dsi-h-back-porch = <0x3c>; | |
| qcom,mdss-dsi-h-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-sync-skew = <0x0>; | |
| qcom,mdss-dsi-v-back-porch = <0xc>; | |
| qcom,mdss-dsi-v-front-porch = <0x73>; | |
| qcom,mdss-dsi-v-pulse-width = <0x4>; | |
| qcom,mdss-dsi-h-left-border = <0x0>; | |
| qcom,mdss-dsi-h-right-border = <0x0>; | |
| qcom,mdss-dsi-v-top-border = <0x0>; | |
| qcom,mdss-dsi-v-bottom-border = <0x0>; | |
| qcom,mdss-dsi-bpp = <0x18>; | |
| qcom,mdss-dsi-underflow-color = <0xff>; | |
| qcom,mdss-dsi-border-color = <0x0>; | |
| qcom,mdss-dsi-h-sync-pulse = <0x0>; | |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; | |
| qcom,mdss-dsi-bllp-eof-power-mode; | |
| qcom,mdss-dsi-bllp-power-mode; | |
| qcom,mdss-dsi-lane-0-state; | |
| qcom,mdss-dsi-lane-1-state; | |
| qcom,mdss-dsi-lane-2-state; | |
| qcom,mdss-dsi-lane-3-state; | |
| qcom,mdss-dsi-panel-timings = <0xfe3c2a00 0x70742e40 0x30030400>; | |
| qcom,mdss-dsi-t-clk-post = <0xf>; | |
| qcom,mdss-dsi-t-clk-pre = <0x37>; | |
| qcom,mdss-dsi-bl-min-level = <0x1>; | |
| qcom,mdss-dsi-bl-max-level = <0xfff>; | |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; | |
| qcom,mdss-dsi-mdp-trigger = "none"; | |
| qcom,mdss-dsi-on-command = [39 00 00 00 00 00 02 00 00 39 00 00 00 00 00 04 ff 87 19 01 39 00 00 00 00 00 02 00 80 39 00 00 00 00 00 03 ff 87 19 39 00 00 00 00 00 02 00 80 39 00 00 00 00 00 0d ca 82 80 80 80 80 80 80 80 80 80 80 80 39 00 00 00 00 00 02 00 90 39 00 00 00 00 00 0a ca fe ff 13 fc ff cc fa ff 66 39 01 00 00 00 00 02 00 a0 39 01 00 00 00 00 0d d6 75 74 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 b0 39 01 00 00 00 00 0d d6 84 80 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 c0 39 01 00 00 00 00 0d d6 7c 81 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 d0 39 01 00 00 00 00 0d d6 81 7e 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 e0 39 01 00 00 00 00 0d d6 8b 99 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 f0 39 01 00 00 00 00 0d d6 79 7b 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 00 39 01 00 00 00 00 0d d7 80 80 80 80 80 80 80 80 80 80 80 80 39 01 00 00 00 00 02 00 10 39 01 00 00 00 00 0d d7 80 80 80 80 80 80 80 80 80 80 80 80 39 00 00 00 00 00 02 00 80 39 00 00 00 00 00 0b d9 fd 01 06 00 fd 0f fa 0f e1 01 39 00 00 00 00 00 02 00 90 39 00 00 00 00 00 09 d9 0f 00 07 00 1c 00 7e 01 39 00 00 00 00 00 02 00 00 39 00 00 00 00 00 03 51 ff 0f 39 00 00 00 00 00 02 53 2c 39 00 00 00 00 00 02 55 00 15 01 00 00 78 00 02 11 00 15 01 00 00 14 00 02 29 00]; | |
| qcom,mdss-dsi-off-command = [15 01 00 00 14 00 02 28 00 15 01 00 00 78 00 02 10 00 39 01 00 00 00 00 02 00 00 39 01 00 00 00 00 05 f7 5a a5 95 27]; | |
| qcom,mdss-dsi-ce-on-command = [15 00 00 00 00 00 02 91 80]; | |
| qcom,mdss-dsi-ce-off-command = [15 00 00 00 00 00 02 91 00]; | |
| qcom,mdss-dsi-srgb-on-command = [39 00 00 00 00 00 02 96 80]; | |
| qcom,mdss-dsi-srgb-off-command = [39 00 00 00 00 00 02 96 00]; | |
| qcom,mdss-dsi-cabc-on-command = [39 01 00 00 00 00 02 55 01]; | |
| qcom,mdss-dsi-cabc-off-command = [39 01 00 00 00 00 02 55 00]; | |
| qcom,mdss-dsi-gamma0-command; | |
| qcom,mdss-dsi-gamma1-command; | |
| qcom,mdss-dsi-gamma2-command; | |
| qcom,mdss-dsi-gamma3-command; | |
| qcom,mdss-dsi-gamma4-command; | |
| qcom,mdss-dsi-gamma5-command; | |
| qcom,mdss-dsi-gamma6-command; | |
| qcom,mdss-dsi-gamma7-command; | |
| qcom,mdss-dsi-gamma8-command; | |
| qcom,mdss-dsi-gamma9-command; | |
| qcom,mdss-dsi-gamma10-command; | |
| qcom,mdss-dsi-gamma11-command; | |
| qcom,mdss-dsi-gamma12-command; | |
| qcom,mdss-dsi-gamma13-command; | |
| qcom,mdss-dsi-gamma14-command; | |
| qcom,mdss-dsi-gamma15-command; | |
| qcom,mdss-dsi-gamma16-command; | |
| qcom,mdss-dsi-gamma17-command; | |
| qcom,mdss-dsi-gamma18-command; | |
| qcom,mdss-dsi-gamma19-command; | |
| qcom,mdss-dsi-gamma20-command; | |
| qcom,mdss-dsi-gamma21-command; | |
| qcom,mdss-dsi-gamma22-command; | |
| qcom,mdss-dsi-gamma23-command; | |
| qcom,mdss-dsi-gamma24-command; | |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; | |
| qcom,mdss-dsi-ce-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-ce-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-srgb-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-on-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-cabc-off-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-gamma-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; | |
| qcom,mdss-dsi-reset-sequence = <0x1 0x4 0x0 0x1 0x1 0xb>; | |
| qcom,mdss-dsi-tx-eot-append; | |
| qcom,mdss-dsi-post-init-delay = <0x1>; | |
| qcom,esd-check-enabled; | |
| qcom,mdss-dsi-panel-status-command = <0x6010001 0x500010a>; | |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; | |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; | |
| qcom,mdss-dsi-panel-status-read-length = <0x1>; | |
| qcom,mdss-dsi-panel-status-value = <0x9c>; | |
| qcom,mdss-dsi-panel-max-error-count = <0x3>; | |
| qcom,mdss-dsi-panel-timings-phy-v2 = <0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x2621090b 0x60304a0 0x26200a0b 0x60304a0>; | |
| qcom,mdss-dsi-min-refresh-rate = <0x30>; | |
| qcom,mdss-dsi-max-refresh-rate = <0x3c>; | |
| linux,phandle = <0x3bf>; | |
| phandle = <0x3bf>; | |
| }; | |
| }; | |
| qcom,mdss_dsi@0 { | |
| compatible = "qcom,mdss-dsi"; | |
| #address-cells = <0x1>; | |
| #size-cells = <0x1>; | |
| gdsc-supply = <0x165>; | |
| vdda-1p2-supply = <0x109>; | |
| vdda-0p9-supply = <0x105>; | |
| ranges = <0xc994000 0xc994000 0x400 0xc994400 0xc994400 0x588 0xc828000 0xc828000 0xac 0xc996000 0xc996000 0x400 0xc996400 0xc996400 0x588 0xc828000 0xc828000 0xac>; | |
| qcom,msm-bus,name = "mdss_dsi"; | |
| qcom,msm-bus,num-cases = <0x2>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x3e8>; | |
| qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; | |
| clocks = <0x74 0xa2 0x74 0xa9 0x74 0x92 0x74 0x93 0x74 0xa7 0x271 0x0 0x272 0xc 0x271 0x2 0x272 0xe>; | |
| clock-names = "mdp_core_clk", "mnoc_clk", "iface_clk", "bus_clk", "core_mmss_clk", "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", "ext_pixel1_clk"; | |
| hw-config = "split_dsi"; | |
| linux,phandle = <0x3c0>; | |
| phandle = <0x3c0>; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,core-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-min-voltage = <0x0>; | |
| qcom,supply-max-voltage = <0x0>; | |
| qcom,supply-enable-load = <0x0>; | |
| qcom,supply-disable-load = <0x0>; | |
| }; | |
| }; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,ctrl-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "vdda-1p2"; | |
| qcom,supply-min-voltage = <0x124f80>; | |
| qcom,supply-max-voltage = <0x1312d0>; | |
| qcom,supply-enable-load = <0x3110>; | |
| qcom,supply-disable-load = <0x4>; | |
| }; | |
| }; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,phy-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| qcom,supply-max-voltage = <0xe1d48>; | |
| qcom,supply-enable-load = <0x11eb8>; | |
| qcom,supply-disable-load = <0x20>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_ctrl0@c994000 { | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| label = "MDSS DSI CTRL->0"; | |
| cell-index = <0x0>; | |
| reg = <0xc994000 0x400 0xc994400 0x588 0xc828000 0xac>; | |
| reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; | |
| qcom,timing-db-mode; | |
| wqhd-vddio-supply = <0x17e>; | |
| vdda-3p3-supply = <0x197>; | |
| lab-supply = <0x273>; | |
| ibb-supply = <0x274>; | |
| qcom,mdss-mdp = <0x275>; | |
| qcom,mdss-fb-map = <0x276>; | |
| clocks = <0x74 0x94 0x74 0xa3 0x74 0x9f 0x74 0x6 0x74 0xb8 0x74 0x95>; | |
| clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "byte_intf_clk"; | |
| qcom,null-insertion-enabled; | |
| qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>; | |
| qcom,dsi-pref-prim-pan = <0x277>; | |
| pinctrl-names = "mdss_default", "mdss_sleep"; | |
| pinctrl-0 = <0x278 0x279>; | |
| pinctrl-1 = <0x27a 0x27b>; | |
| qcom,platform-reset-gpio = <0xe7 0x35 0x0>; | |
| qcom,platform-te-gpio = <0xe7 0x3b 0x0>; | |
| linux,phandle = <0x270>; | |
| phandle = <0x270>; | |
| }; | |
| qcom,mdss_dsi_ctrl1@c996000 { | |
| compatible = "qcom,mdss-dsi-ctrl"; | |
| label = "MDSS DSI CTRL->1"; | |
| cell-index = <0x1>; | |
| reg = <0xc996000 0x400 0xc996400 0x588 0xc828000 0xac>; | |
| reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; | |
| qcom,timing-db-mode; | |
| wqhd-vddio-supply = <0x17e>; | |
| lab-supply = <0x273>; | |
| ibb-supply = <0x274>; | |
| qcom,mdss-mdp = <0x275>; | |
| qcom,mdss-fb-map = <0x276>; | |
| clocks = <0x74 0x97 0x74 0xa4 0x74 0xa0 0x74 0x7 0x74 0xb9 0x74 0x98>; | |
| clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "byte_intf_clk"; | |
| qcom,null-insertion-enabled; | |
| qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; | |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; | |
| qcom,platform-lane-config = <0x100f 0x100f 0x100f 0x100f 0x108f>; | |
| linux,phandle = <0x3c1>; | |
| phandle = <0x3c1>; | |
| }; | |
| }; | |
| qcom,mdss_wb_panel { | |
| compatible = "qcom,mdss_wb"; | |
| qcom,mdss_pan_res = <0x280 0x1e0>; | |
| qcom,mdss_pan_bpp = <0x18>; | |
| qcom,mdss-fb-map = <0x27c>; | |
| }; | |
| qcom,msm_ext_disp { | |
| status = "ok"; | |
| compatible = "qcom,msm-ext-disp"; | |
| linux,phandle = <0x27d>; | |
| phandle = <0x27d>; | |
| qcom,msm-ext-disp-audio-codec-rx { | |
| compatible = "qcom,msm-ext-disp-audio-codec-rx"; | |
| qcom,msm_ext_disp = <0x27d>; | |
| linux,phandle = <0x228>; | |
| phandle = <0x228>; | |
| }; | |
| }; | |
| qcom,dp_ctrl@c990000 { | |
| status = "ok"; | |
| cell-index = <0x0>; | |
| compatible = "qcom,mdss-dp"; | |
| qcom,mdss-fb-map = <0x27e>; | |
| gdsc-supply = <0x165>; | |
| vdda-1p8-supply = <0xc9>; | |
| vdda-0p9-supply = <0x105>; | |
| reg = <0xc990000 0xa8c 0xc011000 0x910 0x1fcb200 0x50 0xc8c2200 0x1a0 0x780000 0x621c 0xc9e1000 0x2c>; | |
| reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc", "qfprom_physical", "hdcp_physical"; | |
| clocks = <0x74 0xa9 0x74 0x92 0x74 0x93 0x74 0xa2 0x74 0xa1 0x74 0x99 0x26 0x2e 0xa1 0x6e 0xa1 0x71 0x74 0x9c 0x74 0x9d 0x74 0x9a 0x74 0x9e 0x74 0x18 0x27f 0x4>; | |
| clock-names = "core_mnoc_clk", "core_iface_clk", "core_bus_clk", "core_mdp_core_clk", "core_alt_iface_clk", "core_aux_clk", "core_ref_clk_src", "core_ref_clk", "core_ahb_phy_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent"; | |
| qcom,dp-usbpd-detection = <0x176>; | |
| qcom,msm_ext_disp = <0x27d>; | |
| qcom,aux-cfg0-settings = [20 00]; | |
| qcom,aux-cfg1-settings = <0x2413231d>; | |
| qcom,aux-cfg2-settings = [28 00]; | |
| qcom,aux-cfg3-settings = [2c 00]; | |
| qcom,aux-cfg4-settings = [30 0a]; | |
| qcom,aux-cfg5-settings = [34 28]; | |
| qcom,aux-cfg6-settings = [38 0a]; | |
| qcom,aux-cfg7-settings = [3c 03]; | |
| qcom,aux-cfg8-settings = [40 b7]; | |
| qcom,aux-cfg9-settings = [44 03]; | |
| qcom,logical2physical-lane-map = <0x10203>; | |
| qcom,phy-register-offset = <0x4>; | |
| qcom,max-pclk-frequency-khz = <0x493e0>; | |
| pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; | |
| pinctrl-0 = <0x280 0x281>; | |
| pinctrl-1 = <0x282 0x283>; | |
| qcom,aux-en-gpio = <0xe7 0x37 0x0>; | |
| qcom,aux-sel-gpio = <0xe7 0x38 0x0>; | |
| qcom,usbplug-cc-gpio = <0xe7 0x3a 0x0>; | |
| linux,phandle = <0x266>; | |
| phandle = <0x266>; | |
| qcom,core-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,core-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-min-voltage = <0x0>; | |
| qcom,supply-max-voltage = <0x0>; | |
| qcom,supply-enable-load = <0x0>; | |
| qcom,supply-disable-load = <0x0>; | |
| }; | |
| }; | |
| qcom,ctrl-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,ctrl-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "vdda-1p8"; | |
| qcom,supply-min-voltage = <0x1b2920>; | |
| qcom,supply-max-voltage = <0x1dc130>; | |
| qcom,supply-enable-load = <0x3110>; | |
| qcom,supply-disable-load = <0x4>; | |
| }; | |
| }; | |
| qcom,phy-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,phy-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "vdda-0p9"; | |
| qcom,supply-min-voltage = <0xd6d80>; | |
| qcom,supply-max-voltage = <0xe1d48>; | |
| qcom,supply-enable-load = <0x11eb8>; | |
| qcom,supply-disable-load = <0x20>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_rotator { | |
| compatible = "qcom,sde_rotator"; | |
| reg = <0xc900000 0xab100 0xc9b0000 0x1040>; | |
| reg-names = "mdp_phys", "rot_vbif_phys"; | |
| qcom,mdss-rot-mode = <0x1>; | |
| qcom,mdss-highest-bank-bit = <0x1>; | |
| qcom,msm-bus,name = "mdss_rotator"; | |
| qcom,msm-bus,num-cases = <0x3>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,vectors-KBps = <0x16 0x200 0x0 0x0 0x16 0x200 0x0 0x61a800 0x16 0x200 0x0 0x61a800>; | |
| rot-vdd-supply = <0x165>; | |
| qcom,supply-names = "rot-vdd"; | |
| clocks = <0x74 0xa9 0x74 0x92 0x74 0xba 0x74 0xa5 0x74 0x93>; | |
| clock-names = "mnoc_clk", "iface_clk", "rot_core_clk", "rot_clk", "axi_clk"; | |
| interrupt-parent = <0x275>; | |
| interrupts = <0x2 0x0>; | |
| qcom,mdss-rot-vbif-qos-setting = <0x1 0x1 0x1 0x1>; | |
| qcom,mdss-rot-xin-id = <0xe 0xf>; | |
| qcom,mdss-default-ot-rd-limit = <0x20>; | |
| qcom,mdss-default-ot-wr-limit = <0x20>; | |
| linux,phandle = <0x3c2>; | |
| phandle = <0x3c2>; | |
| qcom,sde-reg-bus { | |
| qcom,msm-bus,name = "mdss_rot_reg"; | |
| qcom,msm-bus,num-cases = <0x4>; | |
| qcom,msm-bus,num-paths = <0x1>; | |
| qcom,msm-bus,active-only; | |
| qcom,msm-bus,vectors-KBps = <0x1 0x24e 0x0 0x0 0x1 0x24e 0x0 0x12c00 0x1 0x24e 0x0 0x27100 0x1 0x24e 0x0 0x4e200>; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| linux,phandle = <0x268>; | |
| phandle = <0x268>; | |
| qcom,panel-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "wqhd-vddio"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1dc130>; | |
| qcom,supply-enable-load = <0x7d00>; | |
| qcom,supply-disable-load = <0x50>; | |
| qcom,supply-post-on-sleep = <0x2>; | |
| qcom,supply-pre-off-sleep = <0xa>; | |
| }; | |
| qcom,panel-supply-entry@1 { | |
| reg = <0x1>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-pre-on-sleep = <0x8>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| reg = <0x2>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| qcom,supply-max-voltage = <0x5b8d80>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-disable-load = <0x64>; | |
| qcom,supply-post-on-sleep = <0xa>; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_labibb_amoled { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| linux,phandle = <0x26f>; | |
| phandle = <0x26f>; | |
| qcom,panel-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "wqhd-vddio"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1dc130>; | |
| qcom,supply-enable-load = <0x7d00>; | |
| qcom,supply-disable-load = <0x50>; | |
| }; | |
| qcom,panel-supply-entry@1 { | |
| reg = <0x1>; | |
| qcom,supply-name = "vdda-3p3"; | |
| qcom,supply-min-voltage = <0x325aa0>; | |
| qcom,supply-max-voltage = <0x325aa0>; | |
| qcom,supply-enable-load = <0x3390>; | |
| qcom,supply-disable-load = <0x50>; | |
| }; | |
| qcom,panel-supply-entry@2 { | |
| reg = <0x2>; | |
| qcom,supply-name = "lab"; | |
| qcom,supply-min-voltage = <0x4630c0>; | |
| qcom,supply-max-voltage = <0x5d1420>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,panel-supply-entry@3 { | |
| reg = <0x3>; | |
| qcom,supply-name = "ibb"; | |
| qcom,supply-min-voltage = <0x3d0900>; | |
| qcom,supply-max-voltage = <0x602160>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| qcom,panel-supply-entry@4 { | |
| reg = <0x4>; | |
| qcom,supply-name = "oledb"; | |
| qcom,supply-min-voltage = <0x4c4b40>; | |
| qcom,supply-max-voltage = <0x7b98a0>; | |
| qcom,supply-enable-load = <0x186a0>; | |
| qcom,supply-disable-load = <0x64>; | |
| }; | |
| }; | |
| dsi_panel_pwr_supply_no_labibb { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| linux,phandle = <0x3c3>; | |
| phandle = <0x3c3>; | |
| qcom,panel-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "wqhd-vddio"; | |
| qcom,supply-min-voltage = <0x1b7740>; | |
| qcom,supply-max-voltage = <0x1dc130>; | |
| qcom,supply-enable-load = <0x7d00>; | |
| qcom,supply-disable-load = <0x50>; | |
| }; | |
| }; | |
| qcom,mdss_dsi_pll@c994400 { | |
| compatible = "qcom,mdss_dsi_pll_sdm660"; | |
| status = "ok"; | |
| label = "MDSS DSI 0 PLL"; | |
| cell-index = <0x0>; | |
| #clock-cells = <0x1>; | |
| reg = <0xc994400 0x588 0xc8c2300 0x8>; | |
| reg-names = "pll_base", "gdsc_base"; | |
| gdsc-supply = <0x165>; | |
| clocks = <0x74 0x92>; | |
| clock-names = "iface_clk"; | |
| clock-rate = <0x0>; | |
| qcom,dsi-pll-ssc-en; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| linux,phandle = <0x271>; | |
| phandle = <0x271>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,platform-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-min-voltage = <0x0>; | |
| qcom,supply-max-voltage = <0x0>; | |
| qcom,supply-enable-load = <0x0>; | |
| qcom,supply-disable-load = <0x0>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dsi_pll@c996400 { | |
| compatible = "qcom,mdss_dsi_pll_sdm660"; | |
| status = "ok"; | |
| label = "MDSS DSI 1 PLL"; | |
| cell-index = <0x1>; | |
| #clock-cells = <0x1>; | |
| reg = <0xc996400 0x588 0xc8c2300 0x8>; | |
| reg-names = "pll_base", "gdsc_base"; | |
| gdsc-supply = <0x165>; | |
| clocks = <0x74 0x92>; | |
| clock-names = "iface_clk"; | |
| clock-rate = <0x0>; | |
| qcom,dsi-pll-ssc-en; | |
| qcom,dsi-pll-ssc-mode = "down-spread"; | |
| linux,phandle = <0x272>; | |
| phandle = <0x272>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,platform-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-min-voltage = <0x0>; | |
| qcom,supply-max-voltage = <0x0>; | |
| qcom,supply-enable-load = <0x0>; | |
| qcom,supply-disable-load = <0x0>; | |
| }; | |
| }; | |
| }; | |
| qcom,mdss_dp_pll@c011000 { | |
| compatible = "qcom,mdss_dp_pll_sdm660"; | |
| status = "ok"; | |
| label = "MDSS DP PLL"; | |
| cell-index = <0x0>; | |
| #clock-cells = <0x1>; | |
| reg = <0xc011c00 0x190 0xc011000 0x910 0xc8c2300 0x8>; | |
| reg-names = "pll_base", "phy_base", "gdsc_base"; | |
| gdsc-supply = <0x165>; | |
| clocks = <0x74 0x92 0x26 0x2e 0xa1 0x6e>; | |
| clock-names = "iface_clk", "ref_clk_src", "ref_clk"; | |
| clock-rate = <0x0>; | |
| linux,phandle = <0x27f>; | |
| phandle = <0x27f>; | |
| qcom,platform-supply-entries { | |
| #address-cells = <0x1>; | |
| #size-cells = <0x0>; | |
| qcom,platform-supply-entry@0 { | |
| reg = <0x0>; | |
| qcom,supply-name = "gdsc"; | |
| qcom,supply-min-voltage = <0x0>; | |
| qcom,supply-max-voltage = <0x0>; | |
| qcom,supply-enable-load = <0x0>; | |
| qcom,supply-disable-load = <0x0>; | |
| }; | |
| }; | |
| }; | |
| qcom,camera-flash@0 { | |
| cell-index = <0x0>; | |
| compatible = "qcom,camera-flash"; | |
| qcom,flash-source = <0x284 0x285>; | |
| qcom,torch-source = <0x286 0x287>; | |
| qcom,switch-source = <0x288>; | |
| status = "ok"; | |
| linux,phandle = <0x1dd>; | |
| phandle = <0x1dd>; | |
| }; | |
| cam_avdd_fixed_regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "cam_avdd_gpio_regulator"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| enable-active-high; | |
| gpio = <0xe7 0x3e 0x0>; | |
| vin-supply = <0xae>; | |
| linux,phandle = <0x1d3>; | |
| phandle = <0x1d3>; | |
| }; | |
| cam_rear_avdd_fixed_regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "cam_rear_avdd_gpio_regulator"; | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| enable-active-high; | |
| gpio = <0xe7 0x2e 0x0>; | |
| vin-supply = <0xae>; | |
| linux,phandle = <0x1cd>; | |
| phandle = <0x1cd>; | |
| }; | |
| cam_dvdd_fixed_regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "cam_dvdd_gpio_regulator"; | |
| regulator-min-microvolt = <0x149970>; | |
| regulator-max-microvolt = <0x149970>; | |
| enable-active-high; | |
| gpio = <0x264 0x3 0x0>; | |
| vin-supply = <0x289>; | |
| linux,phandle = <0x1ce>; | |
| phandle = <0x1ce>; | |
| }; | |
| cam_rear_dvdd_fixed_regulator { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "cam_rear_dvdd_gpio_regulator"; | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-max-microvolt = <0x124f80>; | |
| enable-active-high; | |
| gpio = <0x264 0x4 0x0>; | |
| vin-supply = <0x289>; | |
| linux,phandle = <0x1d4>; | |
| phandle = <0x1d4>; | |
| }; | |
| goodix_fp { | |
| compatible = "goodix,fingerprint"; | |
| interrupt-parent = <0xe7>; | |
| interrupt = <0x48 0x0>; | |
| vcc_spi-supply = <0x28a>; | |
| vcc_ana-supply = <0x28a>; | |
| vdd_io-supply = <0x28a>; | |
| fp-gpio-irq = <0xe7 0x48 0x0>; | |
| fp-gpio-reset = <0xe7 0x14 0x0>; | |
| status = "okay"; | |
| }; | |
| fpc1020 { | |
| status = "ok"; | |
| compatible = "fpc,fpc1020"; | |
| interrupt-parent = <0xe7>; | |
| interrupts = <0x48 0x0>; | |
| fpc,gpio_rst = <0xe7 0x14 0x0>; | |
| fpc,gpio_irq = <0xe7 0x48 0x0>; | |
| vcc_spi-supply = <0x28b>; | |
| vdd_io-supply = <0x28b>; | |
| vdd_ana-supply = <0x28b>; | |
| pinctrl-names = "fpc1020_reset_reset", "fpc1020_reset_active", "fpc1020_irq_active"; | |
| pinctrl-0 = <0x28c>; | |
| pinctrl-1 = <0x28d>; | |
| pinctrl-2 = <0x28e>; | |
| }; | |
| qcom,msm-ssc-sensors { | |
| compatible = "qcom,msm-ssc-sensors"; | |
| }; | |
| ant_check { | |
| compatible = "ant_check"; | |
| ant_check_gpio = <0xe7 0x4a 0x0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x28f>; | |
| }; | |
| }; | |
| chosen { | |
| pureason = <0x40001>; | |
| linux,initrd-end = <0x0 0x444138c7>; | |
| linux,initrd-start = <0x0 0x43400000>; | |
| kaslr-seed = <0x0 0x0>; | |
| stdout-path = "serial0"; | |
| bootargs = "rcupdate.rcu_expedited=1 console=ttyMSM0,115200,n8 androidboot.console=ttyMSM0 earlycon=msm_serial_dm,0xc170000 androidboot.hardware=qcom user_debug=31 msm_rtb.filter=0x37 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 sched_enable_hmp=1 sched_enable_power_aware=1 service_locator.enable=1 swiotlb=1 firmware_class.path=/vendor/firmware_mnt/image loop.max_part=7 androidboot.selinux=permissive buildvariant=eng androidboot.verifiedbootstate=orange androidboot.keymaster=1 root=PARTUUID=2a7f6d6d-1c23-febe-7efb-9ccfa1432ace androidboot.bootdevice=c0c4000.sdhci androidboot.serialno=ac1dde4e androidboot.cpuid=0x39148c8c androidboot.dp=0x0 androidboot.baseband=sdm mdss_mdp.panel=1:dsi:0:qcom,mdss_dsi_nt36672a_tianma_fhdplus_video:config0:1:none:cfg:single_dsi rootwait ro init=/init androidboot.dtbo_idx=0 androidboot.fpsensor=fpc androidboot.secureboot=1 androidboot.hwc=Global androidboot.hwversion=1.29.0 androidboot.hwlevel=MP androidboot.hwdevice=lavender"; | |
| }; | |
| aliases { | |
| serial0 = "/soc/serial@0c170000"; | |
| sdhc1 = "/soc/sdhci@c0c4000"; | |
| sdhc2 = "/soc/sdhci@c084000"; | |
| spi1 = "/soc/spi@c175000"; | |
| spi2 = "/soc/spi@c176000"; | |
| spi3 = "/soc/spi@c177000"; | |
| spi4 = "/soc/spi@c178000"; | |
| spi5 = "/soc/spi@c1b5000"; | |
| spi6 = "/soc/spi@c1b6000"; | |
| spi7 = "/soc/spi@c1b7000"; | |
| spi8 = "/soc/spi@c1b8000"; | |
| i2c1 = "/soc/i2c@c175000"; | |
| i2c2 = "/soc/i2c@c176000"; | |
| i2c3 = "/soc/i2c@c177000"; | |
| i2c4 = "/soc/i2c@c178000"; | |
| i2c5 = "/soc/i2c@c1b5000"; | |
| i2c6 = "/soc/i2c@c1b6000"; | |
| i2c7 = "/soc/i2c@c1b7000"; | |
| i2c8 = "/soc/i2c@c1b8000"; | |
| }; | |
| memory { | |
| device_type = "memory"; | |
| reg = <0x0 0x40000000 0x0 0x60000000 0x0 0xa0000000 0x0 0x5eac0000>; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| clocks { | |
| xo_board { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x0>; | |
| clock-frequency = <0x124f800>; | |
| clock-output-names = "xo_board"; | |
| }; | |
| sleep_clk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x0>; | |
| clock-frequency = <0x7ffc>; | |
| clock-output-names = "sleep_clk"; | |
| }; | |
| }; | |
| firmware { | |
| linux,phandle = <0x3c4>; | |
| phandle = <0x3c4>; | |
| android { | |
| compatible = "android,firmware"; | |
| vbmeta { | |
| compatible = "android,vbmeta"; | |
| parts = "vbmeta,boot,system,vendor,dtbo,recovery"; | |
| }; | |
| fstab { | |
| compatible = "android,fstab"; | |
| vendor { | |
| compatible = "android,vendor"; | |
| dev = "/dev/block/platform/soc/c0c4000.sdhci/by-name/vendor"; | |
| type = "ext4"; | |
| mnt_flags = "ro,barrier=1,discard"; | |
| fsmgr_flags = "wait"; | |
| status = "ok"; | |
| }; | |
| }; | |
| }; | |
| }; | |
| reserved-memory { | |
| #address-cells = <0x2>; | |
| #size-cells = <0x2>; | |
| ranges; | |
| wlan_msa_guard@85600000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x85600000 0x0 0x100000>; | |
| linux,phandle = <0x3c5>; | |
| phandle = <0x3c5>; | |
| }; | |
| wlan_msa_mem@85700000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x85700000 0x0 0x100000>; | |
| linux,phandle = <0xf9>; | |
| phandle = <0xf9>; | |
| }; | |
| removed_regions@85800000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x85800000 0x0 0x3700000>; | |
| linux,phandle = <0x3c6>; | |
| phandle = <0x3c6>; | |
| }; | |
| modem_fw_region@8ac00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x8ac00000 0x0 0x7e00000>; | |
| linux,phandle = <0x101>; | |
| phandle = <0x101>; | |
| }; | |
| adsp_fw_region@92a00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x92a00000 0x0 0x1e00000>; | |
| linux,phandle = <0xfb>; | |
| phandle = <0xfb>; | |
| }; | |
| pil_mba_region@94800000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x94800000 0x0 0x200000>; | |
| linux,phandle = <0x104>; | |
| phandle = <0x104>; | |
| }; | |
| cdsp_fw_region@94a00000 { | |
| compatible = "removed-dma-pool"; | |
| no-map; | |
| reg = <0x0 0x94a00000 0x0 0x600000>; | |
| linux,phandle = <0xfe>; | |
| phandle = <0xfe>; | |
| }; | |
| venus_fw_region { | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; | |
| reusable; | |
| alignment = <0x0 0x400000>; | |
| size = <0x0 0x800000>; | |
| linux,phandle = <0xf4>; | |
| phandle = <0xf4>; | |
| }; | |
| adsp_region { | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
| reusable; | |
| alignment = <0x0 0x400000>; | |
| size = <0x0 0x800000>; | |
| linux,phandle = <0xe9>; | |
| phandle = <0xe9>; | |
| }; | |
| qseecom_region { | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
| reusable; | |
| alignment = <0x0 0x400000>; | |
| size = <0x0 0x1400000>; | |
| linux,phandle = <0x10a>; | |
| phandle = <0x10a>; | |
| }; | |
| secure_region { | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
| reusable; | |
| alignment = <0x0 0x400000>; | |
| size = <0x0 0x5c00000>; | |
| linux,phandle = <0x10b>; | |
| phandle = <0x10b>; | |
| }; | |
| linux,cma { | |
| compatible = "shared-dma-pool"; | |
| alloc-ranges = <0x0 0x0 0x0 0xffffffff>; | |
| reusable; | |
| alignment = <0x0 0x400000>; | |
| size = <0x0 0x2c00000>; | |
| linux,cma-default; | |
| }; | |
| splash_region@9d400000 { | |
| reg = <0x0 0x9d400000 0x0 0x2400000>; | |
| label = "cont_splash_mem"; | |
| linux,phandle = <0x265>; | |
| phandle = <0x265>; | |
| }; | |
| pstore_reserve_mem_region@0 { | |
| linux,reserve-contiguous-region; | |
| linux,reserve-region; | |
| linux,remove-completely; | |
| reg = <0x0 0xa0000000 0x0 0x400000>; | |
| label = "pstore_reserve_mem"; | |
| linux,phandle = <0x3c7>; | |
| phandle = <0x3c7>; | |
| }; | |
| }; | |
| bt_wcn3990 { | |
| compatible = "qca,wcn3990"; | |
| qca,bt-vdd-core-supply = <0x290>; | |
| qca,bt-vdd-pa-supply = <0x291>; | |
| qca,bt-vdd-ldo-supply = <0x292>; | |
| qca,bt-chip-pwd-supply = <0x293>; | |
| clocks = <0x26 0x14>; | |
| clock-names = "rf_clk1"; | |
| qca,bt-vdd-core-voltage-level = <0x1b7740 0x1cfde0>; | |
| qca,bt-vdd-pa-voltage-level = <0x13e5c0 0x14e790>; | |
| qca,bt-vdd-ldo-voltage-level = <0x328980 0x33e140>; | |
| qca,bt-chip-pwd-voltage-level = <0x36ee80 0x36ee80>; | |
| qca,bt-vdd-core-current-level = <0x1>; | |
| qca,bt-vdd-pa-current-level = <0x1>; | |
| qca,bt-vdd-ldo-current-level = <0x1>; | |
| linux,phandle = <0x3c8>; | |
| phandle = <0x3c8>; | |
| }; | |
| regulator-gfx-stub { | |
| compatible = "qcom,stub-regulator"; | |
| regulator-name = "gfx_stub_corner"; | |
| regulator-min-microvolt = <0x61a80>; | |
| regulator-max-microvolt = <0x1053b0>; | |
| linux,phandle = <0x15f>; | |
| phandle = <0x15f>; | |
| }; | |
| qcom,battery-data { | |
| qcom,batt-id-range-pct = <0xf>; | |
| linux,phandle = <0x80>; | |
| phandle = <0x80>; | |
| qcom,m6100atl_4000mah { | |
| qcom, = <0x18>; | |
| qcom,max-voltage-uv = <0x432380>; | |
| qcom,fastchg-current-ma = <0xb54>; | |
| qcom,fg-cc-cv-threshold-mv = <0x1126>; | |
| qcom,nom-batt-capacity-mah = <0xfa0>; | |
| qcom,batt-id-kohm = <0x44>; | |
| qcom,battery-beta = <0x109a>; | |
| qcom,battery-full-design = <0xfa0>; | |
| qcom,battery-type = "3633204_lc_m6100_atl4000mah_fg_averaged_masterslave_sep25th2018"; | |
| qcom,checksum = <0x8156>; | |
| qcom,gui-version = "PM660GUI - 0.0.0.45"; | |
| qcom,fg-profile-data = <0x7020ad04 0x1e0bbf05 0xff1c2bfb 0xe304ad03 0xcb17222a 0xc74d295b 0x86000000 0xf000000 0xb0cc 0xcdc42fd2 0x1b000800 0xf5da2be4 0x45fd22f3 0x4bfb5513 0x1705852b 0x1c060920 0x27001400 0x19201405 0xeb0ad705 0xcf1ce702 0xc0c2a12 0x8818fc23 0xbc4d915b 0x6c000000 0xd000000 0xf807 0xd8c262c2 0x16000000 0x1aeb2be4 0x45f497eb 0x61072202 0xd1fda81a 0xa433ccff 0x7100000 0xb80f6646 0x16004000 0x6e010afa 0xff000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| }; | |
| qcom,m6100sun_4000mah { | |
| qcom, = <0x18>; | |
| qcom,max-voltage-uv = <0x432380>; | |
| qcom,fastchg-current-ma = <0xb54>; | |
| qcom,fg-cc-cv-threshold-mv = <0x1126>; | |
| qcom,nom-batt-capacity-mah = <0xfa0>; | |
| qcom,batt-id-kohm = <0x14a>; | |
| qcom,battery-beta = <0x109a>; | |
| qcom,battery-full-design = <0xfa0>; | |
| qcom,battery-type = "3632066_lc_m6100_sunwoda_4000mah_fg_averaged_masterslave_oct17th2018"; | |
| qcom,checksum = <0xfac0>; | |
| qcom,gui-version = "PM660GUI - 0.0.0.45"; | |
| qcom,fg-profile-data = <0xd01ee7fc 0xae03ee06 0xbf1c7402 0xaa0ced0b 0x9117262a 0xc84d265b 0x63000000 0xf000000 0x2ccd 0xe8c453d2 0x1c000800 0x9ae246ed 0x6dfc39fa 0x99ec5b12 0x1ff5482a 0x31060920 0x27001400 0x1d201405 0xe00aeb05 0xbb1c2003 0xd7155612 0x7818d923 0xe64d305b 0x6b000000 0xe000000 0x94d5 0x3eca89c2 0x16000000 0x850046ed 0xf30616f2 0xcdec4002 0x5faa11a 0xb433ccff 0x7100000 0xab0f6646 0x16004000 0x79010afa 0xff000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| }; | |
| qcom,m6100default_4000mah { | |
| qcom, = <0x18>; | |
| qcom,max-voltage-uv = <0x432380>; | |
| qcom,fastchg-current-ma = <0xb54>; | |
| qcom,fg-cc-cv-threshold-mv = <0x1126>; | |
| qcom,nom-batt-capacity-mah = <0xbb8>; | |
| qcom,batt-id-kohm = <0x29a>; | |
| qcom,battery-beta = <0xd6b>; | |
| qcom,battery-full-design = <0xfa0>; | |
| qcom,battery-type = "unknown-default"; | |
| qcom,checksum = <0xee03>; | |
| qcom,gui-version = "PM660GUI - 0.0.0.45"; | |
| qcom,fg-profile-data = <0xcc1f5905 0xaf0a35fc 0xee1cc501 0x45042c0a 0xd417f023 0x29448e5a 0x7c000000 0x10000000 0xbdcd 0xcacd05d2 0x22000800 0x8fe299ed 0x65fc0901 0x83f3c013 0x77d3202a 0x28060920 0x27001400 0xf01f4105 0xd10ae805 0xc61cf602 0xfb153a12 0x9118cb23 0xed4d255b 0x6a000000 0xe000000 0x4ecc 0xa4c227b2 0x19000000 0x87eb99ed 0xe606f5eb 0xcd0617fb 0x2dfc7d1a 0x9933ccff 0x7100000 0x800b6646 0x19004000 0xa8010afa 0xff000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; | |
| }; | |
| }; | |
| __symbols__ { | |
| CPU0 = "/cpus/cpu@0"; | |
| L2_0 = "/cpus/cpu@0/l2-cache"; | |
| L1_I_0 = "/cpus/cpu@0/l1-icache"; | |
| L1_D_0 = "/cpus/cpu@0/l1-dcache"; | |
| L1_TLB_0 = "/cpus/cpu@0/l1-tlb"; | |
| CPU1 = "/cpus/cpu@1"; | |
| L1_I_1 = "/cpus/cpu@1/l1-icache"; | |
| L1_D_1 = "/cpus/cpu@1/l1-dcache"; | |
| L1_TLB_1 = "/cpus/cpu@1/l1-tlb"; | |
| CPU2 = "/cpus/cpu@2"; | |
| L1_I_2 = "/cpus/cpu@2/l1-icache"; | |
| L1_D_2 = "/cpus/cpu@2/l1-dcache"; | |
| L1_TLB_2 = "/cpus/cpu@2/l1-tlb"; | |
| CPU3 = "/cpus/cpu@3"; | |
| L1_I_3 = "/cpus/cpu@3/l1-icache"; | |
| L1_D_3 = "/cpus/cpu@3/l1-dcache"; | |
| L1_TLB_3 = "/cpus/cpu@3/l1-tlb"; | |
| CPU4 = "/cpus/cpu@100"; | |
| L2_1 = "/cpus/cpu@100/l2-cache"; | |
| L1_I_100 = "/cpus/cpu@100/l1-icache"; | |
| L1_D_100 = "/cpus/cpu@100/l1-dcache"; | |
| L1_TLB_100 = "/cpus/cpu@100/l1-tlb"; | |
| CPU5 = "/cpus/cpu@101"; | |
| L1_I_101 = "/cpus/cpu@101/l1-icache"; | |
| L1_D_101 = "/cpus/cpu@101/l1-dcache"; | |
| L1_TLB_101 = "/cpus/cpu@101/l1-tlb"; | |
| CPU6 = "/cpus/cpu@102"; | |
| L1_I_102 = "/cpus/cpu@102/l1-icache"; | |
| L1_D_102 = "/cpus/cpu@102/l1-dcache"; | |
| L1_TLB_102 = "/cpus/cpu@102/l1-tlb"; | |
| CPU7 = "/cpus/cpu@103"; | |
| L1_I_103 = "/cpus/cpu@103/l1-icache"; | |
| L1_D_103 = "/cpus/cpu@103/l1-dcache"; | |
| L1_TLB_103 = "/cpus/cpu@103/l1-tlb"; | |
| soc = "/soc"; | |
| smp2pgpio_smp2p_15_in = "/soc/qcom,smp2pgpio-smp2p-15-in"; | |
| smp2pgpio_smp2p_15_out = "/soc/qcom,smp2pgpio-smp2p-15-out"; | |
| smp2pgpio_smp2p_1_in = "/soc/qcom,smp2pgpio-smp2p-1-in"; | |
| smp2pgpio_smp2p_1_out = "/soc/qcom,smp2pgpio-smp2p-1-out"; | |
| smp2pgpio_smp2p_2_in = "/soc/qcom,smp2pgpio-smp2p-2-in"; | |
| smp2pgpio_smp2p_2_out = "/soc/qcom,smp2pgpio-smp2p-2-out"; | |
| smp2pgpio_sleepstate_2_out = "/soc/qcom,smp2pgpio-sleepstate-gpio-2-out"; | |
| smp2pgpio_smp2p_5_in = "/soc/qcom,smp2pgpio-smp2p-5-in"; | |
| smp2pgpio_smp2p_5_out = "/soc/qcom,smp2pgpio-smp2p-5-out"; | |
| smp2pgpio_ssr_smp2p_1_in = "/soc/qcom,smp2pgpio-ssr-smp2p-1-in"; | |
| smp2pgpio_ssr_smp2p_1_out = "/soc/qcom,smp2pgpio-ssr-smp2p-1-out"; | |
| smp2pgpio_ssr_smp2p_2_in = "/soc/qcom,smp2pgpio-ssr-smp2p-2-in"; | |
| smp2pgpio_ssr_smp2p_2_out = "/soc/qcom,smp2pgpio-ssr-smp2p-2-out"; | |
| smp2pgpio_ssr_smp2p_5_in = "/soc/qcom,smp2pgpio-ssr-smp2p-5-in"; | |
| smp2pgpio_ssr_smp2p_5_out = "/soc/qcom,smp2pgpio-ssr-smp2p-5-out"; | |
| tmc_etr = "/soc/tmc@6048000"; | |
| tmc_etr_in_replicator = "/soc/tmc@6048000/port/endpoint"; | |
| replicator = "/soc/replicator@6046000"; | |
| replicator_out_tmc_etr = "/soc/replicator@6046000/ports/port@0/endpoint"; | |
| replicator_in_tmc_etf = "/soc/replicator@6046000/ports/port@1/endpoint"; | |
| tmc_etf = "/soc/tmc@6047000"; | |
| tmc_etf_out_replicator = "/soc/tmc@6047000/ports/port@0/endpoint"; | |
| tmc_etf_in_funnel_merg = "/soc/tmc@6047000/ports/port@1/endpoint"; | |
| funnel_merg = "/soc/funnel@6045000"; | |
| funnel_merg_out_tmc_etf = "/soc/funnel@6045000/ports/port@0/endpoint"; | |
| funnel_merg_in_funnel_in0 = "/soc/funnel@6045000/ports/port@1/endpoint"; | |
| funnel_merg_in_funnel_in1 = "/soc/funnel@6045000/ports/port@2/endpoint"; | |
| funnel_in0 = "/soc/funnel@6041000"; | |
| funnel_in0_out_funnel_merg = "/soc/funnel@6041000/ports/port@0/endpoint"; | |
| funnel_in0_in_funnel_qatb = "/soc/funnel@6041000/ports/port@2/endpoint"; | |
| funnel_in0_in_stm = "/soc/funnel@6041000/ports/port@3/endpoint"; | |
| funnel_in0_in_rpm_etm0 = "/soc/funnel@6041000/ports/port@4/endpoint"; | |
| funnel_in1 = "/soc/funnel@6042000"; | |
| funnel_in1_out_funnel_merg = "/soc/funnel@6042000/ports/port@0/endpoint"; | |
| funnel_in1_in_tpda_nav = "/soc/funnel@6042000/ports/port@1/endpoint"; | |
| funnel_in1_in_modem_etm0 = "/soc/funnel@6042000/ports/port@2/endpoint"; | |
| funnel_in1_in_funnel_apss_merg = "/soc/funnel@6042000/ports/port@3/endpoint"; | |
| funnel_in1_in_turing_etm0 = "/soc/funnel@6042000/ports/port@4/endpoint"; | |
| funnel_apss_merg = "/soc/funnel@7b70000"; | |
| funnel_apss_merg_out_funnel_in1 = "/soc/funnel@7b70000/ports/port@0/endpoint"; | |
| funnel_apss_merg_in_funnel_apss = "/soc/funnel@7b70000/ports/port@1/endpoint"; | |
| funnel_apss_merg_in_tpda_olc = "/soc/funnel@7b70000/ports/port@2/endpoint"; | |
| funnel_apss_merg_in_tpda_apss = "/soc/funnel@7b70000/ports/port@3/endpoint"; | |
| funnel_apss = "/soc/funnel@7b60000"; | |
| funnel_apss_out_funnel_apss_merg = "/soc/funnel@7b60000/ports/port@0/endpoint"; | |
| funnel_apss_in_etm0 = "/soc/funnel@7b60000/ports/port@1/endpoint"; | |
| funnel_apss_in_etm1 = "/soc/funnel@7b60000/ports/port@2/endpoint"; | |
| funnel_apss_in_etm2 = "/soc/funnel@7b60000/ports/port@3/endpoint"; | |
| funnel_apss_in_etm3 = "/soc/funnel@7b60000/ports/port@4/endpoint"; | |
| funnel_apss_in_etm4 = "/soc/funnel@7b60000/ports/port@5/endpoint"; | |
| funnel_apss_in_etm5 = "/soc/funnel@7b60000/ports/port@6/endpoint"; | |
| funnel_apss_in_etm6 = "/soc/funnel@7b60000/ports/port@7/endpoint"; | |
| funnel_apss_in_etm7 = "/soc/funnel@7b60000/ports/port@8/endpoint"; | |
| stm = "/soc/stm@6002000"; | |
| stm_out_funnel_in0 = "/soc/stm@6002000/port/endpoint"; | |
| etm0 = "/soc/etm@7840000"; | |
| etm0_out_funnel_apss = "/soc/etm@7840000/port/endpoint"; | |
| etm1 = "/soc/etm@7940000"; | |
| etm1_out_funnel_apss = "/soc/etm@7940000/port/endpoint"; | |
| etm2 = "/soc/etm@7a40000"; | |
| etm2_out_funnel_apss = "/soc/etm@7a40000/port/endpoint"; | |
| etm3 = "/soc/etm@7b40000"; | |
| etm3_out_funnel_apss = "/soc/etm@7b40000/port/endpoint"; | |
| etm4 = "/soc/etm@7c40000"; | |
| etm4_out_funnel_apss = "/soc/etm@7c40000/port/endpoint"; | |
| etm5 = "/soc/etm@7d40000"; | |
| etm5_out_funnel_apss = "/soc/etm@7d40000/port/endpoint"; | |
| etm6 = "/soc/etm@7e40000"; | |
| etm6_out_funnel_apss = "/soc/etm@7e40000/port/endpoint"; | |
| etm7 = "/soc/etm@7f40000"; | |
| etm7_out_funnel_apss = "/soc/etm@7f40000/port/endpoint"; | |
| cti0 = "/soc/cti@6010000"; | |
| cti1 = "/soc/cti@6011000"; | |
| cti2 = "/soc/cti@6012000"; | |
| cti3 = "/soc/cti@6013000"; | |
| cti4 = "/soc/cti@6014000"; | |
| cti5 = "/soc/cti@6015000"; | |
| cti6 = "/soc/cti@6016000"; | |
| cti7 = "/soc/cti@6017000"; | |
| cti8 = "/soc/cti@6018000"; | |
| cti9 = "/soc/cti@6019000"; | |
| cti10 = "/soc/cti@601a000"; | |
| cti11 = "/soc/cti@601b000"; | |
| cti12 = "/soc/cti@601c000"; | |
| cti13 = "/soc/cti@601d000"; | |
| cti14 = "/soc/cti@601e000"; | |
| cti15 = "/soc/cti@601f000"; | |
| cti_cpu0 = "/soc/cti@7820000"; | |
| cti_cpu1 = "/soc/cti@7920000"; | |
| cti_cpu2 = "/soc/cti@7a20000"; | |
| cti_cpu3 = "/soc/cti@7b20000"; | |
| cti_cpu4 = "/soc/cti@7c20000"; | |
| cti_cpu5 = "/soc/cti@7d20000"; | |
| cti_cpu6 = "/soc/cti@7e20000"; | |
| cti_cpu7 = "/soc/cti@7f20000"; | |
| cti_apss = "/soc/cti@7b80000"; | |
| cti_apss_dl = "/soc/cti@7bc1000"; | |
| cti_olc = "/soc/cti@7b91000"; | |
| cti_turing = "/soc/cti@7068000"; | |
| cti_wcss0 = "/soc/cti@71a4000"; | |
| cti_wcss1 = "/soc/cti@71a5000"; | |
| cti_wcss2 = "/soc/cti@71a6000"; | |
| cti_mmss = "/soc/cti@7188000"; | |
| cti_isdb = "/soc/cti@7121000"; | |
| cti_rpm = "/soc/cti@7048000"; | |
| cti_mss = "/soc/cti@7041000"; | |
| qpdi = "/soc/qpdi@1fc1000"; | |
| funnel_qatb = "/soc/funnel@6005000"; | |
| funnel_qatb_out_funnel_in0 = "/soc/funnel@6005000/ports/port@0/endpoint"; | |
| funnel_qatb_in_tpda = "/soc/funnel@6005000/ports/port@1/endpoint"; | |
| funnel_qatb_in_funnel_dlct = "/soc/funnel@6005000/ports/port@2/endpoint"; | |
| tpda = "/soc/tpda@6004000"; | |
| tpda_out_funnel_qatb = "/soc/tpda@6004000/ports/port@0/endpoint"; | |
| tpda_in_funnel_dlct = "/soc/tpda@6004000/ports/port@2/endpoint"; | |
| tpda_in_tpdm_vsense = "/soc/tpda@6004000/ports/port@3/endpoint"; | |
| tpda_in_tpdm_dcc = "/soc/tpda@6004000/ports/port@4/endpoint"; | |
| tpda_in_tpdm_prng = "/soc/tpda@6004000/ports/port@5/endpoint"; | |
| tpda_in_tpdm_qm = "/soc/tpda@6004000/ports/port@6/endpoint"; | |
| tpda_in_tpdm_pimem = "/soc/tpda@6004000/ports/port@7/endpoint"; | |
| tpda_in_tpdm = "/soc/tpda@6004000/ports/port@8/endpoint"; | |
| tpdm_vsense = "/soc/tpdm@7038000"; | |
| tpdm_vsense_out_tpda = "/soc/tpdm@7038000/port/endpoint"; | |
| tpdm_dcc = "/soc/tpdm@7054000"; | |
| tpdm_dcc_out_tpda = "/soc/tpdm@7054000/port/endpoint"; | |
| tpdm_prng = "/soc/tpdm@704c000"; | |
| tpdm_prng_out_tpda = "/soc/tpdm@704c000/port/endpoint"; | |
| tpdm_qm = "/soc/tpdm@71d0000"; | |
| tpdm_qm_out_tpda = "/soc/tpdm@71d0000/port/endpoint"; | |
| tpdm_pimem = "/soc/tpdm@7050000"; | |
| tpdm_pimem_out_tpda = "/soc/tpdm@7050000/port/endpoint"; | |
| tpdm = "/soc/tpdm@6006000"; | |
| tpdm_out_tpda = "/soc/tpdm@6006000/port/endpoint"; | |
| tpda_nav = "/soc/tpda@7191000"; | |
| tpda_nav_out_funnel_in1 = "/soc/tpda@7191000/ports/port@0/endpoint"; | |
| tpda_nav_in_tpdm_nav = "/soc/tpda@7191000/ports/port@1/endpoint"; | |
| tpda_apss = "/soc/tpda@7bc2000"; | |
| tpda_apss_out_funnel_apss_merg = "/soc/tpda@7bc2000/ports/port@0/endpoint"; | |
| tpda_apss_in_tpdm_apss = "/soc/tpda@7bc2000/ports/port@1/endpoint"; | |
| tpdm_apss = "/soc/tpdm@7bc0000"; | |
| tpdm_apss_out_tpda_apss = "/soc/tpdm@7bc0000/port/endpoint"; | |
| tpda_mss = "/soc/tpda@7043000"; | |
| tpda_mss_out_funnel_dlct = "/soc/tpda@7043000/ports/port@0/endpoint"; | |
| tpda_mss_in_tpdm_mss = "/soc/tpda@7043000/ports/port@1/endpoint"; | |
| tpdm_mss = "/soc/tpdm@7042000"; | |
| tpdm_mss_out_tpda_mss = "/soc/tpdm@7042000/port/endpoint"; | |
| tpdm_nav = "/soc/tpdm@7190000"; | |
| tpdm_nav_out_tpda_nav = "/soc/tpdm@7190000/port/endpoint"; | |
| tpda_olc = "/soc/tpda@7b92000"; | |
| tpda_olc_out_funnel_apss_merg = "/soc/tpda@7b92000/ports/port@0/endpoint"; | |
| tpda_olc_in_tpdm_olc = "/soc/tpda@7b92000/ports/port@1/endpoint"; | |
| tpdm_olc = "/soc/tpdm@7b90000"; | |
| tpdm_olc_out_tpda_olc = "/soc/tpdm@7b90000/port/endpoint"; | |
| funnel_dlct = "/soc/funnel@71c3000"; | |
| funnel_dlct_out_tpda = "/soc/funnel@71c3000/ports/port@0/endpoint"; | |
| funnel_dlct_out_funnel_qatb = "/soc/funnel@71c3000/ports/port@1/endpoint"; | |
| funnel_dlct_in_tpdm_dlct = "/soc/funnel@71c3000/ports/port@2/endpoint"; | |
| funnel_dlct_in_audio_etm0 = "/soc/funnel@71c3000/ports/port@4/endpoint"; | |
| funnel_dlct_in_tpda_mss = "/soc/funnel@71c3000/ports/port@5/endpoint"; | |
| tpdm_dlct = "/soc/tpdm@71c2000"; | |
| tpdm_dlct_out_funnel_dlct = "/soc/tpdm@71c2000/port/endpoint"; | |
| hwevent = "/soc/hwevent@158000"; | |
| csr = "/soc/csr@6001000"; | |
| modem_etm0_out_funnel_in1 = "/soc/modem_etm0/port/endpoint"; | |
| audio_etm0_out_funnel_dlct = "/soc/audio_etm0/port/endpoint"; | |
| rpm_etm0_out_funnel_in0 = "/soc/rpm_etm0/port/endpoint"; | |
| turing_etm0_out_funnel_in1 = "/soc/turing_etm0/port/endpoint"; | |
| intc = "/soc/interrupt-controller@17a00000"; | |
| dma_blsp1 = "/soc/qcom,sps-dma@0xc144000"; | |
| dma_blsp2 = "/soc/qcom,sps-dma@0xc184000"; | |
| spmi_bus = "/soc/qcom,spmi@800f000"; | |
| pm660_revid = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,revid@100"; | |
| pm660_misc = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,misc@900"; | |
| pm660_gpios = "/soc/qcom,spmi@800f000/qcom,pm660@0/gpios"; | |
| pm660_coincell = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,coincell@2800"; | |
| pm660_rtc = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,pm660_rtc"; | |
| pm660_vadc = "/soc/qcom,spmi@800f000/qcom,pm660@0/vadc@3100"; | |
| pm660_charger = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,qpnp-smb2"; | |
| smb2_vbus = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,qpnp-smb2/qcom,smb2-vbus"; | |
| smb2_vconn = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,qpnp-smb2/qcom,smb2-vconn"; | |
| pm660_pdphy = "/soc/qcom,spmi@800f000/qcom,pm660@0/qcom,usb-pdphy@1700"; | |
| pm660_adc_tm = "/soc/qcom,spmi@800f000/qcom,pm660@0/vadc@3400"; | |
| pm660_rradc = "/soc/qcom,spmi@800f000/qcom,pm660@0/rradc@4500"; | |
| pm660_fg = "/soc/qcom,spmi@800f000/qcom,pm660@0/qpnp,fg"; | |
| pm660_haptics = "/soc/qcom,spmi@800f000/qcom,pm660@1/qcom,haptic@c000"; | |
| pm660l_revid = "/soc/qcom,spmi@800f000/qcom,pm660l@2/qcom,revid@100"; | |
| pm660l_pbs = "/soc/qcom,spmi@800f000/qcom,pm660l@2/qcom,pbs@7300"; | |
| pm660l_gpios = "/soc/qcom,spmi@800f000/qcom,pm660l@2/gpios"; | |
| pm660l_3 = "/soc/qcom,spmi@800f000/qcom,pm660l@3"; | |
| pm660l_pwm_1 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/pwm@b100"; | |
| pm660l_pwm_2 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/pwm@b200"; | |
| pm660l_pwm_3 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/pwm@b300"; | |
| pm660l_pwm_4 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/pwm@b400"; | |
| red_led = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d000/qcom,rgb_0"; | |
| green_led = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d000/qcom,rgb_1"; | |
| blue_led = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d000/qcom,rgb_2"; | |
| pm660l_wled = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d800"; | |
| flash_led = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300"; | |
| pm660l_flash0 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,flash_0"; | |
| pm660l_flash1 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,flash_1"; | |
| pm660l_flash2 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,flash_2"; | |
| pm660l_torch0 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,torch_0"; | |
| pm660l_torch1 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,torch_1"; | |
| pm660l_torch2 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,torch_2"; | |
| pm660l_switch0 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,led_switch_0"; | |
| pm660l_switch1 = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qcom,leds@d300/qcom,led_switch_1"; | |
| pm660l_lcdb = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-lcdb@ec00"; | |
| lcdb_ldo_vreg = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-lcdb@ec00/ldo"; | |
| lcdb_ncp_vreg = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-lcdb@ec00/ncp"; | |
| pm660a_oledb = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-oledb@e000"; | |
| pm660a_labibb = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-labibb-regulator"; | |
| ibb_regulator = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-labibb-regulator/qcom,ibb@dc00"; | |
| lab_regulator = "/soc/qcom,spmi@800f000/qcom,pm660l@3/qpnp-labibb-regulator/qcom,lab@de00"; | |
| pmic_analog_codec = "/soc/qcom,spmi@800f000/qcom,pm660l@3/analog-codec@f000"; | |
| msm_digital_codec = "/soc/qcom,spmi@800f000/qcom,pm660l@3/analog-codec@f000/msm-dig-codec"; | |
| wdog = "/soc/qcom,wdt@17817000"; | |
| mem_client_3_size = "/soc/qcom,memshare/qcom,client_3"; | |
| tsens = "/soc/tsens@10ad000"; | |
| uartblsp1dm1 = "/soc/serial@0c170000"; | |
| sensor_information0 = "/soc/qcom,sensor-information/qcom,sensor-information-0"; | |
| sensor_information1 = "/soc/qcom,sensor-information/qcom,sensor-information-1"; | |
| sensor_information2 = "/soc/qcom,sensor-information/qcom,sensor-information-2"; | |
| sensor_information3 = "/soc/qcom,sensor-information/qcom,sensor-information-3"; | |
| sensor_information4 = "/soc/qcom,sensor-information/qcom,sensor-information-4"; | |
| sensor_information5 = "/soc/qcom,sensor-information/qcom,sensor-information-5"; | |
| sensor_information6 = "/soc/qcom,sensor-information/qcom,sensor-information-6"; | |
| sensor_information7 = "/soc/qcom,sensor-information/qcom,sensor-information-7"; | |
| sensor_information8 = "/soc/qcom,sensor-information/qcom,sensor-information-8"; | |
| sensor_information9 = "/soc/qcom,sensor-information/qcom,sensor-information-9"; | |
| sensor_information10 = "/soc/qcom,sensor-information/qcom,sensor-information-10"; | |
| sensor_information11 = "/soc/qcom,sensor-information/qcom,sensor-information-11"; | |
| sensor_information12 = "/soc/qcom,sensor-information/qcom,sensor-information-12"; | |
| sensor_information13 = "/soc/qcom,sensor-information/qcom,sensor-information-13"; | |
| sensor_information14 = "/soc/qcom,sensor-information/qcom,sensor-information-14"; | |
| sensor_information15 = "/soc/qcom,sensor-information/qcom,sensor-information-15"; | |
| sensor_information16 = "/soc/qcom,sensor-information/qcom,sensor-information-16"; | |
| sensor_information17 = "/soc/qcom,sensor-information/qcom,sensor-information-17"; | |
| sensor_information18 = "/soc/qcom,sensor-information/qcom,sensor-information-18"; | |
| sensor_information19 = "/soc/qcom,sensor-information/qcom,sensor-information-19"; | |
| sensor_information20 = "/soc/qcom,sensor-information/qcom,sensor-information-20"; | |
| sensor_information21 = "/soc/qcom,sensor-information/qcom,sensor-information-21"; | |
| sensor_information22 = "/soc/qcom,sensor-information/qcom,sensor-information-22"; | |
| mitigation_profile0 = "/soc/qcom,limit_info-0"; | |
| mitigation_profile1 = "/soc/qcom,limit_info-1"; | |
| mitigation_profile2 = "/soc/qcom,limit_info-2"; | |
| mitigation_profile3 = "/soc/qcom,limit_info-3"; | |
| mitigation_profile4 = "/soc/qcom,limit_info-4"; | |
| msm_thermal_freq = "/soc/qcom,msm-thermal/qcom,vdd-apps-rstr"; | |
| cx_ipeak_lm = "/soc/cx_ipeak@1fe5040"; | |
| ea0 = "/soc/qcom,msm-core@780000/ea0"; | |
| ea1 = "/soc/qcom,msm-core@780000/ea1"; | |
| ea2 = "/soc/qcom,msm-core@780000/ea2"; | |
| ea3 = "/soc/qcom,msm-core@780000/ea3"; | |
| ea4 = "/soc/qcom,msm-core@780000/ea4"; | |
| ea5 = "/soc/qcom,msm-core@780000/ea5"; | |
| ea6 = "/soc/qcom,msm-core@780000/ea6"; | |
| ea7 = "/soc/qcom,msm-core@780000/ea7"; | |
| uartblsp2dm1 = "/soc/serial@0c1b0000"; | |
| slim_aud = "/soc/slim@151c0000"; | |
| wcd9335 = "/soc/slim@151c0000/tasha_codec"; | |
| wsa_spkr_sd1 = "/soc/slim@151c0000/tasha_codec/msm_cdc_pinctrll"; | |
| wsa_spkr_sd2 = "/soc/slim@151c0000/tasha_codec/msm_cdc_pinctrlr"; | |
| tasha_hph_en0 = "/soc/slim@151c0000/tasha_codec/msm_cdc_pinctrl_hph_en0"; | |
| tasha_hph_en1 = "/soc/slim@151c0000/tasha_codec/msm_cdc_pinctrl_hph_en1"; | |
| wsa881x_211 = "/soc/slim@151c0000/tasha_codec/swr_master/wsa881x@20170211"; | |
| wsa881x_212 = "/soc/slim@151c0000/tasha_codec/swr_master/wsa881x@20170212"; | |
| wsa881x_213 = "/soc/slim@151c0000/tasha_codec/swr_master/wsa881x@21170213"; | |
| wsa881x_214 = "/soc/slim@151c0000/tasha_codec/swr_master/wsa881x@21170214"; | |
| wcd934x_cdc = "/soc/slim@151c0000/tavil_codec"; | |
| wcd = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5"; | |
| us_euro_sw_wcd_active = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/us_euro_sw_wcd_active"; | |
| us_euro_sw_wcd_sleep = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/us_euro_sw_wcd_sleep"; | |
| spkr_1_wcd_en_active = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/spkr_1_wcd_en_active"; | |
| spkr_1_wcd_en_sleep = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/spkr_1_wcd_en_sleep"; | |
| spkr_2_wcd_en_active = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/spkr_2_sd_n_active"; | |
| spkr_2_wcd_en_sleep = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/spkr_2_sd_n_sleep"; | |
| hph_en0_wcd_active = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/hph_en0_wcd_active"; | |
| hph_en0_wcd_sleep = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/hph_en0_wcd_sleep"; | |
| hph_en1_wcd_active = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/hph_en1_wcd_active"; | |
| hph_en1_wcd_sleep = "/soc/slim@151c0000/tavil_codec/wcd_pinctrl@5/hph_en1_wcd_sleep"; | |
| wsa_spkr_wcd_sd1 = "/soc/slim@151c0000/tavil_codec/msm_cdc_pinctrll"; | |
| wsa_spkr_wcd_sd2 = "/soc/slim@151c0000/tavil_codec/msm_cdc_pinctrlr"; | |
| tavil_us_euro_sw = "/soc/slim@151c0000/tavil_codec/msm_cdc_pinctrl_us_euro_sw"; | |
| tavil_hph_en0 = "/soc/slim@151c0000/tavil_codec/msm_cdc_pinctrl_hph_en0"; | |
| tavil_hph_en1 = "/soc/slim@151c0000/tavil_codec/msm_cdc_pinctrl_hph_en1"; | |
| wsa881x_0211 = "/soc/slim@151c0000/tavil_codec/swr_master/wsa881x@20170211"; | |
| wsa881x_0212 = "/soc/slim@151c0000/tavil_codec/swr_master/wsa881x@20170212"; | |
| wsa881x_0213 = "/soc/slim@151c0000/tavil_codec/swr_master/wsa881x@21170213"; | |
| wsa881x_0214 = "/soc/slim@151c0000/tavil_codec/swr_master/wsa881x@21170214"; | |
| wcd_spi_0 = "/soc/slim@151c0000/tavil_codec/wcd_spi"; | |
| dai_slim = "/soc/slim@151c0000/msm_dai_slim"; | |
| slim_qca = "/soc/slim@15240000"; | |
| btfmslim_codec = "/soc/slim@15240000/wcn3990"; | |
| clock_rpmcc = "/soc/qcom,rpmcc"; | |
| clock_gcc = "/soc/clock-controller@100000"; | |
| clock_mmss = "/soc/clock-controller@c8c0000"; | |
| clock_gpu = "/soc/clock-controller@5065000"; | |
| clock_gfx = "/soc/gfx@5065000"; | |
| cpu_debug = "/soc/syscon@1791101c"; | |
| gpu_debug = "/soc/syscon@05065120"; | |
| mmss_debug = "/soc/syscon@c8c0900"; | |
| clock_debug = "/soc/qcom,cc-debug@62000"; | |
| cpubw = "/soc/qcom,cpubw"; | |
| bwmon = "/soc/qcom,cpu-bwmon"; | |
| mincpubw = "/soc/qcom,mincpubw"; | |
| memlat_cpu0 = "/soc/qcom,memlat-cpu0"; | |
| memlat_cpu4 = "/soc/qcom,memlat-cpu4"; | |
| devfreq_memlat_0 = "/soc/qcom,arm-memlat-mon-0"; | |
| devfreq_memlat_4 = "/soc/qcom,arm-memlat-mon-4"; | |
| devfreq_cpufreq = "/soc/devfreq-cpufreq"; | |
| clock_cpu = "/soc/qcom,clk-cpu-660@179c0000"; | |
| lmh_dcvs0 = "/soc/qcom,clk-cpu-660@179c0000/qcom,limits-dcvs@0"; | |
| lmh_dcvs1 = "/soc/qcom,clk-cpu-660@179c0000/qcom,limits-dcvs@1"; | |
| msm_cpufreq = "/soc/qcom,msm-cpufreq"; | |
| sdhc_1 = "/soc/sdhci@c0c4000"; | |
| sdhc_2 = "/soc/sdhci@c084000"; | |
| ipa_hw = "/soc/qcom,ipa@14780000"; | |
| ipa_smmu_ap = "/soc/qcom,ipa@14780000/ipa_smmu_ap"; | |
| ipa_smmu_wlan = "/soc/qcom,ipa@14780000/ipa_smmu_wlan"; | |
| ipa_smmu_uc = "/soc/qcom,ipa@14780000/ipa_smmu_uc"; | |
| dcc = "/soc/dcc@10b3000"; | |
| glink_qos_adsp = "/soc/qcom,glink-qos-config-adsp"; | |
| glink_mpss = "/soc/qcom,glink-ssr-modem"; | |
| glink_lpass = "/soc/qcom,glink-ssr-adsp"; | |
| glink_rpm = "/soc/qcom,glink-ssr-rpm"; | |
| glink_cdsp = "/soc/qcom,glink-ssr-cdsp"; | |
| glink_spi_xprt_wdsp = "/soc/qcom,glink-spi-xprt-wdsp"; | |
| glink_fifo_wdsp = "/soc/qcom,glink-fifo-config-wdsp"; | |
| glink_qos_wdsp = "/soc/qcom,glink-qos-config-wdsp"; | |
| rpm_bus = "/soc/qcom,rpm-smd"; | |
| pm660_s4 = "/soc/qcom,rpm-smd/rpm-regulator-smpa4/regulator-s4"; | |
| pm660_s5 = "/soc/qcom,rpm-smd/rpm-regulator-smpa5/regulator-s5"; | |
| pm660_s6 = "/soc/qcom,rpm-smd/rpm-regulator-smpa6/regulator-s6"; | |
| pm660_l1 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa1/regulator-l1"; | |
| pm660_l2 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa2/regulator-l2"; | |
| pm660_l3 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa3/regulator-l3"; | |
| pm660_l5 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa5/regulator-l5"; | |
| pm660_l6 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa6/regulator-l6"; | |
| pm660_l6_pin_ctrl = "/soc/qcom,rpm-smd/rpm-regulator-ldoa6/regulator-l6-pin-ctrl"; | |
| pm660_l7 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa7/regulator-l7"; | |
| pm660_l8 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa8/regulator-l8"; | |
| pm660_l9 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa9/regulator-l9"; | |
| pm660_l9_pin_ctrl = "/soc/qcom,rpm-smd/rpm-regulator-ldoa9/regulator-l9-pin-ctrl"; | |
| pm660_l10 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa10/regulator-l10"; | |
| pm660_l11 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa11/regulator-l11"; | |
| pm660_l12 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa12/regulator-l12"; | |
| pm660_l13 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa13/regulator-l13"; | |
| pm660_l14 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa14/regulator-l14"; | |
| pm660_l15 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa15/regulator-l15"; | |
| pm660_l17 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa17/regulator-l17"; | |
| pm660_l19 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa19/regulator-l19"; | |
| pm660_l19_pin_ctrl = "/soc/qcom,rpm-smd/rpm-regulator-ldoa19/regulator-l19-pin-ctrl"; | |
| pm660l_s1 = "/soc/qcom,rpm-smd/rpm-regulator-smpb1/regulator-s1"; | |
| pm660l_s2 = "/soc/qcom,rpm-smd/rpm-regulator-smpb2/regulator-s2"; | |
| pm660l_s3_level = "/soc/qcom,rpm-smd/rpm-regulator-smpb3/regulator-s3-level"; | |
| pm660l_s3_floor_level = "/soc/qcom,rpm-smd/rpm-regulator-smpb3/regulator-s3-floor-level"; | |
| pm660l_s3_level_ao = "/soc/qcom,rpm-smd/rpm-regulator-smpb3/regulator-s3-level-ao"; | |
| pm660l_s5_level = "/soc/qcom,rpm-smd/rpm-regulator-smpb5/regulator-s5-level"; | |
| pm660l_s5_floor_level = "/soc/qcom,rpm-smd/rpm-regulator-smpb5/regulator-s5-floor-level"; | |
| pm660l_s5_level_ao = "/soc/qcom,rpm-smd/rpm-regulator-smpb5/regulator-s5-level-ao"; | |
| pm660l_l1 = "/soc/qcom,rpm-smd/rpm-regulator-ldob1/regulator-l1"; | |
| pm660l_l2 = "/soc/qcom,rpm-smd/rpm-regulator-ldob2/regulator-l2"; | |
| pm660l_l3 = "/soc/qcom,rpm-smd/rpm-regulator-ldob3/regulator-l3"; | |
| pm660l_l4 = "/soc/qcom,rpm-smd/rpm-regulator-ldob4/regulator-l4"; | |
| pm660l_l5 = "/soc/qcom,rpm-smd/rpm-regulator-ldob5/regulator-l5"; | |
| pm660l_l6 = "/soc/qcom,rpm-smd/rpm-regulator-ldob6/regulator-l6"; | |
| pm660l_l7 = "/soc/qcom,rpm-smd/rpm-regulator-ldob7/regulator-l7"; | |
| pm660l_l8 = "/soc/qcom,rpm-smd/rpm-regulator-ldob8/regulator-l8"; | |
| pm660l_l9_level = "/soc/qcom,rpm-smd/rpm-regulator-ldob9/regulator-l9-level"; | |
| pm660l_l9_floor_level = "/soc/qcom,rpm-smd/rpm-regulator-ldob9/regulator-l9-floor-level"; | |
| pm660l_l10_level = "/soc/qcom,rpm-smd/rpm-regulator-ldob10/regulator-l10-level"; | |
| pm660l_l10_floor_level = "/soc/qcom,rpm-smd/rpm-regulator-ldob10/regulator-l10-floor-level"; | |
| pm660l_bob = "/soc/qcom,rpm-smd/rpm-regulator-bobb/regulator-bob"; | |
| pm660l_bob_pin1 = "/soc/qcom,rpm-smd/rpm-regulator-bobb/regulator-bob-pin1"; | |
| pm660l_bob_pin2 = "/soc/qcom,rpm-smd/rpm-regulator-bobb/regulator-bob-pin2"; | |
| pm660l_bob_pin3 = "/soc/qcom,rpm-smd/rpm-regulator-bobb/regulator-bob-pin3"; | |
| pm660_l16 = "/soc/qcom,rpm-smd/rpm-regulator-ldoa16/regulator-l16"; | |
| pil_modem = "/soc/qcom,mss@4080000"; | |
| cpu_pmu = "/soc/cpu-pmu"; | |
| qcom_seecom = "/soc/qseecom@86d00000"; | |
| qcom_cedev = "/soc/qcedev@1de0000"; | |
| qcom_crypto = "/soc/qcrypto@1de0000"; | |
| qcom_tzlog = "/soc/tz-log@146bf720"; | |
| qcom_rng = "/soc/qrng@793000"; | |
| ufsphy1 = "/soc/ufsphy@1da7000"; | |
| ufs1 = "/soc/ufshc@1da4000"; | |
| jtag_fuse = "/soc/jtagfuse@786040"; | |
| sn_fuse = "/soc/snfuse@0xA4128"; | |
| jtag_mm0 = "/soc/jtagmm@7840000"; | |
| jtag_mm1 = "/soc/jtagmm@7940000"; | |
| jtag_mm2 = "/soc/jtagmm@7a40000"; | |
| jtag_mm3 = "/soc/jtagmm@7b40000"; | |
| jtag_mm4 = "/soc/jtagmm@7c40000"; | |
| jtag_mm5 = "/soc/jtagmm@7d40000"; | |
| jtag_mm6 = "/soc/jtagmm@7e40000"; | |
| jtag_mm7 = "/soc/jtagmm@7f40000"; | |
| system_heap = "/soc/qcom,ion/qcom,ion-heap@25"; | |
| ad_hoc_bus = "/soc/ad-hoc-bus"; | |
| fab_a2noc = "/soc/ad-hoc-bus/fab-a2noc"; | |
| fab_bimc = "/soc/ad-hoc-bus/fab-bimc"; | |
| fab_cnoc = "/soc/ad-hoc-bus/fab-cnoc"; | |
| fab_gnoc = "/soc/ad-hoc-bus/fab-gnoc"; | |
| fab_mnoc = "/soc/ad-hoc-bus/fab-mnoc"; | |
| fab_snoc = "/soc/ad-hoc-bus/fab-snoc"; | |
| fab_mnoc_ahb = "/soc/ad-hoc-bus/fab-mnoc-ahb"; | |
| mas_ipa = "/soc/ad-hoc-bus/mas-ipa"; | |
| mas_cnoc_a2noc = "/soc/ad-hoc-bus/mas-cnoc-a2noc"; | |
| mas_sdcc_1 = "/soc/ad-hoc-bus/mas-sdcc-1"; | |
| mas_sdcc_2 = "/soc/ad-hoc-bus/mas-sdcc-2"; | |
| mas_blsp_1 = "/soc/ad-hoc-bus/mas-blsp-1"; | |
| mas_blsp_2 = "/soc/ad-hoc-bus/mas-blsp-2"; | |
| mas_ufs = "/soc/ad-hoc-bus/mas-ufs"; | |
| mas_usb_hs = "/soc/ad-hoc-bus/mas-usb-hs"; | |
| mas_usb3 = "/soc/ad-hoc-bus/mas-usb3"; | |
| mas_crypto_c0 = "/soc/ad-hoc-bus/mas-crypto-c0"; | |
| mas_gnoc_bimc = "/soc/ad-hoc-bus/mas-gnoc-bimc"; | |
| mas_oxili = "/soc/ad-hoc-bus/mas-oxili"; | |
| mas_mnoc_bimc = "/soc/ad-hoc-bus/mas-mnoc-bimc"; | |
| mas_snoc_bimc = "/soc/ad-hoc-bus/mas-snoc-bimc"; | |
| mas_pimem = "/soc/ad-hoc-bus/mas-pimem"; | |
| mas_snoc_cnoc = "/soc/ad-hoc-bus/mas-snoc-cnoc"; | |
| mas_qdss_dap = "/soc/ad-hoc-bus/mas-qdss-dap"; | |
| mas_apps_proc = "/soc/ad-hoc-bus/mas-apps-proc"; | |
| mas_cnoc_mnoc_mmss_cfg = "/soc/ad-hoc-bus/mas-cnoc-mnoc-mmss-cfg"; | |
| mas_cnoc_mnoc_cfg = "/soc/ad-hoc-bus/mas-cnoc-mnoc-cfg"; | |
| mas_cpp = "/soc/ad-hoc-bus/mas-cpp"; | |
| mas_jpeg = "/soc/ad-hoc-bus/mas-jpeg"; | |
| mas_mdp_p0 = "/soc/ad-hoc-bus/mas-mdp-p0"; | |
| mas_mdp_p1 = "/soc/ad-hoc-bus/mas-mdp-p1"; | |
| mas_venus = "/soc/ad-hoc-bus/mas-venus"; | |
| mas_vfe = "/soc/ad-hoc-bus/mas-vfe"; | |
| mas_qdss_etr = "/soc/ad-hoc-bus/mas-qdss-etr"; | |
| mas_qdss_bam = "/soc/ad-hoc-bus/mas-qdss-bam"; | |
| mas_snoc_cfg = "/soc/ad-hoc-bus/mas-snoc-cfg"; | |
| mas_bimc_snoc = "/soc/ad-hoc-bus/mas-bimc-snoc"; | |
| mas_a2noc_snoc = "/soc/ad-hoc-bus/mas-a2noc-snoc"; | |
| slv_a2noc_snoc = "/soc/ad-hoc-bus/slv-a2noc-snoc"; | |
| slv_ebi = "/soc/ad-hoc-bus/slv-ebi"; | |
| slv_hmss_l3 = "/soc/ad-hoc-bus/slv-hmss-l3"; | |
| slv_bimc_snoc = "/soc/ad-hoc-bus/slv-bimc-snoc"; | |
| slv_cnoc_a2noc = "/soc/ad-hoc-bus/slv-cnoc-a2noc"; | |
| slv_mpm = "/soc/ad-hoc-bus/slv-mpm"; | |
| slv_pmic_arb = "/soc/ad-hoc-bus/slv-pmic-arb"; | |
| slv_tlmm_north = "/soc/ad-hoc-bus/slv-tlmm-north"; | |
| slv_tcsr = "/soc/ad-hoc-bus/slv-tcsr"; | |
| slv_pimem_cfg = "/soc/ad-hoc-bus/slv-pimem-cfg"; | |
| slv_imem_cfg = "/soc/ad-hoc-bus/slv-imem-cfg"; | |
| slv_message_ram = "/soc/ad-hoc-bus/slv-message-ram"; | |
| slv_glm = "/soc/ad-hoc-bus/slv-glm"; | |
| slv_bimc_cfg = "/soc/ad-hoc-bus/slv-bimc-cfg"; | |
| slv_prng = "/soc/ad-hoc-bus/slv-prng"; | |
| slv_spdm = "/soc/ad-hoc-bus/slv-spdm"; | |
| slv_qdss_cfg = "/soc/ad-hoc-bus/slv-qdss-cfg"; | |
| slv_cnoc_mnoc_cfg = "/soc/ad-hoc-bus/slv-cnoc-mnoc-cfg"; | |
| slv_snoc_cfg = "/soc/ad-hoc-bus/slv-snoc-cfg"; | |
| slv_qm_cfg = "/soc/ad-hoc-bus/slv-qm-cfg"; | |
| slv_clk_ctl = "/soc/ad-hoc-bus/slv-clk-ctl"; | |
| slv_mss_cfg = "/soc/ad-hoc-bus/slv-mss-cfg"; | |
| slv_tlmm_south = "/soc/ad-hoc-bus/slv-tlmm-south"; | |
| slv_ufs_cfg = "/soc/ad-hoc-bus/slv-ufs-cfg"; | |
| slv_a2noc_cfg = "/soc/ad-hoc-bus/slv-a2noc-cfg"; | |
| slv_a2noc_smmu_cfg = "/soc/ad-hoc-bus/slv-a2noc-smmu-cfg"; | |
| slv_gpuss_cfg = "/soc/ad-hoc-bus/slv-gpuss-cfg"; | |
| slv_ahb2phy = "/soc/ad-hoc-bus/slv-ahb2phy"; | |
| slv_blsp_1 = "/soc/ad-hoc-bus/slv-blsp-1"; | |
| slv_sdcc_1 = "/soc/ad-hoc-bus/slv-sdcc-1"; | |
| slv_sdcc_2 = "/soc/ad-hoc-bus/slv-sdcc-2"; | |
| slv_tlmm_center = "/soc/ad-hoc-bus/slv-tlmm-center"; | |
| slv_blsp_2 = "/soc/ad-hoc-bus/slv-blsp-2"; | |
| slv_pdm = "/soc/ad-hoc-bus/slv-pdm"; | |
| slv_cnoc_mnoc_mmss_cfg = "/soc/ad-hoc-bus/slv-cnoc-mnoc-mmss-cfg"; | |
| slv_usb_hs = "/soc/ad-hoc-bus/slv-usb-hs"; | |
| slv_usb3_0 = "/soc/ad-hoc-bus/slv-usb3-0"; | |
| slv_srvc_cnoc = "/soc/ad-hoc-bus/slv-srvc-cnoc"; | |
| slv_gnoc_bimc = "/soc/ad-hoc-bus/slv-gnoc-bimc"; | |
| slv_gnoc_snoc = "/soc/ad-hoc-bus/slv-gnoc-snoc"; | |
| mas_gnoc_snoc = "/soc/ad-hoc-bus/mas-gnoc-snoc"; | |
| slv_camera_cfg = "/soc/ad-hoc-bus/slv-camera-cfg"; | |
| slv_camera_throttle_cfg = "/soc/ad-hoc-bus/slv-camera-throttle-cfg"; | |
| slv_misc_cfg = "/soc/ad-hoc-bus/slv-misc-cfg"; | |
| slv_venus_throttle_cfg = "/soc/ad-hoc-bus/slv-venus-throttle-cfg"; | |
| slv_venus_cfg = "/soc/ad-hoc-bus/slv-venus-cfg"; | |
| slv_mmss_clk_xpu_cfg = "/soc/ad-hoc-bus/slv-mmss-clk-xpu-cfg"; | |
| slv_mmss_clk_cfg = "/soc/ad-hoc-bus/slv-mmss-clk-cfg"; | |
| slv_mnoc_mpu_cfg = "/soc/ad-hoc-bus/slv-mnoc-mpu-cfg"; | |
| slv_display_cfg = "/soc/ad-hoc-bus/slv-display-cfg"; | |
| slv_csi_phy_cfg = "/soc/ad-hoc-bus/slv-csi-phy-cfg"; | |
| slv_display_throttle_cfg = "/soc/ad-hoc-bus/slv-display-throttle-cfg"; | |
| slv_smmu_cfg = "/soc/ad-hoc-bus/slv-smmu-cfg"; | |
| slv_mnoc_bimc = "/soc/ad-hoc-bus/slv-mnoc-bimc"; | |
| slv_srvc_mnoc = "/soc/ad-hoc-bus/slv-srvc-mnoc"; | |
| slv_hmss = "/soc/ad-hoc-bus/slv-hmss"; | |
| slv_lpass = "/soc/ad-hoc-bus/slv-lpass"; | |
| slv_wlan = "/soc/ad-hoc-bus/slv-wlan"; | |
| slv_cdsp = "/soc/ad-hoc-bus/slv-cdsp"; | |
| slv_ipa = "/soc/ad-hoc-bus/slv-ipa"; | |
| slv_snoc_bimc = "/soc/ad-hoc-bus/slv-snoc-bimc"; | |
| slv_snoc_cnoc = "/soc/ad-hoc-bus/slv-snoc-cnoc"; | |
| slv_imem = "/soc/ad-hoc-bus/slv-imem"; | |
| slv_pimem = "/soc/ad-hoc-bus/slv-pimem"; | |
| slv_qdss_stm = "/soc/ad-hoc-bus/slv-qdss-stm"; | |
| slv_srvc_snoc = "/soc/ad-hoc-bus/slv-srvc-snoc"; | |
| gfx_mem_acc_vreg = "/soc/regulator@01fcf004"; | |
| gfx_ldo_vreg = "/soc/ldo@0506e000"; | |
| gfx_cpr = "/soc/cpr4-ctrl@05061000"; | |
| gfx_vreg_corner = "/soc/cpr4-ctrl@05061000/thread@0/regulator"; | |
| apc0_cpr = "/soc/cprh-ctrl@179c8000"; | |
| apc0_pwrcl_vreg = "/soc/cprh-ctrl@179c8000/thread@0/regulator"; | |
| apc1_cpr = "/soc/cprh-ctrl@179c4000"; | |
| apc1_perfcl_vreg = "/soc/cprh-ctrl@179c4000/thread@0/regulator"; | |
| gdsc_usb30 = "/soc/qcom,gdsc@10f004"; | |
| gdsc_ufs = "/soc/qcom,gdsc@175004"; | |
| gdsc_hlos1_vote_lpass_adsp = "/soc/qcom,gdsc@17d034"; | |
| gdsc_hlos1_vote_turing_adsp = "/soc/qcom,gdsc@17d04c"; | |
| gdsc_hlos2_vote_turing_adsp = "/soc/qcom,gdsc@17e04c"; | |
| bimc_smmu_hw_ctrl = "/soc/syscon@c8ce024"; | |
| gdsc_bimc_smmu = "/soc/qcom,gdsc@c8ce020"; | |
| gdsc_venus = "/soc/qcom,gdsc@c8c1024"; | |
| gdsc_venus_core0 = "/soc/qcom,gdsc@c8c1040"; | |
| gdsc_camss_top = "/soc/qcom,gdsc@c8c34a0"; | |
| gdsc_vfe0 = "/soc/qcom,gdsc@c8c3664"; | |
| gdsc_vfe1 = "/soc/qcom,gdsc@c8c3674"; | |
| gdsc_cpp = "/soc/qcom,gdsc@c8c36d4"; | |
| gdsc_mdss = "/soc/qcom,gdsc@c8c2304"; | |
| gpu_cx_hw_ctrl = "/soc/syscon@5066008"; | |
| gdsc_gpu_cx = "/soc/qcom,gdsc@5066004"; | |
| gpu_gx_domain_addr = "/soc/syscon@5065130"; | |
| gpu_gx_sw_reset = "/soc/syscon@5066090"; | |
| gdsc_gpu_gx = "/soc/qcom,gdsc@5066094"; | |
| pil_gpu = "/soc/qcom,kgsl-hyp"; | |
| msm_bus = "/soc/qcom,kgsl-busmon"; | |
| gpubw = "/soc/qcom,gpubw"; | |
| msm_gpu = "/soc/qcom,kgsl-3d0@5000000"; | |
| kgsl_msm_iommu = "/soc/qcom,kgsl-iommu"; | |
| gfx3d_user = "/soc/qcom,kgsl-iommu/gfx3d_user"; | |
| gfx3d_secure = "/soc/qcom,kgsl-iommu/gfx3d_secure"; | |
| rpm_msg_ram = "/soc/memory@0x200000"; | |
| rpm_code_ram = "/soc/rpm-memory@0x778000"; | |
| anoc2_smmu = "/soc/arm,smmu-anoc2@16c0000"; | |
| lpass_q6_smmu = "/soc/arm,smmu-lpass_q6@5100000"; | |
| mmss_bimc_smmu = "/soc/arm,smmu-mmss@cd00000"; | |
| kgsl_smmu = "/soc/arm,smmu-kgsl@5040000"; | |
| turing_q6_smmu = "/soc/arm,smmu-turing_q6@5180000"; | |
| ufs_ice = "/soc/ufsice@1db0000"; | |
| sdcc1_ice = "/soc/sdcc1ice@c0c8000"; | |
| usb3 = "/soc/ssusb@a800000"; | |
| qusb_phy0 = "/soc/qusb@c012000"; | |
| ssphy = "/soc/ssphy@c010000"; | |
| dbm_1p5 = "/soc/dbm@a8f8000"; | |
| usb2s = "/soc/hsusb@c200000"; | |
| qusb_phy1 = "/soc/qusb@c014000"; | |
| usb_nop_phy = "/soc/usb_nop_phy"; | |
| tlmm = "/soc/pinctrl@03000000"; | |
| msm_gpio_20 = "/soc/pinctrl@03000000/msm_gpio_20"; | |
| msm_gpio_20_output_high = "/soc/pinctrl@03000000/msm_gpio_20_output_high"; | |
| msm_gpio_72 = "/soc/pinctrl@03000000/msm_gpio_72"; | |
| uart_console_active = "/soc/pinctrl@03000000/uart_console_active"; | |
| led_enable = "/soc/pinctrl@03000000/led_enable"; | |
| led_disable = "/soc/pinctrl@03000000/led_disable"; | |
| trigout_a = "/soc/pinctrl@03000000/trigout_a"; | |
| sdc1_clk_on = "/soc/pinctrl@03000000/sdc1_clk_on"; | |
| sdc1_clk_off = "/soc/pinctrl@03000000/sdc1_clk_off"; | |
| sdc1_cmd_on = "/soc/pinctrl@03000000/sdc1_cmd_on"; | |
| sdc1_cmd_off = "/soc/pinctrl@03000000/sdc1_cmd_off"; | |
| sdc1_data_on = "/soc/pinctrl@03000000/sdc1_data_on"; | |
| sdc1_data_off = "/soc/pinctrl@03000000/sdc1_data_off"; | |
| sdc1_rclk_on = "/soc/pinctrl@03000000/sdc1_rclk_on"; | |
| sdc1_rclk_off = "/soc/pinctrl@03000000/sdc1_rclk_off"; | |
| sdc2_clk_on = "/soc/pinctrl@03000000/sdc2_clk_on"; | |
| sdc2_clk_off = "/soc/pinctrl@03000000/sdc2_clk_off"; | |
| sdc2_cmd_on = "/soc/pinctrl@03000000/sdc2_cmd_on"; | |
| sdc2_cmd_off = "/soc/pinctrl@03000000/sdc2_cmd_off"; | |
| sdc2_data_on = "/soc/pinctrl@03000000/sdc2_data_on"; | |
| sdc2_data_off = "/soc/pinctrl@03000000/sdc2_data_off"; | |
| sdc2_cd_on = "/soc/pinctrl@03000000/cd_on"; | |
| sdc2_cd_off = "/soc/pinctrl@03000000/cd_off"; | |
| i2c_1_active = "/soc/pinctrl@03000000/i2c_1/i2c_1_active"; | |
| i2c_1_sleep = "/soc/pinctrl@03000000/i2c_1/i2c_1_sleep"; | |
| i2c_1_bitbang = "/soc/pinctrl@03000000/i2c_1/i2c_1_bitbang"; | |
| i2c_2_active = "/soc/pinctrl@03000000/i2c_2/i2c_2_active"; | |
| i2c_2_sleep = "/soc/pinctrl@03000000/i2c_2/i2c_2_sleep"; | |
| i2c_2_bitbang = "/soc/pinctrl@03000000/i2c_2/i2c_2_bitbang"; | |
| i2c_3_active = "/soc/pinctrl@03000000/i2c_3/i2c_3_active"; | |
| i2c_3_sleep = "/soc/pinctrl@03000000/i2c_3/i2c_3_sleep"; | |
| i2c_3_bitbang = "/soc/pinctrl@03000000/i2c_3/i2c_3_bitbang"; | |
| i2c_4_active = "/soc/pinctrl@03000000/i2c_4/i2c_4_active"; | |
| i2c_4_sleep = "/soc/pinctrl@03000000/i2c_4/i2c_4_sleep"; | |
| i2c_4_bitbang = "/soc/pinctrl@03000000/i2c_4/i2c_4_bitbang"; | |
| i2c_5_active = "/soc/pinctrl@03000000/i2c_5/i2c_5_active"; | |
| i2c_5_sleep = "/soc/pinctrl@03000000/i2c_5/i2c_5_sleep"; | |
| i2c_5_bitbang = "/soc/pinctrl@03000000/i2c_5/i2c_5_bitbang"; | |
| i2c_6_active = "/soc/pinctrl@03000000/i2c_6/i2c_6_active"; | |
| i2c_6_sleep = "/soc/pinctrl@03000000/i2c_6/i2c_6_sleep"; | |
| i2c_6_bitbang = "/soc/pinctrl@03000000/i2c_6/i2c_6_bitbang"; | |
| nfc_int_active = "/soc/pinctrl@03000000/nfc/nfc_int_active"; | |
| nfc_int_suspend = "/soc/pinctrl@03000000/nfc/nfc_int_suspend"; | |
| nfc_enable_active = "/soc/pinctrl@03000000/nfc/nfc_enable_active"; | |
| nfc_enable_suspend = "/soc/pinctrl@03000000/nfc/nfc_enable_suspend"; | |
| i2c_7_active = "/soc/pinctrl@03000000/i2c_7/i2c_7_active"; | |
| i2c_7_sleep = "/soc/pinctrl@03000000/i2c_7/i2c_7_sleep"; | |
| i2c_7_bitbang = "/soc/pinctrl@03000000/i2c_7/i2c_7_bitbang"; | |
| i2c_8_active = "/soc/pinctrl@03000000/i2c_8/i2c_8_active"; | |
| i2c_8_sleep = "/soc/pinctrl@03000000/i2c_8/i2c_8_sleep"; | |
| i2c_8_bitbang = "/soc/pinctrl@03000000/i2c_8/i2c_8_bitbang"; | |
| spi_1_active = "/soc/pinctrl@03000000/spi_1/spi_1_active"; | |
| spi_1_sleep = "/soc/pinctrl@03000000/spi_1/spi_1_sleep"; | |
| spi_2_active = "/soc/pinctrl@03000000/spi_2/spi_2_active"; | |
| spi_2_sleep = "/soc/pinctrl@03000000/spi_2/spi_2_sleep"; | |
| spi_3_active = "/soc/pinctrl@03000000/spi_3/spi_3_active"; | |
| spi_3_sleep = "/soc/pinctrl@03000000/spi_3/spi_3_sleep"; | |
| spi_4_active = "/soc/pinctrl@03000000/spi_4/spi_4_active"; | |
| spi_4_sleep = "/soc/pinctrl@03000000/spi_4/spi_4_sleep"; | |
| spi_5_active = "/soc/pinctrl@03000000/spi_5/spi_5_active"; | |
| spi_5_sleep = "/soc/pinctrl@03000000/spi_5/spi_5_sleep"; | |
| spi_6_active = "/soc/pinctrl@03000000/spi_6/spi_6_active"; | |
| spi_6_sleep = "/soc/pinctrl@03000000/spi_6/spi_6_sleep"; | |
| spi_7_active = "/soc/pinctrl@03000000/spi_7/spi_7_active"; | |
| spi_7_sleep = "/soc/pinctrl@03000000/spi_7/spi_7_sleep"; | |
| spi_8_active = "/soc/pinctrl@03000000/spi_8/spi_8_active"; | |
| spi_8_sleep = "/soc/pinctrl@03000000/spi_8/spi_8_sleep"; | |
| ant_check_default = "/soc/pinctrl@03000000/ant-check-pin/ant_check_default"; | |
| wcd_usbc_analog_en1_idle = "/soc/pinctrl@03000000/wcd_usbc_analog_en1/wcd_usbc_ana_en1_idle"; | |
| wcd_usbc_analog_en1_active = "/soc/pinctrl@03000000/wcd_usbc_analog_en1/wcd_usbc_ana_en1_active"; | |
| wcd_usbc_analog_en2n_idle = "/soc/pinctrl@03000000/wcd_usbc_analog_en2n/wcd_usbc_ana_en2n_idle"; | |
| wcd_usbc_analog_en2n_active = "/soc/pinctrl@03000000/wcd_usbc_analog_en2n/wcd_usbc_ana_en2n_active"; | |
| sdw_clk_sleep = "/soc/pinctrl@03000000/sdw_clk_pin/sdw_clk_sleep"; | |
| sdw_clk_active = "/soc/pinctrl@03000000/sdw_clk_pin/sdw_clk_active"; | |
| sdw_data_sleep = "/soc/pinctrl@03000000/sdw_clk_data/sdw_data_sleep"; | |
| sdw_data_active = "/soc/pinctrl@03000000/sdw_clk_data/sdw_data_active"; | |
| pri_mi2s_sck_sleep = "/soc/pinctrl@03000000/pri_mi2s_sck/pri_mi2s_sck_sleep"; | |
| pri_mi2s_sck_active = "/soc/pinctrl@03000000/pri_mi2s_sck/pri_mi2s_sck_active"; | |
| pri_mi2s_ws_sleep = "/soc/pinctrl@03000000/pri_mi2s_ws/pri_mi2s_ws_sleep"; | |
| pri_mi2s_ws_active = "/soc/pinctrl@03000000/pri_mi2s_ws/pri_mi2s_ws_active"; | |
| pri_mi2s_sd0_sleep = "/soc/pinctrl@03000000/pri_mi2s_sd0/pri_mi2s_sd0_sleep"; | |
| pri_mi2s_sd0_active = "/soc/pinctrl@03000000/pri_mi2s_sd0/pri_mi2s_sd0_active"; | |
| pri_mi2s_sd1_sleep = "/soc/pinctrl@03000000/pri_mi2s_sd1/pri_mi2s_sd1_sleep"; | |
| pri_mi2s_sd1_active = "/soc/pinctrl@03000000/pri_mi2s_sd1/pri_mi2s_sd1_active"; | |
| spkr_1_sd_n_sleep = "/soc/pinctrl@03000000/spkr_1_sd_n/spkr_1_sd_n_sleep"; | |
| spkr_1_sd_n_active = "/soc/pinctrl@03000000/spkr_1_sd_n/spkr_1_sd_n_active"; | |
| spkr_2_sd_n_sleep = "/soc/pinctrl@03000000/spkr_2_sd_n/spkr_2_sd_n_sleep"; | |
| spkr_2_sd_n_active = "/soc/pinctrl@03000000/spkr_2_sd_n/spkr_2_sd_n_active"; | |
| wcd_gnd_mic_swap_idle = "/soc/pinctrl@03000000/wcd_gnd_mic_swap/wcd_gnd_mic_swap_idle"; | |
| wcd_gnd_mic_swap_active = "/soc/pinctrl@03000000/wcd_gnd_mic_swap/wcd_gnd_mic_swap_active"; | |
| hph_en0_sleep = "/soc/pinctrl@03000000/msm_hph_en0/hph_en0_sleep"; | |
| hph_en0_active = "/soc/pinctrl@03000000/msm_hph_en0/hph_en0_active"; | |
| hph_en1_sleep = "/soc/pinctrl@03000000/msm_hph_en1/hph_en1_sleep"; | |
| hph_en1_active = "/soc/pinctrl@03000000/msm_hph_en1/hph_en1_active"; | |
| cci0_active = "/soc/pinctrl@03000000/cci0_active"; | |
| cci0_suspend = "/soc/pinctrl@03000000/cci0_suspend"; | |
| cci1_active = "/soc/pinctrl@03000000/cci1_active"; | |
| cci1_suspend = "/soc/pinctrl@03000000/cci1_suspend"; | |
| cam_actuator_vaf_active0 = "/soc/pinctrl@03000000/cam_actuator_vaf_active0"; | |
| cam_actuator_vaf_suspend0 = "/soc/pinctrl@03000000/cam_actuator_vaf_suspend0"; | |
| cam_actuator_vaf_active = "/soc/pinctrl@03000000/cam_actuator_vaf_active"; | |
| cam_actuator_vaf_suspend = "/soc/pinctrl@03000000/cam_actuator_vaf_suspend"; | |
| cam_tof_active = "/soc/pinctrl@03000000/cam_tof_active"; | |
| cam_tof_suspend = "/soc/pinctrl@03000000/cam_tof_suspend"; | |
| cam_sensor_mclk0_active = "/soc/pinctrl@03000000/cam_sensor_mclk0_active"; | |
| cam_sensor_mclk0_suspend = "/soc/pinctrl@03000000/cam_sensor_mclk0_suspend"; | |
| cam_sensor_rear_active = "/soc/pinctrl@03000000/cam_sensor_rear_active"; | |
| cam_sensor_rear_suspend = "/soc/pinctrl@03000000/cam_sensor_rear_suspend"; | |
| cam_sensor_mclk1_active = "/soc/pinctrl@03000000/cam_sensor_mclk1_active"; | |
| cam_sensor_mclk1_suspend = "/soc/pinctrl@03000000/cam_sensor_mclk1_suspend"; | |
| cam_sensor_rear2_active = "/soc/pinctrl@03000000/cam_sensor_rear2_active"; | |
| cam_sensor_rear2_suspend = "/soc/pinctrl@03000000/cam_sensor_rear2_suspend"; | |
| cam_sensor_mclk2_active = "/soc/pinctrl@03000000/cam_sensor_mclk2_active"; | |
| cam_sensor_mclk2_suspend = "/soc/pinctrl@03000000/cam_sensor_mclk2_suspend"; | |
| cam_sensor_front_active = "/soc/pinctrl@03000000/cam_sensor_front_active"; | |
| cam_sensor_front_suspend = "/soc/pinctrl@03000000/cam_sensor_front_suspend"; | |
| cam_sensor_mclk3_active = "/soc/pinctrl@03000000/cam_sensor_mclk3_active"; | |
| cam_sensor_mclk3_suspend = "/soc/pinctrl@03000000/cam_sensor_mclk3_suspend"; | |
| cam_sensor_front_iris_active = "/soc/pinctrl@03000000/cam_sensor_front_iris_active"; | |
| cam_sensor_front_iris_suspend = "/soc/pinctrl@03000000/cam_sensor_front_iris_suspend"; | |
| blsp1_uart1_active = "/soc/pinctrl@03000000/blsp1_uart1_active"; | |
| blsp1_uart1_sleep = "/soc/pinctrl@03000000/blsp1_uart1_sleep"; | |
| blsp1_uart2_active = "/soc/pinctrl@03000000/blsp1_uart2_active"; | |
| blsp1_uart2_sleep = "/soc/pinctrl@03000000/blsp1_uart2_sleep"; | |
| blsp2_uart1 = "/soc/pinctrl@03000000/blsp2_uart1"; | |
| blsp2_uart1_tx_active = "/soc/pinctrl@03000000/blsp2_uart1/blsp2_uart1_tx_active"; | |
| blsp2_uart1_tx_sleep = "/soc/pinctrl@03000000/blsp2_uart1/blsp2_uart1_tx_sleep"; | |
| blsp2_uart1_rxcts_active = "/soc/pinctrl@03000000/blsp2_uart1/blsp2_uart1_rxcts_active"; | |
| blsp2_uart1_rxcts_sleep = "/soc/pinctrl@03000000/blsp2_uart1/blsp2_uart1_rxcts_sleep"; | |
| blsp2_uart1_rfr_active = "/soc/pinctrl@03000000/blsp2_uart1/blsp2_uart1_rfr_active"; | |
| blsp2_uart1_rfr_sleep = "/soc/pinctrl@03000000/blsp2_uart1/blsp2_uart1_rfr_sleep"; | |
| blsp2_uart2_active = "/soc/pinctrl@03000000/blsp2_uart2_active"; | |
| blsp2_uart2_sleep = "/soc/pinctrl@03000000/blsp2_uart2_sleep"; | |
| gpio_key_active = "/soc/pinctrl@03000000/tlmm_gpio_key/gpio_key_active"; | |
| gpio_key_suspend = "/soc/pinctrl@03000000/tlmm_gpio_key/gpio_key_suspend"; | |
| pmx_mdss = "/soc/pinctrl@03000000/pmx_mdss"; | |
| mdss_dsi_active = "/soc/pinctrl@03000000/pmx_mdss/mdss_dsi_active"; | |
| mdss_dsi_suspend = "/soc/pinctrl@03000000/pmx_mdss/mdss_dsi_suspend"; | |
| mdss_te_active = "/soc/pinctrl@03000000/pmx_mdss_te/mdss_te_active"; | |
| mdss_te_suspend = "/soc/pinctrl@03000000/pmx_mdss_te/mdss_te_suspend"; | |
| mdss_dp_aux_active = "/soc/pinctrl@03000000/mdss_dp_aux_active"; | |
| mdss_dp_aux_suspend = "/soc/pinctrl@03000000/mdss_dp_aux_suspend"; | |
| mdss_dp_usbplug_cc_active = "/soc/pinctrl@03000000/mdss_dp_usbplug_cc_active"; | |
| mdss_dp_usbplug_cc_suspend = "/soc/pinctrl@03000000/mdss_dp_usbplug_cc_suspend"; | |
| ts_active = "/soc/pinctrl@03000000/ts_mux/ts_active"; | |
| ts_reset_suspend = "/soc/pinctrl@03000000/ts_mux/ts_reset_suspend"; | |
| ts_int_suspend = "/soc/pinctrl@03000000/ts_mux/ts_int_suspend"; | |
| i2c_1 = "/soc/i2c@c175000"; | |
| i2c_2 = "/soc/i2c@c176000"; | |
| i2c_3 = "/soc/i2c@c177000"; | |
| i2c_4 = "/soc/i2c@c178000"; | |
| i2c_5 = "/soc/i2c@c1b5000"; | |
| i2c_6 = "/soc/i2c@c1b6000"; | |
| i2c_7 = "/soc/i2c@c1b7000"; | |
| i2c_8 = "/soc/i2c@c1b8000"; | |
| spi_1 = "/soc/spi@c175000"; | |
| spi_2 = "/soc/spi@c176000"; | |
| spi_3 = "/soc/spi@c177000"; | |
| spi_4 = "/soc/spi@c178000"; | |
| spi_5 = "/soc/spi@c1b5000"; | |
| spi_6 = "/soc/spi@c1b6000"; | |
| spi_7 = "/soc/spi@c1b7000"; | |
| spi_8 = "/soc/spi@c1b8000"; | |
| blsp1_uart1_hs = "/soc/uart@c16f000"; | |
| blsp1_uart2_hs = "/soc/uart@c170000"; | |
| blsp2_uart1_hs = "/soc/uart@c1af000"; | |
| blsp2_uart2_hs = "/soc/uart@c1b0000"; | |
| smp2pgpio_rdbg_2_in = "/soc/qcom,smp2pgpio-rdbg-2-in"; | |
| smp2pgpio_rdbg_2_out = "/soc/qcom,smp2pgpio-rdbg-2-out"; | |
| smp2pgpio_rdbg_1_in = "/soc/qcom,smp2pgpio-rdbg-1-in"; | |
| smp2pgpio_rdbg_1_out = "/soc/qcom,smp2pgpio-rdbg-1-out"; | |
| smp2pgpio_rdbg_5_in = "/soc/qcom,smp2pgpio-rdbg-5-in"; | |
| smp2pgpio_rdbg_5_out = "/soc/qcom,smp2pgpio-rdbg-5-out"; | |
| vfe0 = "/soc/qcom,vfe0@ca10000"; | |
| vfe1 = "/soc/qcom,vfe1@ca14000"; | |
| cci = "/soc/qcom,cci@ca0c000"; | |
| i2c_freq_100Khz = "/soc/qcom,cci@ca0c000/qcom,i2c_standard_mode"; | |
| i2c_freq_400Khz = "/soc/qcom,cci@ca0c000/qcom,i2c_fast_mode"; | |
| i2c_freq_custom = "/soc/qcom,cci@ca0c000/qcom,i2c_custom_mode"; | |
| i2c_freq_1Mhz = "/soc/qcom,cci@ca0c000/qcom,i2c_fast_plus_mode"; | |
| actuator1 = "/soc/qcom,cci@ca0c000/qcom,actuator@1"; | |
| eeprom0 = "/soc/qcom,cci@ca0c000/qcom,eeprom@0"; | |
| eeprom1 = "/soc/qcom,cci@ca0c000/qcom,eeprom@1"; | |
| eeprom2 = "/soc/qcom,cci@ca0c000/qcom,eeprom@2"; | |
| eeprom3 = "/soc/qcom,cci@ca0c000/qcom,eeprom@3"; | |
| eeprom4 = "/soc/qcom,cci@ca0c000/qcom,eeprom@4"; | |
| eeprom5 = "/soc/qcom,cci@ca0c000/qcom,eeprom@5"; | |
| msm_vidc = "/soc/qcom,vidc@cc00000"; | |
| venus_secure_pixel_cb = "/soc/qcom,vidc@cc00000/secure_pixel_cb"; | |
| venus_secure_non_pixel_cb = "/soc/qcom,vidc@cc00000/secure_non_pixel_cb"; | |
| pcm0 = "/soc/qcom,msm-pcm"; | |
| routing = "/soc/qcom,msm-pcm-routing"; | |
| compr = "/soc/qcom,msm-compr-dsp"; | |
| pcm2 = "/soc/qcom,msm-ultra-low-latency"; | |
| pcm1 = "/soc/qcom,msm-pcm-low-latency"; | |
| pcm_noirq = "/soc/qcom,msm-pcm-dsp-noirq"; | |
| cpe = "/soc/qcom,msm-cpe-lsm"; | |
| cpe3 = "/soc/qcom,msm-cpe-lsm@3"; | |
| wdsp_mgr = "/soc/qcom,wcd-dsp-mgr"; | |
| wdsp_glink = "/soc/qcom,wcd-dsp-glink"; | |
| compress = "/soc/qcom,msm-compress-dsp"; | |
| voip = "/soc/qcom,msm-voip-dsp"; | |
| voice = "/soc/qcom,msm-pcm-voice"; | |
| stub_codec = "/soc/qcom,msm-stub-codec"; | |
| afe = "/soc/qcom,msm-pcm-afe"; | |
| dai_dp = "/soc/qcom,msm-dai-q6-dp"; | |
| loopback = "/soc/qcom,msm-pcm-loopback"; | |
| dai_mi2s0 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-prim"; | |
| dai_mi2s1 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-sec"; | |
| dai_mi2s3 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quat"; | |
| dai_mi2s2 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-tert"; | |
| dai_mi2s5 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-quin"; | |
| dai_mi2s6 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-mi2s-senary"; | |
| dai_int_mi2s0 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s0"; | |
| dai_int_mi2s1 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s1"; | |
| dai_int_mi2s2 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s2"; | |
| dai_int_mi2s3 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s3"; | |
| dai_int_mi2s4 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s4"; | |
| dai_int_mi2s5 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s5"; | |
| dai_int_mi2s6 = "/soc/qcom,msm-dai-mi2s/qcom,msm-dai-q6-int-mi2s6"; | |
| lsm = "/soc/qcom,msm-lsm-client"; | |
| sb_0_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-rx"; | |
| sb_0_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-0-tx"; | |
| sb_1_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-rx"; | |
| sb_1_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-1-tx"; | |
| sb_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-rx"; | |
| sb_2_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-2-tx"; | |
| sb_3_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-rx"; | |
| sb_3_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-3-tx"; | |
| sb_4_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-rx"; | |
| sb_4_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-4-tx"; | |
| sb_5_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-tx"; | |
| sb_5_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-5-rx"; | |
| sb_6_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-6-rx"; | |
| sb_7_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-tx"; | |
| sb_7_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-7-rx"; | |
| sb_8_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-tx"; | |
| sb_8_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-sb-8-rx"; | |
| bt_sco_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-rx"; | |
| bt_sco_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-bt-sco-tx"; | |
| int_fm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-rx"; | |
| int_fm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-int-fm-tx"; | |
| afe_pcm_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-rx"; | |
| afe_pcm_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-be-afe-pcm-tx"; | |
| afe_proxy_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-rx"; | |
| afe_proxy_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-afe-proxy-tx"; | |
| incall_record_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-rx"; | |
| incall_record_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-record-tx"; | |
| incall_music_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-rx"; | |
| incall_music_2_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-incall-music-2-rx"; | |
| usb_audio_rx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-rx"; | |
| usb_audio_tx = "/soc/qcom,msm-dai-q6/qcom,msm-dai-q6-usb-audio-tx"; | |
| hostless = "/soc/qcom,msm-pcm-hostless"; | |
| dai_pri_auxpcm = "/soc/qcom,msm-pri-auxpcm"; | |
| dai_sec_auxpcm = "/soc/qcom,msm-sec-auxpcm"; | |
| dai_tert_auxpcm = "/soc/qcom,msm-tert-auxpcm"; | |
| dai_quat_auxpcm = "/soc/qcom,msm-quat-auxpcm"; | |
| dai_pri_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-pri-rx/qcom,msm-dai-q6-tdm-pri-rx-0"; | |
| dai_pri_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-pri-tx/qcom,msm-dai-q6-tdm-pri-tx-0"; | |
| dai_sec_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-sec-rx/qcom,msm-dai-q6-tdm-sec-rx-0"; | |
| dai_sec_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-sec-tx/qcom,msm-dai-q6-tdm-sec-tx-0"; | |
| dai_tert_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-tert-rx/qcom,msm-dai-q6-tdm-tert-rx-0"; | |
| dai_tert_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-tert-tx/qcom,msm-dai-q6-tdm-tert-tx-0"; | |
| dai_quat_tdm_rx_0 = "/soc/qcom,msm-dai-tdm-quat-rx/qcom,msm-dai-q6-tdm-quat-rx-0"; | |
| dai_quat_tdm_tx_0 = "/soc/qcom,msm-dai-tdm-quat-tx/qcom,msm-dai-q6-tdm-quat-tx-0"; | |
| tasha_snd = "/soc/sound-9335"; | |
| tavil_snd = "/soc/sound-tavil"; | |
| int_codec = "/soc/sound"; | |
| us_euro_gpio = "/soc/msm_cdc_pinctrl@75"; | |
| wcd9xxx_intc = "/soc/wcd9xxx-irq"; | |
| clock_audio = "/soc/audio_ext_clk"; | |
| clock_audio_lnbb = "/soc/audio_ext_clk_lnbb"; | |
| wcd_rst_gpio = "/soc/msm_cdc_pinctrl@64"; | |
| wcd_usbc_analog_en1_gpio = "/soc/msm_cdc_pinctrl_usbc_audio_en1"; | |
| wcd_usbc_analog_en2n_gpio = "/soc/msm_cdc_pinctrl_usbc_audio_en2"; | |
| lpi_tlmm = "/soc/lpi_pinctrl@15070000"; | |
| lpi_mclk0_active = "/soc/lpi_pinctrl@15070000/lpi_mclk0_active"; | |
| lpi_mclk0_sleep = "/soc/lpi_pinctrl@15070000/lpi_mclk0_sleep"; | |
| cdc_pdm_gpios_active = "/soc/lpi_pinctrl@15070000/cdc_pdm_gpios_active"; | |
| cdc_pdm_gpios_sleep = "/soc/lpi_pinctrl@15070000/cdc_pdm_gpios_sleep"; | |
| cdc_pdm_2_gpios_active = "/soc/lpi_pinctrl@15070000/cdc_pdm_2_gpios_active"; | |
| cdc_pdm_2_gpios_sleep = "/soc/lpi_pinctrl@15070000/cdc_pdm_2_gpios_sleep"; | |
| cdc_comp_gpios_active = "/soc/lpi_pinctrl@15070000/cdc_pdm_comp_gpios_active"; | |
| cdc_comp_gpios_sleep = "/soc/lpi_pinctrl@15070000/cdc_pdm_comp_gpios_sleep"; | |
| lpi_cdc_reset_active = "/soc/lpi_pinctrl@15070000/lpi_cdc_reset_active"; | |
| lpi_cdc_reset_sleep = "/soc/lpi_pinctrl@15070000/lpi_cdc_reset_sleep"; | |
| cdc_dmic12_gpios_active = "/soc/lpi_pinctrl@15070000/dmic12_gpios_active"; | |
| cdc_dmic12_gpios_sleep = "/soc/lpi_pinctrl@15070000/dmic12_gpios_sleep"; | |
| cdc_dmic34_gpios_active = "/soc/lpi_pinctrl@15070000/dmic34_gpios_active"; | |
| cdc_dmic34_gpios_sleep = "/soc/lpi_pinctrl@15070000/dmic34_gpios_sleep"; | |
| cdc_pdm_gpios = "/soc/cdc_pdm_pinctrl"; | |
| cdc_comp_gpios = "/soc/cdc_comp_pinctrl"; | |
| cdc_dmic_gpios = "/soc/cdc_dmic_pinctrl"; | |
| cdc_sdw_gpios = "/soc/sdw_clk_data_pinctrl"; | |
| wsa_spkr_en1 = "/soc/wsa_spkr_en1_pinctrl"; | |
| wsa_spkr_en2 = "/soc/wsa_spkr_en2_pinctrl"; | |
| msm_sdw_codec = "/soc/msm-sdw-codec@152c1000"; | |
| wsa881x_211_en = "/soc/msm-sdw-codec@152c1000/swr_master/wsa881x_en@20170211"; | |
| wsa881x_212_en = "/soc/msm-sdw-codec@152c1000/swr_master/wsa881x_en@20170212"; | |
| wsa881x_213_en = "/soc/msm-sdw-codec@152c1000/swr_master/wsa881x_en@21170213"; | |
| wsa881x_214_en = "/soc/msm-sdw-codec@152c1000/swr_master/wsa881x_en@21170214"; | |
| mdss_mdp = "/soc/qcom,mdss_mdp@c900000"; | |
| smmu_mdp_unsec = "/soc/qcom,mdss_mdp@c900000/qcom,smmu_mdp_unsec_cb"; | |
| smmu_mdp_sec = "/soc/qcom,mdss_mdp@c900000/qcom,smmu_mdp_sec_cb"; | |
| mdss_fb0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_fb_primary"; | |
| mdss_fb1 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_fb_wfd"; | |
| mdss_fb2 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_fb_dp"; | |
| dsi_sim_vid = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_sim_video"; | |
| dsi_dual_sim_vid = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_dual_sim_video"; | |
| dsi_dual_nt35597_truly_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_video_truly"; | |
| dsi_dual_nt35597_truly_video_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_video_truly/config0"; | |
| dsi_dual_nt35597_truly_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd"; | |
| dsi_dual_nt35597_truly_cmd_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_truly_wqxga_cmd/config0"; | |
| dsi_dual_nt36850_truly_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36850_truly_wqhd_cmd"; | |
| dsi_dual_sharp_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_sharp_wqxga_video"; | |
| dsi_dual_sharp_video_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_sharp_wqxga_video/config0"; | |
| dsi_dual_sharp_video_config1 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_sharp_wqxga_video/config1"; | |
| dsi_nt35597_truly_dsc_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_video_truly"; | |
| dsi_nt35597_truly_dsc_video_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_video_truly/config0"; | |
| dsi_nt35597_truly_dsc_video_config1 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_video_truly/config1"; | |
| dsi_nt35597_truly_dsc_video_config2 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_video_truly/config2"; | |
| dsi_nt35597_truly_dsc_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_cmd_truly"; | |
| dsi_nt35597_truly_dsc_cmd_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_cmd_truly/config0"; | |
| dsi_nt35597_truly_dsc_cmd_config1 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_cmd_truly/config1"; | |
| dsi_nt35597_truly_dsc_cmd_config2 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_dsc_cmd_truly/config2"; | |
| dsi_dual_nt35597_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_video"; | |
| dsi_dual_nt35597_video_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_video/config0"; | |
| dsi_dual_nt35597_video_config1 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_video/config1"; | |
| dsi_dual_nt35597_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_cmd"; | |
| dsi_dual_nt35597_cmd_config0 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_cmd/config0"; | |
| dsi_dual_nt35597_cmd_config1 = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35597_wqxga_cmd/config1"; | |
| dsi_nt35695b_truly_fhd_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35695b_truly_fhd_video"; | |
| dsi_nt35695b_truly_fhd_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt35695b_truly_fhd_cmd"; | |
| dsi_truly_1080_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_truly_1080p_cmd"; | |
| dsi_truly_1080_vid = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_truly_1080p_video"; | |
| dsi_rm67195_amoled_fhd_cmd = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_rm67195_amoled_fhd_cmd"; | |
| dsi_lgd_incell_sw49106_fhd_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_lgd_incell_sw49106_fhd_video"; | |
| dsi_hx8399c_truly_vid = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_hx8399_truly_fhd_video"; | |
| dsi_nt36672_tianma_fhd_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36672_tianma_fhd_video"; | |
| dsi_nt36672_jdi_fhd_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36672_jdi_fhd_video"; | |
| dsi_nt36672a_tianma_fhdplus_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36672a_tianma_fhdplus_video"; | |
| dsi_nt36672a_shenchao_fhdplus_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36672a_shenchao_fhdplus_video"; | |
| dsi_td4320_boe_fhdplus_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_td4320_boe_fhdplus_video"; | |
| dsi_nt36672a_e7t_tianma_fhdplus_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36672a_e7t_tianma_fhdplus_video"; | |
| dsi_nt36672a_e7t_shenchao_fhdplus_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_nt36672a_e7t_shenchao_fhdplus_video"; | |
| dsi_ft8719_e7t_boe_fhdplus_video = "/soc/qcom,mdss_mdp@c900000/qcom,mdss_dsi_ft8719_e7t_boe_fhdplus_video"; | |
| mdss_dsi = "/soc/qcom,mdss_dsi@0"; | |
| mdss_dsi0 = "/soc/qcom,mdss_dsi@0/qcom,mdss_dsi_ctrl0@c994000"; | |
| mdss_dsi1 = "/soc/qcom,mdss_dsi@0/qcom,mdss_dsi_ctrl1@c996000"; | |
| msm_ext_disp = "/soc/qcom,msm_ext_disp"; | |
| ext_disp_audio_codec = "/soc/qcom,msm_ext_disp/qcom,msm-ext-disp-audio-codec-rx"; | |
| mdss_dp_ctrl = "/soc/qcom,dp_ctrl@c990000"; | |
| mdss_rotator = "/soc/qcom,mdss_rotator"; | |
| dsi_panel_pwr_supply = "/soc/dsi_panel_pwr_supply"; | |
| dsi_panel_pwr_supply_labibb_amoled = "/soc/dsi_panel_pwr_supply_labibb_amoled"; | |
| dsi_panel_pwr_supply_no_labibb = "/soc/dsi_panel_pwr_supply_no_labibb"; | |
| mdss_dsi0_pll = "/soc/qcom,mdss_dsi_pll@c994400"; | |
| mdss_dsi1_pll = "/soc/qcom,mdss_dsi_pll@c996400"; | |
| mdss_dp_pll = "/soc/qcom,mdss_dp_pll@c011000"; | |
| led_flash0 = "/soc/qcom,camera-flash@0"; | |
| cam_avdd_gpio_regulator = "/soc/cam_avdd_fixed_regulator"; | |
| cam_rear_avdd_gpio_regulator = "/soc/cam_rear_avdd_fixed_regulator"; | |
| cam_dvdd_gpio_regulator = "/soc/cam_dvdd_fixed_regulator"; | |
| cam_rear_dvdd_gpio_regulator = "/soc/cam_rear_dvdd_fixed_regulator"; | |
| firmware = "/firmware"; | |
| wlan_msa_guard = "/reserved-memory/wlan_msa_guard@85600000"; | |
| wlan_msa_mem = "/reserved-memory/wlan_msa_mem@85700000"; | |
| removed_regions = "/reserved-memory/removed_regions@85800000"; | |
| modem_fw_mem = "/reserved-memory/modem_fw_region@8ac00000"; | |
| adsp_fw_mem = "/reserved-memory/adsp_fw_region@92a00000"; | |
| pil_mba_mem = "/reserved-memory/pil_mba_region@94800000"; | |
| cdsp_fw_mem = "/reserved-memory/cdsp_fw_region@94a00000"; | |
| venus_fw_mem = "/reserved-memory/venus_fw_region"; | |
| adsp_mem = "/reserved-memory/adsp_region"; | |
| qseecom_mem = "/reserved-memory/qseecom_region"; | |
| secure_display_memory = "/reserved-memory/secure_region"; | |
| cont_splash_mem = "/reserved-memory/splash_region@9d400000"; | |
| pstore_reserve_mem = "/reserved-memory/pstore_reserve_mem_region@0"; | |
| bluetooth = "/bt_wcn3990"; | |
| gfx_stub_vreg = "/regulator-gfx-stub"; | |
| mtp_batterydata = "/qcom,battery-data"; | |
| }; | |
| }; |
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| sdm660-mtp_f7a.o: \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-mtp_f7a.dts \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/skeleton64.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-sdm660.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpu-sdm660.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,mmcc-sdm660.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmcc.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/audio-ext-clk.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/regulator/qcom,rpm-smd-regulator.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,cpu-osm.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-ion.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-bus.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/msm/msm-bus-ids.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-pm660_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/spmi/spmi.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-pm660l.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/msm/power-on.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-pm.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-common_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-rdbg.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-camera.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/msm-audio.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-audio.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/scripts/dtc/include-prefixes/dt-bindings/clock/mdss-pll-clk.h \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-truly-1080p-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-truly-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-rm67195-amoled-fhd-cmd.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-lgd-incell-sw49106-fhd-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-hx8399c-fhd-plus-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-tianma-nt36672-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-jdi-nt36672-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-tianma-nt36672a-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-shenchao-nt36672a-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-boe-td4320-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-tianma-e7t-nt36672a-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-shenchao-e7t-nt36672a-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/dsi-panel-boe-e7t-ft8719-1080p-video.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-mtp_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-novatek-i2c_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-synaptics-tcm-i2c_f7a.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/fg-gen3-batterydata-m6100atl-4000mah.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/fg-gen3-batterydata-m6100sun-4000mah.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/fg-gen3-batterydata-m6100default-4000mah.dtsi \ | |
| /home/minnehanov/dev/kernels/android_kernel_xiaomi_lavender/arch/arm/boot/dts/qcom/sdm660-internal-codec.dtsi |
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