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MimasV2 mor1kx tuning patches
Raw
README.md

Patches for the configs used to look at the resource usage.

  • Base mor1kx - v5.0
  • Base HDMI2USB-litex-firmware rev - or1k-fixing
  • 9949934e2804238be9ccda9e17e60e34c233cfab - git+ssh://git@github.com/mithro/HDMI2USB-litex-firmware.git
  • Base LiteX rev - or1k-mimasv2
  • 1b7fa415b6c51faf1f616bbc36f06679e5fb6568 - git+ssh://github.com/mithro/litex.git
Raw
attempt2-firmware-bss-in-ddr.patch
diff --git a/firmware/linker.ld b/firmware/linker.ld
index 420a48d..3cc8aff 100644
--- a/firmware/linker.ld
+++ b/firmware/linker.ld
@@ -47,7 +47,7 @@ SECTIONS
. = ALIGN(4);
_ebss = .;
_end = .;
- } > sram
+ } > main_ram
}
PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);
diff --git a/targets/mimasv2/base.py b/targets/mimasv2/base.py
index 19266af..05b1772 100644
--- a/targets/mimasv2/base.py
+++ b/targets/mimasv2/base.py
@@ -196,14 +196,14 @@ class BaseSoC(SoCSDRAM):
SoCSDRAM.__init__(self, platform, clk_freq,
#integrated_rom_size=0x8000,
integrated_rom_size=None,
- integrated_sram_size=0x4000,
+ #integrated_sram_size=0x4000,
uart_baudrate=(19200, 115200)[int(os.environ.get('JIMMO', '0'))],
cpu_reset_address=cpu_reset_address,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
- self.submodules.info = info.Info(platform, "mimasv2", self.__class__.__name__[:8])
+ #self.submodules.info = info.Info(platform, "mimasv2", self.__class__.__name__[:8])
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
@@ -237,6 +237,6 @@ class BaseSoC(SoCSDRAM):
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
- self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
+ #self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
SoC = BaseSoC
Raw
attempt3-disable-everything.patch
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 8511fff5..cc871b9d 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -16,30 +16,48 @@ class MOR1KX(Module):
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("mor1kx",
- p_FEATURE_INSTRUCTIONCACHE="ENABLED",
+ p_FEATURE_INSTRUCTIONCACHE="NONE",
+ #p_FEATURE_INSTRUCTIONCACHE="NONE",
p_OPTION_ICACHE_BLOCK_WIDTH=4,
p_OPTION_ICACHE_SET_WIDTH=8,
p_OPTION_ICACHE_WAYS=1,
p_OPTION_ICACHE_LIMIT_WIDTH=31,
- p_FEATURE_DATACACHE="ENABLED",
+ p_FEATURE_DATACACHE="None",
+ #p_FEATURE_DATACACHE="NONE",
p_OPTION_DCACHE_BLOCK_WIDTH=4,
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
+ p_FEATURE_IMMU="NONE",
+ p_FEATURE_DMMU="NONE",
p_FEATURE_TIMER="NONE",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
p_FEATURE_RANGE="NONE",
+ p_FEATURE_DSX="NONE",
p_FEATURE_OVERFLOW="NONE",
- p_FEATURE_ADDC="ENABLED",
- p_FEATURE_CMOV="ENABLED",
- p_FEATURE_FFL1="ENABLED",
+ p_FEATURE_CARRY_FLAG="NONE",
+
+ p_FEATURE_MULTIPLIER="NONE",
+ p_FEATURE_DIVIDER="NONE",
+ p_OPTION_SHIFTER="SERIAL",
+
+ p_FEATURE_ADDC="NONE",
+ p_FEATURE_SRA="NONE",
+ p_FEATURE_ROR="NONE",
+ p_FEATURE_CMOV="NONE",
+ p_FEATURE_ATOMIC="NONE",
+ p_FEATURE_FFL1="NONE",
+ p_FEATURE_EXT="NONE",
+
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
+ p_FEATURE_STORE_BUFFER="NONE",
+
i_clk=ClockSignal(),
i_rst=ResetSignal(),
Raw
attempt4-reenable-caches.patch
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 8511fff5..fbe91804 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -26,20 +26,36 @@ class MOR1KX(Module):
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
+ p_FEATURE_IMMU="ENABLED",
+ p_FEATURE_DMMU="ENABLED",
p_FEATURE_TIMER="NONE",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
p_FEATURE_RANGE="NONE",
+ p_FEATURE_DSX="NONE",
p_FEATURE_OVERFLOW="NONE",
- p_FEATURE_ADDC="ENABLED",
- p_FEATURE_CMOV="ENABLED",
- p_FEATURE_FFL1="ENABLED",
+ p_FEATURE_ADDC="NONE",
+ p_FEATURE_CMOV="NONE",
+ p_FEATURE_FFL1="NONE",
+
+ p_FEATURE_SRA="NONE",
+ p_FEATURE_ROR="NONE",
+ p_FEATURE_ATOMIC="NONE",
+ p_FEATURE_EXT="NONE",
+
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
+ p_FEATURE_CARRY_FLAG="NONE",
+ p_FEATURE_MULTIPLIER="NONE",
+ p_FEATURE_DIVIDER="NONE",
+ p_OPTION_SHIFTER="SERIAL",
+
+ #p_FEATURE_STORE_BUFFER="NONE",
+
i_clk=ClockSignal(),
i_rst=ResetSignal(),
Raw
attempt7-50MHZ-renable.patch
diff --git a/firmware/linker.ld b/firmware/linker.ld
index 420a48d..3cc8aff 100644
--- a/firmware/linker.ld
+++ b/firmware/linker.ld
@@ -47,7 +47,7 @@ SECTIONS
. = ALIGN(4);
_ebss = .;
_end = .;
- } > sram
+ } > main_ram
}
PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4);
diff --git a/targets/mimasv2/base.py b/targets/mimasv2/base.py
index 19266af..94d5286 100644
--- a/targets/mimasv2/base.py
+++ b/targets/mimasv2/base.py
@@ -192,18 +192,17 @@ class BaseSoC(SoCSDRAM):
cpu_reset_address = self.mem_map["spiflash"]+platform.gateware_size
- clk_freq = (83 + Fraction(1, 3))*1000*1000
+ clk_freq = 50 * 1000 * 1000 #(83 + Fraction(1, 3))*1000*1000
SoCSDRAM.__init__(self, platform, clk_freq,
- #integrated_rom_size=0x8000,
integrated_rom_size=None,
- integrated_sram_size=0x4000,
+ #integrated_sram_size=0x4000,
uart_baudrate=(19200, 115200)[int(os.environ.get('JIMMO', '0'))],
cpu_reset_address=cpu_reset_address,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
- self.submodules.info = info.Info(platform, "mimasv2", self.__class__.__name__[:8])
+ #self.submodules.info = info.Info(platform, "mimasv2", self.__class__.__name__[:8])
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
@@ -237,6 +236,6 @@ class BaseSoC(SoCSDRAM):
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
- self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
+ #self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
SoC = BaseSoC
Raw
b1.patch
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -26,7 +26,9 @@ class MOR1KX(Module):
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
- p_FEATURE_TIMER="NONE",
+ p_FEATURE_IMMU="ENABLED",
+ p_FEATURE_DMMU="ENABLED",
+ p_FEATURE_TIMER="ENABLED",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
@@ -35,11 +37,24 @@ class MOR1KX(Module):
p_FEATURE_ADDC="ENABLED",
p_FEATURE_CMOV="ENABLED",
p_FEATURE_FFL1="ENABLED",
+
+ #p_FEATURE_SRA="NONE",
+ #p_FEATURE_ROR="NONE",
+ #p_FEATURE_ATOMIC="NONE",
+ #p_FEATURE_EXT="NONE",
+
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
+ #p_FEATURE_CARRY_FLAG="NONE",
+ #p_FEATURE_MULTIPLIER="SERIAL",
+ #p_FEATURE_DIVIDER="SERIAL",
+ #p_OPTION_SHIFTER="SERIAL",
+
+ #p_FEATURE_STORE_BUFFER="ENABLED",
+
i_clk=ClockSignal(),
i_rst=ResetSignal(),
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