Test Architecture for VPR

.gitignore

*.log
*.echo
*.xml
*.net
*.route

arch.xml

<?xml version="1.0"?>
<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
 <models/>
 <layout>
  <fixed_layout height="8" name="2x4" width="8">
   <col priority="10" startx="0" type="EMPTY"/>
   <col priority="10" startx="1" type="BLK_IG-IBUF"/>
   <col priority="10" startx="2" type="EMPTY"/>
   <col priority="10" startx="3" type="BLK_TI-LUTFF"/>
   <col priority="10" startx="4" type="BLK_TI-LUTFF"/>
   <col priority="10" startx="5" type="EMPTY"/>
   <col priority="10" startx="6" type="BLK_IG-OBUF"/>
   <col priority="10" startx="7" type="EMPTY"/>
   <row priority="11" starty="0" type="EMPTY"/>
   <row priority="11" starty="7" type="EMPTY"/>
  </fixed_layout>
 </layout>
 <device>
  <sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
  <area grid_logic_tile_area="14813.392"/>
  <connection_block input_switch_name="1"/>
  <switch_block fs="3" type="wilton"/>
  <chan_width_distr>
   <x distr="uniform" peak="1.000000"/>
   <y distr="uniform" peak="1.000000"/>
  </chan_width_distr>
 </device>
 <switchlist>
  <switch Cin=".77e-15" Cout="4e-15" R="551" Tdel="58e-12" buf_size="27.645901" mux_trans_size="2.630740" name="1" type="mux"/>
 </switchlist>
 <segmentlist>
  <segment Cmetal="22.5e-15" Rmetal="101" freq="0.250000" length="4" name="span" type="unidir">
   <sb type="pattern">1 1 1 1 1</sb>
   <cb type="pattern">1 1 1 1</cb>
   <mux name="1"/>
   <wire_switch name="1"/>
   <opin_switch name="1"/>
  </segment>
  <segment Cmetal="22.5e-15" Rmetal="101" freq="0.750000" length="1" name="local" type="unidir">
   <sb type="pattern">1 1</sb>
   <cb type="pattern">1</cb>
   <mux name="1"/>
   <wire_switch name="1"/>
   <opin_switch name="1"/>
  </segment>
 </segmentlist>
 <complexblocklist>
  <!-- An IO pin found on an FPGA -->
  <pb_type capacity="1" name="BLK_IG-IBUF">
   <output name="I" num_pins="1"/>
   <pb_type blif_model=".input" name="BLK_BB-IBUF" num_pb="1">
    <output name="inpad" num_pins="1"/>
   </pb_type>
   <interconnect>
    <direct input="BLK_BB-IBUF.inpad" name="IBUF" output="BLK_IG-IBUF.I"/>
   </interconnect>
   <fc default_in_type="abs" default_in_val="2" default_out_type="abs" default_out_val="2"/>
   <pinlocations pattern="custom">
    <loc side="left">BLK_IG-IBUF.I</loc>
    <loc side="top">BLK_IG-IBUF.I</loc>
    <loc side="right">BLK_IG-IBUF.I</loc>
    <loc side="bottom">BLK_IG-IBUF.I</loc>
   </pinlocations>
  </pb_type>
  <pb_type capacity="1" name="BLK_IG-OBUF">
   <input name="O" num_pins="1"/>
   <pb_type blif_model=".output" name="BLK_BB-OBUF" num_pb="1">
    <input name="outpad" num_pins="1"/>
   </pb_type>
   <interconnect>
    <direct input="BLK_IG-OBUF.O" name="OBUF" output="BLK_BB-OBUF.outpad"/>
   </interconnect>
   <fc default_in_type="abs" default_in_val="2" default_out_type="abs" default_out_val="2"/>
   <pinlocations pattern="custom">
    <loc side="left">BLK_IG-OBUF.O</loc>
    <loc side="top">BLK_IG-OBUF.O</loc>
    <loc side="right">BLK_IG-OBUF.O</loc>
    <loc side="bottom">BLK_IG-OBUF.O</loc>
   </pinlocations>
  </pb_type>
  <pb_type name="BLK_TI-LUTFF" num_pb="1">
   <!-- Tile Inputs -->
   <clock name="CLK" num_pins="2"/>
   <input name="IN" num_pins="6"/>
   <!-- Tile Outputs -->
   <output name="OUT" num_pins="2"/>
   <!-- Internal LUTFF -->
   <pb_type name="BLK_SI-LUTFF" num_pb="1">
    <input equivalent="false" name="I" num_pins="4"/>
    <clock equivalent="false" name="C" num_pins="1"/>
    <output equivalent="false" name="O" num_pins="1"/>
    <pb_type name="BLK_IG-LUTFF" num_pb="1">
     <input equivalent="false" name="I" num_pins="4"/>
     <clock equivalent="false" name="C" num_pins="1"/>
     <output equivalent="false" name="O" num_pins="1"/>
     <pb_type blif_model=".names" class="lut" name="BEL_LT-LUT" num_pb="1">
      <input name="in" num_pins="4" port_class="lut_in"/>
      <output name="out" num_pins="1" port_class="lut_out"/>
      <delay_matrix in_port="BEL_LT-LUT.in" out_port="BEL_LT-LUT.out" type="max">
       10e-12
       10e-12
       10e-12
       10e-12
      </delay_matrix>
     </pb_type>
     <!-- FlipFlop -->
     <pb_type blif_model=".latch" class="flipflop" name="BEL_FF-FF" num_pb="1">
      <clock name="clk" num_pins="1" port_class="clock"/>
      <input name="D" num_pins="1" port_class="D"/>
      <output name="Q" num_pins="1" port_class="Q"/>
      <T_setup clock="clk" port="BEL_FF-FF.D" value="10e-12"/>
      <T_clock_to_Q clock="clk" max="10e-12" port="BEL_FF-FF.Q"/>
     </pb_type>
     <interconnect>
      <direct input="BLK_IG-LUTFF.I" name="BEL_LT-LUT.in" output="BEL_LT-LUT.in"/>
      <direct input="BLK_IG-LUTFF.C" name="BEL_FF-FF.C" output="BEL_FF-FF.clk"/>
      <direct input="BEL_LT-LUT.out" name="BEL_FF-FF.D" output="BEL_FF-FF.D"/>
      <mux input="BEL_LT-LUT.out BEL_FF-FF.Q" name="BLK_IG-LUTFF.O" output="BLK_IG-LUTFF.O"/>
     </interconnect>
    </pb_type>
    <interconnect>
     <direct input="BLK_SI-LUTFF.I" name="BLK_IG-LUTFF.I" output="BLK_IG-LUTFF.I"/>
     <direct input="BLK_SI-LUTFF.C" name="BLK_IG-LUTFF.C" output="BLK_IG-LUTFF.C"/>
     <direct input="BLK_IG-LUTFF.O" name="BLK_SI-LUTFF.O" output="BLK_SI-LUTFF.O"/>
    </interconnect>
   </pb_type>
   <interconnect>
    <!-- Clock input mux -->
    <mux input="BLK_TI-LUTFF.CLK[0] BLK_TI-LUTFF.CLK[1]" name="BLK_SI-LUTFF.C" output="BLK_SI-LUTFF.C"/>
    <!-- Logic input muxes -->
    <mux input="BLK_TI-LUTFF.IN[0] BLK_TI-LUTFF.IN[1] BLK_TI-LUTFF.IN[2]" name="BLK_SI-LUTFF.I0" output="BLK_SI-LUTFF.I[0]"/>
    <mux input="BLK_TI-LUTFF.IN[1] BLK_TI-LUTFF.IN[2] BLK_TI-LUTFF.IN[3]" name="BLK_SI-LUTFF.I1" output="BLK_SI-LUTFF.I[1]"/>
    <mux input="BLK_TI-LUTFF.IN[2] BLK_TI-LUTFF.IN[3] BLK_TI-LUTFF.IN[4]" name="BLK_SI-LUTFF.I2" output="BLK_SI-LUTFF.I[2]"/>
    <mux input="BLK_TI-LUTFF.IN[3] BLK_TI-LUTFF.IN[4] BLK_TI-LUTFF.IN[5]" name="BLK_SI-LUTFF.I3" output="BLK_SI-LUTFF.I[3]"/>
    <!-- Output -->
    <direct input="BLK_SI-LUTFF.O" name="BLK_TI-LUTFF.OUT0" output="BLK_TI-LUTFF.OUT[0]"/>
    <direct input="BLK_SI-LUTFF.O" name="BLK_TI-LUTFF.OUT1" output="BLK_TI-LUTFF.OUT[1]"/>
   </interconnect>
   <pinlocations pattern="custom">
    <loc side="top">   BLK_TI-LUTFF.IN[0] BLK_TI-LUTFF.IN[1] BLK_TI-LUTFF.IN[2]  BLK_TI-LUTFF.OUT[0]  BLK_TI-LUTFF.CLK[0]</loc>
    <loc side="bottom">BLK_TI-LUTFF.IN[3] BLK_TI-LUTFF.IN[4] BLK_TI-LUTFF.IN[5]  BLK_TI-LUTFF.OUT[1]  BLK_TI-LUTFF.CLK[1]</loc>
    <loc side="right"/>
    <loc side="left"/>
   </pinlocations>
   <fc default_in_type="frac" default_in_val="1.0" default_out_type="frac" default_out_val="1.0">
    <fc_override fc_type="frac" fc_val="1.0" port_name="CLK"/>
   </fc>
  </pb_type>
 </complexblocklist>
</architecture>

Makefile

VPR ?= vpr

DEVICE_FILE = arch.xml
DEVICE = 2x4

# VPR commands
VPR_ARGS ?=
VPR_FULL_CMD = $(VPR) $(VPR_ARGS) $(DEVICE_FILE) --device $(DEVICE)

ROUTE_CHAN_WIDTH ?= 6

%.rr_graph.xml: %.eblif $(DEVICE_FILE)
	$(VPR_FULL_CMD) $(notdir $<) --route_chan_width $(ROUTE_CHAN_WIDTH) --write_rr_graph $(notdir $@)

%.disp: %.eblif $(DEVICE_FILE)
	$(VPR_FULL_CMD) $(notdir $<) --disp on

%.echo: %.eblif $(DEVICE_FILE)
	$(VPR_FULL_CMD) $(notdir $<) --echo_file on --full_stats on

%.verilog: %.eblif $(DEVICE_FILE)
	$(VPR_FULL_CMD) $(notdir $<) --gen_post_synthesis_netlist on

wire.eblif

.model top
.inputs di
.outputs do
.names di do
1 1
.end