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[0.456363] HW.GFX.GMA.Panel.Setup_PP_Sequencer
[0.456370] HW.GFX.GMA.Registers.Read: 0x0e200064 <- 0x000c7208:PCH_PP_ON_DELAYS
[0.456378] HW.GFX.GMA.Registers.Read: 0x13880e20 <- 0x000c720c:PCH_PP_OFF_DELAYS
[0.456385] HW.GFX.GMA.Registers.Read: 0x0004af06 <- 0x000c7210:PCH_PP_DIVISOR
[0.456386] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL
[0.456393] HW.GFX.GMA.Registers.Read: 0x00000008 <- 0x000c7204:PCH_PP_CONTROL
[0.456394] HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x000c7204:PCH_PP_CONTROL
[0.456401] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
[0.456402] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
[0.456403] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[0.456410] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL
[0.456411] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL
[0.456418] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
[0.456425] HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c2014:SFUSE_STRAP
[0.456426] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[0.456433] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL
[0.456434] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL
[0.456441] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
[0.456448] HW.GFX.GMA.Registers.Read: 0x00000007 <- 0x000c2014:SFUSE_STRAP
[0.456449] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
[0.456456] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL
[0.456457] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL
[0.456464] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1
[0.456466] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2
[0.456467] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1
[0.456469] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2
[0.456470] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1
[0.456472] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2
[0.456473] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1
[0.456474] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2
[0.456475] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1
[0.456476] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2
[0.456477] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1
[0.456478] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2
[0.456479] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1
[0.456480] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2
[0.456481] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1
[0.456482] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2
[0.456483] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1
[0.456484] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2
[0.456485] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1
[0.456486] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2
[0.456487] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1
[0.456488] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2
[0.456489] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1
[0.456490] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2
[0.456491] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1
[0.456492] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2
[0.456493] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1
[0.456494] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2
[0.456495] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1
[0.456496] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2
[0.456497] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1
[0.456498] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2
[0.456499] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1
[0.456500] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2
[0.456501] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1
[0.456502] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2
[0.456503] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1
[0.456505] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2
[0.456506] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1
[0.456507] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2
[0.456509] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1
[0.456510] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2
[0.456511] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1
[0.456512] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2
[0.456513] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1
[0.456514] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2
[0.456515] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1
[0.456516] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2
[0.456517] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1
[0.456518] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2
[0.456519] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1
[0.456520] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2
[0.456521] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1
[0.456522] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2
[0.456523] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1
[0.456524] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064efc:DDI_BUF_TRANS_C_S7T2
[0.456525] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1
[0.456526] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2
[0.456527] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1
[0.456528] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2
[0.456529] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0
[0.456530] HW.GFX.GMA.Registers.Read: 0x0886d800 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0
[0.456531] HW.GFX.GMA.Registers.Write: 0x0036db00 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0
[0.456533] Fully initialised.
[0.456533] Handle post-reset
[0.456636] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
[0.456644] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL
[0.456652] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
[0.456661] HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2
[0.456668] HW.GFX.GMA.Registers.Read: 0x00af0001 <- 0x0006c05c:DPLL_CTRL2
[0.456676] HW.GFX.GMA.Registers.Write: 0x00af8001 -> 0x0006c05c:DPLL_CTRL2
[0.456684] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT
[0.456691] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT
[0.456699] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT
[0.456707] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS
[0.456718] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.456723] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.456732] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.456741] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.456749] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.456758] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.456766] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.456774] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER
[0.456782] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.456790] HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.456798] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.456809] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS
[0.456819] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.456823] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.456832] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.456841] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.456849] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.456857] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.456865] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.456872] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER
[0.456879] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.456887] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.456895] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.456905] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL
[0.456913] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL
[0.456920] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
[0.456928] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL
[0.456936] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
[0.456946] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[0.456951] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.456962] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[0.456970] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[0.456979] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[0.456988] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.456998] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
[0.457005] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[0.457010] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457019] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[0.457027] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[0.457035] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[0.457043] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457052] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
[0.457059] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[0.457064] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457073] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[0.457081] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[0.457089] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[0.457097] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457106] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
[0.457113] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[0.457118] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457127] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[0.457135] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[0.457143] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[0.457151] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457160] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00138128:GT_MAILBOX_DATA
[0.457168] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[0.457173] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457182] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
[0.457190] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[0.457198] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[0.457207] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457217] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
[0.457225] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write
[0.457229] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457238] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
[0.457246] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
[0.457254] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
[0.457262] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
[0.457271] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
[0.457278] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL
[0.457285] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL
[0.457294] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
[0.457305] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
[0.457317] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ
[0.457325] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ
[0.457339] Setting initialized to true
[0.457342] Init: success
[0.457345] HW.GFX.GMA.Panel.On
[0.457348] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
[0.457359] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
[0.457366] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
[0.457379] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x000c7204:PCH_PP_CONTROL
[0.457386] HW.GFX.GMA.Registers.Write: 0x0000000b -> 0x000c7204:PCH_PP_CONTROL
[0.457400] HW.GFX.GMA.Display_Probing.Read_EDID
[0.457406] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.457410] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.457419] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.457427] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.457435] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.457444] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.457452] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.457459] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
[0.457466] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.457474] HW.GFX.GMA.Registers.Write: 0xf0000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.457483] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.457494] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
[0.457504] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.457508] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.457517] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.457526] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.457534] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.457543] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.457551] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.457558] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.457568] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER
[0.457575] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.457583] HW.GFX.GMA.Registers.Write: 0xf0000023 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.457592] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.457604] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
[0.457609] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
[0.457617] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
[0.457626] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
[0.457632] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
[0.457639] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
[0.457648] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
[0.458022] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458030] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
[0.458035] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458043] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
[0.458051] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
[0.458056] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458063] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
[0.458071] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
[0.458445] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458453] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
[0.458458] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458465] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
[0.458473] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
[0.458479] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458486] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
[0.458494] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
[0.458869] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
[0.458878] HW.GFX.GMA.Display_Probing.Read_EDID
[0.458882] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.458887] HW.GFX.GMA.Registers.Read: 0xf0000013 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.458896] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.458905] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.458913] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.458921] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.458929] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.458937] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.458942] HW.GFX.GMA.Registers.Read: 0xf0000013 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.458951] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.458959] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.458967] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.458975] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.458983] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.458991] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.459001] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER
[0.459008] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.459016] HW.GFX.GMA.Registers.Write: 0xf00000b3 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.459025] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.459035] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
[0.459040] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
[0.459047] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
[0.459056] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
[0.459062] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
[0.459069] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
[0.459077] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
[0.459457] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.459465] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
[0.459470] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.459478] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
[0.459487] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
[0.459492] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.459499] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
[0.459507] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
[0.459884] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.459892] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
[0.459897] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.459904] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
[0.459912] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
[0.459918] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.459925] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
[0.459933] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
[0.460310] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
[0.460318] HW.GFX.GMA.Display_Probing.Read_EDID
[0.460322] HW.GFX.GMA.I2C.I2C_Read
[0.460325] HW.GFX.GMA.I2C.Init_GMBUS
[0.460328] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
[0.460341] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[0.460348] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[0.460362] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[0.460385] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
[0.460393] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0
[0.460407] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[0.460420] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[0.460433] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[0.460447] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[0.460581] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
[0.460589] HW.GFX.GMA.I2C.Release_GMBUS
[0.460592] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[0.460605] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[0.460619] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
[0.460632] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[0.460640] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[0.460654] HW.GFX.GMA.Display_Probing.Read_EDID
[0.460658] HW.GFX.GMA.I2C.I2C_Read
[0.460661] HW.GFX.GMA.I2C.Init_GMBUS
[0.460664] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
[0.460677] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[0.460684] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[0.460698] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
[0.460720] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
[0.460727] HW.GFX.GMA.I2C.Reset_GMBUS
[0.460730] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
[0.460744] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
[0.460758] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[0.460779] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
[0.460786] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0
[0.460800] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
[0.460813] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
[0.460826] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
[0.460840] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
[0.460976] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
[0.460983] HW.GFX.GMA.I2C.Release_GMBUS
[0.460986] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
[0.460999] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
[0.461013] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
[0.461026] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
[0.461034] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[0.461048] HW.GFX.GMA.Panel.Wait_On
[0.819001] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
[0.819008] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
[0.819015] HW.GFX.GMA.Registers.Read: 0x0000000b <- 0x000c7204:PCH_PP_CONTROL
[0.819016] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x000c7204:PCH_PP_CONTROL
[0.819023] HW.GFX.GMA.Display_Probing.Read_EDID
[0.819023] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[0.819024] HW.GFX.GMA.Registers.Read: 0xf0000053 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819025] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819026] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.819027] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.819028] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.819029] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.819030] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.819031] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
[0.819032] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819033] HW.GFX.GMA.Registers.Write: 0xf00000fb -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.819034] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.819035] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
[0.819036] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
[0.819037] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
[0.819038] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
[0.819038] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
[0.819040] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
[0.819041] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
[0.819370] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
[0.819371] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00064014:DDI_AUX_DATA_A_1
[0.819372] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[0.819372] HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819374] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819375] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.819376] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.819377] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.819378] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.819379] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[0.819379] HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819381] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819382] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.819383] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.819384] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.819385] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.819386] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.819387] HW.GFX.GMA.Registers.Unset_Mask: 0x00000080 !S PWR_WELL_CTL_DRIVER
[0.819388] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819389] HW.GFX.GMA.Registers.Write: 0xf000007f -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.819390] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[0.819390] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819392] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819393] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.819394] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.819395] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.819396] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.819397] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.819398] HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER
[0.819399] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819400] HW.GFX.GMA.Registers.Write: 0xf000001f -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.819401] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[0.819401] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819403] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819404] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.819405] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.819406] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.819407] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.819408] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.819409] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
[0.819410] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819411] HW.GFX.GMA.Registers.Write: 0xf0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.819412] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[0.819412] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819414] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819415] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
[0.819416] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
[0.819417] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
[0.819418] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
[0.819419] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
[0.819420] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS
[0.819421] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
[0.819422] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS
[0.819423] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER
[0.819424] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
[0.819425] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
[0.819426] HW.GFX.GMA.Panel.Off
[0.819426] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
[0.819433] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[0.819434] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL
[0.819441] HW.GFX.GMA.Registers.Read: 0x00000003 <- 0x000c7204:PCH_PP_CONTROL
[0.819442] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL
[1.319450] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
[1.655321] Primary port is disabled
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