Created
February 9, 2020 22:27
-
-
Save mkaczanowski/908fed6fc00818d2715d2b11d71a8f83 to your computer and use it in GitHub Desktop.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
diff --git a/src/common/hdl/oh_mux.v b/src/common/hdl/oh_mux.v | |
index 7bda282..4025884 100644 | |
--- a/src/common/hdl/oh_mux.v | |
+++ b/src/common/hdl/oh_mux.v | |
@@ -21,7 +21,7 @@ module oh_mux #( parameter DW = 1, // width of data inputs | |
begin | |
out[DW-1:0] = 'b0; | |
for(i=0;i<N;i=i+1) | |
- out[DW-1:0] |= {(DW){sel[i]}} & in[((i+1)*DW-1)-:DW]; | |
+ out[DW-1:0] = out[DW-1:0] | {(DW){sel[i]}} & in[((i+1)*DW-1)-:DW]; | |
end | |
endmodule // oh_mux | |
diff --git a/src/elink/hdl/erx_io.v b/src/elink/hdl/erx_io.v | |
index 4faa3cf..aca5c93 100644 | |
--- a/src/elink/hdl/erx_io.v | |
+++ b/src/elink/hdl/erx_io.v | |
@@ -318,6 +318,7 @@ module erx_io (/*AUTOARG*/ | |
if(PLATFORM=="ULTRASCALE") | |
begin : ultrascale | |
+ genvar j; | |
for(j=0; j<9; j=j+1) | |
begin : gen_idelay | |
`define IDELAYCTRL_WONT_SYNTHESIZE | |
diff --git a/src/parallella/fpga/headless_e16_z7010/system_bd.tcl b/src/parallella/fpga/headless_e16_z7010/system_bd.tcl | |
index 3f3f7da..07ffed3 100644 | |
--- a/src/parallella/fpga/headless_e16_z7010/system_bd.tcl | |
+++ b/src/parallella/fpga/headless_e16_z7010/system_bd.tcl | |
@@ -10,7 +10,7 @@ | |
################################################################ | |
# Check if script is running in correct Vivado version. | |
################################################################ | |
-set scripts_vivado_version 2015.2 | |
+set scripts_vivado_version 2019.1 | |
set current_vivado_version [version -short] | |
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { | |
diff --git a/src/parallella/fpga/headless_e16_z7010/system_params.tcl b/src/parallella/fpga/headless_e16_z7010/system_params.tcl | |
index 4ce1a4c..fdfdee0 100644 | |
--- a/src/parallella/fpga/headless_e16_z7010/system_params.tcl | |
+++ b/src/parallella/fpga/headless_e16_z7010/system_params.tcl | |
@@ -25,3 +25,4 @@ set constraints_files [list \ | |
# PREPARE FOR SYNTHESIS | |
########################################################### | |
set oh_synthesis_options "-verilog_define CFG_ASIC=0" | |
+set oh_verilog_define "CFG_ASIC=0 TARGET_SIM=1 CFG_PLATFORM=\"ZYNQ\"" | |
diff --git a/src/parallella/fpga/headless_e16_z7020/system_bd.tcl b/src/parallella/fpga/headless_e16_z7020/system_bd.tcl | |
index 6dc4308..2828be2 100644 | |
--- a/src/parallella/fpga/headless_e16_z7020/system_bd.tcl | |
+++ b/src/parallella/fpga/headless_e16_z7020/system_bd.tcl | |
@@ -10,7 +10,7 @@ | |
################################################################ | |
# Check if script is running in correct Vivado version. | |
################################################################ | |
-set scripts_vivado_version 2015.2 | |
+set scripts_vivado_version 2019.1 | |
set current_vivado_version [version -short] | |
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { | |
diff --git a/src/parallella/fpga/sdr_fmcomms/system_bd.tcl b/src/parallella/fpga/sdr_fmcomms/system_bd.tcl | |
index 63b568e..3394d6f 100644 | |
--- a/src/parallella/fpga/sdr_fmcomms/system_bd.tcl | |
+++ b/src/parallella/fpga/sdr_fmcomms/system_bd.tcl | |
@@ -10,7 +10,7 @@ | |
################################################################ | |
# Check if script is running in correct Vivado version. | |
################################################################ | |
-set scripts_vivado_version 2015.2 | |
+set scripts_vivado_version 2019.1 | |
set current_vivado_version [version -short] | |
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment