some.v

module sync_counter_1bit_pn (input up,dn,clk,rst,output reg q,output wire next_up,next_dn);
wire nq,prev;
not(nq,q);
or(prev,up,dn);
and(next_up,up,q);
and(next_dn,dn,nq);
initial q <= 1'b0;
always @(posedge clk or negedge rst) begin
  if(!rst) begin
    q <= 1'b0;
  end else begin
    if(prev) begin
      q <= nq;
    end
  end
end
endmodule