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modjo756/secoA62Lvds_Spi.patch

Created October 7, 2016 14:18
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patch to use lvds, spi, can and i2c on secoA62
Raw
secoA62Lvds_Spi.patch
--- git.orig/arch/arm/boot/dts/imx6qdl-seco_SBC_A62.dtsi 2016-10-03 10:53:07.000000000 +0200
+++ git/arch/arm/boot/dts/imx6qdl-seco_SBC_A62.dtsi 2016-10-06 13:42:01.499875220 +0200
@@ -24,11 +24,16 @@
mmc1 = &usdhc2;
mmc2 = &usdhc1;
mmc3 = &usdhc4;
+ spi0 = &ecspi2;
};
memory {
reg = <0x10000000 0x40000000>;
};
+
+/* __________________________________________________________________________
+ * |_______________________________ CLOCKING _________________________________|
+ */
clocks {
codec_osc: anaclk2 {
@@ -42,6 +47,24 @@
clocks = <&clks IMX6QDL_CLK_CKO2>;
#clock-cells = <0>;
};
+
+/* __________________________________________________________________________
+ * |___________________________ POWER MANAGEMENT _____________________________|
+ */
+ power_signal: power_signal {
+ power-gpio = <&gpio2 4 0>;
+ set_high;
+ only_for_poweroff;
+ };
+
+ pwr_button: pwr_button {
+ compatible = "seco,power_button";
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ halt-gpio = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ pwr-gpio = <&gpio2 3 GPIO_ACTIVE_LOW>;
+
+ };
regulators {
compatible = "simple-bus";
@@ -81,14 +104,37 @@
};
};
+
+/* __________________________________________________________________________
+ * |____________________________ AUDIO ALC655 ________________________________|
+ */
+ codec_alc655: codec_alc655 {
+ compatible = "realtek,alc655";
+ status = "okay";
+ };
+ sound_alc655: sound_alc655 {
+ compatible = "fsl,imx-alc655-audio";
+ model = "fsl,imx-alc655-audio";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec_alc655>;
+ mux-int-port = <1>;
+ mux-ext-port = <6>;
+ status = "okay";
+ };
+
+/* __________________________________________________________________________
+ * |__________________________________________________________________________|
+ */
sound-hdmi {
compatible = "fsl,imx6q-audio-hdmi",
"fsl,imx-audio-hdmi";
model = "imx-audio-hdmi";
hdmi-controller = <&hdmi_audio>;
};
-
+/* __________________________________________________________________________
+ * |____________________________ FRAME BUFFER ________________________________|
+ */
mxcfb1: fb@0 {
compatible = "fsl,mxc_sdc_fb";
@@ -135,10 +181,17 @@
#include <dt-bindings/pwm/pwm.h>
backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 12 16 20 24 28 32 36
+ 40 44 48 52 56 60 64 68 72 76
+ 80 84 88 92 96 100 104 108 112 116
+ 120 124 128 132 136 140 144 148 152 156
+ 160 164 168 172 176 180 184 188 192 196
+ 200 204 208 212 216 220 224 228 232 236
+ 240 244 248 252 255
+ >;
+ default-brightness-level = <65>;
enable-gpios = <&gpio1 4 0>;
status = "okay";
};
@@ -167,13 +220,24 @@
};
&clks {
- assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
- <&clks IMX6QDL_PLL4_BYPASS>,
- <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
-
- assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
- <&clks IMX6QDL_PLL4_BYPASS_SRC>;
- assigned-clock-rates = <0>, <0>, <24576000>;
+ assigned-clocks =
+ <&clks IMX6QDL_PLL4_BYPASS_SRC>,
+ <&clks IMX6QDL_PLL4_BYPASS>,
+
+ <&clks IMX6QDL_CLK_EMI_SEL>,
+ <&clks IMX6QDL_CLK_EMI_SLOW_SEL>,
+
+ <&clks IMX6QDL_CLK_PLL4_POST_DIV>,
+ <&clks IMX6QDL_CLK_EMI_SLOW_PODF>;
+
+ assigned-clock-parents =
+ <&clks IMX6QDL_CLK_LVDS2_IN>,
+ <&clks IMX6QDL_PLL4_BYPASS_SRC>,
+
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_AXI>;
+
+ assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>, <8>;
};
@@ -195,13 +259,26 @@
MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1f071
/* Reset */
MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1f071
-
- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0
+ /* PWR CONTROLLER */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* ON_OFF */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* POWER ON */
+
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0
/* LVDS */
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f071
-
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f071
+
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* Ethernet Power on */
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* Phy Interrupt */
+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1f071 /* Camera Power Enable */
+ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1f071 /* Camera Reset */
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0 // CSI master clock (CN11)
+
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* SATA led activity*/
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* HDMI - check */
+ //MX6QDL_PAD_EIM_D30__USB_H1_OC 0x80000000 /*USB Over Current*/
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x80000000 /*WIFI Tx antenna enable*/
>;
};
@@ -209,6 +286,14 @@
/* __________________________________________________________________________
* |________________________________ UART ____________________________________|
*/
+ /* UART4 */
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
@@ -220,6 +305,14 @@
/* __________________________________________________________________________
* |_________________________________ I2C ____________________________________|
*/
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -247,6 +340,17 @@
>;
};
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ /* CS SPI 2 */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
+
+ >;
+ };
+
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
@@ -340,14 +444,27 @@
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
-
- };
-};
/* __________________________________________________________________________
- * |__________________________________________________________________________|
+ * |________________________________ TOUCH ___________________________________|
*/
+ pinctrl_st1232: st1232grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 // Touch Interrupt
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000 // Touch Reset
+ >;
+ };
+/* __________________________________________________________________________
+ * |________________________________ CAN ___________________________________|
+ */
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
+ >;
+ };
-
+ };
+};
/* __________________________________________________________________________
@@ -355,6 +472,12 @@
* | UART |
* |__________________________________________________________________________|
*/
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -425,6 +548,19 @@
};
+&ecspi2 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 29 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <2000000>;
+ };
+};
+
&ecspi3 {
fsl,spi-num-chipselects = <1>;
@@ -443,6 +579,13 @@
* | I2C INTERFACE/DEVICE |
* |__________________________________________________________________________|
*/
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -476,6 +619,29 @@
mclk = <24000000>;
mclk_source = <0>;
};
+
+ st1232-ts@55 {
+ compatible = "sitronix,st1232";
+ reg = <0x55>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_st1232>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
+
+ gt928@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_st1232>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ };
};
/* __________________________________________________________________________
* |__________________________________________________________________________|
@@ -525,6 +691,26 @@
* |__________________________________________________________________________|
*/
+/* __________________________________________________________________________
+ * | |
+ * | AUDIO |
+ * |__________________________________________________________________________|
+ */
+/*&ssi1 {
+ fsl,mode = "ac97-slave";
+ pinctrl-names = "default", "ac97-running", "ac97-reset", "ac97-warm-reset";
+ pinctrl-0 = <&ac97link_running>;
+ pinctrl-1 = <&ac97link_running>;
+ pinctrl-2 = <&ac97link_reset>;
+ pinctrl-3 = <&ac97link_warm_reset>;
+ //sync, sdata (output), reset
+ ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 31 0>;
+ status = "okay";
+};
+
+&audmux {
+ status = "okay";
+};*/
/* __________________________________________________________________________
* | |
@@ -547,15 +733,20 @@
* |__________________________________________________________________________|
*/
&mipi_csi {
- status = "okay";
- ipu_id = <0>;
- csi_id = <0>;
+ ipu_id = <0>;
+ csi_id = <0>;
v_channel = <0>;
- lanes = <2>;
+ lanes = <2>;
+ status = "okay";
};
/* __________________________________________________________________________
- * |__________________________________________________________________________|
+ * |__________________________________CAN________________________________________|
*/
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
/* __________________________________________________________________________
@@ -596,17 +787,16 @@
native-mode = <&timing0>;
timing0: LDB-WVGA {
- clock-frequency = <38000000>;
+ clock-frequency = <33660000>;
hactive = <800>;
vactive = <480>;
hback-porch = <56>;
hfront-porch = <50>;
- vback-porch = <20>;
- vfront-porch = <53>;
- hsync-len = <180>;
- vsync-len = <30>;
+ vback-porch = <23>;
+ vfront-porch = <20>;
+ hsync-len = <150>;
+ vsync-len = <2>;
};
-
timing1: LDB-SVGA {
clock-frequency = <40000000>;
hactive = <800>;
@@ -683,30 +873,6 @@
};
};
- lvds-channel@1 {
- reg = <1>;
- fsl,data-mapping = "spwg";
- fsl,data-width = <18>;
- status = "okay";
-
- crtc = "ipu2-di1";
- display-timings {
- native-mode = <&timing7>;
-
- timing7: seco_lvds1 {
- clock-frequency = <38000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <56>;
- hfront-porch = <50>;
- vback-porch = <20>;
- vfront-porch = <23>;
- hsync-len = <150>;
- vsync-len = <60>;
- };
- };
- };
-
};
/* __________________________________________________________________________
* |__________________________________________________________________________|
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