synthesis file

test.py

from nmigen import *
from nmigen_boards.rz_easyfpga_a2_2 import RZEasyFPGAA2_2Platform

from disp import TestDisplay
from buzz import TestBuzzer
from butt import TestButtons
from leds import TestLeds
from vga import TestVGA

class RZEFPGATest(Elaboratable):
    def elaborate(self, platform):
        m = Module()

        clk50 = platform.request("clk50")
        m.submodules.disp = TestDisplay(clk50)
        m.submodules.buzz = TestBuzzer(clk50)
        m.submodules.vga = TestVGA(clk50)
        m.submodules.butt = TestButtons()
        m.submodules.leds = TestLeds()

        m.d.comb += m.submodules.leds.a.eq(m.submodules.butt.y)
        m.d.comb += m.submodules.buzz.speed.eq(m.submodules.butt.y)

        return m

if __name__ == "__main__":
    RZEasyFPGAA2_2Platform().build(RZEFPGATest(), do_program=True)