not working VGA implementation

vga.py

from nmigen import *
from nmigen.sim import *

# Dummy VGA connector for testbench purposes
class DummyVGA(Elaboratable):
    def __init__(self):
        self.r = Signal(1, reset=0)
        self.g = Signal(1, reset=0)
        self.b = Signal(1, reset=0)
        self.hs = Signal(1, reset=0)
        self.vs = Signal(1, reset=0)

# VGA module
# Outputs a green 200x600 frame at 60Hz on SVGA 800x600 mode.
# Expects a 10MHz clock on Testbench, creates 10MHz clock from clk50 on Cyclone IV.
class TestVGA(Elaboratable):
    def __init__(self, clk50):
        self.clk50 = clk50

    def elaborate(self, platform):
        m = Module()

        vga = DummyVGA()
        if platform != None:
            vga = platform.request("vga")

            cd_sync = ClockDomain()
            m.domains += cd_sync

            m.submodules.pll = Instance(
                "altpll",
                p_operation_mode = "NORMAL",
                p_inclk0_input_frequency = 20000, # 50MHz = 20000ps period
                p_compensate_clock = "CLK0",
                # 50 MHz -> 10 MHz
                p_clk0_divide_by = 5,
                p_clk0_multiply_by = 1,
                i_inclk = self.clk50,
                o_clk = cd_sync.clk,
            )

        hctr = Signal(9, reset=0)
        vctr = Signal(10, reset=0)

        # Incrementing / Resetting
        with m.If(hctr == 263):
            m.d.sync += hctr.eq(0)
            with m.If(vctr == 627):
                m.d.sync += vctr.eq(0)
            with m.Else():
                m.d.sync += vctr.eq(vctr + 1)
        with m.Else():
            m.d.sync += hctr.eq(hctr + 1)
        
        with m.If(vctr < 600):
            with m.If(hctr < 200): # 800 @ 40MHz
                m.d.comb += [
                    vga.r.eq(0),
                    vga.g.eq(1),
                    vga.b.eq(0),
                    vga.hs.eq(1),
                    vga.vs.eq(1)
                ]
            with m.Elif(hctr < 210): # 840 @ 40MHz
                m.d.comb += [
                    vga.r.eq(0),
                    vga.g.eq(0),
                    vga.b.eq(0),
                    vga.hs.eq(1),
                    vga.vs.eq(1)
                ]
            with m.Elif(hctr < 242): # 968 @ 40MHz
                m.d.comb += [
                    vga.r.eq(0),
                    vga.g.eq(0),
                    vga.b.eq(0),
                    vga.hs.eq(0),
                    vga.vs.eq(1)
                ]
            with m.Else():
                m.d.comb += [
                    vga.r.eq(0),
                    vga.g.eq(0),
                    vga.b.eq(0),
                    vga.hs.eq(1),
                    vga.vs.eq(1)
                ]
        with m.Elif(vctr < 601):
            m.d.comb += [
                vga.r.eq(0),
                vga.g.eq(0),
                vga.b.eq(0),
                vga.hs.eq(1),
                vga.vs.eq(1)
            ]
        with m.Elif(vctr < 605):
            m.d.comb += [
                vga.r.eq(0),
                vga.g.eq(0),
                vga.b.eq(0),
                vga.hs.eq(1),
                vga.vs.eq(0)
            ]
        with m.Else():
            m.d.comb += [
                vga.r.eq(0),
                vga.g.eq(0),
                vga.b.eq(0),
                vga.hs.eq(1),
                vga.vs.eq(1)
            ]
        
        return m

        
if __name__ == "__main__":
    dut = TestVGA(Signal()) # TestVGA with dummy clk50. No need for it in testbench.

    sim = Simulator(dut)

    def proc():
        for _ in range(333334): # just about 2 frames
            yield Tick()
            yield Settle()
    
    sim.add_clock(1e-7) # 10MHz
    sim.add_sync_process(proc)
    with sim.write_vcd("vga.vcd", "vga.gtkw"):
        sim.run()