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@mohamed
Created May 22, 2023 13:54
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cocotb example
# Run with make SIM=verilator
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = $(shell pwd)/skid_buffer.sv
TOPLEVEL = skid_buffer
MODULE = skid_buffer_tb
EXTRA_ARGS += --coverage --trace-fst --trace-structs
include $(shell cocotb-config --makefiles)/Makefile.sim
#!/usr/bin/env python3
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
@cocotb.test()
async def skid_simple_test(dut):
clock = Clock(dut.clk_i, 10, units="ns")
cocotb.start_soon(clock.start(start_high=False))
dut.wr_valid_i.value = 0
dut.rd_ready_i.value = 1
dut.wr_data_i.value = 0
dut.rst_ni.value = 0
# Reset the DUT
for _ in range(3):
await RisingEdge(dut.clk_i)
dut.rst_ni.value = 1
await RisingEdge(dut.clk_i)
expected_val = 0 # Matches initial input value
for i in range(100):
val = random.randint(1, 255)
dut.wr_data_i.value = val
dut.wr_valid_i.value = 1
assert dut.wr_ready_o.value == 1
await RisingEdge(dut.clk_i)
assert dut.rd_data_o.value == expected_val, f"output was incorrect on the {i}th cycle"
expected_val = val # Save random value for next RisingEdge
# Check the final input on the next clock
await RisingEdge(dut.clk_i)
assert dut.rd_data_o.value == expected_val, "output was incorrect on the last cycle"
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