mohammadfa91

#include "components.h"
#include "SPC58NN_GTM.h"
#define CLK_ENABLE     0x2UL
/* Register CMU_CLK_EN bit */
#define SPC5_GTM_CMU_EN_CLK0                     0U
#define SPC5_GTM_CMU_EN_CLK1                     2U
#define SPC5_GTM_CMU_EN_CLK2                     4U
#define SPC5_GTM_CMU_EN_CLK3                     6U
#define SPC5_GTM_CMU_EN_CLK4                     8U
#define SPC5_GTM_CMU_EN_CLK5                     10U

mohammadfa91

#include "components.h"
#include "SPC58NN_GTM.h"
#include "Reg_eSys_GTM.h"

void ATOM_config(void){
//	REG_WRITE32(GTM_CMU_CLK_0_CTRL, 0x79UL);
	REG_WRITE32(GTM_ATOM_CH_CTRL(0, 1), 0x00000802);	/* SL=1, MODE=2 (SOMP) */
	REG_WRITE32(GTM_ATOM_CH_SR1(0, 1), 5000); 			/* Set reload of duty to half */
	REG_WRITE32(GTM_ATOM_CH_CM1(0, 1), 5000); 			/* Set actual duty to half */
	REG_WRITE32(GTM_ATOM_CH_SR0(0, 1), 10000); 			/* Set reload of period */

mohammadfa91

#include "components.h"
#include "SPC58NN_GTM.h"

/*
 * Application entry point.
 */
void ATOM_config(void){
//	GTM.CMU.CLK_0_CTRL.R = 79UL;
//	GTM.CMU.CLK_EN.R |= 2UL;
	GTM.ATOM[0].CH[1].CTRL.R = 0x00000802;		/* SL=1, MODE=2 (SOMP) */