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Muhammed Okumuş mokumus

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mokumus / client.c
Last active September 24, 2021 08:08
C SQL Simulation, Multi-threaded Server, Read/Writer Paradigm
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <unistd.h> // getopt(), access(), read(), close()
#include <arpa/inet.h>
#include <time.h> // time()
#define MAX_IP 64
#define MAX_PATH 1024
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mokumus / main.c
Created June 17, 2020 16:05
C printf macro to add timestamp at each print
#include <stdio.h>
#include <time.h>
#include <string.h>
char * timestamp();
#define print_log(f_, ...) printf("%s ", timestamp()), printf((f_), ##__VA_ARGS__), printf("\n")
@mokumus
mokumus / is_fibonacci.v
Last active June 7, 2020 11:45
Fibonacci FSM in verilog. Check repo for other modules and FSM design: https://github.com/mokumus/NumberAnalyzerFSM
module is_fibonacci(
input CLK,
input RESET,
input [31:0] N,
output reg O,
output reg DONE
);
reg [31:0] a;
reg [31:0] b;
@mokumus
mokumus / Main.java
Last active May 28, 2020 08:44
Interview Question #1 - Swap without a third variable
package com.company;
public class Main {
public static void main(String[] args) {
int A = 30, B = 66;
System.out.println("Before swap\nA: " + A + " B: " + B);
A = A + B;
B = A - B;
A = A - B;
System.out.println("After swap\nA: " + A + " B: " + B);
@mokumus
mokumus / sqd_structural.v
Last active May 20, 2020 11:16
5-bit sequence detector that detects '10111' bit pattern. Implemented using structural Verilog HDL. State diagram and truth table can be viewed at: https://github.com/mokumus/BitSequenceDetector-VHDL/blob/master/Report.pdf
module sqd_structural(
input CLK,
input X,
input RESET,
output Z_OUT
);
wire Q0,Q0N,Q1,Q1N,Q2,Q2N; //State Bits
wire A1,A2,A3,A4,A5; //Gate output wires
wire D0,D1,D2; //D Flip-Flop inputs