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@moonheart08
Created May 12, 2021 18:42
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// Standard form 1.
{reg:
[
{bits: 1, name: '0', type: 1},
{bits: 6, name: 'opcode', type: 2},
{bits: 3, name: 'func1', type: 3},
{bits: 3, name: 'dest[2:0]', type: 4},
{bits: 3, name: 'src1[2:0]', type: 5},
{bits: 1, name: '1', type: 1},
{bits: 2, name: 'dest[4:3]', type: 4},
{bits: 2, name: 'src1[4:3]', type: 5},
{bits: 5, name: 'src2', type: 6},
{bits: 1, name: 'mode', type: 7},
{bits: 5, name: 'adjust', type: 7},
],
config: {
bits: 32,
lanes: 2
}
}
// Immediate standard form 1.
{reg:
[
{bits: 1, name: '0', type: 1},
{bits: 6, name: 'opcode', type: 2, attr: 0b000_000},
{bits: 3, name: 'func1', type: 3, attr: 0b001},
{bits: 3, name: 'dest[2:0]', type: 4},
{bits: 3, name: 'imm[2:0]', type: 5},
{bits: 1, name: '1', type: 1, attr: 'opt.'},
{bits: 2, name: 'dest[4:3]', type: 4},
{bits: 2, name: 'imm[4:3]', type: 5},
{bits: 5, name: 'src2', type: 6},
{bits: 6, name: 'imm[10:5]', type: 5},
{bits: 1, name: '1', type: 1, attr: 'opt.'},
{bits: 15, name: 'imm[25:11]', type: 5},
{bits: 1, name: '1', type: 1, attr: 'opt.'},
{bits: 6, name: 'imm[31:26]', type: 5},
{bits: 9, type: 0, attr: 0b000_000_000 },
],
config: { // Change values to get smaller forms of instruction.
bits: 64, // 48, 32, 16
lanes: 4, // 3, 2, 1
hspace:'555',
vspace:'55',
}
}
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