adc.rs

#[entry]
fn main() -> ! {
    let stm32f3_peripherals = stm32f303::Peripherals::take().unwrap();
    let rcc = &stm32f3_peripherals.RCC;
    let adc1 = &stm32f3_peripherals.ADC1;

    rcc.cr.modify(|_, w| {
        w.hsebyp().set_bit()
         .hseon().set_bit()
    });
    rcc.cfgr2.modify(|_, w| {
        w.prediv().div1()
    });
    rcc.cr.modify(|_, w| {
        w.pllon().off()
    });
    rcc.cfgr.modify(|_, w| {
        w.pllmul().mul6()
         .pllsrc().hse_div_prediv()
    });
    rcc.cr.modify(|_, w| {
        w.pllon().on()
    });
    rcc.cfgr2.modify(|_, w| {
        w.adc12pres().div1()
    });
    rcc.ahbenr.modify(|_, w| {
        w.iopaen().set_bit()
         .adc12en().set_bit()
    });
    adc1.sqr1.modify(|r, w| {
        // select channel 2: I couldn't find a safe function for these bits
        unsafe { w.bits((r.bits() & !0x000007C0) | 0x00000080) }
    });
    
    loop {
        adc1.cr.modify(|_, w| {
            w.aden().set_bit()
        });
        // Wait until ready: The loop does not work, this may be because of some optimization. The
        // hprintln makese it work slightly better.
        // while adc1.isr.read().adrdy().is_not_ready() {};
        hprintln!("TODO").unwrap();

        adc1.isr.modify(|_, w| {
            w.eoc().set_bit()
             .eos().set_bit()
             .ovr().set_bit()
        });
        adc1.cr.modify(|_, w| {
            w.adstart().start()
        });

        // Print the value
        hprintln!("{}", adc1.dr.read().rdata().bits()).unwrap();

        adc1.cr.modify(|_, w| {
            w.adstp().stop()
        });
    }
}

Reference: https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.c

There are some issues:
*

      adc1.isr.modify(|_, w| {
            w.eoc().set_bit()
             .eos().set_bit()
             .ovr().set_bit()
        });

(should all be clear_bit)

• adc is stopped and started every loop-cycle.
• pin is not configured as analog