yosys_trial

_my_yosys_trial.md

my yosys trial

yosys を試したときのファイル一式。

1. Installing yosys

yosys の Release から最新版を DL し、make, sudo make install する。 make は -j<n> オプションが使えるが、<n> を省略すると RAM の限界を超えるスレッド数でコンパイルが走り、失敗する（kill される）ので注意。

2. Read SystemVerilog code

read -sv でよい。

3. Batch mode

yosys -s path/to/script.txt

count_axi4_lite_slv.sv

`default_nettype none

`include "count_param_def.svh"

module count_axi4_lite_slv #(
    localparam int COUNT_BIT_WIDTH = 4
)(
    /* ---------- AXI4-Lite signals ---------- */
    /* global signals */
    input wire logic s_axi4_lite_aclk,
    input wire logic s_axi4_lite_aresetn,

    /* write address channel */
    input wire logic s_axi4_lite_awvalid,
    output wire logic s_axi4_lite_awready,
    input wire logic [AXI4_LITE_ADDR_WIDTH-1:0] s_axi4_lite_awaddr,
    input wire logic [2:0] s_axi4_lite_awprot,

    /* write data channel */
    input logic s_axi4_lite_wvalid,
    output logic s_axi4_lite_wready,
    input logic [AXI4_LITE_BUS_WIDTH-1:0] s_axi4_lite_wdata,
    input logic [AXI4_LITE_BUS_WIDTH/8-1:0] s_axi4_lite_wstrb,

    /* write response channel */
    output logic s_axi4_lite_bvalid,
    input logic s_axi4_lite_bready,
    output logic [1:0] s_axi4_lite_bresp,

    /* read address channel */
    input logic s_axi4_arvalid,
    output logic s_axi4_arready,
    input logic [AXI4_LITE_ADDR_WIDTH-1:0] s_axi4_araddr,
    input logic [2:0] s_axi4_arprot,

    /* read data channel */
    output logic s_axi4_rvalid,
    input logic s_axi4_rready,
    output logic [AXI4_LITE_BUS_WIDTH-1:0] s_axi4_rdata,
    output logic [1:0] s_axi4_rresp,
    /* -------------------- */

    output wire logic [COUNT_BIT_WIDTH-1:0] or_count
);
    wire logic w_rst_cnt;

    count_csr count_csr_0 (
        .o_rst_cnt(w_rst_cnt),
        .*
    );

    always_ff @(posedge s_axi4_lite_aclk) begin
        if (!s_axi4_lite_aresetn | w_rst_cnt) begin
            or_count <= '0;
        end else begin
            or_count <= or_count + COUNT_BIT_WIDTH'(1);
        end
    end
endmodule

`default_nettype wire

count_csr.sv

`default_nettype none

`include "count_param_def.svh"

module count_csr (
    /* ---------- AXI4-Lite signals ---------- */
    /* global signals */
    input wire logic s_axi4_lite_aclk,
    input wire logic s_axi4_lite_aresetn,

    /* write address channel */
    input wire logic s_axi4_lite_awvalid,
    output wire logic s_axi4_lite_awready,
    input wire logic [AXI4_LITE_ADDR_WIDTH-1:0] s_axi4_lite_awaddr,
    input wire logic [2:0] s_axi4_lite_awprot,

    /* write data channel */
    input logic s_axi4_lite_wvalid,
    output logic s_axi4_lite_wready,
    input logic [AXI4_LITE_BUS_WIDTH-1:0] s_axi4_lite_wdata,
    input logic [AXI4_LITE_BUS_WIDTH/8-1:0] s_axi4_lite_wstrb,

    /* write response channel */
    output logic s_axi4_lite_bvalid,
    input logic s_axi4_lite_bready,
    output logic [1:0] s_axi4_lite_bresp,

    /* read address channel */
    input logic s_axi4_arvalid,
    output logic s_axi4_arready,
    input logic [AXI4_LITE_ADDR_WIDTH-1:0] s_axi4_araddr,
    input logic [2:0] s_axi4_arprot,

    /* read data channel */
    output logic s_axi4_rvalid,
    input logic s_axi4_rready,
    output logic [AXI4_LITE_BUS_WIDTH-1:0] s_axi4_rdata,
    output logic [1:0] s_axi4_rresp,
    /* -------------------- */

    output wire logic o_rst_cnt,
);

    always_ff @(posedge s_axi4_lite_aclk) begin
        if (!s_axi4_lite_aresetn) begin
        end else begin
        end
    end
endmodule

`default_nettype wire

count_param_def.svh

localparam int AXI4_LITE_ADDR_WIDTH = 32;
localparam int AXI4_LITE_BUS_WIDTH = 32;

yosys_script.txt

read -sv count_param_def.svh
read -sv count_csr.sv
read -sv count_axi4_lite_slv.sv

prep -top count_axi4_lite_slv

write_json count_axi4_lite_slv.json

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