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January 13, 2021 20:21
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[39m################################################################ | |
## ## | |
## CHIPSEC: Platform Hardware Security Assessment Framework ## | |
## ## | |
################################################################[0m | |
[39m[CHIPSEC] Version 1.5.8[0m | |
[39m[CHIPSEC] Arguments: [0m | |
[39m[0m | |
[39m****** Chipsec Linux Kernel module is licensed under GPL 2.0[0m | |
[39m[CHIPSEC] API mode: using CHIPSEC kernel module API[0m | |
[39m[CHIPSEC] OS : Linux 5.4.0-60-generic #67-Ubuntu SMP Tue Jan 5 18:31:36 UTC 2021 x86_64[0m | |
[39m[CHIPSEC] Python : 2.7.18 (64-bit)[0m | |
[39m[CHIPSEC] Helper : LinuxHelper (/home/mouad/Documents/chipsec/chipsec/helper/linux/chipsec.ko)[0m | |
[39m[CHIPSEC] Platform: (IceLake U 4 Cores) | |
[CHIPSEC] VID: 8086 | |
[CHIPSEC] DID: 8A12 | |
[CHIPSEC] RID: 03[0m | |
[39m[CHIPSEC] PCH : Intel 495 series PCH-LP Prem-U | |
[CHIPSEC] VID: 8086 | |
[CHIPSEC] DID: 3482 | |
[CHIPSEC] RID: 30[0m | |
[39m [0m | |
[39m[*] loading common modules from "./chipsec/modules/common" ..[0m | |
[39m[*] No platform specific modules to load[0m | |
[39m[*] loading modules from "./chipsec/modules" ..[0m | |
[39m[+] loaded chipsec.modules.common.bios_kbrd_buffer[0m | |
[39m[+] loaded chipsec.modules.common.bios_smi[0m | |
[39m[+] loaded chipsec.modules.common.bios_ts[0m | |
[39m[+] loaded chipsec.modules.common.bios_wp[0m | |
[39m[+] loaded chipsec.modules.common.cpu.cpu_info[0m | |
[39m[+] loaded chipsec.modules.common.cpu.ia_untrusted[0m | |
[39m[+] loaded chipsec.modules.common.cpu.spectre_v2[0m | |
[39m[+] loaded chipsec.modules.common.debugenabled[0m | |
[39m[+] loaded chipsec.modules.common.ia32cfg[0m | |
[39m[+] loaded chipsec.modules.common.me_mfg_mode[0m | |
[39m[+] loaded chipsec.modules.common.memconfig[0m | |
[39m[+] loaded chipsec.modules.common.memlock[0m | |
[39m[+] loaded chipsec.modules.common.remap[0m | |
[39m[+] loaded chipsec.modules.common.rtclock[0m | |
[39m[+] loaded chipsec.modules.common.secureboot.variables[0m | |
[39m[+] loaded chipsec.modules.common.sgx_check[0m | |
[39m[+] loaded chipsec.modules.common.smm[0m | |
[39m[+] loaded chipsec.modules.common.smm_dma[0m | |
[39m[+] loaded chipsec.modules.common.smrr[0m | |
[39m[+] loaded chipsec.modules.common.spd_wd[0m | |
[39m[+] loaded chipsec.modules.common.spi_access[0m | |
[39m[+] loaded chipsec.modules.common.spi_desc[0m | |
[39m[+] loaded chipsec.modules.common.spi_fdopss[0m | |
[39m[+] loaded chipsec.modules.common.spi_lock[0m | |
[39m[+] loaded chipsec.modules.common.uefi.access_uefispec[0m | |
[39m[+] loaded chipsec.modules.common.uefi.s3bootscript[0m | |
[39m[*] running loaded modules ..[0m | |
[39m | |
[*] running module: chipsec.modules.common.bios_kbrd_buffer[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Pre-boot Passwords in the BIOS Keyboard Buffer | |
[x][ =======================================================================[0m | |
[39m[*] Keyboard buffer head pointer = 0x1E (at 0x41A), tail pointer = 0x1E (at 0x41C)[0m | |
[39m[*] Keyboard buffer contents (at 0x41E):[0m | |
[39m00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | | |
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | [0m | |
[39m[*] Checking contents of the keyboard buffer.. | |
[0m | |
[32m[+] PASSED: Keyboard buffer looks empty. Pre-boot passwords don't seem to be exposed[0m | |
[39m | |
[*] running module: chipsec.modules.common.bios_smi[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SMI Events Configuration | |
[x][ =======================================================================[0m | |
[32m[+] SMM BIOS region write protection is enabled (SMM_BWP is used) | |
[0m | |
[39m[*] Checking SMI enables..[0m | |
[39m Global SMI enable: 1[0m | |
[39m TCO SMI enable : 1[0m | |
[32m[+] All required SMI events are enabled[0m | |
[39m[0m | |
[39m[*] Checking SMI configuration locks..[0m | |
[32m[+] TCO SMI configuration is locked (TCO SMI Lock)[0m | |
[32m[+] SMI events global configuration is locked (SMI Lock)[0m | |
[39m[0m | |
[32m[+] PASSED: All required SMI sources seem to be enabled and locked[0m | |
[39m | |
[*] running module: chipsec.modules.common.bios_ts[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: BIOS Interface Lock (including Top Swap Mode) | |
[x][ =======================================================================[0m | |
[39m[*] BiosInterfaceLockDown (BILD) control = 1[0m | |
[39m[*] BIOS Top Swap mode is disabled (TSS = 0)[0m | |
[39m[*] RTC TopSwap control (TS) = 0[0m | |
[32m[+] PASSED: BIOS Interface is locked (including Top Swap Mode)[0m | |
[39m | |
[*] running module: chipsec.modules.common.bios_wp[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: BIOS Region Write Protection | |
[x][ =======================================================================[0m | |
[39m[*] BC = 0x000008AA << BIOS Control (b:d.f 00:31.5 + 0xDC) | |
[00] BIOSWE = 0 << BIOS Write Enable | |
[01] BLE = 1 << BIOS Lock Enable | |
[02] SRC = 2 << SPI Read Configuration | |
[04] TSS = 0 << Top Swap Status | |
[05] SMM_BWP = 1 << SMM BIOS Write Protection | |
[06] BBS = 0 << Boot BIOS Strap | |
[07] BILD = 1 << BIOS Interface Lock Down | |
[11] ASE_BWP = 1 << Async SMI Enable for BIOS Write Protection [0m | |
[32m[+] BIOS region write protection is enabled (writes restricted to SMM)[0m | |
[39m | |
[*] BIOS Region: Base = 0x00500000, Limit = 0x00FFFFFF[0m | |
[39mSPI Protected Ranges[0m | |
[39m------------------------------------------------------------[0m | |
[39mPRx (offset) | Value | Base | Limit | WP? | RP?[0m | |
[39m------------------------------------------------------------[0m | |
[39mPR0 (84) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m | |
[39mPR1 (88) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m | |
[39mPR2 (8C) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m | |
[39mPR3 (90) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m | |
[39mPR4 (94) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m | |
[39m[0m | |
[31m[!] None of the SPI protected ranges write-protect BIOS region[0m | |
[39m[0m | |
[32m[+] PASSED: BIOS is write protected[0m | |
[39m | |
[*] running module: chipsec.modules.common.cpu.cpu_info[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Current Processor Information: | |
[x][ =======================================================================[0m | |
[39m[*] Thread 0000[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0001[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0002[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0003[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0004[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0005[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0006[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[39m[*] Thread 0007[0m | |
[39m[*] Processor: Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz[0m | |
[39m[*] Family: 06 Model: 7E Stepping: 5[0m | |
[39m[*] Microcode: 000000A0[0m | |
[39m[*][0m | |
[32m[#] INFORMATION: Processor information displayed[0m | |
[39m | |
[*] running module: chipsec.modules.common.cpu.ia_untrusted[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: IA_UNTRUSTED Check | |
[x][ =======================================================================[0m | |
[39m[*] Check that untrusted mode has been set.[0m | |
[32m[+] SoC_BIOS_DONE set.[0m | |
[39m[0m | |
[32m[+] IA_UNTRUSTED set on thread 0.[0m | |
[32m[+] IA_UNTRUSTED set on thread 1.[0m | |
[32m[+] IA_UNTRUSTED set on thread 2.[0m | |
[32m[+] IA_UNTRUSTED set on thread 3.[0m | |
[32m[+] IA_UNTRUSTED set on thread 4.[0m | |
[32m[+] IA_UNTRUSTED set on thread 5.[0m | |
[32m[+] IA_UNTRUSTED set on thread 6.[0m | |
[32m[+] IA_UNTRUSTED set on thread 7.[0m | |
[39m[0m | |
[32m[+] PASSED: IA_UNTRUSTED set on all threads[0m | |
[39m | |
[*] running module: chipsec.modules.common.cpu.spectre_v2[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Checks for Branch Target Injection / Spectre v2 (CVE-2017-5715) | |
[x][ =======================================================================[0m | |
[39m[*] CPUID.7H:EDX[26] = 1 Indirect Branch Restricted Speculation (IBRS) & Predictor Barrier (IBPB)[0m | |
[39m[*] CPUID.7H:EDX[27] = 1 Single Thread Indirect Branch Predictors (STIBP)[0m | |
[39m[*] CPUID.7H:EDX[29] = 1 IA32_ARCH_CAPABILITIES[0m | |
[32m[+] CPU supports IBRS and IBPB[0m | |
[32m[+] CPU supports STIBP[0m | |
[39m[*] checking enhanced IBRS support in IA32_ARCH_CAPABILITIES...[0m | |
[39m[*] cpu0: IBRS_ALL = 1[0m | |
[39m[*] cpu1: IBRS_ALL = 1[0m | |
[39m[*] cpu2: IBRS_ALL = 1[0m | |
[39m[*] cpu3: IBRS_ALL = 1[0m | |
[39m[*] cpu4: IBRS_ALL = 1[0m | |
[39m[*] cpu5: IBRS_ALL = 1[0m | |
[39m[*] cpu6: IBRS_ALL = 1[0m | |
[39m[*] cpu7: IBRS_ALL = 1[0m | |
[32m[+] CPU supports enhanced IBRS (on all logical CPU)[0m | |
[39m[*] checking if OS is using Enhanced IBRS...[0m | |
[39m[*] cpu0: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu0: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu1: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu1: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu2: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu2: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu3: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu3: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu4: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu4: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu5: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu5: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu6: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu6: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[39m[*] cpu7: IA32_SPEC_CTRL[IBRS] = 1[0m | |
[39m[*] cpu7: IA32_SPEC_CTRL[STIBP] = 0[0m | |
[32m[+] OS enabled Enhanced IBRS (on all logical processors)[0m | |
[32m[#] INFORMATION: Unable to determine if the OS uses STIBP[0m | |
[32m[+] PASSED: CPU and OS support hardware mitigations[0m | |
[31m[!] OS may be using software based mitigation (eg. retpoline)[0m | |
[33m[!] WARNING: 'retpoline_enabled' is not implemented[0m | |
[39m | |
[*] running module: chipsec.modules.common.debugenabled[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Debug features test | |
[x][ =======================================================================[0m | |
[39m | |
[*] Checking IA32_DEBUG_INTERFACE msr status[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[32m[+] CPU debug interface state is correct.[0m | |
[39m | |
[*] Checking DCI register status[0m | |
[32m[+] DCI Debug is disabled[0m | |
[39m | |
[*] Module Result[0m | |
[32m[+] PASSED: All checks have successfully passed[0m | |
[39m | |
[*] running module: chipsec.modules.common.ia32cfg[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: IA32 Feature Control Lock | |
[x][ =======================================================================[0m | |
[39m[*] Verifying IA32_Feature_Control MSR is locked on all logical CPUs..[0m | |
[39m[*] cpu0: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu1: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu2: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu3: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu4: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu5: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu6: IA32_Feature_Control Lock = 1[0m | |
[39m[*] cpu7: IA32_Feature_Control Lock = 1[0m | |
[32m[+] PASSED: IA32_FEATURE_CONTROL MSR is locked on all logical CPUs[0m | |
[39m | |
[*] running module: chipsec.modules.common.me_mfg_mode[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: ME Manufacturing Mode | |
[x][ =======================================================================[0m | |
[32m[+] PASSED: ME is not in Manufacturing Mode[0m | |
[39m | |
[*] running module: chipsec.modules.common.memconfig[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Host Bridge Memory Map Locks | |
[x][ =======================================================================[0m | |
[39m[*][0m | |
[39m[*] Checking legacy register lock state:[0m | |
[32m[+] PCI0.0.0_BDSM = 0x 6C800001 - LOCKED - Base of Graphics Stolen Memory[0m | |
[32m[+] PCI0.0.0_BGSM = 0x 6C000001 - LOCKED - Base of GTT Stolen Memory[0m | |
[32m[+] PCI0.0.0_DPR = 0x 6B000001 - LOCKED - DMA Protected Range[0m | |
[32m[+] PCI0.0.0_GGC = 0x FEC1 - LOCKED - Graphics Control[0m | |
[39m[?] Skipping Validation: Register PCI0.0.0_MESEG_MASK or field MELCK was not defined for this platform.[0m | |
[32m[+] PCI0.0.0_PAVPC = 0x 702000C7 - LOCKED - PAVP Configuration[0m | |
[39m[?] Skipping Validation: Register PCI0.0.0_REMAPBASE or field LOCK was not defined for this platform.[0m | |
[39m[?] Skipping Validation: Register PCI0.0.0_REMAPLIMIT or field LOCK was not defined for this platform.[0m | |
[32m[+] PCI0.0.0_TOLUD = 0x 70400001 - LOCKED - Top of Low Usable DRAM[0m | |
[32m[+] PCI0.0.0_TOM = 0x 200000001 - LOCKED - Top of Memory[0m | |
[32m[+] PCI0.0.0_TOUUD = 0x 28FC00001 - LOCKED - Top of Upper Usable DRAM[0m | |
[31m[-] PCI0.0.0_TSEGMB = 0x 6B000000 - UNLOCKED - TSEG Memory Base[0m | |
[39m[*][0m | |
[39m[*] Checking if IA Untrusted mode is used to lock registers[0m | |
[32m[+] IA Untrusted mode set[0m | |
[39m[*][0m | |
[32m[+] PASSED: All memory map registers seem to be locked down[0m | |
[39m | |
[*] running module: chipsec.modules.common.memlock[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Check MSR_LT_LOCK_MEMORY | |
[x][ =======================================================================[0m | |
[39m[X] Checking MSR_LT_LOCK_MEMORY status[0m | |
[39m[*] cpu0: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu1: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu2: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu3: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu4: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu5: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu6: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[39m[*] cpu7: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m | |
[32m[+] PASSED: Check have successfully passed[0m | |
[39m | |
[*] running module: chipsec.modules.common.remap[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Memory Remapping Configuration | |
[x][ =======================================================================[0m | |
[39m[*] Registers:[0m | |
[39m[*] TOUUD : 0x000000028FC00001[0m | |
[39m[*] REMAPLIMIT: 0x000000028FB00000[0m | |
[39m[*] REMAPBASE : 0x0000000200000000[0m | |
[39m[*] TOLUD : 0x70400001[0m | |
[39m[*] TSEGMB : 0x6B000000 | |
[0m | |
[39m[*] Memory Map:[0m | |
[39m[*] Top Of Upper Memory: 0x000000028FC00000[0m | |
[39m[*] Remap Limit Address: 0x000000028FBFFFFF[0m | |
[39m[*] Remap Base Address : 0x0000000200000000[0m | |
[39m[*] 4GB : 0x0000000100000000[0m | |
[39m[*] Top Of Low Memory : 0x0000000070400000[0m | |
[39m[*] TSEG (SMRAM) Base : 0x000000006B000000 | |
[0m | |
[39m[*] checking memory remap configuration..[0m | |
[39m[*] Memory Remap is enabled[0m | |
[32m[+] Remap window configuration is correct: REMAPBASE <= REMAPLIMIT < TOUUD[0m | |
[32m[+] All addresses are 1MB aligned[0m | |
[39m[*] checking if memory remap configuration is locked..[0m | |
[32m[+] TOUUD is locked[0m | |
[32m[+] TOLUD is locked[0m | |
[32m[+] REMAPBASE and REMAPLIMIT are locked[0m | |
[32m[+] PASSED: Memory Remap is configured correctly and locked[0m | |
[39m | |
[*] running module: chipsec.modules.common.rtclock[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Protected RTC memory locations | |
[x][ =======================================================================[0m | |
[33m[!] WARNING: Unable to test lock bits without attempting to modify CMOS.[0m | |
[39m[*] Run chipsec_main manually with the following commandline flags.[0m | |
[39m[*] python chipsec_main -m common.rtclock -a modify[0m | |
[39m | |
[*] running module: chipsec.modules.common.secureboot.variables[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Attributes of Secure Boot EFI Variables | |
[x][ =======================================================================[0m | |
[39m[*] Checking protections of UEFI variable 8be4df61-93ca-11d2-aa0d-00e098032b8c:SecureBoot[0m | |
[39m[*] Checking protections of UEFI variable 8be4df61-93ca-11d2-aa0d-00e098032b8c:SetupMode[0m | |
[39m[*] Checking protections of UEFI variable 8be4df61-93ca-11d2-aa0d-00e098032b8c:PK[0m | |
[32m[+] Variable 8be4df61-93ca-11d2-aa0d-00e098032b8c:PK is authenticated (TIME_BASED_AUTHENTICATED_WRITE_ACCESS)[0m | |
[39m[*] Checking protections of UEFI variable 8be4df61-93ca-11d2-aa0d-00e098032b8c:KEK[0m | |
[32m[+] Variable 8be4df61-93ca-11d2-aa0d-00e098032b8c:KEK is authenticated (TIME_BASED_AUTHENTICATED_WRITE_ACCESS)[0m | |
[39m[*] Checking protections of UEFI variable d719b2cb-3d3a-4596-a3bc-dad00e67656f:db[0m | |
[32m[+] Variable d719b2cb-3d3a-4596-a3bc-dad00e67656f:db is authenticated (TIME_BASED_AUTHENTICATED_WRITE_ACCESS)[0m | |
[39m[*] Checking protections of UEFI variable d719b2cb-3d3a-4596-a3bc-dad00e67656f:dbx[0m | |
[32m[+] Variable d719b2cb-3d3a-4596-a3bc-dad00e67656f:dbx is authenticated (TIME_BASED_AUTHENTICATED_WRITE_ACCESS)[0m | |
[39m[0m | |
[39m[*] Secure Boot appears to be disabled[0m | |
[32m[+] PASSED: All Secure Boot UEFI variables are protected[0m | |
[39m | |
[*] running module: chipsec.modules.common.sgx_check[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Check SGX feature support | |
[x][ =======================================================================[0m | |
[39m[*] Test if CPU has support for SGX[0m | |
[39m | |
[*] SGX BIOS enablement check[0m | |
[39m[*] Verifying IA32_FEATURE_CONTROL MSR is configured[0m | |
[33m[!] WARNING: Intel SGX is not enabled in BIOS[0m | |
[39m | |
[*] Verifying IA32_FEATURE_CONTROL MSR is locked[0m | |
[32m[+] IA32_Feature_Control locked[0m | |
[39m | |
[*] Verifying if Protected Memory Range (PRMRR) is configured[0m | |
[32m[+] Protected Memory Range configuration is supported[0m | |
[39m | |
[*] Verifying PRMRR Configuration on each core.[0m | |
[32m[+] PRMRR config is uniform across all CPUs[0m | |
[39m[*] PRMRR config supports: 2M, 64M, 128M, 256M[0m | |
[39m[*] PRMRR base address: 0x00000006AA00[0m | |
[39m[*] Verifying PRMR memory type is valid[0m | |
[39m[*] PRMRR memory type : 0x6[0m | |
[32m[+] PRMRR memory type is WB as expected[0m | |
[39m[*] PRMRR mask address: 0x000007FFFE00[0m | |
[39m[*] Verifying PRMR address are valid[0m | |
[39m[*] PRMRR uncore mask valid: 0x0[0m | |
[32m[+] Mcheck marked PRMRR address as valid[0m | |
[39m[*] Verifying if PRMR mask register is locked[0m | |
[39m[*] PRMRR mask lock: 0x1[0m | |
[32m[+] PRMRR MASK register is locked[0m | |
[39m | |
[*] Verifying if SGX is available to use[0m | |
[33m[!] WARNING: Intel SGX instructions disabled by firmware[0m | |
[39m | |
[*] BIOS_SE_SVN : 0x0000FFFFFFFF000A[0m | |
[39m[*] PFAT_SE_SVN : 0xFF[0m | |
[39m[*] ANC_SE_SVN : 0xFF[0m | |
[39m[*] SCLEAN_SE_SVN : 0xFF[0m | |
[39m[*] SINIT_SE_SVN : 0xFF[0m | |
[39m[*] BIOS_SE_SVN_STATUS : 0x0000000000000000[0m | |
[39m[*] BIOS_SE_SVN ACM threshold lock : 0x0[0m | |
[39m | |
[*] Check SGX debug feature settings[0m | |
[39m[*] SGX Debug Enable : 0[0m | |
[39m[*] Check Silicon debug feature settings[0m | |
[39m[*] IA32_DEBUG_INTERFACE : 0x40000000[0m | |
[39m[*] Debug enabled : 0[0m | |
[39m[*] Lock : 1[0m | |
[32m[+] SGX debug mode is disabled[0m | |
[32m[+] Silicon debug features are disabled[0m | |
[32m[+] Silicon debug Feature Control register is locked[0m | |
[33m[!] WARNING: One or more SGX checks detected a warning[0m | |
[39m | |
[*] running module: chipsec.modules.common.smm[0m | |
[39mSkipping module chipsec.modules.common.smm since it is not supported in this platform[0m | |
[39m | |
[*] running module: chipsec.modules.common.smm_dma[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SMM TSEG Range Configuration Check | |
[x][ =======================================================================[0m | |
[39m[*] TSEG : 0x000000006B000000 - 0x000000006BFFFFFF (size = 0x01000000)[0m | |
[39m[*] SMRR range: 0x000000006B000000 - 0x000000006BFFFFFF (size = 0x01000000) | |
[0m | |
[39m[*] checking TSEG range configuration..[0m | |
[32m[+] TSEG range covers entire SMRAM[0m | |
[32m[+] TSEG range is locked[0m | |
[32m[+] PASSED: TSEG is properly configured. SMRAM is protected from DMA attacks[0m | |
[39m | |
[*] running module: chipsec.modules.common.smrr[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: CPU SMM Cache Poisoning / System Management Range Registers | |
[x][ =======================================================================[0m | |
[32m[+] OK. SMRR range protection is supported[0m | |
[39m[0m | |
[39m[*] Checking SMRR range base programming..[0m | |
[39m[*] IA32_SMRR_PHYSBASE = 0x6B000006 << SMRR Base Address MSR (MSR 0x1F2) | |
[00] Type = 6 << SMRR memory type | |
[12] PhysBase = 6B000 << SMRR physical base address [0m | |
[39m[*] SMRR range base: 0x000000006B000000[0m | |
[39m[*] SMRR range memory type is Writeback (WB)[0m | |
[32m[+] OK so far. SMRR range base is programmed[0m | |
[39m[0m | |
[39m[*] Checking SMRR range mask programming..[0m | |
[39m[*] IA32_SMRR_PHYSMASK = 0xFF000C00 << SMRR Range Mask MSR (MSR 0x1F3) | |
[11] Valid = 1 << SMRR valid | |
[12] PhysMask = FF000 << SMRR address range mask [0m | |
[39m[*] SMRR range mask: 0x00000000FF000000[0m | |
[32m[+] OK so far. SMRR range is enabled[0m | |
[39m[0m | |
[39m[*] Verifying that SMRR range base & mask are the same on all logical CPUs..[0m | |
[39m[CPU0] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU1] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU2] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU3] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU4] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU5] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU6] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[39m[CPU7] SMRR_PHYSBASE = 000000006B000006, SMRR_PHYSMASK = 00000000FF000C00[0m | |
[32m[+] OK so far. SMRR range base/mask match on all logical CPUs[0m | |
[39m[*] Trying to read memory at SMRR base 0x6B000000..[0m | |
[32m[+] PASSED: SMRR reads are blocked in non-SMM mode[0m | |
[39m[0m | |
[32m[+] PASSED: SMRR protection against cache attack is properly configured[0m | |
[39m | |
[*] running module: chipsec.modules.common.spd_wd[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SPD Write Disable | |
[x][ =======================================================================[0m | |
[32m[+] PASSED: SPD Write Disable is set[0m | |
[39m | |
[*] running module: chipsec.modules.common.spi_access[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SPI Flash Region Access Control | |
[x][ =======================================================================[0m | |
[39mSPI Flash Region Access Permissions[0m | |
[39m------------------------------------------------------------[0m | |
[39m[0m | |
[39mBIOS Region Write Access Grant (00):[0m | |
[39m FREG0_FLASHD: 0[0m | |
[39m FREG1_BIOS : 0[0m | |
[39m FREG2_ME : 0[0m | |
[39m FREG3_GBE : 0[0m | |
[39m FREG4_PD : 0[0m | |
[39m FREG5 : 0[0m | |
[39m FREG6 : 0[0m | |
[39mBIOS Region Read Access Grant (00):[0m | |
[39m FREG0_FLASHD: 0[0m | |
[39m FREG1_BIOS : 0[0m | |
[39m FREG2_ME : 0[0m | |
[39m FREG3_GBE : 0[0m | |
[39m FREG4_PD : 0[0m | |
[39m FREG5 : 0[0m | |
[39m FREG6 : 0[0m | |
[39mBIOS Region Write Access (4A):[0m | |
[39m FREG0_FLASHD: 0[0m | |
[39m FREG1_BIOS : 1[0m | |
[39m FREG2_ME : 0[0m | |
[39m FREG3_GBE : 1[0m | |
[39m FREG4_PD : 0[0m | |
[39m FREG5 : 0[0m | |
[39m FREG6 : 1[0m | |
[39mBIOS Region Read Access (CF):[0m | |
[39m FREG0_FLASHD: 1[0m | |
[39m FREG1_BIOS : 1[0m | |
[39m FREG2_ME : 1[0m | |
[39m FREG3_GBE : 1[0m | |
[39m FREG4_PD : 0[0m | |
[39m FREG5 : 0[0m | |
[39m FREG6 : 1[0m | |
[33m[!] WARNING: Software has write access to GBe region in SPI flash[0m | |
[33m[!] WARNING: Certain SPI flash regions are writeable by software[0m | |
[39m | |
[*] running module: chipsec.modules.common.spi_desc[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SPI Flash Region Access Control | |
[x][ =======================================================================[0m | |
[39m[*] FRAP = 0x00004ACF << SPI Flash Regions Access Permissions Register (SPIBAR + 0x50) | |
[00] BRRA = CF << BIOS Region Read Access | |
[08] BRWA = 4A << BIOS Region Write Access | |
[16] BMRAG = 0 << BIOS Master Read Access Grant | |
[24] BMWAG = 0 << BIOS Master Write Access Grant [0m | |
[39m[*] Software access to SPI flash regions: read = 0xCF, write = 0x4A[0m | |
[39m[0m | |
[32m[+] PASSED: SPI flash permissions prevent SW from writing to flash descriptor[0m | |
[39m | |
[*] running module: chipsec.modules.common.spi_fdopss[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SPI Flash Descriptor Security Override Pin-Strap | |
[x][ =======================================================================[0m | |
[39m[*] HSFS = 0x0000E800 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) | |
[00] FDONE = 0 << Flash Cycle Done | |
[01] FCERR = 0 << Flash Cycle Error | |
[02] AEL = 0 << Access Error Log | |
[05] SCIP = 0 << SPI cycle in progress | |
[11] WRSDIS = 1 << Write status disable | |
[12] PR34LKD = 0 << PRR3 PRR4 Lock-Down | |
[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status | |
[14] FDV = 1 << Flash Descriptor Valid | |
[15] FLOCKDN = 1 << Flash Configuration Lock-Down | |
[16] FGO = 0 << Flash cycle go | |
[17] FCYCLE = 0 << Flash Cycle Type | |
[21] WET = 0 << Write Enable Type | |
[24] FDBC = 0 << Flash Data Byte Count | |
[31] FSMIE = 0 << Flash SPI SMI# Enable [0m | |
[32m[+] PASSED: SPI Flash Descriptor Security Override is disabled[0m | |
[39m | |
[*] running module: chipsec.modules.common.spi_lock[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: SPI Flash Controller Configuration Locks | |
[x][ =======================================================================[0m | |
[39m[*] HSFS = 0x0000E800 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) | |
[00] FDONE = 0 << Flash Cycle Done | |
[01] FCERR = 0 << Flash Cycle Error | |
[02] AEL = 0 << Access Error Log | |
[05] SCIP = 0 << SPI cycle in progress | |
[11] WRSDIS = 1 << Write status disable | |
[12] PR34LKD = 0 << PRR3 PRR4 Lock-Down | |
[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status | |
[14] FDV = 1 << Flash Descriptor Valid | |
[15] FLOCKDN = 1 << Flash Configuration Lock-Down | |
[16] FGO = 0 << Flash cycle go | |
[17] FCYCLE = 0 << Flash Cycle Type | |
[21] WET = 0 << Write Enable Type | |
[24] FDBC = 0 << Flash Data Byte Count | |
[31] FSMIE = 0 << Flash SPI SMI# Enable [0m | |
[32m[+] SPI write status disable set.[0m | |
[32m[+] SPI Flash Controller configuration is locked[0m | |
[32m[+] PASSED: SPI Flash Controller locked correctly.[0m | |
[39m | |
[*] running module: chipsec.modules.common.uefi.access_uefispec[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: Access Control of EFI Variables | |
[x][ =======================================================================[0m | |
[39m[*] Testing UEFI variables ..[0m | |
[39m[*] Variable WAND (NV+BS+RT)[0m | |
[39m[*] Variable PlatformLangCodes (BS+RT)[0m | |
[39m[*] Variable BootOrder (NV+BS+RT)[0m | |
[39m[*] Variable SetupCpuFeatures (NV+BS+RT)[0m | |
[39m[*] Variable InitSetupVariable (NV+BS+RT)[0m | |
[39m[*] Variable dbx (NV+BS+RT+TBAWS)[0m | |
[39m[*] Variable SystemAudioVolume (NV+BS+RT)[0m | |
[39m[*] Variable UserManagerVar (NV+BS+RT)[0m | |
[39m[*] Variable ConOut (NV+BS+RT)[0m | |
[39m[*] Variable TcgSetup (NV+BS+RT)[0m | |
[39m[*] Variable SPLC (NV+BS+RT)[0m | |
[39m[*] Variable OilRetentionVariable (NV+BS+RT)[0m | |
[39m[*] Variable OilSetup (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0014 (BS+RT)[0m | |
[39m[*] Variable VarErrorFlag (NV+BS+RT)[0m | |
[39m[*] Variable csr-active-config (NV+BS+RT)[0m | |
[39m[*] Variable opencore-version (NV+BS+RT)[0m | |
[39m[*] Variable CpuSetupVolatileData (BS+RT)[0m | |
[39m[*] Variable LenovoComputraceFpConfig (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0017 (BS+RT)[0m | |
[39m[*] Variable OrgLoadOptionCrcTable (NV+BS+RT)[0m | |
[39m[*] Variable BRDS (NV+BS+RT)[0m | |
[39m[*] Variable Tcg2PhysicalPresenceFlags (NV+BS+RT)[0m | |
[39m[*] Variable Setup (NV+BS+RT)[0m | |
[39m[*] Variable db (NV+BS+RT+TBAWS)[0m | |
[39m[*] Variable GPC (NV+BS+RT)[0m | |
[39m[*] Variable lvar (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0001 (BS+RT)[0m | |
[39m[*] Variable OfflineUniqueIDEKPubCRC (NV+BS+RT)[0m | |
[39m[*] Variable SMBIOSMEMSIZE (NV+BS+RT)[0m | |
[39m[*] Variable VendorKeys (BS+RT)[0m | |
[39m[*] Variable SiSetup (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0019 (BS+RT)[0m | |
[39m[*] Variable ConOutDev (BS+RT)[0m | |
[39m[*] Variable PreDefinedBootOptions (NV+BS+RT)[0m | |
[39m[*] Variable System (NV+BS+RT)[0m | |
[39m[*] Variable LastBootCurrent (NV+BS+RT)[0m | |
[39m[*] Variable WGDS (NV+BS+RT)[0m | |
[39m[*] Variable SFRM_NVRAM (NV+BS+RT)[0m | |
[39m[*] Variable Tcg2PhysicalPresence (NV+BS+RT)[0m | |
[39m[*] Variable lBoot001B (BS+RT)[0m | |
[39m[*] Variable lBoot001C (BS+RT)[0m | |
[39m[*] Variable UnlockIDCopy (NV+BS+RT)[0m | |
[39m[*] Variable CpuSetup (NV+BS+RT)[0m | |
[39m[*] Variable MeSetup (NV+BS+RT)[0m | |
[39m[*] Variable boot-args (NV+BS+RT)[0m | |
[39m[*] Variable DIAGSPLSHSCRN (BS+RT)[0m | |
[39m[*] Variable lBoot001A (BS+RT)[0m | |
[39m[*] Variable LenovoSecurityStatus (NV+BS+RT)[0m | |
[39m[*] Variable HDD_Password_Status (NV+BS+RT)[0m | |
[39m[*] Variable SetupMode (BS+RT)[0m | |
[39m[*] Variable PK (NV+BS+RT+TBAWS)[0m | |
[39m[*] Variable L05OkrData (NV+BS+RT)[0m | |
[39m[*] Variable SCT_SECURE_BOOT_CONFIGURATION (NV+BS+RT)[0m | |
[39m[*] Variable SMBIOSELOG000 (NV+BS+RT)[0m | |
[39m[*] Variable RTL-pwrovr (NV+BS+RT)[0m | |
[39m[*] Variable LBLDESP (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0000 (BS+RT)[0m | |
[39m[*] Variable OilEraseVar (NV+BS+RT)[0m | |
[39m[*] Variable OsIndications (NV+BS+RT)[0m | |
[39m[*] Variable CapsuleLongModeBuffer (NV+BS+RT)[0m | |
[39m[*] Variable UCR (NV+BS+RT)[0m | |
[39m[*] Variable BootOptionSupport (BS+RT)[0m | |
[39m[*] Variable OfflineUniqueIDEKPub (NV+BS+RT)[0m | |
[39m[*] Variable ConInDev (BS+RT)[0m | |
[39m[*] Variable ErrOutDev (BS+RT)[0m | |
[39m[*] Variable prev-lang:kbd (NV+BS+RT)[0m | |
[39m[*] Variable Key0002 (NV+BS+RT)[0m | |
[39m[*] Variable Key0000 (NV+BS+RT)[0m | |
[39m[*] Variable Key0001 (NV+BS+RT)[0m | |
[39m[*] Variable MeSetupStorage (NV+BS+RT)[0m | |
[39m[*] Variable ProtectedBootOptions (NV+BS+RT)[0m | |
[39m[*] Variable boot-feature-usage (NV+BS+RT)[0m | |
[39m[*] Variable PciBusSetup (NV+BS+RT)[0m | |
[39m[*] Variable SMBIOSELOGNUMBER (NV+BS+RT)[0m | |
[39m[*] Variable OsProfile (NV+BS+RT)[0m | |
[39m[*] Variable LastBootOrder (NV+BS+RT)[0m | |
[39m[*] Variable EWRD (NV+BS+RT)[0m | |
[39m[*] Variable SaSetup (NV+BS+RT)[0m | |
[39m[*] Variable WRDS (NV+BS+RT)[0m | |
[39m[*] Variable Timeout (NV+BS+RT)[0m | |
[39m[*] Variable OilSetupVarInited (NV+BS+RT)[0m | |
[39m[*] Variable BootOrderDefault (NV+BS+RT)[0m | |
[39m[*] Variable SignatureSupport (BS+RT)[0m | |
[39m[*] Variable KEK (NV+BS+RT+TBAWS)[0m | |
[39m[*] Variable lBoot0015 (BS+RT)[0m | |
[39m[*] Variable PchSetup (NV+BS+RT)[0m | |
[39m[*] Variable OpromDevicePath (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0002 (BS+RT)[0m | |
[39m[*] Variable TbtSetupVolatileData (BS+RT)[0m | |
[39m[*] Variable Boot0000 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0001 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0002 (NV+BS+RT)[0m | |
[39m[*] Variable SecureBoot (BS+RT)[0m | |
[39m[*] Variable WRDD (NV+BS+RT)[0m | |
[39m[*] Variable OilTpmVarInited (NV+BS+RT)[0m | |
[39m[*] Variable certdbv (BS+RT+TBAWS)[0m | |
[39m[*] Variable PBRDevicePath (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0016 (BS+RT)[0m | |
[39m[*] Variable run-efi-updater (NV+BS+RT)[0m | |
[39m[*] Variable BootState (NV+BS+RT)[0m | |
[39m[*] Variable ConfigurationPagePrivate (NV+BS+RT)[0m | |
[39m[*] Variable Boot001C (NV+BS+RT)[0m | |
[39m[*] Variable Boot001B (NV+BS+RT)[0m | |
[39m[*] Variable Boot001A (NV+BS+RT)[0m | |
[39m[*] Variable LoadOptionCrcTable (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0012 (BS+RT)[0m | |
[39m[*] Variable lBoot0013 (BS+RT)[0m | |
[39m[*] Variable lBoot0010 (BS+RT)[0m | |
[39m[*] Variable lBoot0011 (BS+RT)[0m | |
[39m[*] Variable ConIn (NV+BS+RT)[0m | |
[39m[*] Variable lBoot0018 (BS+RT)[0m | |
[39m[*] Variable ReservedConfiguration (NV+BS+RT)[0m | |
[39m[*] Variable Boot0013 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0012 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0011 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0010 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0017 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0016 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0015 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0014 (NV+BS+RT)[0m | |
[39m[*] Variable CurrentPolicy (NV+BS+RT+TBAWS)[0m | |
[39m[*] Variable RstOptaneConfig (NV+BS+RT)[0m | |
[39m[*] Variable Boot0019 (NV+BS+RT)[0m | |
[39m[*] Variable Boot0018 (NV+BS+RT)[0m | |
[39m[*] Variable OsIndicationsSupported (BS+RT)[0m | |
[39m[*] Variable PbaStatusVar (NV+BS+RT)[0m | |
[39m[*] Variable SADS (NV+BS+RT)[0m | |
[39m[*] Variable MTC (NV+BS+RT)[0m | |
[39m[*] Variable PreviousBoot (NV+BS+RT)[0m | |
[39m[*] Variable UIScale (NV+BS+RT)[0m | |
[39m[*] Variable EventLog (BS+RT)[0m | |
[39m[*] Variable HDDPWD (NV+BS+RT)[0m | |
[39m[*] Variable SOFTWAREGUARDSTATUS (BS+RT)[0m | |
[39m[*] Variable certdb (NV+BS+RT+TBAWS)[0m | |
[39m[*] Variable BootCurrent (BS+RT)[0m | |
[39m[*] Variable PlatformLang (NV+BS+RT)[0m | |
[39m[0m | |
[32m[+] PASSED: All checked EFI variables are protected according to spec.[0m | |
[39m | |
[*] running module: chipsec.modules.common.uefi.s3bootscript[0m | |
[34m[x][ ======================================================================= | |
[x][ Module: S3 Resume Boot-Script Protections | |
[x][ =======================================================================[0m | |
[39m[*] SMRAM: Base = 0x000000006B000000, Limit = 0x000000006BFFFFFF, Size = 0x01000000[0m | |
[32m[+] Didn't find any S3 boot-scripts in EFI variables[0m | |
[33m[!] WARNING: S3 Boot-Script was not found. Firmware may be using other ways to store/locate it, or OS might be blocking access.[0m | |
[39m | |
[CHIPSEC] *************************** SUMMARY ***************************[0m | |
[39m[CHIPSEC] Time elapsed 0.121[0m | |
[39m[CHIPSEC] Modules total 26[0m | |
[39m[CHIPSEC] Modules failed to run 0:[0m | |
[39m[CHIPSEC] Modules passed 20:[0m | |
[32m[+] PASSED: chipsec.modules.common.bios_kbrd_buffer[0m | |
[32m[+] PASSED: chipsec.modules.common.bios_smi[0m | |
[32m[+] PASSED: chipsec.modules.common.bios_ts[0m | |
[32m[+] PASSED: chipsec.modules.common.bios_wp[0m | |
[32m[+] PASSED: chipsec.modules.common.cpu.ia_untrusted[0m | |
[32m[+] PASSED: chipsec.modules.common.cpu.spectre_v2[0m | |
[32m[+] PASSED: chipsec.modules.common.debugenabled[0m | |
[32m[+] PASSED: chipsec.modules.common.ia32cfg[0m | |
[32m[+] PASSED: chipsec.modules.common.me_mfg_mode[0m | |
[32m[+] PASSED: chipsec.modules.common.memconfig[0m | |
[32m[+] PASSED: chipsec.modules.common.memlock[0m | |
[32m[+] PASSED: chipsec.modules.common.remap[0m | |
[32m[+] PASSED: chipsec.modules.common.secureboot.variables[0m | |
[32m[+] PASSED: chipsec.modules.common.smm_dma[0m | |
[32m[+] PASSED: chipsec.modules.common.smrr[0m | |
[32m[+] PASSED: chipsec.modules.common.spd_wd[0m | |
[32m[+] PASSED: chipsec.modules.common.spi_desc[0m | |
[32m[+] PASSED: chipsec.modules.common.spi_fdopss[0m | |
[32m[+] PASSED: chipsec.modules.common.spi_lock[0m | |
[32m[+] PASSED: chipsec.modules.common.uefi.access_uefispec[0m | |
[39m[CHIPSEC] Modules information 1:[0m | |
[32m[#] INFORMATION: chipsec.modules.common.cpu.cpu_info[0m | |
[39m[CHIPSEC] Modules failed 0:[0m | |
[39m[CHIPSEC] Modules with warnings 4:[0m | |
[33m[!] WARNING: chipsec.modules.common.rtclock[0m | |
[33m[!] WARNING: chipsec.modules.common.sgx_check[0m | |
[33m[!] WARNING: chipsec.modules.common.spi_access[0m | |
[33m[!] WARNING: chipsec.modules.common.uefi.s3bootscript[0m | |
[39m[CHIPSEC] Modules not implemented 0:[0m | |
[39m[CHIPSEC] Modules not applicable 1:[0m | |
[33m[*] NOT APPLICABLE: chipsec.modules.common.smm[0m | |
[39m[CHIPSEC] *****************************************************************[0m |
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