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#pragma once
#ifdef NDEBUG
//#define verify(f) ((f) ? (void)(0):(void)(0))
#else
#define static_assert(cond) \
__attribute__((unused)) extern char \
dummy_assert_array[(cond) ? 1 : -1]
#define verify(f) (assert(f))
@mrsoliman
mrsoliman / change_endian.vhd
Created December 20, 2018 02:00
This two VHDL functions change the endianess. This enables to change from Big to Little Endian and vice versa. It is assumed that 1 byte is 8 bits. http://firefox3107.blogspot.com/2011/01/vhdl-change-endianess.html
-- changes the endianess BIG <-> LITTLE
function ChangeEndian(vec : std_ulogic_vector) return std_ulogic_vector is
variable vRet : std_ulogic_vector(vec'range);
constant cNumBytes : natural := vec'length / 8;
begin
for i in 0 to cNumBytes-1 loop
for j in 7 downto 0 loop
vRet(8*i + j) := vec(8*(cNumBytes-1-i) + j);
@mrsoliman
mrsoliman / overwrite.py
Created December 5, 2018 23:38
Overwrite the previous printed line.
import sys
print("FAILED...")
\!h sys.stdout.write("\033[F") #back to previous line
\!h sys.stdout.write("\033[K") #clear line
print("SUCCESS!")