CodeEmitterGen is a TableGen backend that generates instruction encoder functions for MCCodeEmitter
from a concise TableGen syntax. It is, however, almost exclusively designed for targets that use fixed-length instructions. It's nearly impossible to use this infrastructure to describe instruction encoding scheme for ISAs with variable-length instructions, like X86 and M68k.
To have a better understanding on this problem, let's look at an example. For a fixed-length instruction ISA, developers write the following TableGen syntax to describe an instruction encoding:
class MyInst<(outs GR64:$dst), (ins GR64, i16imm:$imm)> : Instruction {
bits<32> Inst;
bits<4> dst;